?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pc: piix4/ich9: add 'cpu-hotplug-legacy' property
[qemu/ar7.git] / target-mips / op_helper.c
blob1ae1dda0af0d84bfcdf1c0938f3d6a4214ed89ef
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "sysemu/kvm.h"
26
27 /*****************************************************************************/
28 /* Exceptions processing helpers */
29
30 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
31 int error_code)
32 {
33 do_raise_exception_err(env, exception, error_code, 0);
34 }
35
36 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
37 {
38 do_raise_exception(env, exception, GETPC());
39 }
40
41 void helper_raise_exception_debug(CPUMIPSState *env)
42 {
43 do_raise_exception(env, EXCP_DEBUG, 0);
44 }
45
46 static void raise_exception(CPUMIPSState *env, uint32_t exception)
47 {
48 do_raise_exception(env, exception, 0);
49 }
50
51 #if defined(CONFIG_USER_ONLY)
52 #define HELPER_LD(name, insn, type) \
53 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
54 int mem_idx, uintptr_t retaddr) \
55 { \
56 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
57 }
58 #else
59 #define HELPER_LD(name, insn, type) \
60 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
61 int mem_idx, uintptr_t retaddr) \
62 { \
63 switch (mem_idx) \
64 { \
65 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
66 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
67 default: \
68 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
69 } \
70 }
71 #endif
72 HELPER_LD(lw, ldl, int32_t)
73 #if defined(TARGET_MIPS64)
74 HELPER_LD(ld, ldq, int64_t)
75 #endif
76 #undef HELPER_LD
77
78 #if defined(CONFIG_USER_ONLY)
79 #define HELPER_ST(name, insn, type) \
80 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
81 type val, int mem_idx, uintptr_t retaddr) \
82 { \
83 cpu_##insn##_data_ra(env, addr, val, retaddr); \
84 }
85 #else
86 #define HELPER_ST(name, insn, type) \
87 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
88 type val, int mem_idx, uintptr_t retaddr) \
89 { \
90 switch (mem_idx) \
91 { \
92 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
93 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
94 default: \
95 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
96 } \
97 }
98 #endif
99 HELPER_ST(sb, stb, uint8_t)
100 HELPER_ST(sw, stl, uint32_t)
101 #if defined(TARGET_MIPS64)
102 HELPER_ST(sd, stq, uint64_t)
103 #endif
104 #undef HELPER_ST
105
106 target_ulong helper_clo (target_ulong arg1)
107 {
108 return clo32(arg1);
109 }
110
111 target_ulong helper_clz (target_ulong arg1)
112 {
113 return clz32(arg1);
114 }
115
116 #if defined(TARGET_MIPS64)
117 target_ulong helper_dclo (target_ulong arg1)
118 {
119 return clo64(arg1);
120 }
121
122 target_ulong helper_dclz (target_ulong arg1)
123 {
124 return clz64(arg1);
125 }
126 #endif /* TARGET_MIPS64 */
127
128 /* 64 bits arithmetic for 32 bits hosts */
129 static inline uint64_t get_HILO(CPUMIPSState *env)
130 {
131 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
132 }
133
134 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
135 {
136 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
137 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
138 }
139
140 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
141 {
142 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
143 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
144 return tmp;
145 }
146
147 /* Multiplication variants of the vr54xx. */
148 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
149 target_ulong arg2)
150 {
151 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
152 (int64_t)(int32_t)arg2));
153 }
154
155 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
156 target_ulong arg2)
157 {
158 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
159 (uint64_t)(uint32_t)arg2);
160 }
161
162 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
163 target_ulong arg2)
164 {
165 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
166 (int64_t)(int32_t)arg2);
167 }
168
169 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
170 target_ulong arg2)
171 {
172 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
173 (int64_t)(int32_t)arg2);
174 }
175
176 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
177 target_ulong arg2)
178 {
179 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
180 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
181 }
182
183 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
184 target_ulong arg2)
185 {
186 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
187 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
188 }
189
190 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
191 target_ulong arg2)
192 {
193 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
194 (int64_t)(int32_t)arg2);
195 }
196
197 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
198 target_ulong arg2)
199 {
200 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
201 (int64_t)(int32_t)arg2);
202 }
203
204 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
205 target_ulong arg2)
206 {
207 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
208 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
209 }
210
211 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
212 target_ulong arg2)
213 {
214 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
215 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
216 }
217
218 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
219 target_ulong arg2)
220 {
221 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
222 }
223
224 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
225 target_ulong arg2)
226 {
227 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
228 (uint64_t)(uint32_t)arg2);
229 }
230
231 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
232 target_ulong arg2)
233 {
234 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
235 (int64_t)(int32_t)arg2);
236 }
237
238 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
239 target_ulong arg2)
240 {
241 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
242 (uint64_t)(uint32_t)arg2);
243 }
244
245 static inline target_ulong bitswap(target_ulong v)
246 {
247 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
248 ((v & (target_ulong)0x5555555555555555ULL) << 1);
249 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
250 ((v & (target_ulong)0x3333333333333333ULL) << 2);
251 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
252 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
253 return v;
254 }
255
256 #ifdef TARGET_MIPS64
257 target_ulong helper_dbitswap(target_ulong rt)
258 {
259 return bitswap(rt);
260 }
261 #endif
262
263 target_ulong helper_bitswap(target_ulong rt)
264 {
265 return (int32_t)bitswap(rt);
266 }
267
268 #ifndef CONFIG_USER_ONLY
269
270 static inline hwaddr do_translate_address(CPUMIPSState *env,
271 target_ulong address,
272 int rw, uintptr_t retaddr)
273 {
274 hwaddr lladdr;
275 CPUState *cs = CPU(mips_env_get_cpu(env));
276
277 lladdr = cpu_mips_translate_address(env, address, rw);
278
279 if (lladdr == -1LL) {
280 cpu_loop_exit_restore(cs, retaddr);
281 } else {
282 return lladdr;
283 }
284 }
285
286 #define HELPER_LD_ATOMIC(name, insn, almask) \
287 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
288 { \
289 if (arg & almask) { \
290 env->CP0_BadVAddr = arg; \
291 do_raise_exception(env, EXCP_AdEL, GETPC()); \
292 } \
293 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
294 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
295 return env->llval; \
296 }
297 HELPER_LD_ATOMIC(ll, lw, 0x3)
298 #ifdef TARGET_MIPS64
299 HELPER_LD_ATOMIC(lld, ld, 0x7)
300 #endif
301 #undef HELPER_LD_ATOMIC
302
303 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
304 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
305 target_ulong arg2, int mem_idx) \
306 { \
307 target_long tmp; \
308 \
309 if (arg2 & almask) { \
310 env->CP0_BadVAddr = arg2; \
311 do_raise_exception(env, EXCP_AdES, GETPC()); \
312 } \
313 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
314 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
315 if (tmp == env->llval) { \
316 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
317 return 1; \
318 } \
319 } \
320 return 0; \
321 }
322 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
323 #ifdef TARGET_MIPS64
324 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
325 #endif
326 #undef HELPER_ST_ATOMIC
327 #endif
328
329 #ifdef TARGET_WORDS_BIGENDIAN
330 #define GET_LMASK(v) ((v) & 3)
331 #define GET_OFFSET(addr, offset) (addr + (offset))
332 #else
333 #define GET_LMASK(v) (((v) & 3) ^ 3)
334 #define GET_OFFSET(addr, offset) (addr - (offset))
335 #endif
336
337 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
338 int mem_idx)
339 {
340 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
341
342 if (GET_LMASK(arg2) <= 2) {
343 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
344 GETPC());
345 }
346
347 if (GET_LMASK(arg2) <= 1) {
348 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
349 GETPC());
350 }
351
352 if (GET_LMASK(arg2) == 0) {
353 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
354 GETPC());
355 }
356 }
357
358 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
359 int mem_idx)
360 {
361 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
362
363 if (GET_LMASK(arg2) >= 1) {
364 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
365 GETPC());
366 }
367
368 if (GET_LMASK(arg2) >= 2) {
369 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
370 GETPC());
371 }
372
373 if (GET_LMASK(arg2) == 3) {
374 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
375 GETPC());
376 }
377 }
378
379 #if defined(TARGET_MIPS64)
380 /* "half" load and stores. We must do the memory access inline,
381 or fault handling won't work. */
382
383 #ifdef TARGET_WORDS_BIGENDIAN
384 #define GET_LMASK64(v) ((v) & 7)
385 #else
386 #define GET_LMASK64(v) (((v) & 7) ^ 7)
387 #endif
388
389 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
390 int mem_idx)
391 {
392 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
393
394 if (GET_LMASK64(arg2) <= 6) {
395 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
396 GETPC());
397 }
398
399 if (GET_LMASK64(arg2) <= 5) {
400 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
401 GETPC());
402 }
403
404 if (GET_LMASK64(arg2) <= 4) {
405 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
406 GETPC());
407 }
408
409 if (GET_LMASK64(arg2) <= 3) {
410 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
411 GETPC());
412 }
413
414 if (GET_LMASK64(arg2) <= 2) {
415 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
416 GETPC());
417 }
418
419 if (GET_LMASK64(arg2) <= 1) {
420 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
421 GETPC());
422 }
423
424 if (GET_LMASK64(arg2) <= 0) {
425 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
426 GETPC());
427 }
428 }
429
430 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
431 int mem_idx)
432 {
433 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
434
435 if (GET_LMASK64(arg2) >= 1) {
436 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
437 GETPC());
438 }
439
440 if (GET_LMASK64(arg2) >= 2) {
441 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
442 GETPC());
443 }
444
445 if (GET_LMASK64(arg2) >= 3) {
446 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
447 GETPC());
448 }
449
450 if (GET_LMASK64(arg2) >= 4) {
451 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
452 GETPC());
453 }
454
455 if (GET_LMASK64(arg2) >= 5) {
456 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
457 GETPC());
458 }
459
460 if (GET_LMASK64(arg2) >= 6) {
461 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
462 GETPC());
463 }
464
465 if (GET_LMASK64(arg2) == 7) {
466 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
467 GETPC());
468 }
469 }
470 #endif /* TARGET_MIPS64 */
471
472 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
473
474 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
475 uint32_t mem_idx)
476 {
477 target_ulong base_reglist = reglist & 0xf;
478 target_ulong do_r31 = reglist & 0x10;
479
480 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
481 target_ulong i;
482
483 for (i = 0; i < base_reglist; i++) {
484 env->active_tc.gpr[multiple_regs[i]] =
485 (target_long)do_lw(env, addr, mem_idx, GETPC());
486 addr += 4;
487 }
488 }
489
490 if (do_r31) {
491 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
492 GETPC());
493 }
494 }
495
496 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
497 uint32_t mem_idx)
498 {
499 target_ulong base_reglist = reglist & 0xf;
500 target_ulong do_r31 = reglist & 0x10;
501
502 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
503 target_ulong i;
504
505 for (i = 0; i < base_reglist; i++) {
506 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
507 GETPC());
508 addr += 4;
509 }
510 }
511
512 if (do_r31) {
513 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
514 }
515 }
516
517 #if defined(TARGET_MIPS64)
518 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
519 uint32_t mem_idx)
520 {
521 target_ulong base_reglist = reglist & 0xf;
522 target_ulong do_r31 = reglist & 0x10;
523
524 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
525 target_ulong i;
526
527 for (i = 0; i < base_reglist; i++) {
528 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
529 GETPC());
530 addr += 8;
531 }
532 }
533
534 if (do_r31) {
535 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
536 }
537 }
538
539 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
540 uint32_t mem_idx)
541 {
542 target_ulong base_reglist = reglist & 0xf;
543 target_ulong do_r31 = reglist & 0x10;
544
545 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
546 target_ulong i;
547
548 for (i = 0; i < base_reglist; i++) {
549 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
550 GETPC());
551 addr += 8;
552 }
553 }
554
555 if (do_r31) {
556 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
557 }
558 }
559 #endif
560
561 #ifndef CONFIG_USER_ONLY
562 /* SMP helpers. */
563 static bool mips_vpe_is_wfi(MIPSCPU *c)
564 {
565 CPUState *cpu = CPU(c);
566 CPUMIPSState *env = &c->env;
567
568 /* If the VPE is halted but otherwise active, it means it's waiting for
569 an interrupt. */
570 return cpu->halted && mips_vpe_active(env);
571 }
572
573 static bool mips_vp_is_wfi(MIPSCPU *c)
574 {
575 CPUState *cpu = CPU(c);
576 CPUMIPSState *env = &c->env;
577
578 return cpu->halted && mips_vp_active(env);
579 }
580
581 static inline void mips_vpe_wake(MIPSCPU *c)
582 {
583 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
584 because there might be other conditions that state that c should
585 be sleeping. */
586 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
587 }
588
589 static inline void mips_vpe_sleep(MIPSCPU *cpu)
590 {
591 CPUState *cs = CPU(cpu);
592
593 /* The VPE was shut off, really go to bed.
594 Reset any old _WAKE requests. */
595 cs->halted = 1;
596 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
597 }
598
599 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
600 {
601 CPUMIPSState *c = &cpu->env;
602
603 /* FIXME: TC reschedule. */
604 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
605 mips_vpe_wake(cpu);
606 }
607 }
608
609 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
610 {
611 CPUMIPSState *c = &cpu->env;
612
613 /* FIXME: TC reschedule. */
614 if (!mips_vpe_active(c)) {
615 mips_vpe_sleep(cpu);
616 }
617 }
618
619 /**
620 * mips_cpu_map_tc:
621 * @env: CPU from which mapping is performed.
622 * @tc: Should point to an int with the value of the global TC index.
623 *
624 * This function will transform @tc into a local index within the
625 * returned #CPUMIPSState.
626 */
627 /* FIXME: This code assumes that all VPEs have the same number of TCs,
628 which depends on runtime setup. Can probably be fixed by
629 walking the list of CPUMIPSStates. */
630 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
631 {
632 MIPSCPU *cpu;
633 CPUState *cs;
634 CPUState *other_cs;
635 int vpe_idx;
636 int tc_idx = *tc;
637
638 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
639 /* Not allowed to address other CPUs. */
640 *tc = env->current_tc;
641 return env;
642 }
643
644 cs = CPU(mips_env_get_cpu(env));
645 vpe_idx = tc_idx / cs->nr_threads;
646 *tc = tc_idx % cs->nr_threads;
647 other_cs = qemu_get_cpu(vpe_idx);
648 if (other_cs == NULL) {
649 return env;
650 }
651 cpu = MIPS_CPU(other_cs);
652 return &cpu->env;
653 }
654
655 /* The per VPE CP0_Status register shares some fields with the per TC
656 CP0_TCStatus registers. These fields are wired to the same registers,
657 so changes to either of them should be reflected on both registers.
658
659 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
660
661 These helper call synchronizes the regs for a given cpu. */
662
663 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
664 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
665 int tc); */
666
667 /* Called for updates to CP0_TCStatus. */
668 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
669 target_ulong v)
670 {
671 uint32_t status;
672 uint32_t tcu, tmx, tasid, tksu;
673 uint32_t mask = ((1U << CP0St_CU3)
674 | (1 << CP0St_CU2)
675 | (1 << CP0St_CU1)
676 | (1 << CP0St_CU0)
677 | (1 << CP0St_MX)
678 | (3 << CP0St_KSU));
679
680 tcu = (v >> CP0TCSt_TCU0) & 0xf;
681 tmx = (v >> CP0TCSt_TMX) & 0x1;
682 tasid = v & 0xff;
683 tksu = (v >> CP0TCSt_TKSU) & 0x3;
684
685 status = tcu << CP0St_CU0;
686 status |= tmx << CP0St_MX;
687 status |= tksu << CP0St_KSU;
688
689 cpu->CP0_Status &= ~mask;
690 cpu->CP0_Status |= status;
691
692 /* Sync the TASID with EntryHi. */
693 cpu->CP0_EntryHi &= ~0xff;
694 cpu->CP0_EntryHi |= tasid;
695
696 compute_hflags(cpu);
697 }
698
699 /* Called for updates to CP0_EntryHi. */
700 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
701 {
702 int32_t *tcst;
703 uint32_t asid, v = cpu->CP0_EntryHi;
704
705 asid = v & 0xff;
706
707 if (tc == cpu->current_tc) {
708 tcst = &cpu->active_tc.CP0_TCStatus;
709 } else {
710 tcst = &cpu->tcs[tc].CP0_TCStatus;
711 }
712
713 *tcst &= ~0xff;
714 *tcst |= asid;
715 }
716
717 /* CP0 helpers */
718 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
719 {
720 return env->mvp->CP0_MVPControl;
721 }
722
723 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
724 {
725 return env->mvp->CP0_MVPConf0;
726 }
727
728 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
729 {
730 return env->mvp->CP0_MVPConf1;
731 }
732
733 target_ulong helper_mfc0_random(CPUMIPSState *env)
734 {
735 return (int32_t)cpu_mips_get_random(env);
736 }
737
738 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
739 {
740 return env->active_tc.CP0_TCStatus;
741 }
742
743 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
744 {
745 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
746 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
747
748 if (other_tc == other->current_tc)
749 return other->active_tc.CP0_TCStatus;
750 else
751 return other->tcs[other_tc].CP0_TCStatus;
752 }
753
754 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
755 {
756 return env->active_tc.CP0_TCBind;
757 }
758
759 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
760 {
761 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
762 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
763
764 if (other_tc == other->current_tc)
765 return other->active_tc.CP0_TCBind;
766 else
767 return other->tcs[other_tc].CP0_TCBind;
768 }
769
770 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
771 {
772 return env->active_tc.PC;
773 }
774
775 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
776 {
777 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
778 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
779
780 if (other_tc == other->current_tc)
781 return other->active_tc.PC;
782 else
783 return other->tcs[other_tc].PC;
784 }
785
786 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
787 {
788 return env->active_tc.CP0_TCHalt;
789 }
790
791 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
792 {
793 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
794 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
795
796 if (other_tc == other->current_tc)
797 return other->active_tc.CP0_TCHalt;
798 else
799 return other->tcs[other_tc].CP0_TCHalt;
800 }
801
802 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
803 {
804 return env->active_tc.CP0_TCContext;
805 }
806
807 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
808 {
809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
810 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
811
812 if (other_tc == other->current_tc)
813 return other->active_tc.CP0_TCContext;
814 else
815 return other->tcs[other_tc].CP0_TCContext;
816 }
817
818 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
819 {
820 return env->active_tc.CP0_TCSchedule;
821 }
822
823 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
824 {
825 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
826 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
827
828 if (other_tc == other->current_tc)
829 return other->active_tc.CP0_TCSchedule;
830 else
831 return other->tcs[other_tc].CP0_TCSchedule;
832 }
833
834 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
835 {
836 return env->active_tc.CP0_TCScheFBack;
837 }
838
839 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
840 {
841 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
842 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
843
844 if (other_tc == other->current_tc)
845 return other->active_tc.CP0_TCScheFBack;
846 else
847 return other->tcs[other_tc].CP0_TCScheFBack;
848 }
849
850 target_ulong helper_mfc0_count(CPUMIPSState *env)
851 {
852 return (int32_t)cpu_mips_get_count(env);
853 }
854
855 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
856 {
857 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
858 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
859
860 return other->CP0_EntryHi;
861 }
862
863 target_ulong helper_mftc0_cause(CPUMIPSState *env)
864 {
865 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
866 int32_t tccause;
867 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
868
869 if (other_tc == other->current_tc) {
870 tccause = other->CP0_Cause;
871 } else {
872 tccause = other->CP0_Cause;
873 }
874
875 return tccause;
876 }
877
878 target_ulong helper_mftc0_status(CPUMIPSState *env)
879 {
880 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
881 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
882
883 return other->CP0_Status;
884 }
885
886 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
887 {
888 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
889 }
890
891 target_ulong helper_mfc0_maar(CPUMIPSState *env)
892 {
893 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
894 }
895
896 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
897 {
898 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
899 }
900
901 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
902 {
903 return (int32_t)env->CP0_WatchLo[sel];
904 }
905
906 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
907 {
908 return env->CP0_WatchHi[sel];
909 }
910
911 target_ulong helper_mfc0_debug(CPUMIPSState *env)
912 {
913 target_ulong t0 = env->CP0_Debug;
914 if (env->hflags & MIPS_HFLAG_DM)
915 t0 |= 1 << CP0DB_DM;
916
917 return t0;
918 }
919
920 target_ulong helper_mftc0_debug(CPUMIPSState *env)
921 {
922 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
923 int32_t tcstatus;
924 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
925
926 if (other_tc == other->current_tc)
927 tcstatus = other->active_tc.CP0_Debug_tcstatus;
928 else
929 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
930
931 /* XXX: Might be wrong, check with EJTAG spec. */
932 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
933 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
934 }
935
936 #if defined(TARGET_MIPS64)
937 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
938 {
939 return env->active_tc.PC;
940 }
941
942 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
943 {
944 return env->active_tc.CP0_TCHalt;
945 }
946
947 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
948 {
949 return env->active_tc.CP0_TCContext;
950 }
951
952 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
953 {
954 return env->active_tc.CP0_TCSchedule;
955 }
956
957 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
958 {
959 return env->active_tc.CP0_TCScheFBack;
960 }
961
962 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
963 {
964 return env->lladdr >> env->CP0_LLAddr_shift;
965 }
966
967 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
968 {
969 return env->CP0_MAAR[env->CP0_MAARI];
970 }
971
972 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
973 {
974 return env->CP0_WatchLo[sel];
975 }
976 #endif /* TARGET_MIPS64 */
977
978 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
979 {
980 uint32_t index_p = env->CP0_Index & 0x80000000;
981 uint32_t tlb_index = arg1 & 0x7fffffff;
982 if (tlb_index < env->tlb->nb_tlb) {
983 if (env->insn_flags & ISA_MIPS32R6) {
984 index_p |= arg1 & 0x80000000;
985 }
986 env->CP0_Index = index_p | tlb_index;
987 }
988 }
989
990 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
991 {
992 uint32_t mask = 0;
993 uint32_t newval;
994
995 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
996 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
997 (1 << CP0MVPCo_EVP);
998 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
999 mask |= (1 << CP0MVPCo_STLB);
1000 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1001
1002 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1003
1004 env->mvp->CP0_MVPControl = newval;
1005 }
1006
1007 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1008 {
1009 uint32_t mask;
1010 uint32_t newval;
1011
1012 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1013 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1014 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1015
1016 /* Yield scheduler intercept not implemented. */
1017 /* Gating storage scheduler intercept not implemented. */
1018
1019 // TODO: Enable/disable TCs.
1020
1021 env->CP0_VPEControl = newval;
1022 }
1023
1024 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1025 {
1026 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1027 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1028 uint32_t mask;
1029 uint32_t newval;
1030
1031 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1032 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1033 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1034
1035 /* TODO: Enable/disable TCs. */
1036
1037 other->CP0_VPEControl = newval;
1038 }
1039
1040 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1041 {
1042 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1043 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1044 /* FIXME: Mask away return zero on read bits. */
1045 return other->CP0_VPEControl;
1046 }
1047
1048 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1049 {
1050 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1051 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1052
1053 return other->CP0_VPEConf0;
1054 }
1055
1056 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1057 {
1058 uint32_t mask = 0;
1059 uint32_t newval;
1060
1061 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1062 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1063 mask |= (0xff << CP0VPEC0_XTC);
1064 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1065 }
1066 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1067
1068 // TODO: TC exclusive handling due to ERL/EXL.
1069
1070 env->CP0_VPEConf0 = newval;
1071 }
1072
1073 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1074 {
1075 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1076 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1077 uint32_t mask = 0;
1078 uint32_t newval;
1079
1080 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1081 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1082
1083 /* TODO: TC exclusive handling due to ERL/EXL. */
1084 other->CP0_VPEConf0 = newval;
1085 }
1086
1087 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1088 {
1089 uint32_t mask = 0;
1090 uint32_t newval;
1091
1092 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1093 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1094 (0xff << CP0VPEC1_NCP1);
1095 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1096
1097 /* UDI not implemented. */
1098 /* CP2 not implemented. */
1099
1100 // TODO: Handle FPU (CP1) binding.
1101
1102 env->CP0_VPEConf1 = newval;
1103 }
1104
1105 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1106 {
1107 /* Yield qualifier inputs not implemented. */
1108 env->CP0_YQMask = 0x00000000;
1109 }
1110
1111 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1112 {
1113 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1114 }
1115
1116 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1117
1118 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1119 {
1120 /* 1k pages not implemented */
1121 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1122 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1123 | (rxi << (CP0EnLo_XI - 30));
1124 }
1125
1126 #if defined(TARGET_MIPS64)
1127 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1128
1129 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1130 {
1131 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1132 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1133 }
1134 #endif
1135
1136 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1137 {
1138 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1139 uint32_t newval;
1140
1141 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1142
1143 env->active_tc.CP0_TCStatus = newval;
1144 sync_c0_tcstatus(env, env->current_tc, newval);
1145 }
1146
1147 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1148 {
1149 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1150 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1151
1152 if (other_tc == other->current_tc)
1153 other->active_tc.CP0_TCStatus = arg1;
1154 else
1155 other->tcs[other_tc].CP0_TCStatus = arg1;
1156 sync_c0_tcstatus(other, other_tc, arg1);
1157 }
1158
1159 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1160 {
1161 uint32_t mask = (1 << CP0TCBd_TBE);
1162 uint32_t newval;
1163
1164 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1165 mask |= (1 << CP0TCBd_CurVPE);
1166 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1167 env->active_tc.CP0_TCBind = newval;
1168 }
1169
1170 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1171 {
1172 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1173 uint32_t mask = (1 << CP0TCBd_TBE);
1174 uint32_t newval;
1175 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1176
1177 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1178 mask |= (1 << CP0TCBd_CurVPE);
1179 if (other_tc == other->current_tc) {
1180 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1181 other->active_tc.CP0_TCBind = newval;
1182 } else {
1183 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1184 other->tcs[other_tc].CP0_TCBind = newval;
1185 }
1186 }
1187
1188 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1189 {
1190 env->active_tc.PC = arg1;
1191 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1192 env->lladdr = 0ULL;
1193 /* MIPS16 not implemented. */
1194 }
1195
1196 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1197 {
1198 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1199 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1200
1201 if (other_tc == other->current_tc) {
1202 other->active_tc.PC = arg1;
1203 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1204 other->lladdr = 0ULL;
1205 /* MIPS16 not implemented. */
1206 } else {
1207 other->tcs[other_tc].PC = arg1;
1208 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1209 other->lladdr = 0ULL;
1210 /* MIPS16 not implemented. */
1211 }
1212 }
1213
1214 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1215 {
1216 MIPSCPU *cpu = mips_env_get_cpu(env);
1217
1218 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1219
1220 // TODO: Halt TC / Restart (if allocated+active) TC.
1221 if (env->active_tc.CP0_TCHalt & 1) {
1222 mips_tc_sleep(cpu, env->current_tc);
1223 } else {
1224 mips_tc_wake(cpu, env->current_tc);
1225 }
1226 }
1227
1228 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1229 {
1230 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1231 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1232 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1233
1234 // TODO: Halt TC / Restart (if allocated+active) TC.
1235
1236 if (other_tc == other->current_tc)
1237 other->active_tc.CP0_TCHalt = arg1;
1238 else
1239 other->tcs[other_tc].CP0_TCHalt = arg1;
1240
1241 if (arg1 & 1) {
1242 mips_tc_sleep(other_cpu, other_tc);
1243 } else {
1244 mips_tc_wake(other_cpu, other_tc);
1245 }
1246 }
1247
1248 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1249 {
1250 env->active_tc.CP0_TCContext = arg1;
1251 }
1252
1253 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1254 {
1255 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1256 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1257
1258 if (other_tc == other->current_tc)
1259 other->active_tc.CP0_TCContext = arg1;
1260 else
1261 other->tcs[other_tc].CP0_TCContext = arg1;
1262 }
1263
1264 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1265 {
1266 env->active_tc.CP0_TCSchedule = arg1;
1267 }
1268
1269 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1270 {
1271 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1272 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1273
1274 if (other_tc == other->current_tc)
1275 other->active_tc.CP0_TCSchedule = arg1;
1276 else
1277 other->tcs[other_tc].CP0_TCSchedule = arg1;
1278 }
1279
1280 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1281 {
1282 env->active_tc.CP0_TCScheFBack = arg1;
1283 }
1284
1285 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1286 {
1287 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1288 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1289
1290 if (other_tc == other->current_tc)
1291 other->active_tc.CP0_TCScheFBack = arg1;
1292 else
1293 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1294 }
1295
1296 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1297 {
1298 /* 1k pages not implemented */
1299 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1300 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1301 | (rxi << (CP0EnLo_XI - 30));
1302 }
1303
1304 #if defined(TARGET_MIPS64)
1305 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1306 {
1307 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1308 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1309 }
1310 #endif
1311
1312 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1313 {
1314 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1315 }
1316
1317 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1318 {
1319 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1320 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1321 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1322 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1323 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1324 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1325 }
1326 }
1327
1328 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1329 {
1330 /* SmartMIPS not implemented */
1331 /* 1k pages not implemented */
1332 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1333 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1334 compute_hflags(env);
1335 restore_pamask(env);
1336 }
1337
1338 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1339 {
1340 if (env->insn_flags & ISA_MIPS32R6) {
1341 if (arg1 < env->tlb->nb_tlb) {
1342 env->CP0_Wired = arg1;
1343 }
1344 } else {
1345 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1346 }
1347 }
1348
1349 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1350 {
1351 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1352 }
1353
1354 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1355 {
1356 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1357 }
1358
1359 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1360 {
1361 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1362 }
1363
1364 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1365 {
1366 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1367 }
1368
1369 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1370 {
1371 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1372 }
1373
1374 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1375 {
1376 uint32_t mask = 0x0000000F;
1377
1378 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1379 (env->insn_flags & ISA_MIPS32R6)) {
1380 mask |= (1 << 4);
1381 }
1382 if (env->insn_flags & ISA_MIPS32R6) {
1383 mask |= (1 << 5);
1384 }
1385 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1386 mask |= (1 << 29);
1387
1388 if (arg1 & (1 << 29)) {
1389 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1390 } else {
1391 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1392 }
1393 }
1394
1395 env->CP0_HWREna = arg1 & mask;
1396 }
1397
1398 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1399 {
1400 cpu_mips_store_count(env, arg1);
1401 }
1402
1403 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1404 {
1405 target_ulong old, val, mask;
1406 mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1407 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1408 mask |= 1 << CP0EnHi_EHINV;
1409 }
1410
1411 /* 1k pages not implemented */
1412 #if defined(TARGET_MIPS64)
1413 if (env->insn_flags & ISA_MIPS32R6) {
1414 int entryhi_r = extract64(arg1, 62, 2);
1415 int config0_at = extract32(env->CP0_Config0, 13, 2);
1416 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1417 if ((entryhi_r == 2) ||
1418 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1419 /* skip EntryHi.R field if new value is reserved */
1420 mask &= ~(0x3ull << 62);
1421 }
1422 }
1423 mask &= env->SEGMask;
1424 #endif
1425 old = env->CP0_EntryHi;
1426 val = (arg1 & mask) | (old & ~mask);
1427 env->CP0_EntryHi = val;
1428 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1429 sync_c0_entryhi(env, env->current_tc);
1430 }
1431 /* If the ASID changes, flush qemu's TLB. */
1432 if ((old & 0xFF) != (val & 0xFF))
1433 cpu_mips_tlb_flush(env, 1);
1434 }
1435
1436 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1437 {
1438 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1439 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1440
1441 other->CP0_EntryHi = arg1;
1442 sync_c0_entryhi(other, other_tc);
1443 }
1444
1445 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1446 {
1447 cpu_mips_store_compare(env, arg1);
1448 }
1449
1450 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1451 {
1452 MIPSCPU *cpu = mips_env_get_cpu(env);
1453 uint32_t val, old;
1454
1455 old = env->CP0_Status;
1456 cpu_mips_store_status(env, arg1);
1457 val = env->CP0_Status;
1458
1459 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1460 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1461 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1462 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1463 env->CP0_Cause);
1464 switch (env->hflags & MIPS_HFLAG_KSU) {
1465 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1466 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1467 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1468 default:
1469 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1470 break;
1471 }
1472 }
1473 }
1474
1475 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1476 {
1477 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1478 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1479 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1480
1481 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1482 sync_c0_status(env, other, other_tc);
1483 }
1484
1485 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1486 {
1487 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1488 }
1489
1490 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1491 {
1492 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1493 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1494 }
1495
1496 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1497 {
1498 cpu_mips_store_cause(env, arg1);
1499 }
1500
1501 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1502 {
1503 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1504 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1505
1506 cpu_mips_store_cause(other, arg1);
1507 }
1508
1509 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1510 {
1511 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1512 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1513
1514 return other->CP0_EPC;
1515 }
1516
1517 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1518 {
1519 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1520 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1521
1522 return other->CP0_EBase;
1523 }
1524
1525 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1526 {
1527 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1528 }
1529
1530 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1531 {
1532 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1533 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1534 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1535 }
1536
1537 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1538 {
1539 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1540 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1541
1542 switch (idx) {
1543 case 0: return other->CP0_Config0;
1544 case 1: return other->CP0_Config1;
1545 case 2: return other->CP0_Config2;
1546 case 3: return other->CP0_Config3;
1547 /* 4 and 5 are reserved. */
1548 case 6: return other->CP0_Config6;
1549 case 7: return other->CP0_Config7;
1550 default:
1551 break;
1552 }
1553 return 0;
1554 }
1555
1556 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1557 {
1558 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1559 }
1560
1561 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1562 {
1563 /* tertiary/secondary caches not implemented */
1564 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1565 }
1566
1567 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1568 {
1569 if (env->insn_flags & ASE_MICROMIPS) {
1570 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1571 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1572 }
1573 }
1574
1575 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1576 {
1577 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1578 (arg1 & env->CP0_Config4_rw_bitmask);
1579 }
1580
1581 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1582 {
1583 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1584 (arg1 & env->CP0_Config5_rw_bitmask);
1585 compute_hflags(env);
1586 }
1587
1588 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1589 {
1590 target_long mask = env->CP0_LLAddr_rw_bitmask;
1591 arg1 = arg1 << env->CP0_LLAddr_shift;
1592 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1593 }
1594
1595 #define MTC0_MAAR_MASK(env) \
1596 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1597
1598 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1599 {
1600 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1601 }
1602
1603 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1604 {
1605 env->CP0_MAAR[env->CP0_MAARI] =
1606 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1607 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1608 }
1609
1610 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1611 {
1612 int index = arg1 & 0x3f;
1613 if (index == 0x3f) {
1614 /* Software may write all ones to INDEX to determine the
1615 maximum value supported. */
1616 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1617 } else if (index < MIPS_MAAR_MAX) {
1618 env->CP0_MAARI = index;
1619 }
1620 /* Other than the all ones, if the
1621 value written is not supported, then INDEX is unchanged
1622 from its previous value. */
1623 }
1624
1625 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1626 {
1627 /* Watch exceptions for instructions, data loads, data stores
1628 not implemented. */
1629 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1630 }
1631
1632 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1633 {
1634 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1635 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1636 }
1637
1638 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1639 {
1640 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1641 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1642 }
1643
1644 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1645 {
1646 env->CP0_Framemask = arg1; /* XXX */
1647 }
1648
1649 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1650 {
1651 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1652 if (arg1 & (1 << CP0DB_DM))
1653 env->hflags |= MIPS_HFLAG_DM;
1654 else
1655 env->hflags &= ~MIPS_HFLAG_DM;
1656 }
1657
1658 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1659 {
1660 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1661 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1662 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1663
1664 /* XXX: Might be wrong, check with EJTAG spec. */
1665 if (other_tc == other->current_tc)
1666 other->active_tc.CP0_Debug_tcstatus = val;
1667 else
1668 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1669 other->CP0_Debug = (other->CP0_Debug &
1670 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1671 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1672 }
1673
1674 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1675 {
1676 env->CP0_Performance0 = arg1 & 0x000007ff;
1677 }
1678
1679 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1680 {
1681 int32_t wst = arg1 & (1 << CP0EC_WST);
1682 int32_t spr = arg1 & (1 << CP0EC_SPR);
1683 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1684
1685 env->CP0_ErrCtl = wst | spr | itc;
1686
1687 if (itc && !wst && !spr) {
1688 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1689 } else {
1690 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1691 }
1692 }
1693
1694 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1695 {
1696 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1697 /* If CACHE instruction is configured for ITC tags then make all
1698 CP0.TagLo bits writable. The actual write to ITC Configuration
1699 Tag will take care of the read-only bits. */
1700 env->CP0_TagLo = arg1;
1701 } else {
1702 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1703 }
1704 }
1705
1706 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1707 {
1708 env->CP0_DataLo = arg1; /* XXX */
1709 }
1710
1711 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1712 {
1713 env->CP0_TagHi = arg1; /* XXX */
1714 }
1715
1716 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1717 {
1718 env->CP0_DataHi = arg1; /* XXX */
1719 }
1720
1721 /* MIPS MT functions */
1722 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1723 {
1724 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1725 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1726
1727 if (other_tc == other->current_tc)
1728 return other->active_tc.gpr[sel];
1729 else
1730 return other->tcs[other_tc].gpr[sel];
1731 }
1732
1733 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1734 {
1735 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1736 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1737
1738 if (other_tc == other->current_tc)
1739 return other->active_tc.LO[sel];
1740 else
1741 return other->tcs[other_tc].LO[sel];
1742 }
1743
1744 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1745 {
1746 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1747 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1748
1749 if (other_tc == other->current_tc)
1750 return other->active_tc.HI[sel];
1751 else
1752 return other->tcs[other_tc].HI[sel];
1753 }
1754
1755 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1756 {
1757 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1758 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1759
1760 if (other_tc == other->current_tc)
1761 return other->active_tc.ACX[sel];
1762 else
1763 return other->tcs[other_tc].ACX[sel];
1764 }
1765
1766 target_ulong helper_mftdsp(CPUMIPSState *env)
1767 {
1768 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1769 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1770
1771 if (other_tc == other->current_tc)
1772 return other->active_tc.DSPControl;
1773 else
1774 return other->tcs[other_tc].DSPControl;
1775 }
1776
1777 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1778 {
1779 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1780 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1781
1782 if (other_tc == other->current_tc)
1783 other->active_tc.gpr[sel] = arg1;
1784 else
1785 other->tcs[other_tc].gpr[sel] = arg1;
1786 }
1787
1788 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1789 {
1790 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1791 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1792
1793 if (other_tc == other->current_tc)
1794 other->active_tc.LO[sel] = arg1;
1795 else
1796 other->tcs[other_tc].LO[sel] = arg1;
1797 }
1798
1799 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1800 {
1801 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1802 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1803
1804 if (other_tc == other->current_tc)
1805 other->active_tc.HI[sel] = arg1;
1806 else
1807 other->tcs[other_tc].HI[sel] = arg1;
1808 }
1809
1810 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1811 {
1812 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1813 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1814
1815 if (other_tc == other->current_tc)
1816 other->active_tc.ACX[sel] = arg1;
1817 else
1818 other->tcs[other_tc].ACX[sel] = arg1;
1819 }
1820
1821 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1822 {
1823 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1824 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1825
1826 if (other_tc == other->current_tc)
1827 other->active_tc.DSPControl = arg1;
1828 else
1829 other->tcs[other_tc].DSPControl = arg1;
1830 }
1831
1832 /* MIPS MT functions */
1833 target_ulong helper_dmt(void)
1834 {
1835 // TODO
1836 return 0;
1837 }
1838
1839 target_ulong helper_emt(void)
1840 {
1841 // TODO
1842 return 0;
1843 }
1844
1845 target_ulong helper_dvpe(CPUMIPSState *env)
1846 {
1847 CPUState *other_cs = first_cpu;
1848 target_ulong prev = env->mvp->CP0_MVPControl;
1849
1850 CPU_FOREACH(other_cs) {
1851 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1852 /* Turn off all VPEs except the one executing the dvpe. */
1853 if (&other_cpu->env != env) {
1854 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1855 mips_vpe_sleep(other_cpu);
1856 }
1857 }
1858 return prev;
1859 }
1860
1861 target_ulong helper_evpe(CPUMIPSState *env)
1862 {
1863 CPUState *other_cs = first_cpu;
1864 target_ulong prev = env->mvp->CP0_MVPControl;
1865
1866 CPU_FOREACH(other_cs) {
1867 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1868
1869 if (&other_cpu->env != env
1870 /* If the VPE is WFI, don't disturb its sleep. */
1871 && !mips_vpe_is_wfi(other_cpu)) {
1872 /* Enable the VPE. */
1873 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1874 mips_vpe_wake(other_cpu); /* And wake it up. */
1875 }
1876 }
1877 return prev;
1878 }
1879 #endif /* !CONFIG_USER_ONLY */
1880
1881 void helper_fork(target_ulong arg1, target_ulong arg2)
1882 {
1883 // arg1 = rt, arg2 = rs
1884 // TODO: store to TC register
1885 }
1886
1887 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1888 {
1889 target_long arg1 = arg;
1890
1891 if (arg1 < 0) {
1892 /* No scheduling policy implemented. */
1893 if (arg1 != -2) {
1894 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1895 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1896 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1897 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1898 do_raise_exception(env, EXCP_THREAD, GETPC());
1899 }
1900 }
1901 } else if (arg1 == 0) {
1902 if (0 /* TODO: TC underflow */) {
1903 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1904 do_raise_exception(env, EXCP_THREAD, GETPC());
1905 } else {
1906 // TODO: Deallocate TC
1907 }
1908 } else if (arg1 > 0) {
1909 /* Yield qualifier inputs not implemented. */
1910 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1911 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1912 do_raise_exception(env, EXCP_THREAD, GETPC());
1913 }
1914 return env->CP0_YQMask;
1915 }
1916
1917 /* R6 Multi-threading */
1918 #ifndef CONFIG_USER_ONLY
1919 target_ulong helper_dvp(CPUMIPSState *env)
1920 {
1921 CPUState *other_cs = first_cpu;
1922 target_ulong prev = env->CP0_VPControl;
1923
1924 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1925 CPU_FOREACH(other_cs) {
1926 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1927 /* Turn off all VPs except the one executing the dvp. */
1928 if (&other_cpu->env != env) {
1929 mips_vpe_sleep(other_cpu);
1930 }
1931 }
1932 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1933 }
1934 return prev;
1935 }
1936
1937 target_ulong helper_evp(CPUMIPSState *env)
1938 {
1939 CPUState *other_cs = first_cpu;
1940 target_ulong prev = env->CP0_VPControl;
1941
1942 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1943 CPU_FOREACH(other_cs) {
1944 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1945 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1946 /* If the VP is WFI, don't disturb its sleep.
1947 * Otherwise, wake it up. */
1948 mips_vpe_wake(other_cpu);
1949 }
1950 }
1951 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1952 }
1953 return prev;
1954 }
1955 #endif /* !CONFIG_USER_ONLY */
1956
1957 #ifndef CONFIG_USER_ONLY
1958 /* TLB management */
1959 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1960 {
1961 /* Discard entries from env->tlb[first] onwards. */
1962 while (env->tlb->tlb_in_use > first) {
1963 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1964 }
1965 }
1966
1967 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1968 {
1969 #if defined(TARGET_MIPS64)
1970 return extract64(entrylo, 6, 54);
1971 #else
1972 return extract64(entrylo, 6, 24) | /* PFN */
1973 (extract64(entrylo, 32, 32) << 24); /* PFNX */
1974 #endif
1975 }
1976
1977 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1978 {
1979 r4k_tlb_t *tlb;
1980
1981 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1982 tlb = &env->tlb->mmu.r4k.tlb[idx];
1983 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1984 tlb->EHINV = 1;
1985 return;
1986 }
1987 tlb->EHINV = 0;
1988 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1989 #if defined(TARGET_MIPS64)
1990 tlb->VPN &= env->SEGMask;
1991 #endif
1992 tlb->ASID = env->CP0_EntryHi & 0xFF;
1993 tlb->PageMask = env->CP0_PageMask;
1994 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1995 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1996 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1997 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1998 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1999 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2000 tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
2001 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2002 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2003 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2004 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2005 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2006 tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
2007 }
2008
2009 void r4k_helper_tlbinv(CPUMIPSState *env)
2010 {
2011 int idx;
2012 r4k_tlb_t *tlb;
2013 uint8_t ASID = env->CP0_EntryHi & 0xFF;
2014
2015 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2016 tlb = &env->tlb->mmu.r4k.tlb[idx];
2017 if (!tlb->G && tlb->ASID == ASID) {
2018 tlb->EHINV = 1;
2019 }
2020 }
2021 cpu_mips_tlb_flush(env, 1);
2022 }
2023
2024 void r4k_helper_tlbinvf(CPUMIPSState *env)
2025 {
2026 int idx;
2027
2028 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2029 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2030 }
2031 cpu_mips_tlb_flush(env, 1);
2032 }
2033
2034 void r4k_helper_tlbwi(CPUMIPSState *env)
2035 {
2036 r4k_tlb_t *tlb;
2037 int idx;
2038 target_ulong VPN;
2039 uint8_t ASID;
2040 bool G, V0, D0, V1, D1;
2041
2042 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2043 tlb = &env->tlb->mmu.r4k.tlb[idx];
2044 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2045 #if defined(TARGET_MIPS64)
2046 VPN &= env->SEGMask;
2047 #endif
2048 ASID = env->CP0_EntryHi & 0xff;
2049 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2050 V0 = (env->CP0_EntryLo0 & 2) != 0;
2051 D0 = (env->CP0_EntryLo0 & 4) != 0;
2052 V1 = (env->CP0_EntryLo1 & 2) != 0;
2053 D1 = (env->CP0_EntryLo1 & 4) != 0;
2054
2055 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2056 permissions on the current entry. */
2057 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2058 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2059 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
2060 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2061 }
2062
2063 r4k_invalidate_tlb(env, idx, 0);
2064 r4k_fill_tlb(env, idx);
2065 }
2066
2067 void r4k_helper_tlbwr(CPUMIPSState *env)
2068 {
2069 int r = cpu_mips_get_random(env);
2070
2071 r4k_invalidate_tlb(env, r, 1);
2072 r4k_fill_tlb(env, r);
2073 }
2074
2075 void r4k_helper_tlbp(CPUMIPSState *env)
2076 {
2077 r4k_tlb_t *tlb;
2078 target_ulong mask;
2079 target_ulong tag;
2080 target_ulong VPN;
2081 uint8_t ASID;
2082 int i;
2083
2084 ASID = env->CP0_EntryHi & 0xFF;
2085 for (i = 0; i < env->tlb->nb_tlb; i++) {
2086 tlb = &env->tlb->mmu.r4k.tlb[i];
2087 /* 1k pages are not supported. */
2088 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2089 tag = env->CP0_EntryHi & ~mask;
2090 VPN = tlb->VPN & ~mask;
2091 #if defined(TARGET_MIPS64)
2092 tag &= env->SEGMask;
2093 #endif
2094 /* Check ASID, virtual page number & size */
2095 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2096 /* TLB match */
2097 env->CP0_Index = i;
2098 break;
2099 }
2100 }
2101 if (i == env->tlb->nb_tlb) {
2102 /* No match. Discard any shadow entries, if any of them match. */
2103 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2104 tlb = &env->tlb->mmu.r4k.tlb[i];
2105 /* 1k pages are not supported. */
2106 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2107 tag = env->CP0_EntryHi & ~mask;
2108 VPN = tlb->VPN & ~mask;
2109 #if defined(TARGET_MIPS64)
2110 tag &= env->SEGMask;
2111 #endif
2112 /* Check ASID, virtual page number & size */
2113 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2114 r4k_mips_tlb_flush_extra (env, i);
2115 break;
2116 }
2117 }
2118
2119 env->CP0_Index |= 0x80000000;
2120 }
2121 }
2122
2123 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2124 {
2125 #if defined(TARGET_MIPS64)
2126 return tlb_pfn << 6;
2127 #else
2128 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2129 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2130 #endif
2131 }
2132
2133 void r4k_helper_tlbr(CPUMIPSState *env)
2134 {
2135 r4k_tlb_t *tlb;
2136 uint8_t ASID;
2137 int idx;
2138
2139 ASID = env->CP0_EntryHi & 0xFF;
2140 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2141 tlb = &env->tlb->mmu.r4k.tlb[idx];
2142
2143 /* If this will change the current ASID, flush qemu's TLB. */
2144 if (ASID != tlb->ASID)
2145 cpu_mips_tlb_flush (env, 1);
2146
2147 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2148
2149 if (tlb->EHINV) {
2150 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2151 env->CP0_PageMask = 0;
2152 env->CP0_EntryLo0 = 0;
2153 env->CP0_EntryLo1 = 0;
2154 } else {
2155 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2156 env->CP0_PageMask = tlb->PageMask;
2157 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2158 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2159 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2160 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2161 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2162 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2163 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2164 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2165 }
2166 }
2167
2168 void helper_tlbwi(CPUMIPSState *env)
2169 {
2170 env->tlb->helper_tlbwi(env);
2171 }
2172
2173 void helper_tlbwr(CPUMIPSState *env)
2174 {
2175 env->tlb->helper_tlbwr(env);
2176 }
2177
2178 void helper_tlbp(CPUMIPSState *env)
2179 {
2180 env->tlb->helper_tlbp(env);
2181 }
2182
2183 void helper_tlbr(CPUMIPSState *env)
2184 {
2185 env->tlb->helper_tlbr(env);
2186 }
2187
2188 void helper_tlbinv(CPUMIPSState *env)
2189 {
2190 env->tlb->helper_tlbinv(env);
2191 }
2192
2193 void helper_tlbinvf(CPUMIPSState *env)
2194 {
2195 env->tlb->helper_tlbinvf(env);
2196 }
2197
2198 /* Specials */
2199 target_ulong helper_di(CPUMIPSState *env)
2200 {
2201 target_ulong t0 = env->CP0_Status;
2202
2203 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2204 return t0;
2205 }
2206
2207 target_ulong helper_ei(CPUMIPSState *env)
2208 {
2209 target_ulong t0 = env->CP0_Status;
2210
2211 env->CP0_Status = t0 | (1 << CP0St_IE);
2212 return t0;
2213 }
2214
2215 static void debug_pre_eret(CPUMIPSState *env)
2216 {
2217 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2218 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2219 env->active_tc.PC, env->CP0_EPC);
2220 if (env->CP0_Status & (1 << CP0St_ERL))
2221 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2222 if (env->hflags & MIPS_HFLAG_DM)
2223 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2224 qemu_log("\n");
2225 }
2226 }
2227
2228 static void debug_post_eret(CPUMIPSState *env)
2229 {
2230 MIPSCPU *cpu = mips_env_get_cpu(env);
2231
2232 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2233 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2234 env->active_tc.PC, env->CP0_EPC);
2235 if (env->CP0_Status & (1 << CP0St_ERL))
2236 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2237 if (env->hflags & MIPS_HFLAG_DM)
2238 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2239 switch (env->hflags & MIPS_HFLAG_KSU) {
2240 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2241 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2242 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2243 default:
2244 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2245 break;
2246 }
2247 }
2248 }
2249
2250 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2251 {
2252 env->active_tc.PC = error_pc & ~(target_ulong)1;
2253 if (error_pc & 1) {
2254 env->hflags |= MIPS_HFLAG_M16;
2255 } else {
2256 env->hflags &= ~(MIPS_HFLAG_M16);
2257 }
2258 }
2259
2260 static inline void exception_return(CPUMIPSState *env)
2261 {
2262 debug_pre_eret(env);
2263 if (env->CP0_Status & (1 << CP0St_ERL)) {
2264 set_pc(env, env->CP0_ErrorEPC);
2265 env->CP0_Status &= ~(1 << CP0St_ERL);
2266 } else {
2267 set_pc(env, env->CP0_EPC);
2268 env->CP0_Status &= ~(1 << CP0St_EXL);
2269 }
2270 compute_hflags(env);
2271 debug_post_eret(env);
2272 }
2273
2274 void helper_eret(CPUMIPSState *env)
2275 {
2276 exception_return(env);
2277 env->lladdr = 1;
2278 }
2279
2280 void helper_eretnc(CPUMIPSState *env)
2281 {
2282 exception_return(env);
2283 }
2284
2285 void helper_deret(CPUMIPSState *env)
2286 {
2287 debug_pre_eret(env);
2288 set_pc(env, env->CP0_DEPC);
2289
2290 env->hflags &= ~MIPS_HFLAG_DM;
2291 compute_hflags(env);
2292 debug_post_eret(env);
2293 }
2294 #endif /* !CONFIG_USER_ONLY */
2295
2296 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2297 {
2298 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2299 return;
2300 }
2301 do_raise_exception(env, EXCP_RI, pc);
2302 }
2303
2304 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2305 {
2306 check_hwrena(env, 0, GETPC());
2307 return env->CP0_EBase & 0x3ff;
2308 }
2309
2310 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2311 {
2312 check_hwrena(env, 1, GETPC());
2313 return env->SYNCI_Step;
2314 }
2315
2316 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2317 {
2318 check_hwrena(env, 2, GETPC());
2319 #ifdef CONFIG_USER_ONLY
2320 return env->CP0_Count;
2321 #else
2322 return (int32_t)cpu_mips_get_count(env);
2323 #endif
2324 }
2325
2326 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2327 {
2328 check_hwrena(env, 3, GETPC());
2329 return env->CCRes;
2330 }
2331
2332 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2333 {
2334 check_hwrena(env, 4, GETPC());
2335 return env->CP0_Performance0;
2336 }
2337
2338 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2339 {
2340 check_hwrena(env, 5, GETPC());
2341 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2342 }
2343
2344 void helper_pmon(CPUMIPSState *env, int function)
2345 {
2346 function /= 2;
2347 switch (function) {
2348 case 2: /* TODO: char inbyte(int waitflag); */
2349 if (env->active_tc.gpr[4] == 0)
2350 env->active_tc.gpr[2] = -1;
2351 /* Fall through */
2352 case 11: /* TODO: char inbyte (void); */
2353 env->active_tc.gpr[2] = -1;
2354 break;
2355 case 3:
2356 case 12:
2357 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2358 break;
2359 case 17:
2360 break;
2361 case 158:
2362 {
2363 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2364 printf("%s", fmt);
2365 }
2366 break;
2367 }
2368 }
2369
2370 void helper_wait(CPUMIPSState *env)
2371 {
2372 CPUState *cs = CPU(mips_env_get_cpu(env));
2373
2374 cs->halted = 1;
2375 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2376 /* Last instruction in the block, PC was updated before
2377 - no need to recover PC and icount */
2378 raise_exception(env, EXCP_HLT);
2379 }
2380
2381 #if !defined(CONFIG_USER_ONLY)
2382
2383 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2384 int access_type, int is_user,
2385 uintptr_t retaddr)
2386 {
2387 MIPSCPU *cpu = MIPS_CPU(cs);
2388 CPUMIPSState *env = &cpu->env;
2389 int error_code = 0;
2390 int excp;
2391
2392 env->CP0_BadVAddr = addr;
2393
2394 if (access_type == MMU_DATA_STORE) {
2395 excp = EXCP_AdES;
2396 } else {
2397 excp = EXCP_AdEL;
2398 if (access_type == MMU_INST_FETCH) {
2399 error_code |= EXCP_INST_NOTAVAIL;
2400 }
2401 }
2402
2403 do_raise_exception_err(env, excp, error_code, retaddr);
2404 }
2405
2406 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2407 uintptr_t retaddr)
2408 {
2409 int ret;
2410
2411 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2412 if (ret) {
2413 MIPSCPU *cpu = MIPS_CPU(cs);
2414 CPUMIPSState *env = &cpu->env;
2415
2416 do_raise_exception_err(env, cs->exception_index,
2417 env->error_code, retaddr);
2418 }
2419 }
2420
2421 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2422 bool is_write, bool is_exec, int unused,
2423 unsigned size)
2424 {
2425 MIPSCPU *cpu = MIPS_CPU(cs);
2426 CPUMIPSState *env = &cpu->env;
2427
2428 /*
2429 * Raising an exception with KVM enabled will crash because it won't be from
2430 * the main execution loop so the longjmp won't have a matching setjmp.
2431 * Until we can trigger a bus error exception through KVM lets just ignore
2432 * the access.
2433 */
2434 if (kvm_enabled()) {
2435 return;
2436 }
2437
2438 if (is_exec) {
2439 raise_exception(env, EXCP_IBE);
2440 } else {
2441 raise_exception(env, EXCP_DBE);
2442 }
2443 }
2444 #endif /* !CONFIG_USER_ONLY */
2445
2446 /* Complex FPU operations which may need stack space. */
2447
2448 #define FLOAT_TWO32 make_float32(1 << 30)
2449 #define FLOAT_TWO64 make_float64(1ULL << 62)
2450 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2451 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2452
2453 /* convert MIPS rounding mode in FCR31 to IEEE library */
2454 unsigned int ieee_rm[] = {
2455 float_round_nearest_even,
2456 float_round_to_zero,
2457 float_round_up,
2458 float_round_down
2459 };
2460
2461 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2462 {
2463 target_ulong arg1 = 0;
2464
2465 switch (reg) {
2466 case 0:
2467 arg1 = (int32_t)env->active_fpu.fcr0;
2468 break;
2469 case 1:
2470 /* UFR Support - Read Status FR */
2471 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2472 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2473 arg1 = (int32_t)
2474 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2475 } else {
2476 do_raise_exception(env, EXCP_RI, GETPC());
2477 }
2478 }
2479 break;
2480 case 5:
2481 /* FRE Support - read Config5.FRE bit */
2482 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2483 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2484 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2485 } else {
2486 helper_raise_exception(env, EXCP_RI);
2487 }
2488 }
2489 break;
2490 case 25:
2491 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2492 break;
2493 case 26:
2494 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2495 break;
2496 case 28:
2497 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2498 break;
2499 default:
2500 arg1 = (int32_t)env->active_fpu.fcr31;
2501 break;
2502 }
2503
2504 return arg1;
2505 }
2506
2507 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2508 {
2509 switch (fs) {
2510 case 1:
2511 /* UFR Alias - Reset Status FR */
2512 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2513 return;
2514 }
2515 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2516 env->CP0_Status &= ~(1 << CP0St_FR);
2517 compute_hflags(env);
2518 } else {
2519 do_raise_exception(env, EXCP_RI, GETPC());
2520 }
2521 break;
2522 case 4:
2523 /* UNFR Alias - Set Status FR */
2524 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2525 return;
2526 }
2527 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2528 env->CP0_Status |= (1 << CP0St_FR);
2529 compute_hflags(env);
2530 } else {
2531 do_raise_exception(env, EXCP_RI, GETPC());
2532 }
2533 break;
2534 case 5:
2535 /* FRE Support - clear Config5.FRE bit */
2536 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2537 return;
2538 }
2539 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2540 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2541 compute_hflags(env);
2542 } else {
2543 helper_raise_exception(env, EXCP_RI);
2544 }
2545 break;
2546 case 6:
2547 /* FRE Support - set Config5.FRE bit */
2548 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2549 return;
2550 }
2551 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2552 env->CP0_Config5 |= (1 << CP0C5_FRE);
2553 compute_hflags(env);
2554 } else {
2555 helper_raise_exception(env, EXCP_RI);
2556 }
2557 break;
2558 case 25:
2559 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2560 return;
2561 }
2562 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2563 ((arg1 & 0x1) << 23);
2564 break;
2565 case 26:
2566 if (arg1 & 0x007c0000)
2567 return;
2568 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2569 break;
2570 case 28:
2571 if (arg1 & 0x007c0000)
2572 return;
2573 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2574 ((arg1 & 0x4) << 22);
2575 break;
2576 case 31:
2577 if (env->insn_flags & ISA_MIPS32R6) {
2578 uint32_t mask = 0xfefc0000;
2579 env->active_fpu.fcr31 = (arg1 & ~mask) |
2580 (env->active_fpu.fcr31 & mask);
2581 } else if (!(arg1 & 0x007c0000)) {
2582 env->active_fpu.fcr31 = arg1;
2583 }
2584 break;
2585 default:
2586 return;
2587 }
2588 /* set rounding mode */
2589 restore_rounding_mode(env);
2590 /* set flush-to-zero mode */
2591 restore_flush_mode(env);
2592 set_float_exception_flags(0, &env->active_fpu.fp_status);
2593 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2594 do_raise_exception(env, EXCP_FPE, GETPC());
2595 }
2596
2597 int ieee_ex_to_mips(int xcpt)
2598 {
2599 int ret = 0;
2600 if (xcpt) {
2601 if (xcpt & float_flag_invalid) {
2602 ret |= FP_INVALID;
2603 }
2604 if (xcpt & float_flag_overflow) {
2605 ret |= FP_OVERFLOW;
2606 }
2607 if (xcpt & float_flag_underflow) {
2608 ret |= FP_UNDERFLOW;
2609 }
2610 if (xcpt & float_flag_divbyzero) {
2611 ret |= FP_DIV0;
2612 }
2613 if (xcpt & float_flag_inexact) {
2614 ret |= FP_INEXACT;
2615 }
2616 }
2617 return ret;
2618 }
2619
2620 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2621 {
2622 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2623
2624 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2625
2626 if (tmp) {
2627 set_float_exception_flags(0, &env->active_fpu.fp_status);
2628
2629 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2630 do_raise_exception(env, EXCP_FPE, pc);
2631 } else {
2632 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2633 }
2634 }
2635 }
2636
2637 /* Float support.
2638 Single precition routines have a "s" suffix, double precision a
2639 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2640 paired single lower "pl", paired single upper "pu". */
2641
2642 /* unary operations, modifying fp status */
2643 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2644 {
2645 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2646 update_fcr31(env, GETPC());
2647 return fdt0;
2648 }
2649
2650 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2651 {
2652 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2653 update_fcr31(env, GETPC());
2654 return fst0;
2655 }
2656
2657 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2658 {
2659 uint64_t fdt2;
2660
2661 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2662 fdt2 = float64_maybe_silence_nan(fdt2);
2663 update_fcr31(env, GETPC());
2664 return fdt2;
2665 }
2666
2667 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2668 {
2669 uint64_t fdt2;
2670
2671 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2672 update_fcr31(env, GETPC());
2673 return fdt2;
2674 }
2675
2676 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2677 {
2678 uint64_t fdt2;
2679
2680 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2681 update_fcr31(env, GETPC());
2682 return fdt2;
2683 }
2684
2685 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2686 {
2687 uint64_t dt2;
2688
2689 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2690 if (get_float_exception_flags(&env->active_fpu.fp_status)
2691 & (float_flag_invalid | float_flag_overflow)) {
2692 dt2 = FP_TO_INT64_OVERFLOW;
2693 }
2694 update_fcr31(env, GETPC());
2695 return dt2;
2696 }
2697
2698 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2699 {
2700 uint64_t dt2;
2701
2702 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2703 if (get_float_exception_flags(&env->active_fpu.fp_status)
2704 & (float_flag_invalid | float_flag_overflow)) {
2705 dt2 = FP_TO_INT64_OVERFLOW;
2706 }
2707 update_fcr31(env, GETPC());
2708 return dt2;
2709 }
2710
2711 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2712 {
2713 uint32_t fst2;
2714 uint32_t fsth2;
2715
2716 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2717 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2718 update_fcr31(env, GETPC());
2719 return ((uint64_t)fsth2 << 32) | fst2;
2720 }
2721
2722 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2723 {
2724 uint32_t wt2;
2725 uint32_t wth2;
2726 int excp, excph;
2727
2728 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2729 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2730 if (excp & (float_flag_overflow | float_flag_invalid)) {
2731 wt2 = FP_TO_INT32_OVERFLOW;
2732 }
2733
2734 set_float_exception_flags(0, &env->active_fpu.fp_status);
2735 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2736 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2737 if (excph & (float_flag_overflow | float_flag_invalid)) {
2738 wth2 = FP_TO_INT32_OVERFLOW;
2739 }
2740
2741 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2742 update_fcr31(env, GETPC());
2743
2744 return ((uint64_t)wth2 << 32) | wt2;
2745 }
2746
2747 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2748 {
2749 uint32_t fst2;
2750
2751 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2752 fst2 = float32_maybe_silence_nan(fst2);
2753 update_fcr31(env, GETPC());
2754 return fst2;
2755 }
2756
2757 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2758 {
2759 uint32_t fst2;
2760
2761 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2762 update_fcr31(env, GETPC());
2763 return fst2;
2764 }
2765
2766 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2767 {
2768 uint32_t fst2;
2769
2770 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2771 update_fcr31(env, GETPC());
2772 return fst2;
2773 }
2774
2775 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2776 {
2777 uint32_t wt2;
2778
2779 wt2 = wt0;
2780 update_fcr31(env, GETPC());
2781 return wt2;
2782 }
2783
2784 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2785 {
2786 uint32_t wt2;
2787
2788 wt2 = wth0;
2789 update_fcr31(env, GETPC());
2790 return wt2;
2791 }
2792
2793 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2794 {
2795 uint32_t wt2;
2796
2797 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2798 if (get_float_exception_flags(&env->active_fpu.fp_status)
2799 & (float_flag_invalid | float_flag_overflow)) {
2800 wt2 = FP_TO_INT32_OVERFLOW;
2801 }
2802 update_fcr31(env, GETPC());
2803 return wt2;
2804 }
2805
2806 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2807 {
2808 uint32_t wt2;
2809
2810 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2811 if (get_float_exception_flags(&env->active_fpu.fp_status)
2812 & (float_flag_invalid | float_flag_overflow)) {
2813 wt2 = FP_TO_INT32_OVERFLOW;
2814 }
2815 update_fcr31(env, GETPC());
2816 return wt2;
2817 }
2818
2819 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2820 {
2821 uint64_t dt2;
2822
2823 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2824 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2825 restore_rounding_mode(env);
2826 if (get_float_exception_flags(&env->active_fpu.fp_status)
2827 & (float_flag_invalid | float_flag_overflow)) {
2828 dt2 = FP_TO_INT64_OVERFLOW;
2829 }
2830 update_fcr31(env, GETPC());
2831 return dt2;
2832 }
2833
2834 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2835 {
2836 uint64_t dt2;
2837
2838 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2839 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2840 restore_rounding_mode(env);
2841 if (get_float_exception_flags(&env->active_fpu.fp_status)
2842 & (float_flag_invalid | float_flag_overflow)) {
2843 dt2 = FP_TO_INT64_OVERFLOW;
2844 }
2845 update_fcr31(env, GETPC());
2846 return dt2;
2847 }
2848
2849 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2850 {
2851 uint32_t wt2;
2852
2853 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2854 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2855 restore_rounding_mode(env);
2856 if (get_float_exception_flags(&env->active_fpu.fp_status)
2857 & (float_flag_invalid | float_flag_overflow)) {
2858 wt2 = FP_TO_INT32_OVERFLOW;
2859 }
2860 update_fcr31(env, GETPC());
2861 return wt2;
2862 }
2863
2864 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2865 {
2866 uint32_t wt2;
2867
2868 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2869 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2870 restore_rounding_mode(env);
2871 if (get_float_exception_flags(&env->active_fpu.fp_status)
2872 & (float_flag_invalid | float_flag_overflow)) {
2873 wt2 = FP_TO_INT32_OVERFLOW;
2874 }
2875 update_fcr31(env, GETPC());
2876 return wt2;
2877 }
2878
2879 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2880 {
2881 uint64_t dt2;
2882
2883 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2884 if (get_float_exception_flags(&env->active_fpu.fp_status)
2885 & (float_flag_invalid | float_flag_overflow)) {
2886 dt2 = FP_TO_INT64_OVERFLOW;
2887 }
2888 update_fcr31(env, GETPC());
2889 return dt2;
2890 }
2891
2892 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2893 {
2894 uint64_t dt2;
2895
2896 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2897 if (get_float_exception_flags(&env->active_fpu.fp_status)
2898 & (float_flag_invalid | float_flag_overflow)) {
2899 dt2 = FP_TO_INT64_OVERFLOW;
2900 }
2901 update_fcr31(env, GETPC());
2902 return dt2;
2903 }
2904
2905 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2906 {
2907 uint32_t wt2;
2908
2909 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2910 if (get_float_exception_flags(&env->active_fpu.fp_status)
2911 & (float_flag_invalid | float_flag_overflow)) {
2912 wt2 = FP_TO_INT32_OVERFLOW;
2913 }
2914 update_fcr31(env, GETPC());
2915 return wt2;
2916 }
2917
2918 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2919 {
2920 uint32_t wt2;
2921
2922 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2923 if (get_float_exception_flags(&env->active_fpu.fp_status)
2924 & (float_flag_invalid | float_flag_overflow)) {
2925 wt2 = FP_TO_INT32_OVERFLOW;
2926 }
2927 update_fcr31(env, GETPC());
2928 return wt2;
2929 }
2930
2931 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2932 {
2933 uint64_t dt2;
2934
2935 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2936 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2937 restore_rounding_mode(env);
2938 if (get_float_exception_flags(&env->active_fpu.fp_status)
2939 & (float_flag_invalid | float_flag_overflow)) {
2940 dt2 = FP_TO_INT64_OVERFLOW;
2941 }
2942 update_fcr31(env, GETPC());
2943 return dt2;
2944 }
2945
2946 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2947 {
2948 uint64_t dt2;
2949
2950 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2951 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2952 restore_rounding_mode(env);
2953 if (get_float_exception_flags(&env->active_fpu.fp_status)
2954 & (float_flag_invalid | float_flag_overflow)) {
2955 dt2 = FP_TO_INT64_OVERFLOW;
2956 }
2957 update_fcr31(env, GETPC());
2958 return dt2;
2959 }
2960
2961 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2962 {
2963 uint32_t wt2;
2964
2965 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2966 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2967 restore_rounding_mode(env);
2968 if (get_float_exception_flags(&env->active_fpu.fp_status)
2969 & (float_flag_invalid | float_flag_overflow)) {
2970 wt2 = FP_TO_INT32_OVERFLOW;
2971 }
2972 update_fcr31(env, GETPC());
2973 return wt2;
2974 }
2975
2976 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2977 {
2978 uint32_t wt2;
2979
2980 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2981 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2982 restore_rounding_mode(env);
2983 if (get_float_exception_flags(&env->active_fpu.fp_status)
2984 & (float_flag_invalid | float_flag_overflow)) {
2985 wt2 = FP_TO_INT32_OVERFLOW;
2986 }
2987 update_fcr31(env, GETPC());
2988 return wt2;
2989 }
2990
2991 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2992 {
2993 uint64_t dt2;
2994
2995 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2996 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2997 restore_rounding_mode(env);
2998 if (get_float_exception_flags(&env->active_fpu.fp_status)
2999 & (float_flag_invalid | float_flag_overflow)) {
3000 dt2 = FP_TO_INT64_OVERFLOW;
3001 }
3002 update_fcr31(env, GETPC());
3003 return dt2;
3004 }
3005
3006 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
3007 {
3008 uint64_t dt2;
3009
3010 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3011 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3012 restore_rounding_mode(env);
3013 if (get_float_exception_flags(&env->active_fpu.fp_status)
3014 & (float_flag_invalid | float_flag_overflow)) {
3015 dt2 = FP_TO_INT64_OVERFLOW;
3016 }
3017 update_fcr31(env, GETPC());
3018 return dt2;
3019 }
3020
3021 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
3022 {
3023 uint32_t wt2;
3024
3025 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3026 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3027 restore_rounding_mode(env);
3028 if (get_float_exception_flags(&env->active_fpu.fp_status)
3029 & (float_flag_invalid | float_flag_overflow)) {
3030 wt2 = FP_TO_INT32_OVERFLOW;
3031 }
3032 update_fcr31(env, GETPC());
3033 return wt2;
3034 }
3035
3036 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
3037 {
3038 uint32_t wt2;
3039
3040 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3041 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3042 restore_rounding_mode(env);
3043 if (get_float_exception_flags(&env->active_fpu.fp_status)
3044 & (float_flag_invalid | float_flag_overflow)) {
3045 wt2 = FP_TO_INT32_OVERFLOW;
3046 }
3047 update_fcr31(env, GETPC());
3048 return wt2;
3049 }
3050
3051 /* unary operations, not modifying fp status */
3052 #define FLOAT_UNOP(name) \
3053 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3054 { \
3055 return float64_ ## name(fdt0); \
3056 } \
3057 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3058 { \
3059 return float32_ ## name(fst0); \
3060 } \
3061 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3062 { \
3063 uint32_t wt0; \
3064 uint32_t wth0; \
3065 \
3066 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3067 wth0 = float32_ ## name(fdt0 >> 32); \
3068 return ((uint64_t)wth0 << 32) | wt0; \
3069 }
3070 FLOAT_UNOP(abs)
3071 FLOAT_UNOP(chs)
3072 #undef FLOAT_UNOP
3073
3074 /* MIPS specific unary operations */
3075 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3076 {
3077 uint64_t fdt2;
3078
3079 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3080 update_fcr31(env, GETPC());
3081 return fdt2;
3082 }
3083
3084 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3085 {
3086 uint32_t fst2;
3087
3088 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3089 update_fcr31(env, GETPC());
3090 return fst2;
3091 }
3092
3093 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3094 {
3095 uint64_t fdt2;
3096
3097 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3098 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3099 update_fcr31(env, GETPC());
3100 return fdt2;
3101 }
3102
3103 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3104 {
3105 uint32_t fst2;
3106
3107 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3108 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3109 update_fcr31(env, GETPC());
3110 return fst2;
3111 }
3112
3113 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3114 {
3115 uint64_t fdt2;
3116
3117 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3118 update_fcr31(env, GETPC());
3119 return fdt2;
3120 }
3121
3122 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3123 {
3124 uint32_t fst2;
3125
3126 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3127 update_fcr31(env, GETPC());
3128 return fst2;
3129 }
3130
3131 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3132 {
3133 uint32_t fst2;
3134 uint32_t fsth2;
3135
3136 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3137 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3138 update_fcr31(env, GETPC());
3139 return ((uint64_t)fsth2 << 32) | fst2;
3140 }
3141
3142 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3143 {
3144 uint64_t fdt2;
3145
3146 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3147 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3148 update_fcr31(env, GETPC());
3149 return fdt2;
3150 }
3151
3152 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3153 {
3154 uint32_t fst2;
3155
3156 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3157 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3158 update_fcr31(env, GETPC());
3159 return fst2;
3160 }
3161
3162 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3163 {
3164 uint32_t fst2;
3165 uint32_t fsth2;
3166
3167 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3168 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3169 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3170 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3171 update_fcr31(env, GETPC());
3172 return ((uint64_t)fsth2 << 32) | fst2;
3173 }
3174
3175 #define FLOAT_RINT(name, bits) \
3176 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3177 uint ## bits ## _t fs) \
3178 { \
3179 uint ## bits ## _t fdret; \
3180 \
3181 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3182 update_fcr31(env, GETPC()); \
3183 return fdret; \
3184 }
3185
3186 FLOAT_RINT(rint_s, 32)
3187 FLOAT_RINT(rint_d, 64)
3188 #undef FLOAT_RINT
3189
3190 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3191 #define FLOAT_CLASS_QUIET_NAN 0x002
3192 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3193 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3194 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3195 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3196 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3197 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3198 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3199 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3200
3201 #define FLOAT_CLASS(name, bits) \
3202 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3203 { \
3204 if (float ## bits ## _is_signaling_nan(arg)) { \
3205 return FLOAT_CLASS_SIGNALING_NAN; \
3206 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3207 return FLOAT_CLASS_QUIET_NAN; \
3208 } else if (float ## bits ## _is_neg(arg)) { \
3209 if (float ## bits ## _is_infinity(arg)) { \
3210 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3211 } else if (float ## bits ## _is_zero(arg)) { \
3212 return FLOAT_CLASS_NEGATIVE_ZERO; \
3213 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3214 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3215 } else { \
3216 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3217 } \
3218 } else { \
3219 if (float ## bits ## _is_infinity(arg)) { \
3220 return FLOAT_CLASS_POSITIVE_INFINITY; \
3221 } else if (float ## bits ## _is_zero(arg)) { \
3222 return FLOAT_CLASS_POSITIVE_ZERO; \
3223 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3224 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3225 } else { \
3226 return FLOAT_CLASS_POSITIVE_NORMAL; \
3227 } \
3228 } \
3229 }
3230
3231 FLOAT_CLASS(class_s, 32)
3232 FLOAT_CLASS(class_d, 64)
3233 #undef FLOAT_CLASS
3234
3235 /* binary operations */
3236 #define FLOAT_BINOP(name) \
3237 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3238 uint64_t fdt0, uint64_t fdt1) \
3239 { \
3240 uint64_t dt2; \
3241 \
3242 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3243 update_fcr31(env, GETPC()); \
3244 return dt2; \
3245 } \
3246 \
3247 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3248 uint32_t fst0, uint32_t fst1) \
3249 { \
3250 uint32_t wt2; \
3251 \
3252 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3253 update_fcr31(env, GETPC()); \
3254 return wt2; \
3255 } \
3256 \
3257 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3258 uint64_t fdt0, \
3259 uint64_t fdt1) \
3260 { \
3261 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3262 uint32_t fsth0 = fdt0 >> 32; \
3263 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3264 uint32_t fsth1 = fdt1 >> 32; \
3265 uint32_t wt2; \
3266 uint32_t wth2; \
3267 \
3268 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3269 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3270 update_fcr31(env, GETPC()); \
3271 return ((uint64_t)wth2 << 32) | wt2; \
3272 }
3273
3274 FLOAT_BINOP(add)
3275 FLOAT_BINOP(sub)
3276 FLOAT_BINOP(mul)
3277 FLOAT_BINOP(div)
3278 #undef FLOAT_BINOP
3279
3280 /* MIPS specific binary operations */
3281 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3282 {
3283 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3284 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3285 update_fcr31(env, GETPC());
3286 return fdt2;
3287 }
3288
3289 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3290 {
3291 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3292 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3293 update_fcr31(env, GETPC());
3294 return fst2;
3295 }
3296
3297 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3298 {
3299 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3300 uint32_t fsth0 = fdt0 >> 32;
3301 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3302 uint32_t fsth2 = fdt2 >> 32;
3303
3304 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3305 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3306 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3307 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3308 update_fcr31(env, GETPC());
3309 return ((uint64_t)fsth2 << 32) | fst2;
3310 }
3311
3312 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3313 {
3314 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3315 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3316 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3317 update_fcr31(env, GETPC());
3318 return fdt2;
3319 }
3320
3321 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3322 {
3323 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3324 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3325 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3326 update_fcr31(env, GETPC());
3327 return fst2;
3328 }
3329
3330 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3331 {
3332 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3333 uint32_t fsth0 = fdt0 >> 32;
3334 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3335 uint32_t fsth2 = fdt2 >> 32;
3336
3337 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3338 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3339 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3340 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3341 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3342 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3343 update_fcr31(env, GETPC());
3344 return ((uint64_t)fsth2 << 32) | fst2;
3345 }
3346
3347 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3348 {
3349 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3350 uint32_t fsth0 = fdt0 >> 32;
3351 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3352 uint32_t fsth1 = fdt1 >> 32;
3353 uint32_t fst2;
3354 uint32_t fsth2;
3355
3356 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3357 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3358 update_fcr31(env, GETPC());
3359 return ((uint64_t)fsth2 << 32) | fst2;
3360 }
3361
3362 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3363 {
3364 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3365 uint32_t fsth0 = fdt0 >> 32;
3366 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3367 uint32_t fsth1 = fdt1 >> 32;
3368 uint32_t fst2;
3369 uint32_t fsth2;
3370
3371 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3372 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3373 update_fcr31(env, GETPC());
3374 return ((uint64_t)fsth2 << 32) | fst2;
3375 }
3376
3377 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3378 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3379 uint ## bits ## _t fs, \
3380 uint ## bits ## _t ft) \
3381 { \
3382 uint ## bits ## _t fdret; \
3383 \
3384 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3385 &env->active_fpu.fp_status); \
3386 update_fcr31(env, GETPC()); \
3387 return fdret; \
3388 }
3389
3390 FLOAT_MINMAX(max_s, 32, maxnum)
3391 FLOAT_MINMAX(max_d, 64, maxnum)
3392 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3393 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3394
3395 FLOAT_MINMAX(min_s, 32, minnum)
3396 FLOAT_MINMAX(min_d, 64, minnum)
3397 FLOAT_MINMAX(mina_s, 32, minnummag)
3398 FLOAT_MINMAX(mina_d, 64, minnummag)
3399 #undef FLOAT_MINMAX
3400
3401 /* ternary operations */
3402 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3403 { \
3404 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3405 if ((flags) & float_muladd_negate_c) { \
3406 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3407 } else { \
3408 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3409 } \
3410 if ((flags) & float_muladd_negate_result) { \
3411 a = prefix##_chs(a); \
3412 } \
3413 }
3414
3415 /* FMA based operations */
3416 #define FLOAT_FMA(name, type) \
3417 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3418 uint64_t fdt0, uint64_t fdt1, \
3419 uint64_t fdt2) \
3420 { \
3421 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3422 update_fcr31(env, GETPC()); \
3423 return fdt0; \
3424 } \
3425 \
3426 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3427 uint32_t fst0, uint32_t fst1, \
3428 uint32_t fst2) \
3429 { \
3430 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3431 update_fcr31(env, GETPC()); \
3432 return fst0; \
3433 } \
3434 \
3435 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3436 uint64_t fdt0, uint64_t fdt1, \
3437 uint64_t fdt2) \
3438 { \
3439 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3440 uint32_t fsth0 = fdt0 >> 32; \
3441 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3442 uint32_t fsth1 = fdt1 >> 32; \
3443 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3444 uint32_t fsth2 = fdt2 >> 32; \
3445 \
3446 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3447 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3448 update_fcr31(env, GETPC()); \
3449 return ((uint64_t)fsth0 << 32) | fst0; \
3450 }
3451 FLOAT_FMA(madd, 0)
3452 FLOAT_FMA(msub, float_muladd_negate_c)
3453 FLOAT_FMA(nmadd, float_muladd_negate_result)
3454 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3455 #undef FLOAT_FMA
3456
3457 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3458 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3459 uint ## bits ## _t fs, \
3460 uint ## bits ## _t ft, \
3461 uint ## bits ## _t fd) \
3462 { \
3463 uint ## bits ## _t fdret; \
3464 \
3465 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3466 &env->active_fpu.fp_status); \
3467 update_fcr31(env, GETPC()); \
3468 return fdret; \
3469 }
3470
3471 FLOAT_FMADDSUB(maddf_s, 32, 0)
3472 FLOAT_FMADDSUB(maddf_d, 64, 0)
3473 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3474 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3475 #undef FLOAT_FMADDSUB
3476
3477 /* compare operations */
3478 #define FOP_COND_D(op, cond) \
3479 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3480 uint64_t fdt1, int cc) \
3481 { \
3482 int c; \
3483 c = cond; \
3484 update_fcr31(env, GETPC()); \
3485 if (c) \
3486 SET_FP_COND(cc, env->active_fpu); \
3487 else \
3488 CLEAR_FP_COND(cc, env->active_fpu); \
3489 } \
3490 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3491 uint64_t fdt1, int cc) \
3492 { \
3493 int c; \
3494 fdt0 = float64_abs(fdt0); \
3495 fdt1 = float64_abs(fdt1); \
3496 c = cond; \
3497 update_fcr31(env, GETPC()); \
3498 if (c) \
3499 SET_FP_COND(cc, env->active_fpu); \
3500 else \
3501 CLEAR_FP_COND(cc, env->active_fpu); \
3502 }
3503
3504 /* NOTE: the comma operator will make "cond" to eval to false,
3505 * but float64_unordered_quiet() is still called. */
3506 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3507 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3508 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3509 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3510 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3511 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3512 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3513 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3514 /* NOTE: the comma operator will make "cond" to eval to false,
3515 * but float64_unordered() is still called. */
3516 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3517 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3518 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3519 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3520 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3521 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3522 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3523 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3524
3525 #define FOP_COND_S(op, cond) \
3526 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3527 uint32_t fst1, int cc) \
3528 { \
3529 int c; \
3530 c = cond; \
3531 update_fcr31(env, GETPC()); \
3532 if (c) \
3533 SET_FP_COND(cc, env->active_fpu); \
3534 else \
3535 CLEAR_FP_COND(cc, env->active_fpu); \
3536 } \
3537 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3538 uint32_t fst1, int cc) \
3539 { \
3540 int c; \
3541 fst0 = float32_abs(fst0); \
3542 fst1 = float32_abs(fst1); \
3543 c = cond; \
3544 update_fcr31(env, GETPC()); \
3545 if (c) \
3546 SET_FP_COND(cc, env->active_fpu); \
3547 else \
3548 CLEAR_FP_COND(cc, env->active_fpu); \
3549 }
3550
3551 /* NOTE: the comma operator will make "cond" to eval to false,
3552 * but float32_unordered_quiet() is still called. */
3553 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3554 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3555 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3556 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3557 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3558 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3559 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3560 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3561 /* NOTE: the comma operator will make "cond" to eval to false,
3562 * but float32_unordered() is still called. */
3563 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3564 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3565 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3566 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3567 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3568 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3569 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3570 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3571
3572 #define FOP_COND_PS(op, condl, condh) \
3573 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3574 uint64_t fdt1, int cc) \
3575 { \
3576 uint32_t fst0, fsth0, fst1, fsth1; \
3577 int ch, cl; \
3578 fst0 = fdt0 & 0XFFFFFFFF; \
3579 fsth0 = fdt0 >> 32; \
3580 fst1 = fdt1 & 0XFFFFFFFF; \
3581 fsth1 = fdt1 >> 32; \
3582 cl = condl; \
3583 ch = condh; \
3584 update_fcr31(env, GETPC()); \
3585 if (cl) \
3586 SET_FP_COND(cc, env->active_fpu); \
3587 else \
3588 CLEAR_FP_COND(cc, env->active_fpu); \
3589 if (ch) \
3590 SET_FP_COND(cc + 1, env->active_fpu); \
3591 else \
3592 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3593 } \
3594 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3595 uint64_t fdt1, int cc) \
3596 { \
3597 uint32_t fst0, fsth0, fst1, fsth1; \
3598 int ch, cl; \
3599 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3600 fsth0 = float32_abs(fdt0 >> 32); \
3601 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3602 fsth1 = float32_abs(fdt1 >> 32); \
3603 cl = condl; \
3604 ch = condh; \
3605 update_fcr31(env, GETPC()); \
3606 if (cl) \
3607 SET_FP_COND(cc, env->active_fpu); \
3608 else \
3609 CLEAR_FP_COND(cc, env->active_fpu); \
3610 if (ch) \
3611 SET_FP_COND(cc + 1, env->active_fpu); \
3612 else \
3613 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3614 }
3615
3616 /* NOTE: the comma operator will make "cond" to eval to false,
3617 * but float32_unordered_quiet() is still called. */
3618 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3619 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3620 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3621 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3622 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3623 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3624 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3625 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3626 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3627 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3628 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3629 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3630 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3631 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3632 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3633 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3634 /* NOTE: the comma operator will make "cond" to eval to false,
3635 * but float32_unordered() is still called. */
3636 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3637 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3638 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3639 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3640 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3641 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3642 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3643 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3644 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3645 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3646 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3647 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3648 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3649 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3650 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3651 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3652
3653 /* R6 compare operations */
3654 #define FOP_CONDN_D(op, cond) \
3655 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3656 uint64_t fdt1) \
3657 { \
3658 uint64_t c; \
3659 c = cond; \
3660 update_fcr31(env, GETPC()); \
3661 if (c) { \
3662 return -1; \
3663 } else { \
3664 return 0; \
3665 } \
3666 }
3667
3668 /* NOTE: the comma operator will make "cond" to eval to false,
3669 * but float64_unordered_quiet() is still called. */
3670 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3671 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3672 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3673 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3674 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3675 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3676 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3677 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3678 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3679 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3680 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3681 /* NOTE: the comma operator will make "cond" to eval to false,
3682 * but float64_unordered() is still called. */
3683 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3684 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3685 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3686 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3687 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3688 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3689 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3690 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3691 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3692 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3693 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3694 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3695 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3696 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3697 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3698 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3699 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3700 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3701 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3702 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3703 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3704 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3705 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3706 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3707 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3708
3709 #define FOP_CONDN_S(op, cond) \
3710 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
3711 uint32_t fst1) \
3712 { \
3713 uint64_t c; \
3714 c = cond; \
3715 update_fcr31(env, GETPC()); \
3716 if (c) { \
3717 return -1; \
3718 } else { \
3719 return 0; \
3720 } \
3721 }
3722
3723 /* NOTE: the comma operator will make "cond" to eval to false,
3724 * but float32_unordered_quiet() is still called. */
3725 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3726 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3727 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3728 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3729 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3730 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3731 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3732 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3733 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3734 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3735 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3736 /* NOTE: the comma operator will make "cond" to eval to false,
3737 * but float32_unordered() is still called. */
3738 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3739 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3740 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3741 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3742 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3743 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3744 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3745 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3746 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3747 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3748 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3749 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3750 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3751 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3752 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3753 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3754 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3755 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3756 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3757 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3758 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3759 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3760 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3761 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3762 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3763
3764 /* MSA */
3765 /* Data format min and max values */
3766 #define DF_BITS(df) (1 << ((df) + 3))
3767
3768 /* Element-by-element access macros */
3769 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3770
3771 #if !defined(CONFIG_USER_ONLY)
3772 #define MEMOP_IDX(DF) \
3773 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
3774 cpu_mmu_index(env, false));
3775 #else
3776 #define MEMOP_IDX(DF)
3777 #endif
3778
3779 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
3780 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3781 target_ulong addr) \
3782 { \
3783 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3784 wr_t wx; \
3785 int i; \
3786 MEMOP_IDX(DF) \
3787 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3788 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
3789 } \
3790 memcpy(pwd, &wx, sizeof(wr_t)); \
3791 }
3792
3793 #if !defined(CONFIG_USER_ONLY)
3794 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETRA())
3795 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETRA())
3796 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETRA())
3797 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETRA())
3798 #else
3799 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
3800 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
3801 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
3802 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3803 #endif
3804
3805 #define MSA_PAGESPAN(x) \
3806 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3807
3808 static inline void ensure_writable_pages(CPUMIPSState *env,
3809 target_ulong addr,
3810 int mmu_idx,
3811 uintptr_t retaddr)
3812 {
3813 #if !defined(CONFIG_USER_ONLY)
3814 target_ulong page_addr;
3815 if (unlikely(MSA_PAGESPAN(addr))) {
3816 /* first page */
3817 probe_write(env, addr, mmu_idx, retaddr);
3818 /* second page */
3819 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3820 probe_write(env, page_addr, mmu_idx, retaddr);
3821 }
3822 #endif
3823 }
3824
3825 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
3826 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3827 target_ulong addr) \
3828 { \
3829 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3830 int mmu_idx = cpu_mmu_index(env, false); \
3831 int i; \
3832 MEMOP_IDX(DF) \
3833 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
3834 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3835 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
3836 } \
3837 }
3838
3839 #if !defined(CONFIG_USER_ONLY)
3840 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETRA())
3841 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETRA())
3842 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETRA())
3843 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3844 #else
3845 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
3846 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
3847 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
3848 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3849 #endif
3850
3851 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
3852 {
3853 #ifndef CONFIG_USER_ONLY
3854 target_ulong index = addr & 0x1fffffff;
3855 if (op == 9) {
3856 /* Index Store Tag */
3857 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
3858 8, MEMTXATTRS_UNSPECIFIED);
3859 } else if (op == 5) {
3860 /* Index Load Tag */
3861 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
3862 8, MEMTXATTRS_UNSPECIFIED);
3863 }
3864 #endif
3865 }
AR7 emulation for QEMU