2 * ARM GIC support - internal interfaces
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef QEMU_ARM_GIC_INTERNAL_H
22 #define QEMU_ARM_GIC_INTERNAL_H
24 #include "hw/sysbus.h"
26 /* Maximum number of possible interrupts, determined by the GIC architecture */
27 #define GIC_MAXIRQ 1020
28 /* First 32 are private to each CPU (SGIs and PPIs). */
29 #define GIC_INTERNAL 32
30 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
33 #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
35 /* The NVIC has 16 internal vectors. However these are not exposed
36 through the normal GIC interface. */
37 #define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
39 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
40 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
41 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
42 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
43 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
44 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
45 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
46 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
47 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
48 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
49 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
50 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
51 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
52 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
53 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
54 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true
55 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false
56 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
57 #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
58 s->priority1[irq][cpu] : \
59 s->priority2[(irq) - GIC_INTERNAL])
60 #define GIC_TARGET(irq) s->irq_target[irq]
62 typedef struct gic_irq_state
{
63 /* The enable bits are only banked for per-cpu interrupts. */
68 bool model
; /* 0 = N:N, 1 = 1:N */
69 bool trigger
; /* nonzero = edge triggered. */
72 typedef struct GICState
{
74 SysBusDevice parent_obj
;
77 qemu_irq parent_irq
[NCPU
];
79 bool cpu_enabled
[NCPU
];
81 gic_irq_state irq_state
[GIC_MAXIRQ
];
82 uint8_t irq_target
[GIC_MAXIRQ
];
83 uint8_t priority1
[GIC_INTERNAL
][NCPU
];
84 uint8_t priority2
[GIC_MAXIRQ
- GIC_INTERNAL
];
85 uint16_t last_active
[GIC_MAXIRQ
][NCPU
];
87 uint16_t priority_mask
[NCPU
];
88 uint16_t running_irq
[NCPU
];
89 uint16_t running_priority
[NCPU
];
90 uint16_t current_pending
[NCPU
];
94 MemoryRegion iomem
; /* Distributor */
95 /* This is just so we can have an opaque pointer which identifies
96 * both this GIC and which CPU interface we should be accessing.
98 struct GICState
*backref
[NCPU
];
99 MemoryRegion cpuiomem
[NCPU
+1]; /* CPU interfaces */
104 /* The special cases for the revision property: */
105 #define REV_11MPCORE 0
106 #define REV_NVIC 0xffffffff
108 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
);
109 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
);
110 void gic_complete_irq(GICState
*s
, int cpu
, int irq
);
111 void gic_update(GICState
*s
);
112 void gic_init_irqs_and_distributor(GICState
*s
, int num_irq
);
114 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
115 #define ARM_GIC_COMMON(obj) \
116 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
117 #define ARM_GIC_COMMON_CLASS(klass) \
118 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
119 #define ARM_GIC_COMMON_GET_CLASS(obj) \
120 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
122 typedef struct ARMGICCommonClass
{
123 SysBusDeviceClass parent_class
;
124 void (*pre_save
)(GICState
*s
);
125 void (*post_load
)(GICState
*s
);
128 #define TYPE_ARM_GIC "arm_gic"
129 #define ARM_GIC(obj) \
130 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
131 #define ARM_GIC_CLASS(klass) \
132 OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
133 #define ARM_GIC_GET_CLASS(obj) \
134 OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
136 typedef struct ARMGICClass
{
137 ARMGICCommonClass parent_class
;
138 DeviceRealize parent_realize
;
141 #endif /* !QEMU_ARM_GIC_INTERNAL_H */