hw/cpu/a9mpcore.c

   1 /*
   2  * Cortex-A9MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2009 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited.
   6  * Written by Paul Brook, Peter Maydell.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw/sysbus.h"
  12
  13 #define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
  14 #define A9MPCORE_PRIV(obj) \
  15     OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
  16
  17 typedef struct A9MPPrivState {
  18     /*< private >*/
  19     SysBusDevice parent_obj;
  20     /*< public >*/
  21
  22     uint32_t num_cpu;
  23     MemoryRegion container;
  24     DeviceState *mptimer;
  25     DeviceState *wdt;
  26     DeviceState *gic;
  27     DeviceState *scu;
  28     uint32_t num_irq;
  29 } A9MPPrivState;
  30
  31 static void a9mp_priv_set_irq(void *opaque, int irq, int level)
  32 {
  33     A9MPPrivState *s = (A9MPPrivState *)opaque;
  34     qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
  35 }
  36
  37 static int a9mp_priv_init(SysBusDevice *dev)
  38 {
  39     A9MPPrivState *s = A9MPCORE_PRIV(dev);
  40     SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
  41     int i;
  42
  43     s->gic = qdev_create(NULL, "arm_gic");
  44     qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
  45     qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
  46     qdev_init_nofail(s->gic);
  47     gicbusdev = SYS_BUS_DEVICE(s->gic);
  48
  49     /* Pass through outbound IRQ lines from the GIC */
  50     sysbus_pass_irq(dev, gicbusdev);
  51
  52     /* Pass through inbound GPIO lines to the GIC */
  53     qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s->num_irq - 32);
  54
  55     s->scu = qdev_create(NULL, "a9-scu");
  56     qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu);
  57     qdev_init_nofail(s->scu);
  58     scubusdev = SYS_BUS_DEVICE(s->scu);
  59
  60     s->mptimer = qdev_create(NULL, "arm_mptimer");
  61     qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
  62     qdev_init_nofail(s->mptimer);
  63     timerbusdev = SYS_BUS_DEVICE(s->mptimer);
  64
  65     s->wdt = qdev_create(NULL, "arm_mptimer");
  66     qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu);
  67     qdev_init_nofail(s->wdt);
  68     wdtbusdev = SYS_BUS_DEVICE(s->wdt);
  69
  70     /* Memory map (addresses are offsets from PERIPHBASE):
  71      *  0x0000-0x00ff -- Snoop Control Unit
  72      *  0x0100-0x01ff -- GIC CPU interface
  73      *  0x0200-0x02ff -- Global Timer
  74      *  0x0300-0x05ff -- nothing
  75      *  0x0600-0x06ff -- private timers and watchdogs
  76      *  0x0700-0x0fff -- nothing
  77      *  0x1000-0x1fff -- GIC Distributor
  78      *
  79      * We should implement the global timer but don't currently do so.
  80      */
  81     memory_region_init(&s->container, OBJECT(s), "a9mp-priv-container", 0x2000);
  82     memory_region_add_subregion(&s->container, 0,
  83                                 sysbus_mmio_get_region(scubusdev, 0));
  84     /* GIC CPU interface */
  85     memory_region_add_subregion(&s->container, 0x100,
  86                                 sysbus_mmio_get_region(gicbusdev, 1));
  87     /* Note that the A9 exposes only the "timer/watchdog for this core"
  88      * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
  89      */
  90     memory_region_add_subregion(&s->container, 0x600,
  91                                 sysbus_mmio_get_region(timerbusdev, 0));
  92     memory_region_add_subregion(&s->container, 0x620,
  93                                 sysbus_mmio_get_region(wdtbusdev, 0));
  94     memory_region_add_subregion(&s->container, 0x1000,
  95                                 sysbus_mmio_get_region(gicbusdev, 0));
  96
  97     sysbus_init_mmio(dev, &s->container);
  98
  99     /* Wire up the interrupt from each watchdog and timer.
 100      * For each core the timer is PPI 29 and the watchdog PPI 30.
 101      */
 102     for (i = 0; i < s->num_cpu; i++) {
 103         int ppibase = (s->num_irq - 32) + i * 32;
 104         sysbus_connect_irq(timerbusdev, i,
 105                            qdev_get_gpio_in(s->gic, ppibase + 29));
 106         sysbus_connect_irq(wdtbusdev, i,
 107                            qdev_get_gpio_in(s->gic, ppibase + 30));
 108     }
 109     return 0;
 110 }
 111
 112 static Property a9mp_priv_properties[] = {
 113     DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
 114     /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
 115      * IRQ lines (with another 32 internal). We default to 64+32, which
 116      * is the number provided by the Cortex-A9MP test chip in the
 117      * Realview PBX-A9 and Versatile Express A9 development boards.
 118      * Other boards may differ and should set this property appropriately.
 119      */
 120     DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
 121     DEFINE_PROP_END_OF_LIST(),
 122 };
 123
 124 static void a9mp_priv_class_init(ObjectClass *klass, void *data)
 125 {
 126     DeviceClass *dc = DEVICE_CLASS(klass);
 127     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 128
 129     k->init = a9mp_priv_init;
 130     dc->props = a9mp_priv_properties;
 131 }
 132
 133 static const TypeInfo a9mp_priv_info = {
 134     .name          = TYPE_A9MPCORE_PRIV,
 135     .parent        = TYPE_SYS_BUS_DEVICE,
 136     .instance_size = sizeof(A9MPPrivState),
 137     .class_init    = a9mp_priv_class_init,
 138 };
 139
 140 static void a9mp_register_types(void)
 141 {
 142     type_register_static(&a9mp_priv_info);
 143 }
 144
 145 type_init(a9mp_register_types)