4 * Copyright (c) 2012 Red Hat Inc.
5 * Author: Michael S. Tsirkin <mst@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/qdev-properties.h"
24 #include "qemu/event_notifier.h"
25 #include "qemu/module.h"
26 #include "sysemu/kvm.h"
27 #include "qom/object.h"
29 typedef struct PCITestDevHdr
{
40 typedef struct IOTest
{
42 EventNotifier notifier
;
50 #define IOTEST_DATAMATCH 0xFA
51 #define IOTEST_NOMATCH 0xCE
53 #define IOTEST_IOSIZE 128
54 #define IOTEST_MEMSIZE 2048
56 static const char *iotest_test
[] = {
62 static const char *iotest_type
[] = {
67 #define IOTEST_TEST(i) (iotest_test[((i) % ARRAY_SIZE(iotest_test))])
68 #define IOTEST_TYPE(i) (iotest_type[((i) / ARRAY_SIZE(iotest_test))])
69 #define IOTEST_MAX_TEST (ARRAY_SIZE(iotest_test))
70 #define IOTEST_MAX_TYPE (ARRAY_SIZE(iotest_type))
71 #define IOTEST_MAX (IOTEST_MAX_TEST * IOTEST_MAX_TYPE)
79 #define IOTEST_ACCESS_TYPE uint8_t
80 #define IOTEST_ACCESS_WIDTH (sizeof(uint8_t))
82 struct PCITestDevState
{
96 #define TYPE_PCI_TEST_DEV "pci-testdev"
98 OBJECT_DECLARE_SIMPLE_TYPE(PCITestDevState
, PCI_TEST_DEV
)
100 #define IOTEST_IS_MEM(i) (strcmp(IOTEST_TYPE(i), "portio"))
101 #define IOTEST_REGION(d, i) (IOTEST_IS_MEM(i) ? &(d)->mmio : &(d)->portio)
102 #define IOTEST_SIZE(i) (IOTEST_IS_MEM(i) ? IOTEST_MEMSIZE : IOTEST_IOSIZE)
103 #define IOTEST_PCI_BAR(i) (IOTEST_IS_MEM(i) ? PCI_BASE_ADDRESS_SPACE_MEMORY : \
104 PCI_BASE_ADDRESS_SPACE_IO)
106 static int pci_testdev_start(IOTest
*test
)
108 test
->hdr
->count
= 0;
109 if (!test
->hasnotifier
) {
112 event_notifier_test_and_clear(&test
->notifier
);
113 memory_region_add_eventfd(test
->mr
,
114 le32_to_cpu(test
->hdr
->offset
),
122 static void pci_testdev_stop(IOTest
*test
)
124 if (!test
->hasnotifier
) {
127 memory_region_del_eventfd(test
->mr
,
128 le32_to_cpu(test
->hdr
->offset
),
136 pci_testdev_reset(PCITestDevState
*d
)
138 if (d
->current
== -1) {
141 pci_testdev_stop(&d
->tests
[d
->current
]);
145 static void pci_testdev_inc(IOTest
*test
, unsigned inc
)
147 uint32_t c
= le32_to_cpu(test
->hdr
->count
);
148 test
->hdr
->count
= cpu_to_le32(c
+ inc
);
152 pci_testdev_write(void *opaque
, hwaddr addr
, uint64_t val
,
153 unsigned size
, int type
)
155 PCITestDevState
*d
= opaque
;
159 if (addr
== offsetof(PCITestDevHdr
, test
)) {
160 pci_testdev_reset(d
);
161 if (val
>= IOTEST_MAX_TEST
) {
164 t
= type
* IOTEST_MAX_TEST
+ val
;
165 r
= pci_testdev_start(&d
->tests
[t
]);
172 if (d
->current
< 0) {
175 test
= &d
->tests
[d
->current
];
176 if (addr
!= le32_to_cpu(test
->hdr
->offset
)) {
179 if (test
->match_data
&& test
->size
!= size
) {
182 if (test
->match_data
&& val
!= test
->hdr
->data
) {
185 pci_testdev_inc(test
, 1);
189 pci_testdev_read(void *opaque
, hwaddr addr
, unsigned size
)
191 PCITestDevState
*d
= opaque
;
194 if (d
->current
< 0) {
197 test
= &d
->tests
[d
->current
];
198 buf
= (const char *)test
->hdr
;
199 if (addr
+ size
>= test
->bufsize
) {
202 if (test
->hasnotifier
) {
203 event_notifier_test_and_clear(&test
->notifier
);
209 pci_testdev_mmio_write(void *opaque
, hwaddr addr
, uint64_t val
,
212 pci_testdev_write(opaque
, addr
, val
, size
, 0);
216 pci_testdev_pio_write(void *opaque
, hwaddr addr
, uint64_t val
,
219 pci_testdev_write(opaque
, addr
, val
, size
, 1);
222 static const MemoryRegionOps pci_testdev_mmio_ops
= {
223 .read
= pci_testdev_read
,
224 .write
= pci_testdev_mmio_write
,
225 .endianness
= DEVICE_LITTLE_ENDIAN
,
227 .min_access_size
= 1,
228 .max_access_size
= 1,
232 static const MemoryRegionOps pci_testdev_pio_ops
= {
233 .read
= pci_testdev_read
,
234 .write
= pci_testdev_pio_write
,
235 .endianness
= DEVICE_LITTLE_ENDIAN
,
237 .min_access_size
= 1,
238 .max_access_size
= 1,
242 static void pci_testdev_realize(PCIDevice
*pci_dev
, Error
**errp
)
244 PCITestDevState
*d
= PCI_TEST_DEV(pci_dev
);
248 bool fastmmio
= kvm_ioeventfd_any_length_enabled();
250 pci_conf
= pci_dev
->config
;
252 pci_conf
[PCI_INTERRUPT_PIN
] = 0; /* no interrupt pin */
254 memory_region_init_io(&d
->mmio
, OBJECT(d
), &pci_testdev_mmio_ops
, d
,
255 "pci-testdev-mmio", IOTEST_MEMSIZE
* 2);
256 memory_region_init_io(&d
->portio
, OBJECT(d
), &pci_testdev_pio_ops
, d
,
257 "pci-testdev-portio", IOTEST_IOSIZE
* 2);
258 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &d
->mmio
);
259 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &d
->portio
);
261 if (d
->membar_size
) {
262 memory_region_init(&d
->membar
, OBJECT(d
), "pci-testdev-membar",
264 pci_register_bar(pci_dev
, 2,
265 PCI_BASE_ADDRESS_SPACE_MEMORY
|
266 PCI_BASE_ADDRESS_MEM_PREFETCH
|
267 PCI_BASE_ADDRESS_MEM_TYPE_64
,
272 d
->tests
= g_malloc0(IOTEST_MAX
* sizeof *d
->tests
);
273 for (i
= 0; i
< IOTEST_MAX
; ++i
) {
274 IOTest
*test
= &d
->tests
[i
];
275 name
= g_strdup_printf("%s-%s", IOTEST_TYPE(i
), IOTEST_TEST(i
));
276 test
->bufsize
= sizeof(PCITestDevHdr
) + strlen(name
) + 1;
277 test
->hdr
= g_malloc0(test
->bufsize
);
278 memcpy(test
->hdr
->name
, name
, strlen(name
) + 1);
280 test
->hdr
->offset
= cpu_to_le32(IOTEST_SIZE(i
) + i
* IOTEST_ACCESS_WIDTH
);
281 test
->match_data
= strcmp(IOTEST_TEST(i
), "wildcard-eventfd");
282 if (fastmmio
&& IOTEST_IS_MEM(i
) && !test
->match_data
) {
285 test
->size
= IOTEST_ACCESS_WIDTH
;
288 test
->hdr
->data
= test
->match_data
? IOTEST_DATAMATCH
: IOTEST_NOMATCH
;
289 test
->hdr
->width
= IOTEST_ACCESS_WIDTH
;
290 test
->mr
= IOTEST_REGION(d
, i
);
291 if (!strcmp(IOTEST_TEST(i
), "no-eventfd")) {
292 test
->hasnotifier
= false;
295 r
= event_notifier_init(&test
->notifier
, 0);
297 test
->hasnotifier
= true;
302 pci_testdev_uninit(PCIDevice
*dev
)
304 PCITestDevState
*d
= PCI_TEST_DEV(dev
);
307 pci_testdev_reset(d
);
308 for (i
= 0; i
< IOTEST_MAX
; ++i
) {
309 if (d
->tests
[i
].hasnotifier
) {
310 event_notifier_cleanup(&d
->tests
[i
].notifier
);
312 g_free(d
->tests
[i
].hdr
);
317 static void qdev_pci_testdev_reset(DeviceState
*dev
)
319 PCITestDevState
*d
= PCI_TEST_DEV(dev
);
320 pci_testdev_reset(d
);
323 static Property pci_testdev_properties
[] = {
324 DEFINE_PROP_SIZE("membar", PCITestDevState
, membar_size
, 0),
325 DEFINE_PROP_END_OF_LIST(),
328 static void pci_testdev_class_init(ObjectClass
*klass
, void *data
)
330 DeviceClass
*dc
= DEVICE_CLASS(klass
);
331 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
333 k
->realize
= pci_testdev_realize
;
334 k
->exit
= pci_testdev_uninit
;
335 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
336 k
->device_id
= PCI_DEVICE_ID_REDHAT_TEST
;
338 k
->class_id
= PCI_CLASS_OTHERS
;
339 dc
->desc
= "PCI Test Device";
340 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
341 dc
->reset
= qdev_pci_testdev_reset
;
342 device_class_set_props(dc
, pci_testdev_properties
);
345 static const TypeInfo pci_testdev_info
= {
346 .name
= TYPE_PCI_TEST_DEV
,
347 .parent
= TYPE_PCI_DEVICE
,
348 .instance_size
= sizeof(PCITestDevState
),
349 .class_init
= pci_testdev_class_init
,
350 .interfaces
= (InterfaceInfo
[]) {
351 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
356 static void pci_testdev_register_types(void)
358 type_register_static(&pci_testdev_info
);
361 type_init(pci_testdev_register_types
)