2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/char/serial.h"
29 #include "migration/vmstate.h"
30 #include "chardev/char-serial.h"
31 #include "qapi/error.h"
32 #include "qemu/timer.h"
33 #include "sysemu/reset.h"
34 #include "sysemu/runstate.h"
35 #include "qemu/error-report.h"
37 #include "hw/qdev-properties.h"
39 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
41 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
42 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
43 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
44 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
46 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
47 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
49 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
50 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
51 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
52 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
53 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
55 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
56 #define UART_IIR_FE 0xC0 /* Fifo enabled */
59 * These are the definitions for the Modem Control Register
61 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
62 #define UART_MCR_OUT2 0x08 /* Out2 complement */
63 #define UART_MCR_OUT1 0x04 /* Out1 complement */
64 #define UART_MCR_RTS 0x02 /* RTS complement */
65 #define UART_MCR_DTR 0x01 /* DTR complement */
68 * These are the definitions for the Modem Status Register
70 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
71 #define UART_MSR_RI 0x40 /* Ring Indicator */
72 #define UART_MSR_DSR 0x20 /* Data Set Ready */
73 #define UART_MSR_CTS 0x10 /* Clear to Send */
74 #define UART_MSR_DDCD 0x08 /* Delta DCD */
75 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
76 #define UART_MSR_DDSR 0x02 /* Delta DSR */
77 #define UART_MSR_DCTS 0x01 /* Delta CTS */
78 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
80 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
81 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
82 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
83 #define UART_LSR_FE 0x08 /* Frame error indicator */
84 #define UART_LSR_PE 0x04 /* Parity error indicator */
85 #define UART_LSR_OE 0x02 /* Overrun error indicator */
86 #define UART_LSR_DR 0x01 /* Receiver data ready */
87 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
89 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
91 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
92 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
93 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
94 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
96 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
97 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
98 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
99 #define UART_FCR_FE 0x01 /* FIFO Enable */
101 #define MAX_XMIT_RETRY 4
103 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
);
104 static void serial_xmit(SerialState
*s
);
106 static inline void recv_fifo_put(SerialState
*s
, uint8_t chr
)
108 /* Receive overruns do not overwrite FIFO contents. */
109 if (!fifo8_is_full(&s
->recv_fifo
)) {
110 fifo8_push(&s
->recv_fifo
, chr
);
112 s
->lsr
|= UART_LSR_OE
;
116 static void serial_update_irq(SerialState
*s
)
118 uint8_t tmp_iir
= UART_IIR_NO_INT
;
120 if ((s
->ier
& UART_IER_RLSI
) && (s
->lsr
& UART_LSR_INT_ANY
)) {
121 tmp_iir
= UART_IIR_RLSI
;
122 } else if ((s
->ier
& UART_IER_RDI
) && s
->timeout_ipending
) {
123 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
124 * this is not in the specification but is observed on existing
126 tmp_iir
= UART_IIR_CTI
;
127 } else if ((s
->ier
& UART_IER_RDI
) && (s
->lsr
& UART_LSR_DR
) &&
128 (!(s
->fcr
& UART_FCR_FE
) ||
129 s
->recv_fifo
.num
>= s
->recv_fifo_itl
)) {
130 tmp_iir
= UART_IIR_RDI
;
131 } else if ((s
->ier
& UART_IER_THRI
) && s
->thr_ipending
) {
132 tmp_iir
= UART_IIR_THRI
;
133 } else if ((s
->ier
& UART_IER_MSI
) && (s
->msr
& UART_MSR_ANY_DELTA
)) {
134 tmp_iir
= UART_IIR_MSI
;
137 s
->iir
= tmp_iir
| (s
->iir
& 0xF0);
139 if (tmp_iir
!= UART_IIR_NO_INT
) {
140 qemu_irq_raise(s
->irq
);
142 qemu_irq_lower(s
->irq
);
146 static void serial_update_parameters(SerialState
*s
)
149 int parity
, data_bits
, stop_bits
, frame_size
;
150 QEMUSerialSetParams ssp
;
170 data_bits
= (s
->lcr
& 0x03) + 5;
171 frame_size
+= data_bits
+ stop_bits
;
172 /* Zero divisor should give about 3500 baud */
173 speed
= (s
->divider
== 0) ? 3500 : (float) s
->baudbase
/ s
->divider
;
176 ssp
.data_bits
= data_bits
;
177 ssp
.stop_bits
= stop_bits
;
178 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
179 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
180 trace_serial_update_parameters(speed
, parity
, data_bits
, stop_bits
);
183 static void serial_update_msl(SerialState
*s
)
188 timer_del(s
->modem_status_poll
);
190 if (qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
,
191 &flags
) == -ENOTSUP
) {
198 s
->msr
= (flags
& CHR_TIOCM_CTS
) ? s
->msr
| UART_MSR_CTS
: s
->msr
& ~UART_MSR_CTS
;
199 s
->msr
= (flags
& CHR_TIOCM_DSR
) ? s
->msr
| UART_MSR_DSR
: s
->msr
& ~UART_MSR_DSR
;
200 s
->msr
= (flags
& CHR_TIOCM_CAR
) ? s
->msr
| UART_MSR_DCD
: s
->msr
& ~UART_MSR_DCD
;
201 s
->msr
= (flags
& CHR_TIOCM_RI
) ? s
->msr
| UART_MSR_RI
: s
->msr
& ~UART_MSR_RI
;
203 if (s
->msr
!= omsr
) {
205 s
->msr
= s
->msr
| ((s
->msr
>> 4) ^ (omsr
>> 4));
206 /* UART_MSR_TERI only if change was from 1 -> 0 */
207 if ((s
->msr
& UART_MSR_TERI
) && !(omsr
& UART_MSR_RI
))
208 s
->msr
&= ~UART_MSR_TERI
;
209 serial_update_irq(s
);
212 /* The real 16550A apparently has a 250ns response latency to line status changes.
213 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
216 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
217 NANOSECONDS_PER_SECOND
/ 100);
221 static gboolean
serial_watch_cb(GIOChannel
*chan
, GIOCondition cond
,
224 SerialState
*s
= opaque
;
230 static void serial_xmit(SerialState
*s
)
233 assert(!(s
->lsr
& UART_LSR_TEMT
));
234 if (s
->tsr_retry
== 0) {
235 assert(!(s
->lsr
& UART_LSR_THRE
));
237 if (s
->fcr
& UART_FCR_FE
) {
238 assert(!fifo8_is_empty(&s
->xmit_fifo
));
239 s
->tsr
= fifo8_pop(&s
->xmit_fifo
);
240 if (!s
->xmit_fifo
.num
) {
241 s
->lsr
|= UART_LSR_THRE
;
245 s
->lsr
|= UART_LSR_THRE
;
247 if ((s
->lsr
& UART_LSR_THRE
) && !s
->thr_ipending
) {
249 serial_update_irq(s
);
253 if (s
->mcr
& UART_MCR_LOOP
) {
254 /* in loopback mode, say that we just received a char */
255 serial_receive1(s
, &s
->tsr
, 1);
257 int rc
= qemu_chr_fe_write(&s
->chr
, &s
->tsr
, 1);
260 (rc
== -1 && errno
== EAGAIN
)) &&
261 s
->tsr_retry
< MAX_XMIT_RETRY
) {
262 assert(s
->watch_tag
== 0);
264 qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
266 if (s
->watch_tag
> 0) {
274 /* Transmit another byte if it is already available. It is only
275 possible when FIFO is enabled and not empty. */
276 } while (!(s
->lsr
& UART_LSR_THRE
));
278 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
279 s
->lsr
|= UART_LSR_TEMT
;
283 is_load flag means, that value is set while loading VM state
284 and interrupt should not be invoked */
285 static void serial_write_fcr(SerialState
*s
, uint8_t val
)
287 /* Set fcr - val only has the bits that are supposed to "stick" */
290 if (val
& UART_FCR_FE
) {
291 s
->iir
|= UART_IIR_FE
;
292 /* Set recv_fifo trigger Level */
293 switch (val
& 0xC0) {
295 s
->recv_fifo_itl
= 1;
298 s
->recv_fifo_itl
= 4;
301 s
->recv_fifo_itl
= 8;
304 s
->recv_fifo_itl
= 14;
308 s
->iir
&= ~UART_IIR_FE
;
312 static void serial_update_tiocm(SerialState
*s
)
316 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
, &flags
);
318 flags
&= ~(CHR_TIOCM_RTS
| CHR_TIOCM_DTR
);
320 if (s
->mcr
& UART_MCR_RTS
) {
321 flags
|= CHR_TIOCM_RTS
;
323 if (s
->mcr
& UART_MCR_DTR
) {
324 flags
|= CHR_TIOCM_DTR
;
327 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_TIOCM
, &flags
);
330 static void serial_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
333 SerialState
*s
= opaque
;
335 assert(size
== 1 && addr
< 8);
336 trace_serial_write(addr
, val
);
340 if (s
->lcr
& UART_LCR_DLAB
) {
342 s
->divider
= (s
->divider
& 0xff00) | val
;
346 serial_update_parameters(s
);
348 s
->thr
= (uint8_t) val
;
349 if(s
->fcr
& UART_FCR_FE
) {
350 /* xmit overruns overwrite data, so make space if needed */
351 if (fifo8_is_full(&s
->xmit_fifo
)) {
352 fifo8_pop(&s
->xmit_fifo
);
354 fifo8_push(&s
->xmit_fifo
, s
->thr
);
357 s
->lsr
&= ~UART_LSR_THRE
;
358 s
->lsr
&= ~UART_LSR_TEMT
;
359 serial_update_irq(s
);
360 if (s
->tsr_retry
== 0) {
366 if (s
->lcr
& UART_LCR_DLAB
) {
367 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
368 serial_update_parameters(s
);
370 uint8_t changed
= (s
->ier
^ val
) & 0x0f;
372 /* If the backend device is a real serial port, turn polling of the modem
373 * status lines on physical port on or off depending on UART_IER_MSI state.
375 if ((changed
& UART_IER_MSI
) && s
->poll_msl
>= 0) {
376 if (s
->ier
& UART_IER_MSI
) {
378 serial_update_msl(s
);
380 timer_del(s
->modem_status_poll
);
385 /* Turning on the THRE interrupt on IER can trigger the interrupt
386 * if LSR.THRE=1, even if it had been masked before by reading IIR.
387 * This is not in the datasheet, but Windows relies on it. It is
388 * unclear if THRE has to be resampled every time THRI becomes
389 * 1, or only on the rising edge. Bochs does the latter, and Windows
390 * always toggles IER to all zeroes and back to all ones, so do the
393 * If IER.THRI is zero, thr_ipending is not used. Set it to zero
394 * so that the thr_ipending subsection is not migrated.
396 if (changed
& UART_IER_THRI
) {
397 if ((s
->ier
& UART_IER_THRI
) && (s
->lsr
& UART_LSR_THRE
)) {
405 serial_update_irq(s
);
410 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
411 if ((val
^ s
->fcr
) & UART_FCR_FE
) {
412 val
|= UART_FCR_XFR
| UART_FCR_RFR
;
417 if (val
& UART_FCR_RFR
) {
418 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
419 timer_del(s
->fifo_timeout_timer
);
420 s
->timeout_ipending
= 0;
421 fifo8_reset(&s
->recv_fifo
);
424 if (val
& UART_FCR_XFR
) {
425 s
->lsr
|= UART_LSR_THRE
;
427 fifo8_reset(&s
->xmit_fifo
);
430 serial_write_fcr(s
, val
& 0xC9);
431 serial_update_irq(s
);
437 serial_update_parameters(s
);
438 break_enable
= (val
>> 6) & 1;
439 if (break_enable
!= s
->last_break_enable
) {
440 s
->last_break_enable
= break_enable
;
441 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
448 int old_mcr
= s
->mcr
;
450 if (val
& UART_MCR_LOOP
)
453 if (s
->poll_msl
>= 0 && old_mcr
!= s
->mcr
) {
454 serial_update_tiocm(s
);
455 /* Update the modem status after a one-character-send wait-time, since there may be a response
456 from the device/computer at the other end of the serial line */
457 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
);
471 static uint64_t serial_ioport_read(void *opaque
, hwaddr addr
, unsigned size
)
473 SerialState
*s
= opaque
;
476 assert(size
== 1 && addr
< 8);
480 if (s
->lcr
& UART_LCR_DLAB
) {
481 ret
= s
->divider
& 0xff;
483 if(s
->fcr
& UART_FCR_FE
) {
484 ret
= fifo8_is_empty(&s
->recv_fifo
) ?
485 0 : fifo8_pop(&s
->recv_fifo
);
486 if (s
->recv_fifo
.num
== 0) {
487 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
489 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
491 s
->timeout_ipending
= 0;
494 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
496 serial_update_irq(s
);
497 if (!(s
->mcr
& UART_MCR_LOOP
)) {
498 /* in loopback mode, don't receive any data */
499 qemu_chr_fe_accept_input(&s
->chr
);
504 if (s
->lcr
& UART_LCR_DLAB
) {
505 ret
= (s
->divider
>> 8) & 0xff;
512 if ((ret
& UART_IIR_ID
) == UART_IIR_THRI
) {
514 serial_update_irq(s
);
525 /* Clear break and overrun interrupts */
526 if (s
->lsr
& (UART_LSR_BI
|UART_LSR_OE
)) {
527 s
->lsr
&= ~(UART_LSR_BI
|UART_LSR_OE
);
528 serial_update_irq(s
);
532 if (s
->mcr
& UART_MCR_LOOP
) {
533 /* in loopback, the modem output pins are connected to the
535 ret
= (s
->mcr
& 0x0c) << 4;
536 ret
|= (s
->mcr
& 0x02) << 3;
537 ret
|= (s
->mcr
& 0x01) << 5;
539 if (s
->poll_msl
>= 0)
540 serial_update_msl(s
);
542 /* Clear delta bits & msr int after read, if they were set */
543 if (s
->msr
& UART_MSR_ANY_DELTA
) {
545 serial_update_irq(s
);
553 trace_serial_read(addr
, ret
);
557 static int serial_can_receive(SerialState
*s
)
559 if(s
->fcr
& UART_FCR_FE
) {
560 if (s
->recv_fifo
.num
< UART_FIFO_LENGTH
) {
562 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
563 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
564 * effect will be to almost always fill the fifo completely before
565 * the guest has a chance to respond, effectively overriding the ITL
566 * that the guest has set.
568 return (s
->recv_fifo
.num
<= s
->recv_fifo_itl
) ?
569 s
->recv_fifo_itl
- s
->recv_fifo
.num
: 1;
574 return !(s
->lsr
& UART_LSR_DR
);
578 static void serial_receive_break(SerialState
*s
)
581 /* When the LSR_DR is set a null byte is pushed into the fifo */
582 recv_fifo_put(s
, '\0');
583 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
584 serial_update_irq(s
);
587 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
588 static void fifo_timeout_int (void *opaque
) {
589 SerialState
*s
= opaque
;
590 if (s
->recv_fifo
.num
) {
591 s
->timeout_ipending
= 1;
592 serial_update_irq(s
);
596 static int serial_can_receive1(void *opaque
)
598 SerialState
*s
= opaque
;
599 return serial_can_receive(s
);
602 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
604 SerialState
*s
= opaque
;
607 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER
, NULL
);
609 if(s
->fcr
& UART_FCR_FE
) {
611 for (i
= 0; i
< size
; i
++) {
612 recv_fifo_put(s
, buf
[i
]);
614 s
->lsr
|= UART_LSR_DR
;
615 /* call the timeout receive callback in 4 char transmit time */
616 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
618 if (s
->lsr
& UART_LSR_DR
)
619 s
->lsr
|= UART_LSR_OE
;
621 s
->lsr
|= UART_LSR_DR
;
623 serial_update_irq(s
);
626 static void serial_event(void *opaque
, QEMUChrEvent event
)
628 SerialState
*s
= opaque
;
629 if (event
== CHR_EVENT_BREAK
)
630 serial_receive_break(s
);
633 static int serial_pre_save(void *opaque
)
635 SerialState
*s
= opaque
;
636 s
->fcr_vmstate
= s
->fcr
;
641 static int serial_pre_load(void *opaque
)
643 SerialState
*s
= opaque
;
644 s
->thr_ipending
= -1;
649 static int serial_post_load(void *opaque
, int version_id
)
651 SerialState
*s
= opaque
;
653 if (version_id
< 3) {
656 if (s
->thr_ipending
== -1) {
657 s
->thr_ipending
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
660 if (s
->tsr_retry
> 0) {
661 /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */
662 if (s
->lsr
& UART_LSR_TEMT
) {
663 error_report("inconsistent state in serial device "
664 "(tsr empty, tsr_retry=%d", s
->tsr_retry
);
668 if (s
->tsr_retry
> MAX_XMIT_RETRY
) {
669 s
->tsr_retry
= MAX_XMIT_RETRY
;
672 assert(s
->watch_tag
== 0);
673 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
676 /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */
677 if (!(s
->lsr
& UART_LSR_TEMT
)) {
678 error_report("inconsistent state in serial device "
679 "(tsr not empty, tsr_retry=0");
684 s
->last_break_enable
= (s
->lcr
>> 6) & 1;
685 /* Initialize fcr via setter to perform essential side-effects */
686 serial_write_fcr(s
, s
->fcr_vmstate
);
687 serial_update_parameters(s
);
691 static bool serial_thr_ipending_needed(void *opaque
)
693 SerialState
*s
= opaque
;
695 if (s
->ier
& UART_IER_THRI
) {
696 bool expected_value
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
697 return s
->thr_ipending
!= expected_value
;
699 /* LSR.THRE will be sampled again when the interrupt is
700 * enabled. thr_ipending is not used in this case, do
707 static const VMStateDescription vmstate_serial_thr_ipending
= {
708 .name
= "serial/thr_ipending",
710 .minimum_version_id
= 1,
711 .needed
= serial_thr_ipending_needed
,
712 .fields
= (VMStateField
[]) {
713 VMSTATE_INT32(thr_ipending
, SerialState
),
714 VMSTATE_END_OF_LIST()
718 static bool serial_tsr_needed(void *opaque
)
720 SerialState
*s
= (SerialState
*)opaque
;
721 return s
->tsr_retry
!= 0;
724 static const VMStateDescription vmstate_serial_tsr
= {
725 .name
= "serial/tsr",
727 .minimum_version_id
= 1,
728 .needed
= serial_tsr_needed
,
729 .fields
= (VMStateField
[]) {
730 VMSTATE_UINT32(tsr_retry
, SerialState
),
731 VMSTATE_UINT8(thr
, SerialState
),
732 VMSTATE_UINT8(tsr
, SerialState
),
733 VMSTATE_END_OF_LIST()
737 static bool serial_recv_fifo_needed(void *opaque
)
739 SerialState
*s
= (SerialState
*)opaque
;
740 return !fifo8_is_empty(&s
->recv_fifo
);
744 static const VMStateDescription vmstate_serial_recv_fifo
= {
745 .name
= "serial/recv_fifo",
747 .minimum_version_id
= 1,
748 .needed
= serial_recv_fifo_needed
,
749 .fields
= (VMStateField
[]) {
750 VMSTATE_STRUCT(recv_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
751 VMSTATE_END_OF_LIST()
755 static bool serial_xmit_fifo_needed(void *opaque
)
757 SerialState
*s
= (SerialState
*)opaque
;
758 return !fifo8_is_empty(&s
->xmit_fifo
);
761 static const VMStateDescription vmstate_serial_xmit_fifo
= {
762 .name
= "serial/xmit_fifo",
764 .minimum_version_id
= 1,
765 .needed
= serial_xmit_fifo_needed
,
766 .fields
= (VMStateField
[]) {
767 VMSTATE_STRUCT(xmit_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
768 VMSTATE_END_OF_LIST()
772 static bool serial_fifo_timeout_timer_needed(void *opaque
)
774 SerialState
*s
= (SerialState
*)opaque
;
775 return timer_pending(s
->fifo_timeout_timer
);
778 static const VMStateDescription vmstate_serial_fifo_timeout_timer
= {
779 .name
= "serial/fifo_timeout_timer",
781 .minimum_version_id
= 1,
782 .needed
= serial_fifo_timeout_timer_needed
,
783 .fields
= (VMStateField
[]) {
784 VMSTATE_TIMER_PTR(fifo_timeout_timer
, SerialState
),
785 VMSTATE_END_OF_LIST()
789 static bool serial_timeout_ipending_needed(void *opaque
)
791 SerialState
*s
= (SerialState
*)opaque
;
792 return s
->timeout_ipending
!= 0;
795 static const VMStateDescription vmstate_serial_timeout_ipending
= {
796 .name
= "serial/timeout_ipending",
798 .minimum_version_id
= 1,
799 .needed
= serial_timeout_ipending_needed
,
800 .fields
= (VMStateField
[]) {
801 VMSTATE_INT32(timeout_ipending
, SerialState
),
802 VMSTATE_END_OF_LIST()
806 static bool serial_poll_needed(void *opaque
)
808 SerialState
*s
= (SerialState
*)opaque
;
809 return s
->poll_msl
>= 0;
812 static const VMStateDescription vmstate_serial_poll
= {
813 .name
= "serial/poll",
815 .needed
= serial_poll_needed
,
816 .minimum_version_id
= 1,
817 .fields
= (VMStateField
[]) {
818 VMSTATE_INT32(poll_msl
, SerialState
),
819 VMSTATE_TIMER_PTR(modem_status_poll
, SerialState
),
820 VMSTATE_END_OF_LIST()
824 const VMStateDescription vmstate_serial
= {
827 .minimum_version_id
= 2,
828 .pre_save
= serial_pre_save
,
829 .pre_load
= serial_pre_load
,
830 .post_load
= serial_post_load
,
831 .fields
= (VMStateField
[]) {
832 VMSTATE_UINT16_V(divider
, SerialState
, 2),
833 VMSTATE_UINT8(rbr
, SerialState
),
834 VMSTATE_UINT8(ier
, SerialState
),
835 VMSTATE_UINT8(iir
, SerialState
),
836 VMSTATE_UINT8(lcr
, SerialState
),
837 VMSTATE_UINT8(mcr
, SerialState
),
838 VMSTATE_UINT8(lsr
, SerialState
),
839 VMSTATE_UINT8(msr
, SerialState
),
840 VMSTATE_UINT8(scr
, SerialState
),
841 VMSTATE_UINT8_V(fcr_vmstate
, SerialState
, 3),
842 VMSTATE_END_OF_LIST()
844 .subsections
= (const VMStateDescription
*[]) {
845 &vmstate_serial_thr_ipending
,
847 &vmstate_serial_recv_fifo
,
848 &vmstate_serial_xmit_fifo
,
849 &vmstate_serial_fifo_timeout_timer
,
850 &vmstate_serial_timeout_ipending
,
851 &vmstate_serial_poll
,
856 static void serial_reset(void *opaque
)
858 SerialState
*s
= opaque
;
860 if (s
->watch_tag
> 0) {
861 g_source_remove(s
->watch_tag
);
867 s
->iir
= UART_IIR_NO_INT
;
869 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
870 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
871 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
873 s
->mcr
= UART_MCR_OUT2
;
876 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ 9600) * 10;
879 s
->timeout_ipending
= 0;
880 timer_del(s
->fifo_timeout_timer
);
881 timer_del(s
->modem_status_poll
);
883 fifo8_reset(&s
->recv_fifo
);
884 fifo8_reset(&s
->xmit_fifo
);
886 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
889 s
->last_break_enable
= 0;
890 qemu_irq_lower(s
->irq
);
892 serial_update_msl(s
);
893 s
->msr
&= ~UART_MSR_ANY_DELTA
;
896 static int serial_be_change(void *opaque
)
898 SerialState
*s
= opaque
;
900 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
901 serial_event
, serial_be_change
, s
, NULL
, true);
903 serial_update_parameters(s
);
905 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
906 &s
->last_break_enable
);
908 s
->poll_msl
= (s
->ier
& UART_IER_MSI
) ? 1 : 0;
909 serial_update_msl(s
);
911 if (s
->poll_msl
>= 0 && !(s
->mcr
& UART_MCR_LOOP
)) {
912 serial_update_tiocm(s
);
915 if (s
->watch_tag
> 0) {
916 g_source_remove(s
->watch_tag
);
917 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
924 static void serial_realize(DeviceState
*dev
, Error
**errp
)
926 SerialState
*s
= SERIAL(dev
);
928 s
->modem_status_poll
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) serial_update_msl
, s
);
930 s
->fifo_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) fifo_timeout_int
, s
);
931 qemu_register_reset(serial_reset
, s
);
933 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
934 serial_event
, serial_be_change
, s
, NULL
, true);
935 fifo8_create(&s
->recv_fifo
, UART_FIFO_LENGTH
);
936 fifo8_create(&s
->xmit_fifo
, UART_FIFO_LENGTH
);
940 static void serial_unrealize(DeviceState
*dev
)
942 SerialState
*s
= SERIAL(dev
);
944 qemu_chr_fe_deinit(&s
->chr
, false);
946 timer_del(s
->modem_status_poll
);
947 timer_free(s
->modem_status_poll
);
949 timer_del(s
->fifo_timeout_timer
);
950 timer_free(s
->fifo_timeout_timer
);
952 fifo8_destroy(&s
->recv_fifo
);
953 fifo8_destroy(&s
->xmit_fifo
);
955 qemu_unregister_reset(serial_reset
, s
);
958 /* Change the main reference oscillator frequency. */
959 void serial_set_frequency(SerialState
*s
, uint32_t frequency
)
961 s
->baudbase
= frequency
;
962 serial_update_parameters(s
);
965 const MemoryRegionOps serial_io_ops
= {
966 .read
= serial_ioport_read
,
967 .write
= serial_ioport_write
,
969 .min_access_size
= 1,
970 .max_access_size
= 1,
972 .endianness
= DEVICE_LITTLE_ENDIAN
,
975 static Property serial_properties
[] = {
976 DEFINE_PROP_CHR("chardev", SerialState
, chr
),
977 DEFINE_PROP_UINT32("baudbase", SerialState
, baudbase
, 115200),
978 DEFINE_PROP_BOOL("wakeup", SerialState
, wakeup
, false),
979 DEFINE_PROP_END_OF_LIST(),
982 static void serial_class_init(ObjectClass
*klass
, void* data
)
984 DeviceClass
*dc
= DEVICE_CLASS(klass
);
986 /* internal device for serialio/serialmm, not user-creatable */
987 dc
->user_creatable
= false;
988 dc
->realize
= serial_realize
;
989 dc
->unrealize
= serial_unrealize
;
990 device_class_set_props(dc
, serial_properties
);
993 static const TypeInfo serial_info
= {
995 .parent
= TYPE_DEVICE
,
996 .instance_size
= sizeof(SerialState
),
997 .class_init
= serial_class_init
,
1000 /* Memory mapped interface */
1001 static uint64_t serial_mm_read(void *opaque
, hwaddr addr
,
1004 SerialMM
*s
= SERIAL_MM(opaque
);
1005 return serial_ioport_read(&s
->serial
, addr
>> s
->regshift
, 1);
1008 static void serial_mm_write(void *opaque
, hwaddr addr
,
1009 uint64_t value
, unsigned size
)
1011 SerialMM
*s
= SERIAL_MM(opaque
);
1013 serial_ioport_write(&s
->serial
, addr
>> s
->regshift
, value
, 1);
1016 static const MemoryRegionOps serial_mm_ops
[3] = {
1017 [DEVICE_NATIVE_ENDIAN
] = {
1018 .read
= serial_mm_read
,
1019 .write
= serial_mm_write
,
1020 .endianness
= DEVICE_NATIVE_ENDIAN
,
1021 .valid
.max_access_size
= 8,
1022 .impl
.max_access_size
= 8,
1024 [DEVICE_LITTLE_ENDIAN
] = {
1025 .read
= serial_mm_read
,
1026 .write
= serial_mm_write
,
1027 .endianness
= DEVICE_LITTLE_ENDIAN
,
1028 .valid
.max_access_size
= 8,
1029 .impl
.max_access_size
= 8,
1031 [DEVICE_BIG_ENDIAN
] = {
1032 .read
= serial_mm_read
,
1033 .write
= serial_mm_write
,
1034 .endianness
= DEVICE_BIG_ENDIAN
,
1035 .valid
.max_access_size
= 8,
1036 .impl
.max_access_size
= 8,
1040 static void serial_mm_realize(DeviceState
*dev
, Error
**errp
)
1042 SerialMM
*smm
= SERIAL_MM(dev
);
1043 SerialState
*s
= &smm
->serial
;
1045 if (!qdev_realize(DEVICE(s
), NULL
, errp
)) {
1049 memory_region_init_io(&s
->io
, OBJECT(dev
),
1050 &serial_mm_ops
[smm
->endianness
], smm
, "serial",
1051 8 << smm
->regshift
);
1052 sysbus_init_mmio(SYS_BUS_DEVICE(smm
), &s
->io
);
1053 sysbus_init_irq(SYS_BUS_DEVICE(smm
), &smm
->serial
.irq
);
1056 static const VMStateDescription vmstate_serial_mm
= {
1059 .minimum_version_id
= 2,
1060 .fields
= (VMStateField
[]) {
1061 VMSTATE_STRUCT(serial
, SerialMM
, 0, vmstate_serial
, SerialState
),
1062 VMSTATE_END_OF_LIST()
1066 SerialMM
*serial_mm_init(MemoryRegion
*address_space
,
1067 hwaddr base
, int regshift
,
1068 qemu_irq irq
, int baudbase
,
1069 Chardev
*chr
, enum device_endian end
)
1071 SerialMM
*smm
= SERIAL_MM(qdev_new(TYPE_SERIAL_MM
));
1074 qdev_prop_set_uint8(DEVICE(smm
), "regshift", regshift
);
1075 qdev_prop_set_uint32(DEVICE(smm
), "baudbase", baudbase
);
1076 qdev_prop_set_chr(DEVICE(smm
), "chardev", chr
);
1077 qdev_set_legacy_instance_id(DEVICE(smm
), base
, 2);
1078 qdev_prop_set_uint8(DEVICE(smm
), "endianness", end
);
1079 sysbus_realize_and_unref(SYS_BUS_DEVICE(smm
), &error_fatal
);
1081 sysbus_connect_irq(SYS_BUS_DEVICE(smm
), 0, irq
);
1082 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(smm
), 0);
1083 memory_region_add_subregion(address_space
, base
, mr
);
1088 static void serial_mm_instance_init(Object
*o
)
1090 SerialMM
*smm
= SERIAL_MM(o
);
1092 object_initialize_child(o
, "serial", &smm
->serial
, TYPE_SERIAL
);
1094 qdev_alias_all_properties(DEVICE(&smm
->serial
), o
);
1097 static Property serial_mm_properties
[] = {
1099 * Set the spacing between adjacent memory-mapped UART registers.
1100 * Each register will be at (1 << regshift) bytes after the
1103 DEFINE_PROP_UINT8("regshift", SerialMM
, regshift
, 0),
1104 DEFINE_PROP_UINT8("endianness", SerialMM
, endianness
, DEVICE_NATIVE_ENDIAN
),
1105 DEFINE_PROP_END_OF_LIST(),
1108 static void serial_mm_class_init(ObjectClass
*oc
, void *data
)
1110 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1112 device_class_set_props(dc
, serial_mm_properties
);
1113 dc
->realize
= serial_mm_realize
;
1114 dc
->vmsd
= &vmstate_serial_mm
;
1117 static const TypeInfo serial_mm_info
= {
1118 .name
= TYPE_SERIAL_MM
,
1119 .parent
= TYPE_SYS_BUS_DEVICE
,
1120 .class_init
= serial_mm_class_init
,
1121 .instance_init
= serial_mm_instance_init
,
1122 .instance_size
= sizeof(SerialMM
),
1125 static void serial_register_types(void)
1127 type_register_static(&serial_info
);
1128 type_register_static(&serial_mm_info
);
1131 type_init(serial_register_types
)