| blob | 407d3019d1b3d5d87993ec81bff145834a8adc44 |
1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2.1 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
30 %size_23 23:2
31 %dtype_23_13 23:2 13:2
32 %index3_22_19 22:1 19:2
33 %index3_19_11 19:2 11:1
34 %index2_20_11 20:1 11:1
36 # A combination of tsz:imm3 -- extract esize.
37 %tszimm_esz 22:2 5:5 !function=tszimm_esz
38 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
39 %tszimm_shr 22:2 5:5 !function=tszimm_shr
40 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
41 %tszimm_shl 22:2 5:5 !function=tszimm_shl
43 # Similarly for the tszh/tszl pair at 22/16 for zzi
44 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
45 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
46 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
48 # Signed 8-bit immediate, optionally shifted left by 8.
49 %sh8_i8s 5:9 !function=expand_imm_sh8s
50 # Unsigned 8-bit immediate, optionally shifted left by 8.
51 %sh8_i8u 5:9 !function=expand_imm_sh8u
53 # Unsigned load of msz into esz=2, represented as a dtype.
54 %msz_dtype 23:2 !function=msz_dtype
56 # Either a copy of rd (at bit 0), or a different source
57 # as propagated via the MOVPRFX instruction.
58 %reg_movprfx 0:5
60 ###########################################################################
61 # Named attribute sets. These are used to make nice(er) names
62 # when creating helpers common to those for the individual
63 # instruction patterns.
65 &rr_esz rd rn esz
66 &rri rd rn imm
67 &rr_dbm rd rn dbm
68 &rrri rd rn rm imm
69 &rri_esz rd rn imm esz
70 &rrri_esz rd rn rm imm esz
71 &rrr_esz rd rn rm esz
72 &rrx_esz rd rn rm index esz
73 &rpr_esz rd pg rn esz
74 &rpr_s rd pg rn s
75 &rprr_s rd pg rn rm s
76 &rprr_esz rd pg rn rm esz
77 &rrrr_esz rd ra rn rm esz
78 &rrxr_esz rd rn rm ra index esz
79 &rprrr_esz rd pg rn rm ra esz
80 &rpri_esz rd pg rn imm esz
81 &ptrue rd esz pat s
82 &incdec_cnt rd pat esz imm d u
83 &incdec2_cnt rd rn pat esz imm d u
84 &incdec_pred rd pg esz d u
85 &incdec2_pred rd rn pg esz d u
86 &rprr_load rd pg rn rm dtype nreg
87 &rpri_load rd pg rn imm dtype nreg
88 &rprr_store rd pg rn rm msz esz nreg
89 &rpri_store rd pg rn imm msz esz nreg
90 &rprr_gather_load rd pg rn rm esz msz u ff xs scale
91 &rpri_gather_load rd pg rn imm esz msz u ff
92 &rprr_scatter_store rd pg rn rm esz msz xs scale
93 &rpri_scatter_store rd pg rn imm esz msz
95 ###########################################################################
96 # Named instruction formats. These are generally used to
97 # reduce the amount of duplication between instruction patterns.
99 # Two operand with unused vector element size
100 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
102 # Two operand
103 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
104 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
106 # Two operand with governing predicate, flags setting
107 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
108 @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0
110 # Three operand with unused vector element size
111 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
113 # Three predicate operand, with governing predicate, flag setting
114 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
116 # Three operand, vector element size
117 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
118 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
119 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
120 &rrr_esz rn=%reg_movprfx
121 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
122 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
123 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
124 &rri_esz rn=%reg_movprfx
125 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
126 &rri_esz rn=%reg_movprfx
128 # Four operand, vector element size
129 @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \
130 &rrrr_esz ra=%reg_movprfx
132 # Four operand with unused vector element size
133 @rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \
134 &rrrr_esz esz=0 rn=%reg_movprfx
136 # Three operand with "memory" size, aka immediate left shift
137 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
139 # Two register operand, with governing predicate, vector element size
140 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
141 &rprr_esz rn=%reg_movprfx
142 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
143 &rprr_esz rm=%reg_movprfx
144 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
145 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
147 # Three register operand, with governing predicate, vector element size
148 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
149 &rprrr_esz ra=%reg_movprfx
150 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
151 &rprrr_esz rn=%reg_movprfx
152 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
153 &rprrr_esz rn=%reg_movprfx
154 @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz
156 # One register operand, with governing predicate, vector element size
157 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
158 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
159 @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
161 # One register operand, with governing predicate, no vector element size
162 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
164 # Two register operands with a 6-bit signed immediate.
165 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
167 # Two register operand, one immediate operand, with predicate,
168 # element size encoded as TSZHL.
169 @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
170 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
171 @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
172 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
174 # Similarly without predicate.
175 @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
176 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
177 @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
178 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
180 # Two register operand, one immediate operand, with 4-bit predicate.
181 # User must fill in imm.
182 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
183 &rpri_esz rn=%reg_movprfx
185 # Two register operand, one one-bit floating-point operand.
186 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
187 &rpri_esz rn=%reg_movprfx
189 # Two register operand, one encoded bitmask.
190 @rdn_dbm ........ .. .... dbm:13 rd:5 \
191 &rr_dbm rn=%reg_movprfx
193 # Predicate output, vector and immediate input,
194 # controlling predicate, element size.
195 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
196 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
198 # Basic Load/Store with 9-bit immediate offset
199 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
200 &rri imm=%imm9_16_10
201 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
202 &rri imm=%imm9_16_10
204 # One register, pattern, and uint4+1.
205 # User must fill in U and D.
206 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
207 &incdec_cnt imm=%imm4_16_p1
208 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
209 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
211 # One register, predicate.
212 # User must fill in U and D.
213 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
214 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
215 &incdec2_pred rn=%reg_movprfx
217 # Loads; user must fill in NREG.
218 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
219 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
221 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
222 &rprr_load dtype=%msz_dtype
223 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
224 &rpri_load dtype=%msz_dtype
226 # Gather Loads.
227 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
228 &rprr_gather_load xs=2
229 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
230 &rprr_gather_load
231 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
232 &rprr_gather_load
233 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
234 &rprr_gather_load
235 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
236 &rprr_gather_load xs=2
237 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
238 &rprr_gather_load xs=2
239 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
240 &rpri_gather_load
242 # Stores; user must fill in ESZ, MSZ, NREG as needed.
243 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
244 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
245 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
246 &rprr_store nreg=0
247 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
248 &rprr_scatter_store
249 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
250 &rpri_scatter_store
252 # Two registers and a scalar by N-bit index
253 @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
254 &rrx_esz index=%index3_22_19
255 @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz
256 @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz
258 # Two registers and a scalar by N-bit index, alternate
259 @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \
260 &rrx_esz index=%index3_19_11
261 @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \
262 &rrx_esz index=%index2_20_11
264 # Three registers and a scalar by N-bit index
265 @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
266 &rrxr_esz ra=%reg_movprfx index=%index3_22_19
267 @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \
268 &rrxr_esz ra=%reg_movprfx
269 @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \
270 &rrxr_esz ra=%reg_movprfx
272 # Three registers and a scalar by N-bit index, alternate
273 @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \
274 &rrxr_esz ra=%reg_movprfx index=%index3_19_11
275 @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \
276 &rrxr_esz ra=%reg_movprfx index=%index2_20_11
278 ###########################################################################
279 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
281 ### SVE Integer Arithmetic - Binary Predicated Group
283 # SVE bitwise logical vector operations (predicated)
284 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
285 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
286 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
287 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
289 # SVE integer add/subtract vectors (predicated)
290 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
291 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
292 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
294 # SVE integer min/max/difference (predicated)
295 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
296 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
297 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
298 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
299 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
300 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
302 # SVE integer multiply/divide (predicated)
303 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
304 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
305 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
306 # Note that divide requires size >= 2; below 2 is unallocated.
307 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
308 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
309 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
310 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
312 ### SVE Integer Reduction Group
314 # SVE bitwise logical reduction (predicated)
315 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
316 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
317 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
319 # SVE constructive prefix (predicated)
320 MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
321 MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn
323 # SVE integer add reduction (predicated)
324 # Note that saddv requires size != 3.
325 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
326 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
328 # SVE integer min/max reduction (predicated)
329 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
330 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
331 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
332 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
334 ### SVE Shift by Immediate - Predicated Group
336 # SVE bitwise shift by immediate (predicated)
337 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
338 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
339 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
340 ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
342 # SVE bitwise shift by vector (predicated)
343 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
344 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
345 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
346 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
347 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
348 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
350 # SVE bitwise shift by wide elements (predicated)
351 # Note these require size != 3.
352 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
353 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
354 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
356 ### SVE Integer Arithmetic - Unary Predicated Group
358 # SVE unary bit operations (predicated)
359 # Note esz != 0 for FABS and FNEG.
360 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
361 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
362 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
363 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
364 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
365 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
366 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
368 # SVE integer unary operations (predicated)
369 # Note esz > original size for extensions.
370 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
371 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
372 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
373 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
374 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
375 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
376 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
377 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
379 ### SVE Floating Point Compare - Vectors Group
381 # SVE floating-point compare vectors
382 FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
383 FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
384 FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
385 FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
386 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
387 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
388 FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
390 ### SVE Integer Multiply-Add Group
392 # SVE integer multiply-add writing addend (predicated)
393 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
394 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
396 # SVE integer multiply-add writing multiplicand (predicated)
397 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
398 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
400 ### SVE Integer Arithmetic - Unpredicated Group
402 # SVE integer add/subtract vectors (unpredicated)
403 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
404 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
405 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
406 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
407 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
408 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
410 ### SVE Logical - Unpredicated Group
412 # SVE bitwise logical operations (unpredicated)
413 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
414 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
415 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
416 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
418 XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \
419 rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr
421 # SVE2 bitwise ternary operations
422 EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0
423 BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
424 BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0
425 BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
426 BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
427 NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
429 ### SVE Index Generation Group
431 # SVE index generation (immediate start, immediate increment)
432 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
434 # SVE index generation (immediate start, register increment)
435 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
437 # SVE index generation (register start, immediate increment)
438 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
440 # SVE index generation (register start, register increment)
441 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
443 ### SVE Stack Allocation Group
445 # SVE stack frame adjustment
446 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
447 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
449 # SVE stack frame size
450 RDVL 00000100 101 11111 01010 imm:s6 rd:5
452 ### SVE Bitwise Shift - Unpredicated Group
454 # SVE bitwise shift by immediate (unpredicated)
455 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
456 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
457 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
459 # SVE bitwise shift by wide elements (unpredicated)
460 # Note esz != 3
461 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
462 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
463 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
465 ### SVE Compute Vector Address Group
467 # SVE vector address generation
468 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
469 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
470 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
471 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
473 ### SVE Integer Misc - Unpredicated Group
475 # SVE constructive prefix (unpredicated)
476 MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5
478 # SVE floating-point exponential accelerator
479 # Note esz != 0
480 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
482 # SVE floating-point trig select coefficient
483 # Note esz != 0
484 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
486 ### SVE Element Count Group
488 # SVE element count
489 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
491 # SVE inc/dec register by element count
492 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
494 # SVE saturating inc/dec register by element count
495 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
496 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
498 # SVE inc/dec vector by element count
499 # Note this requires esz != 0.
500 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
502 # SVE saturating inc/dec vector by element count
503 # Note these require esz != 0.
504 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
506 ### SVE Bitwise Immediate Group
508 # SVE bitwise logical with immediate (unpredicated)
509 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
510 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
511 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
513 # SVE broadcast bitmask immediate
514 DUPM 00000101 11 0000 dbm:13 rd:5
516 ### SVE Integer Wide Immediate - Predicated Group
518 # SVE copy floating-point immediate (predicated)
519 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
521 # SVE copy integer immediate (predicated)
522 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
523 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
525 ### SVE Permute - Extract Group
527 # SVE extract vector (destructive)
528 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
529 &rrri rn=%reg_movprfx imm=%imm8_16_10
531 # SVE2 extract vector (constructive)
532 EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \
533 &rri imm=%imm8_16_10
535 ### SVE Permute - Unpredicated Group
537 # SVE broadcast general register
538 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
540 # SVE broadcast indexed element
541 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
542 &rri imm=%imm7_22_16
544 # SVE insert SIMD&FP scalar register
545 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
547 # SVE insert general register
548 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
550 # SVE reverse vector elements
551 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
553 # SVE vector table lookup
554 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
556 # SVE unpack vector elements
557 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
559 ### SVE Permute - Predicates Group
561 # SVE permute predicate elements
562 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
563 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
564 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
565 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
566 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
567 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
569 # SVE reverse predicate elements
570 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
572 # SVE unpack predicate elements
573 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
574 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
576 ### SVE Permute - Interleaving Group
578 # SVE permute vector elements
579 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
580 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
581 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
582 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
583 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
584 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
586 ### SVE Permute - Predicated Group
588 # SVE compress active elements
589 # Note esz >= 2
590 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
592 # SVE conditionally broadcast element to vector
593 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
594 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
596 # SVE conditionally copy element to SIMD&FP scalar
597 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
598 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
600 # SVE conditionally copy element to general register
601 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
602 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
604 # SVE copy element to SIMD&FP scalar register
605 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
606 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
608 # SVE copy element to general register
609 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
610 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
612 # SVE copy element from SIMD&FP scalar register
613 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
615 # SVE copy element from general register to vector (predicated)
616 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
618 # SVE reverse within elements
619 # Note esz >= operation size
620 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
621 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
622 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
623 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
625 # SVE vector splice (predicated, destructive)
626 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
628 # SVE2 vector splice (predicated, constructive)
629 SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn
631 ### SVE Select Vectors Group
633 # SVE select vector elements (predicated)
634 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
636 ### SVE Integer Compare - Vectors Group
638 # SVE integer compare_vectors
639 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
640 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
641 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
642 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
643 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
644 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
646 # SVE integer compare with wide elements
647 # Note these require esz != 3.
648 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
649 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
650 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
651 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
652 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
653 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
654 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
655 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
656 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
657 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
659 ### SVE Integer Compare - Unsigned Immediate Group
661 # SVE integer compare with unsigned immediate
662 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
663 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
664 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
665 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
667 ### SVE Integer Compare - Signed Immediate Group
669 # SVE integer compare with signed immediate
670 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
671 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
672 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
673 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
674 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
675 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
677 ### SVE Predicate Logical Operations Group
679 # SVE predicate logical operations
680 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
681 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
682 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
683 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
684 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
685 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
686 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
687 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
689 ### SVE Predicate Misc Group
691 # SVE predicate test
692 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
694 # SVE predicate initialize
695 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
697 # SVE initialize FFR
698 SETFFR 00100101 0010 1100 1001 0000 0000 0000
700 # SVE zero predicate register
701 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
703 # SVE predicate read from FFR (predicated)
704 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
706 # SVE predicate read from FFR (unpredicated)
707 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
709 # SVE FFR write from predicate (WRFFR)
710 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
712 # SVE predicate first active
713 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
715 # SVE predicate next active
716 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
718 ### SVE Partition Break Group
720 # SVE propagate break from previous partition
721 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
722 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
724 # SVE partition break condition
725 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
726 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
727 BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
728 BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
730 # SVE propagate break to next partition
731 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
733 ### SVE Predicate Count Group
735 # SVE predicate count
736 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
738 # SVE inc/dec register by predicate count
739 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
741 # SVE inc/dec vector by predicate count
742 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
744 # SVE saturating inc/dec register by predicate count
745 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
746 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
748 # SVE saturating inc/dec vector by predicate count
749 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
751 ### SVE Integer Compare - Scalars Group
753 # SVE conditionally terminate scalars
754 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
756 # SVE integer compare scalar count and limit
757 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4
759 # SVE2 pointer conflict compare
760 WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
762 ### SVE Integer Wide Immediate - Unpredicated Group
764 # SVE broadcast floating-point immediate (unpredicated)
765 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
767 # SVE broadcast integer immediate (unpredicated)
768 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
770 # SVE integer add/subtract immediate (unpredicated)
771 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
772 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
773 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
774 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
775 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
776 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
777 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
779 # SVE integer min/max immediate (unpredicated)
780 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
781 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
782 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
783 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
785 # SVE integer multiply immediate (unpredicated)
786 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
788 # SVE integer dot product (unpredicated)
789 DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \
790 ra=%reg_movprfx
792 #### SVE Multiply - Indexed
794 # SVE integer dot product (indexed)
795 SDOT_zzxw_s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2
796 SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3
797 UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
798 UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
800 # SVE2 integer multiply-add (indexed)
801 MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1
802 MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2
803 MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3
804 MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1
805 MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2
806 MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3
808 # SVE2 saturating multiply-add high (indexed)
809 SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1
810 SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2
811 SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3
812 SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1
813 SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2
814 SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3
816 # SVE2 saturating multiply-add (indexed)
817 SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2
818 SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3
819 SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2
820 SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3
821 SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2
822 SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3
823 SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2
824 SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3
826 # SVE2 saturating multiply (indexed)
827 SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2
828 SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3
829 SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2
830 SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3
832 # SVE2 integer multiply (indexed)
833 MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1
834 MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2
835 MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3
837 # SVE floating-point complex add (predicated)
838 FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \
839 rn=%reg_movprfx
841 # SVE floating-point complex multiply-add (predicated)
842 FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \
843 ra=%reg_movprfx
845 # SVE floating-point complex multiply-add (indexed)
846 FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \
847 ra=%reg_movprfx esz=1
848 FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \
849 ra=%reg_movprfx esz=2
851 ### SVE FP Multiply-Add Indexed Group
853 # SVE floating-point multiply-add (indexed)
854 FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1
855 FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2
856 FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3
857 FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1
858 FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
859 FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
861 ### SVE FP Multiply Indexed Group
863 # SVE floating-point multiply (indexed)
864 FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1
865 FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2
866 FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3
868 ### SVE FP Fast Reduction Group
870 FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn
871 FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn
872 FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
873 FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
874 FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
876 ## SVE Floating Point Unary Operations - Unpredicated Group
878 FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
879 FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
881 ### SVE FP Compare with Zero Group
883 FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
884 FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
885 FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
886 FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
887 FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
888 FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
890 ### SVE FP Accumulating Reduction Group
892 # SVE floating-point serial reduction (predicated)
893 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
895 ### SVE Floating Point Arithmetic - Unpredicated Group
897 # SVE floating-point arithmetic (unpredicated)
898 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
899 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
900 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
901 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
902 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
903 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
905 ### SVE FP Arithmetic Predicated Group
907 # SVE floating-point arithmetic (predicated)
908 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
909 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
910 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
911 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
912 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
913 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
914 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
915 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
916 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
917 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
918 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
919 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
920 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
922 # SVE floating-point arithmetic with immediate (predicated)
923 FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
924 FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
925 FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
926 FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
927 FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
928 FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
929 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
930 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
932 # SVE floating-point trig multiply-add coefficient
933 FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx
935 ### SVE FP Multiply-Add Group
937 # SVE floating-point multiply-accumulate writing addend
938 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
939 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
940 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
941 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
943 # SVE floating-point multiply-accumulate writing multiplicand
944 # Alter the operand extraction order and reuse the helpers from above.
945 # FMAD, FMSB, FNMAD, FNMS
946 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
947 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
948 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
949 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
951 ### SVE FP Unary Operations Predicated Group
953 # SVE floating-point convert precision
954 FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
955 FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
956 FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
957 FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
958 FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
959 FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
961 # SVE floating-point convert to integer
962 FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
963 FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
964 FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
965 FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
966 FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
967 FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
968 FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
969 FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
970 FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
971 FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
972 FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
973 FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
974 FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
975 FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
977 # SVE floating-point round to integral value
978 FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
979 FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
980 FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
981 FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
982 FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
983 FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
984 FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
986 # SVE floating-point unary operations
987 FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
988 FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
990 # SVE integer convert to floating-point
991 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
992 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
993 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
994 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
995 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
996 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
997 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
999 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
1000 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1001 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1002 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1003 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
1004 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1005 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1007 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
1009 # SVE load predicate register
1010 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
1012 # SVE load vector register
1013 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
1015 # SVE load and broadcast element
1016 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
1017 &rpri_load dtype=%dtype_23_13 nreg=0
1019 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
1020 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
1021 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
1022 @rprr_g_load_xs_u esz=2 msz=0 scale=0
1023 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
1024 @rprr_g_load_xs_u_sc esz=2 msz=1
1025 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
1026 @rprr_g_load_xs_sc esz=2 msz=2 u=1
1028 # SVE 32-bit gather load (vector plus immediate)
1029 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
1030 @rpri_g_load esz=2
1032 ### SVE Memory Contiguous Load Group
1034 # SVE contiguous load (scalar plus scalar)
1035 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
1037 # SVE contiguous first-fault load (scalar plus scalar)
1038 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
1040 # SVE contiguous load (scalar plus immediate)
1041 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
1043 # SVE contiguous non-fault load (scalar plus immediate)
1044 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
1046 # SVE contiguous non-temporal load (scalar plus scalar)
1047 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
1048 # SVE load multiple structures (scalar plus scalar)
1049 # LD2B, LD2H, LD2W, LD2D; etc.
1050 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
1052 # SVE contiguous non-temporal load (scalar plus immediate)
1053 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
1054 # SVE load multiple structures (scalar plus immediate)
1055 # LD2B, LD2H, LD2W, LD2D; etc.
1056 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
1058 # SVE load and broadcast quadword (scalar plus scalar)
1059 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
1060 @rprr_load_msz nreg=0
1062 # SVE load and broadcast quadword (scalar plus immediate)
1063 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
1064 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
1065 @rpri_load_msz nreg=0
1067 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
1068 PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
1070 # SVE 32-bit gather prefetch (vector plus immediate)
1071 PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
1073 # SVE contiguous prefetch (scalar plus immediate)
1074 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
1076 # SVE contiguous prefetch (scalar plus scalar)
1077 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
1079 ### SVE Memory 64-bit Gather Group
1081 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
1082 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
1083 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
1084 @rprr_g_load_xs_u esz=3 msz=0 scale=0
1085 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
1086 @rprr_g_load_xs_u_sc esz=3 msz=1
1087 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
1088 @rprr_g_load_xs_u_sc esz=3 msz=2
1089 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
1090 @rprr_g_load_xs_sc esz=3 msz=3 u=1
1092 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
1093 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
1094 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
1095 @rprr_g_load_u esz=3 msz=0 scale=0
1096 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
1097 @rprr_g_load_u_sc esz=3 msz=1
1098 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
1099 @rprr_g_load_u_sc esz=3 msz=2
1100 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
1101 @rprr_g_load_sc esz=3 msz=3 u=1
1103 # SVE 64-bit gather load (vector plus immediate)
1104 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
1105 @rpri_g_load esz=3
1107 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
1108 PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
1110 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
1111 PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
1113 # SVE 64-bit gather prefetch (vector plus immediate)
1114 PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
1116 ### SVE Memory Store Group
1118 # SVE store predicate register
1119 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
1121 # SVE store vector register
1122 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
1124 # SVE contiguous store (scalar plus immediate)
1125 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1126 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
1127 @rpri_store_msz nreg=0
1129 # SVE contiguous store (scalar plus scalar)
1130 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1131 # Enumerate msz lest we conflict with STR_zri.
1132 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
1133 @rprr_store_esz_n0 msz=0
1134 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
1135 @rprr_store_esz_n0 msz=1
1136 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
1137 @rprr_store_esz_n0 msz=2
1138 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
1139 @rprr_store msz=3 esz=3 nreg=0
1141 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
1142 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
1143 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
1144 @rpri_store_msz esz=%size_23
1146 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
1147 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
1148 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
1149 @rprr_store esz=%size_23
1151 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
1152 # Require msz > 0 && msz <= esz.
1153 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
1154 @rprr_scatter_store xs=0 esz=2 scale=1
1155 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
1156 @rprr_scatter_store xs=1 esz=2 scale=1
1158 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
1159 # Require msz <= esz.
1160 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
1161 @rprr_scatter_store xs=0 esz=2 scale=0
1162 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
1163 @rprr_scatter_store xs=1 esz=2 scale=0
1165 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
1166 # Require msz > 0
1167 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
1168 @rprr_scatter_store xs=2 esz=3 scale=1
1170 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
1171 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
1172 @rprr_scatter_store xs=2 esz=3 scale=0
1174 # SVE 64-bit scatter store (vector plus immediate)
1175 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
1176 @rpri_scatter_store esz=3
1178 # SVE 32-bit scatter store (vector plus immediate)
1179 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
1180 @rpri_scatter_store esz=2
1182 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
1183 # Require msz > 0
1184 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
1185 @rprr_scatter_store xs=0 esz=3 scale=1
1186 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
1187 @rprr_scatter_store xs=1 esz=3 scale=1
1189 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
1190 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
1191 @rprr_scatter_store xs=0 esz=3 scale=0
1192 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
1193 @rprr_scatter_store xs=1 esz=3 scale=0
1195 #### SVE2 Support
1197 ### SVE2 Integer Multiply - Unpredicated
1199 # SVE2 integer multiply vectors (unpredicated)
1200 MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm
1201 SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm
1202 UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm
1203 PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0
1205 # SVE2 signed saturating doubling multiply high (unpredicated)
1206 SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm
1207 SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm
1209 ### SVE2 Integer - Predicated
1211 SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn
1212 UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn
1214 ### SVE2 integer unary operations (predicated)
1216 URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
1217 URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
1218 SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
1219 SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
1221 ### SVE2 saturating/rounding bitwise shift left (predicated)
1223 SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm
1224 URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm
1225 SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR
1226 URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR
1228 SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm
1229 UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm
1230 SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR
1231 UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR
1233 SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm
1234 UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm
1235 SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR
1236 UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR
1238 ### SVE2 integer halving add/subtract (predicated)
1240 SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
1241 UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
1242 SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm
1243 UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
1244 SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm
1245 URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm
1246 SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR
1247 UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR
1249 ### SVE2 integer pairwise arithmetic
1251 ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm
1252 SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm
1253 UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm
1254 SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm
1255 UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm
1257 ### SVE2 saturating add/subtract (predicated)
1259 SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
1260 UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
1261 SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm
1262 UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
1263 SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm
1264 USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm
1265 SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR
1266 UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR
1268 #### SVE2 Widening Integer Arithmetic
1270 ## SVE2 integer add/subtract long
1272 SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm
1273 SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm
1274 UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm
1275 UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm
1277 SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm
1278 SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm
1279 USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm
1280 USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm
1282 SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm
1283 SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm
1284 UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm
1285 UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm
1287 ## SVE2 integer add/subtract interleaved long
1289 SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm
1290 SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm
1291 SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm
1293 ## SVE2 integer add/subtract wide
1295 SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm
1296 SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm
1297 UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm
1298 UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm
1300 SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm
1301 SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm
1302 USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm
1303 USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm
1305 ## SVE2 integer multiply long
1307 SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm
1308 SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm
1309 PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm
1310 PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm
1311 SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm
1312 SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm
1313 UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm
1314 UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm
1316 ## SVE2 bitwise shift left long
1318 # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb.
1319 SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl
1320 SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl
1321 USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl
1322 USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl
1324 ## SVE2 bitwise exclusive-or interleaved
1326 EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm
1327 EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm
1329 ## SVE2 bitwise permute
1331 BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm
1332 BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm
1333 BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm
1335 #### SVE2 Accumulate
1337 ## SVE2 complex integer add
1339 CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm
1340 CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm
1341 SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm
1342 SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm
1344 ## SVE2 integer absolute difference and accumulate long
1346 SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm
1347 SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm
1348 UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm
1349 UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm
1351 ## SVE2 integer add/subtract long with carry
1353 # ADC and SBC decoded via size in helper dispatch.
1354 ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
1355 ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
1357 ## SVE2 bitwise shift right and accumulate
1359 # TODO: Use @rda and %reg_movprfx here.
1360 SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr
1361 USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr
1362 SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr
1363 URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr
1365 ## SVE2 bitwise shift and insert
1367 SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr
1368 SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl
1370 ## SVE2 integer absolute difference and accumulate
1372 # TODO: Use @rda and %reg_movprfx here.
1373 SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm
1374 UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm
1376 #### SVE2 Narrowing
1378 ## SVE2 saturating extract narrow
1380 # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0.
1381 SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl
1382 SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl
1383 UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl
1384 UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl
1385 SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl
1386 SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl
1388 ## SVE2 bitwise shift right narrow
1390 # Bit 23 == 0 is handled by esz > 0 in the translator.
1391 SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr
1392 SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr
1393 SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr
1394 SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr
1395 SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr
1396 SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr
1397 RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr
1398 RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr
1399 SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr
1400 SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr
1401 SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr
1402 SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr
1403 UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr
1404 UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr
1405 UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr
1406 UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr
1408 ## SVE2 integer add/subtract narrow high part
1410 ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
1411 ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
1412 RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
1413 RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
1414 SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
1415 SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
1416 RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm
1417 RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm
1419 ### SVE2 Character Match
1421 MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
1422 NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
1424 ### SVE2 Histogram Computation
1426 HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm
1427 HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm
1429 ## SVE2 floating-point pairwise operations
1431 FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm
1432 FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm
1433 FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm
1434 FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm
1435 FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm
1437 #### SVE Integer Multiply-Add (unpredicated)
1439 ## SVE2 saturating multiply-add long
1441 SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm
1442 SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm
1443 SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm
1444 SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm
1446 ## SVE2 saturating multiply-add interleaved long
1448 SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm
1449 SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm
1451 ## SVE2 saturating multiply-add high
1453 SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm
1454 SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm
1456 ## SVE2 integer multiply-add long
1458 SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm
1459 SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm
1460 UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm
1461 UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm
1462 SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm
1463 SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm
1464 UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm
1465 UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm
1467 ## SVE2 complex integer multiply-add
1469 CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
1470 SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
1472 ### SVE2 floating point matrix multiply accumulate
1474 FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm
1476 ### SVE2 Memory Gather Load Group
1478 # SVE2 64-bit gather non-temporal load
1479 # (scalar plus unpacked 32-bit unscaled offsets)
1480 LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
1481 &rprr_gather_load xs=0 esz=3 scale=0 ff=0
1483 # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
1484 LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
1485 &rprr_gather_load xs=0 esz=2 scale=0 ff=0
1487 ### SVE2 Memory Store Group
1489 # SVE2 64-bit scatter non-temporal store (vector plus scalar)
1490 STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
1491 @rprr_scatter_store xs=2 esz=3 scale=0
1493 # SVE2 32-bit scatter non-temporal store (vector plus scalar)
1494 STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
1495 @rprr_scatter_store xs=0 esz=2 scale=0