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i386: hvf: Drop regs in HVFX86EmulatorState
[qemu/ar7.git] / target / i386 / hvf / x86_emu.c
blob1ad2c30e16ba6eab61b0bf4db35ab232b4a25cfb
1 /*
2 * Copyright (C) 2016 Veertu Inc,
3 * Copyright (C) 2017 Google Inc,
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU Lesser General Public
7 * License as published by the Free Software Foundation; either
8 * version 2 of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 /////////////////////////////////////////////////////////////////////////
20 //
21 // Copyright (C) 2001-2012 The Bochs Project
22 //
23 // This library is free software; you can redistribute it and/or
24 // modify it under the terms of the GNU Lesser General Public
25 // License as published by the Free Software Foundation; either
26 // version 2 of the License, or (at your option) any later version.
27 //
28 // This library is distributed in the hope that it will be useful,
29 // but WITHOUT ANY WARRANTY; without even the implied warranty of
30 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
31 // Lesser General Public License for more details.
32 //
33 // You should have received a copy of the GNU Lesser General Public
34 // License along with this library; if not, write to the Free Software
35 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
36 /////////////////////////////////////////////////////////////////////////
37
38 #include "qemu/osdep.h"
39 #include "panic.h"
40 #include "qemu-common.h"
41 #include "x86_decode.h"
42 #include "x86.h"
43 #include "x86_emu.h"
44 #include "x86_mmu.h"
45 #include "x86_flags.h"
46 #include "vmcs.h"
47 #include "vmx.h"
48
49 void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
50 int direction, int size, uint32_t count);
51
52 #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
53 { \
54 fetch_operands(env, decode, 2, true, true, false); \
55 switch (decode->operand_size) { \
56 case 1: \
57 { \
58 uint8_t v1 = (uint8_t)decode->op[0].val; \
59 uint8_t v2 = (uint8_t)decode->op[1].val; \
60 uint8_t diff = v1 cmd v2; \
61 if (save_res) { \
62 write_val_ext(env, decode->op[0].ptr, diff, 1); \
63 } \
64 FLAGS_FUNC##8(env, v1, v2, diff); \
65 break; \
66 } \
67 case 2: \
68 { \
69 uint16_t v1 = (uint16_t)decode->op[0].val; \
70 uint16_t v2 = (uint16_t)decode->op[1].val; \
71 uint16_t diff = v1 cmd v2; \
72 if (save_res) { \
73 write_val_ext(env, decode->op[0].ptr, diff, 2); \
74 } \
75 FLAGS_FUNC##16(env, v1, v2, diff); \
76 break; \
77 } \
78 case 4: \
79 { \
80 uint32_t v1 = (uint32_t)decode->op[0].val; \
81 uint32_t v2 = (uint32_t)decode->op[1].val; \
82 uint32_t diff = v1 cmd v2; \
83 if (save_res) { \
84 write_val_ext(env, decode->op[0].ptr, diff, 4); \
85 } \
86 FLAGS_FUNC##32(env, v1, v2, diff); \
87 break; \
88 } \
89 default: \
90 VM_PANIC("bad size\n"); \
91 } \
92 } \
93
94 target_ulong read_reg(CPUX86State *env, int reg, int size)
95 {
96 switch (size) {
97 case 1:
98 return x86_reg(env, reg)->lx;
99 case 2:
100 return x86_reg(env, reg)->rx;
101 case 4:
102 return x86_reg(env, reg)->erx;
103 case 8:
104 return x86_reg(env, reg)->rrx;
105 default:
106 abort();
107 }
108 return 0;
109 }
110
111 void write_reg(CPUX86State *env, int reg, target_ulong val, int size)
112 {
113 switch (size) {
114 case 1:
115 x86_reg(env, reg)->lx = val;
116 break;
117 case 2:
118 x86_reg(env, reg)->rx = val;
119 break;
120 case 4:
121 x86_reg(env, reg)->rrx = (uint32_t)val;
122 break;
123 case 8:
124 x86_reg(env, reg)->rrx = val;
125 break;
126 default:
127 abort();
128 }
129 }
130
131 target_ulong read_val_from_reg(target_ulong reg_ptr, int size)
132 {
133 target_ulong val;
134
135 switch (size) {
136 case 1:
137 val = *(uint8_t *)reg_ptr;
138 break;
139 case 2:
140 val = *(uint16_t *)reg_ptr;
141 break;
142 case 4:
143 val = *(uint32_t *)reg_ptr;
144 break;
145 case 8:
146 val = *(uint64_t *)reg_ptr;
147 break;
148 default:
149 abort();
150 }
151 return val;
152 }
153
154 void write_val_to_reg(target_ulong reg_ptr, target_ulong val, int size)
155 {
156 switch (size) {
157 case 1:
158 *(uint8_t *)reg_ptr = val;
159 break;
160 case 2:
161 *(uint16_t *)reg_ptr = val;
162 break;
163 case 4:
164 *(uint64_t *)reg_ptr = (uint32_t)val;
165 break;
166 case 8:
167 *(uint64_t *)reg_ptr = val;
168 break;
169 default:
170 abort();
171 }
172 }
173
174 static bool is_host_reg(struct CPUX86State *env, target_ulong ptr)
175 {
176 return (ptr - (target_ulong)&env->regs[0]) < sizeof(env->regs);
177 }
178
179 void write_val_ext(struct CPUX86State *env, target_ulong ptr, target_ulong val, int size)
180 {
181 if (is_host_reg(env, ptr)) {
182 write_val_to_reg(ptr, val, size);
183 return;
184 }
185 vmx_write_mem(env_cpu(env), ptr, &val, size);
186 }
187
188 uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes)
189 {
190 vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, ptr, bytes);
191 return env->hvf_emul->mmio_buf;
192 }
193
194
195 target_ulong read_val_ext(struct CPUX86State *env, target_ulong ptr, int size)
196 {
197 target_ulong val;
198 uint8_t *mmio_ptr;
199
200 if (is_host_reg(env, ptr)) {
201 return read_val_from_reg(ptr, size);
202 }
203
204 mmio_ptr = read_mmio(env, ptr, size);
205 switch (size) {
206 case 1:
207 val = *(uint8_t *)mmio_ptr;
208 break;
209 case 2:
210 val = *(uint16_t *)mmio_ptr;
211 break;
212 case 4:
213 val = *(uint32_t *)mmio_ptr;
214 break;
215 case 8:
216 val = *(uint64_t *)mmio_ptr;
217 break;
218 default:
219 VM_PANIC("bad size\n");
220 break;
221 }
222 return val;
223 }
224
225 static void fetch_operands(struct CPUX86State *env, struct x86_decode *decode,
226 int n, bool val_op0, bool val_op1, bool val_op2)
227 {
228 int i;
229 bool calc_val[3] = {val_op0, val_op1, val_op2};
230
231 for (i = 0; i < n; i++) {
232 switch (decode->op[i].type) {
233 case X86_VAR_IMMEDIATE:
234 break;
235 case X86_VAR_REG:
236 VM_PANIC_ON(!decode->op[i].ptr);
237 if (calc_val[i]) {
238 decode->op[i].val = read_val_from_reg(decode->op[i].ptr,
239 decode->operand_size);
240 }
241 break;
242 case X86_VAR_RM:
243 calc_modrm_operand(env, decode, &decode->op[i]);
244 if (calc_val[i]) {
245 decode->op[i].val = read_val_ext(env, decode->op[i].ptr,
246 decode->operand_size);
247 }
248 break;
249 case X86_VAR_OFFSET:
250 decode->op[i].ptr = decode_linear_addr(env, decode,
251 decode->op[i].ptr,
252 R_DS);
253 if (calc_val[i]) {
254 decode->op[i].val = read_val_ext(env, decode->op[i].ptr,
255 decode->operand_size);
256 }
257 break;
258 default:
259 break;
260 }
261 }
262 }
263
264 static void exec_mov(struct CPUX86State *env, struct x86_decode *decode)
265 {
266 fetch_operands(env, decode, 2, false, true, false);
267 write_val_ext(env, decode->op[0].ptr, decode->op[1].val,
268 decode->operand_size);
269
270 env->eip += decode->len;
271 }
272
273 static void exec_add(struct CPUX86State *env, struct x86_decode *decode)
274 {
275 EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true);
276 env->eip += decode->len;
277 }
278
279 static void exec_or(struct CPUX86State *env, struct x86_decode *decode)
280 {
281 EXEC_2OP_FLAGS_CMD(env, decode, |, SET_FLAGS_OSZAPC_LOGIC, true);
282 env->eip += decode->len;
283 }
284
285 static void exec_adc(struct CPUX86State *env, struct x86_decode *decode)
286 {
287 EXEC_2OP_FLAGS_CMD(env, decode, +get_CF(env)+, SET_FLAGS_OSZAPC_ADD, true);
288 env->eip += decode->len;
289 }
290
291 static void exec_sbb(struct CPUX86State *env, struct x86_decode *decode)
292 {
293 EXEC_2OP_FLAGS_CMD(env, decode, -get_CF(env)-, SET_FLAGS_OSZAPC_SUB, true);
294 env->eip += decode->len;
295 }
296
297 static void exec_and(struct CPUX86State *env, struct x86_decode *decode)
298 {
299 EXEC_2OP_FLAGS_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, true);
300 env->eip += decode->len;
301 }
302
303 static void exec_sub(struct CPUX86State *env, struct x86_decode *decode)
304 {
305 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, true);
306 env->eip += decode->len;
307 }
308
309 static void exec_xor(struct CPUX86State *env, struct x86_decode *decode)
310 {
311 EXEC_2OP_FLAGS_CMD(env, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true);
312 env->eip += decode->len;
313 }
314
315 static void exec_neg(struct CPUX86State *env, struct x86_decode *decode)
316 {
317 /*EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/
318 int32_t val;
319 fetch_operands(env, decode, 2, true, true, false);
320
321 val = 0 - sign(decode->op[1].val, decode->operand_size);
322 write_val_ext(env, decode->op[1].ptr, val, decode->operand_size);
323
324 if (4 == decode->operand_size) {
325 SET_FLAGS_OSZAPC_SUB32(env, 0, 0 - val, val);
326 } else if (2 == decode->operand_size) {
327 SET_FLAGS_OSZAPC_SUB16(env, 0, 0 - val, val);
328 } else if (1 == decode->operand_size) {
329 SET_FLAGS_OSZAPC_SUB8(env, 0, 0 - val, val);
330 } else {
331 VM_PANIC("bad op size\n");
332 }
333
334 /*lflags_to_rflags(env);*/
335 env->eip += decode->len;
336 }
337
338 static void exec_cmp(struct CPUX86State *env, struct x86_decode *decode)
339 {
340 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
341 env->eip += decode->len;
342 }
343
344 static void exec_inc(struct CPUX86State *env, struct x86_decode *decode)
345 {
346 decode->op[1].type = X86_VAR_IMMEDIATE;
347 decode->op[1].val = 0;
348
349 EXEC_2OP_FLAGS_CMD(env, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
350
351 env->eip += decode->len;
352 }
353
354 static void exec_dec(struct CPUX86State *env, struct x86_decode *decode)
355 {
356 decode->op[1].type = X86_VAR_IMMEDIATE;
357 decode->op[1].val = 0;
358
359 EXEC_2OP_FLAGS_CMD(env, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
360 env->eip += decode->len;
361 }
362
363 static void exec_tst(struct CPUX86State *env, struct x86_decode *decode)
364 {
365 EXEC_2OP_FLAGS_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, false);
366 env->eip += decode->len;
367 }
368
369 static void exec_not(struct CPUX86State *env, struct x86_decode *decode)
370 {
371 fetch_operands(env, decode, 1, true, false, false);
372
373 write_val_ext(env, decode->op[0].ptr, ~decode->op[0].val,
374 decode->operand_size);
375 env->eip += decode->len;
376 }
377
378 void exec_movzx(struct CPUX86State *env, struct x86_decode *decode)
379 {
380 int src_op_size;
381 int op_size = decode->operand_size;
382
383 fetch_operands(env, decode, 1, false, false, false);
384
385 if (0xb6 == decode->opcode[1]) {
386 src_op_size = 1;
387 } else {
388 src_op_size = 2;
389 }
390 decode->operand_size = src_op_size;
391 calc_modrm_operand(env, decode, &decode->op[1]);
392 decode->op[1].val = read_val_ext(env, decode->op[1].ptr, src_op_size);
393 write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size);
394
395 env->eip += decode->len;
396 }
397
398 static void exec_out(struct CPUX86State *env, struct x86_decode *decode)
399 {
400 switch (decode->opcode[0]) {
401 case 0xe6:
402 hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 1, 1, 1);
403 break;
404 case 0xe7:
405 hvf_handle_io(env_cpu(env), decode->op[0].val, &RAX(env), 1,
406 decode->operand_size, 1);
407 break;
408 case 0xee:
409 hvf_handle_io(env_cpu(env), DX(env), &AL(env), 1, 1, 1);
410 break;
411 case 0xef:
412 hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1,
413 decode->operand_size, 1);
414 break;
415 default:
416 VM_PANIC("Bad out opcode\n");
417 break;
418 }
419 env->eip += decode->len;
420 }
421
422 static void exec_in(struct CPUX86State *env, struct x86_decode *decode)
423 {
424 target_ulong val = 0;
425 switch (decode->opcode[0]) {
426 case 0xe4:
427 hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 0, 1, 1);
428 break;
429 case 0xe5:
430 hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0,
431 decode->operand_size, 1);
432 if (decode->operand_size == 2) {
433 AX(env) = val;
434 } else {
435 RAX(env) = (uint32_t)val;
436 }
437 break;
438 case 0xec:
439 hvf_handle_io(env_cpu(env), DX(env), &AL(env), 0, 1, 1);
440 break;
441 case 0xed:
442 hvf_handle_io(env_cpu(env), DX(env), &val, 0, decode->operand_size, 1);
443 if (decode->operand_size == 2) {
444 AX(env) = val;
445 } else {
446 RAX(env) = (uint32_t)val;
447 }
448
449 break;
450 default:
451 VM_PANIC("Bad in opcode\n");
452 break;
453 }
454
455 env->eip += decode->len;
456 }
457
458 static inline void string_increment_reg(struct CPUX86State *env, int reg,
459 struct x86_decode *decode)
460 {
461 target_ulong val = read_reg(env, reg, decode->addressing_size);
462 if (env->eflags & DF_MASK) {
463 val -= decode->operand_size;
464 } else {
465 val += decode->operand_size;
466 }
467 write_reg(env, reg, val, decode->addressing_size);
468 }
469
470 static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode,
471 void (*func)(struct CPUX86State *env,
472 struct x86_decode *ins), int rep)
473 {
474 target_ulong rcx = read_reg(env, R_ECX, decode->addressing_size);
475 while (rcx--) {
476 func(env, decode);
477 write_reg(env, R_ECX, rcx, decode->addressing_size);
478 if ((PREFIX_REP == rep) && !get_ZF(env)) {
479 break;
480 }
481 if ((PREFIX_REPN == rep) && get_ZF(env)) {
482 break;
483 }
484 }
485 }
486
487 static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode)
488 {
489 target_ulong addr = linear_addr_size(env_cpu(env), RDI(env),
490 decode->addressing_size, R_ES);
491
492 hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 0,
493 decode->operand_size, 1);
494 vmx_write_mem(env_cpu(env), addr, env->hvf_emul->mmio_buf,
495 decode->operand_size);
496
497 string_increment_reg(env, R_EDI, decode);
498 }
499
500 static void exec_ins(struct CPUX86State *env, struct x86_decode *decode)
501 {
502 if (decode->rep) {
503 string_rep(env, decode, exec_ins_single, 0);
504 } else {
505 exec_ins_single(env, decode);
506 }
507
508 env->eip += decode->len;
509 }
510
511 static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode)
512 {
513 target_ulong addr = decode_linear_addr(env, decode, RSI(env), R_DS);
514
515 vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, addr,
516 decode->operand_size);
517 hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 1,
518 decode->operand_size, 1);
519
520 string_increment_reg(env, R_ESI, decode);
521 }
522
523 static void exec_outs(struct CPUX86State *env, struct x86_decode *decode)
524 {
525 if (decode->rep) {
526 string_rep(env, decode, exec_outs_single, 0);
527 } else {
528 exec_outs_single(env, decode);
529 }
530
531 env->eip += decode->len;
532 }
533
534 static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode)
535 {
536 target_ulong src_addr;
537 target_ulong dst_addr;
538 target_ulong val;
539
540 src_addr = decode_linear_addr(env, decode, RSI(env), R_DS);
541 dst_addr = linear_addr_size(env_cpu(env), RDI(env),
542 decode->addressing_size, R_ES);
543
544 val = read_val_ext(env, src_addr, decode->operand_size);
545 write_val_ext(env, dst_addr, val, decode->operand_size);
546
547 string_increment_reg(env, R_ESI, decode);
548 string_increment_reg(env, R_EDI, decode);
549 }
550
551 static void exec_movs(struct CPUX86State *env, struct x86_decode *decode)
552 {
553 if (decode->rep) {
554 string_rep(env, decode, exec_movs_single, 0);
555 } else {
556 exec_movs_single(env, decode);
557 }
558
559 env->eip += decode->len;
560 }
561
562 static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode)
563 {
564 target_ulong src_addr;
565 target_ulong dst_addr;
566
567 src_addr = decode_linear_addr(env, decode, RSI(env), R_DS);
568 dst_addr = linear_addr_size(env_cpu(env), RDI(env),
569 decode->addressing_size, R_ES);
570
571 decode->op[0].type = X86_VAR_IMMEDIATE;
572 decode->op[0].val = read_val_ext(env, src_addr, decode->operand_size);
573 decode->op[1].type = X86_VAR_IMMEDIATE;
574 decode->op[1].val = read_val_ext(env, dst_addr, decode->operand_size);
575
576 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
577
578 string_increment_reg(env, R_ESI, decode);
579 string_increment_reg(env, R_EDI, decode);
580 }
581
582 static void exec_cmps(struct CPUX86State *env, struct x86_decode *decode)
583 {
584 if (decode->rep) {
585 string_rep(env, decode, exec_cmps_single, decode->rep);
586 } else {
587 exec_cmps_single(env, decode);
588 }
589 env->eip += decode->len;
590 }
591
592
593 static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode)
594 {
595 target_ulong addr;
596 target_ulong val;
597
598 addr = linear_addr_size(env_cpu(env), RDI(env),
599 decode->addressing_size, R_ES);
600 val = read_reg(env, R_EAX, decode->operand_size);
601 vmx_write_mem(env_cpu(env), addr, &val, decode->operand_size);
602
603 string_increment_reg(env, R_EDI, decode);
604 }
605
606
607 static void exec_stos(struct CPUX86State *env, struct x86_decode *decode)
608 {
609 if (decode->rep) {
610 string_rep(env, decode, exec_stos_single, 0);
611 } else {
612 exec_stos_single(env, decode);
613 }
614
615 env->eip += decode->len;
616 }
617
618 static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode)
619 {
620 target_ulong addr;
621
622 addr = linear_addr_size(env_cpu(env), RDI(env),
623 decode->addressing_size, R_ES);
624 decode->op[1].type = X86_VAR_IMMEDIATE;
625 vmx_read_mem(env_cpu(env), &decode->op[1].val, addr, decode->operand_size);
626
627 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
628 string_increment_reg(env, R_EDI, decode);
629 }
630
631 static void exec_scas(struct CPUX86State *env, struct x86_decode *decode)
632 {
633 decode->op[0].type = X86_VAR_REG;
634 decode->op[0].reg = R_EAX;
635 if (decode->rep) {
636 string_rep(env, decode, exec_scas_single, decode->rep);
637 } else {
638 exec_scas_single(env, decode);
639 }
640
641 env->eip += decode->len;
642 }
643
644 static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode)
645 {
646 target_ulong addr;
647 target_ulong val = 0;
648
649 addr = decode_linear_addr(env, decode, RSI(env), R_DS);
650 vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size);
651 write_reg(env, R_EAX, val, decode->operand_size);
652
653 string_increment_reg(env, R_ESI, decode);
654 }
655
656 static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
657 {
658 if (decode->rep) {
659 string_rep(env, decode, exec_lods_single, 0);
660 } else {
661 exec_lods_single(env, decode);
662 }
663
664 env->eip += decode->len;
665 }
666
667 void simulate_rdmsr(struct CPUState *cpu)
668 {
669 X86CPU *x86_cpu = X86_CPU(cpu);
670 CPUX86State *env = &x86_cpu->env;
671 uint32_t msr = ECX(env);
672 uint64_t val = 0;
673
674 switch (msr) {
675 case MSR_IA32_TSC:
676 val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET);
677 break;
678 case MSR_IA32_APICBASE:
679 val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
680 break;
681 case MSR_IA32_UCODE_REV:
682 val = x86_cpu->ucode_rev;
683 break;
684 case MSR_EFER:
685 val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
686 break;
687 case MSR_FSBASE:
688 val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE);
689 break;
690 case MSR_GSBASE:
691 val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE);
692 break;
693 case MSR_KERNELGSBASE:
694 val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE);
695 break;
696 case MSR_STAR:
697 abort();
698 break;
699 case MSR_LSTAR:
700 abort();
701 break;
702 case MSR_CSTAR:
703 abort();
704 break;
705 case MSR_IA32_MISC_ENABLE:
706 val = env->msr_ia32_misc_enable;
707 break;
708 case MSR_MTRRphysBase(0):
709 case MSR_MTRRphysBase(1):
710 case MSR_MTRRphysBase(2):
711 case MSR_MTRRphysBase(3):
712 case MSR_MTRRphysBase(4):
713 case MSR_MTRRphysBase(5):
714 case MSR_MTRRphysBase(6):
715 case MSR_MTRRphysBase(7):
716 val = env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base;
717 break;
718 case MSR_MTRRphysMask(0):
719 case MSR_MTRRphysMask(1):
720 case MSR_MTRRphysMask(2):
721 case MSR_MTRRphysMask(3):
722 case MSR_MTRRphysMask(4):
723 case MSR_MTRRphysMask(5):
724 case MSR_MTRRphysMask(6):
725 case MSR_MTRRphysMask(7):
726 val = env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask;
727 break;
728 case MSR_MTRRfix64K_00000:
729 val = env->mtrr_fixed[0];
730 break;
731 case MSR_MTRRfix16K_80000:
732 case MSR_MTRRfix16K_A0000:
733 val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1];
734 break;
735 case MSR_MTRRfix4K_C0000:
736 case MSR_MTRRfix4K_C8000:
737 case MSR_MTRRfix4K_D0000:
738 case MSR_MTRRfix4K_D8000:
739 case MSR_MTRRfix4K_E0000:
740 case MSR_MTRRfix4K_E8000:
741 case MSR_MTRRfix4K_F0000:
742 case MSR_MTRRfix4K_F8000:
743 val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3];
744 break;
745 case MSR_MTRRdefType:
746 val = env->mtrr_deftype;
747 break;
748 default:
749 /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
750 val = 0;
751 break;
752 }
753
754 RAX(env) = (uint32_t)val;
755 RDX(env) = (uint32_t)(val >> 32);
756 }
757
758 static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode)
759 {
760 simulate_rdmsr(env_cpu(env));
761 env->eip += decode->len;
762 }
763
764 void simulate_wrmsr(struct CPUState *cpu)
765 {
766 X86CPU *x86_cpu = X86_CPU(cpu);
767 CPUX86State *env = &x86_cpu->env;
768 uint32_t msr = ECX(env);
769 uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
770
771 switch (msr) {
772 case MSR_IA32_TSC:
773 break;
774 case MSR_IA32_APICBASE:
775 cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
776 break;
777 case MSR_FSBASE:
778 wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data);
779 break;
780 case MSR_GSBASE:
781 wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data);
782 break;
783 case MSR_KERNELGSBASE:
784 wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data);
785 break;
786 case MSR_STAR:
787 abort();
788 break;
789 case MSR_LSTAR:
790 abort();
791 break;
792 case MSR_CSTAR:
793 abort();
794 break;
795 case MSR_EFER:
796 /*printf("new efer %llx\n", EFER(cpu));*/
797 wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);
798 if (data & MSR_EFER_NXE) {
799 hv_vcpu_invalidate_tlb(cpu->hvf_fd);
800 }
801 break;
802 case MSR_MTRRphysBase(0):
803 case MSR_MTRRphysBase(1):
804 case MSR_MTRRphysBase(2):
805 case MSR_MTRRphysBase(3):
806 case MSR_MTRRphysBase(4):
807 case MSR_MTRRphysBase(5):
808 case MSR_MTRRphysBase(6):
809 case MSR_MTRRphysBase(7):
810 env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base = data;
811 break;
812 case MSR_MTRRphysMask(0):
813 case MSR_MTRRphysMask(1):
814 case MSR_MTRRphysMask(2):
815 case MSR_MTRRphysMask(3):
816 case MSR_MTRRphysMask(4):
817 case MSR_MTRRphysMask(5):
818 case MSR_MTRRphysMask(6):
819 case MSR_MTRRphysMask(7):
820 env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask = data;
821 break;
822 case MSR_MTRRfix64K_00000:
823 env->mtrr_fixed[ECX(env) - MSR_MTRRfix64K_00000] = data;
824 break;
825 case MSR_MTRRfix16K_80000:
826 case MSR_MTRRfix16K_A0000:
827 env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1] = data;
828 break;
829 case MSR_MTRRfix4K_C0000:
830 case MSR_MTRRfix4K_C8000:
831 case MSR_MTRRfix4K_D0000:
832 case MSR_MTRRfix4K_D8000:
833 case MSR_MTRRfix4K_E0000:
834 case MSR_MTRRfix4K_E8000:
835 case MSR_MTRRfix4K_F0000:
836 case MSR_MTRRfix4K_F8000:
837 env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3] = data;
838 break;
839 case MSR_MTRRdefType:
840 env->mtrr_deftype = data;
841 break;
842 default:
843 break;
844 }
845
846 /* Related to support known hypervisor interface */
847 /* if (g_hypervisor_iface)
848 g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
849
850 printf("write msr %llx\n", RCX(cpu));*/
851 }
852
853 static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode)
854 {
855 simulate_wrmsr(env_cpu(env));
856 env->eip += decode->len;
857 }
858
859 /*
860 * flag:
861 * 0 - bt, 1 - btc, 2 - bts, 3 - btr
862 */
863 static void do_bt(struct CPUX86State *env, struct x86_decode *decode, int flag)
864 {
865 int32_t displacement;
866 uint8_t index;
867 bool cf;
868 int mask = (4 == decode->operand_size) ? 0x1f : 0xf;
869
870 VM_PANIC_ON(decode->rex.rex);
871
872 fetch_operands(env, decode, 2, false, true, false);
873 index = decode->op[1].val & mask;
874
875 if (decode->op[0].type != X86_VAR_REG) {
876 if (4 == decode->operand_size) {
877 displacement = ((int32_t) (decode->op[1].val & 0xffffffe0)) / 32;
878 decode->op[0].ptr += 4 * displacement;
879 } else if (2 == decode->operand_size) {
880 displacement = ((int16_t) (decode->op[1].val & 0xfff0)) / 16;
881 decode->op[0].ptr += 2 * displacement;
882 } else {
883 VM_PANIC("bt 64bit\n");
884 }
885 }
886 decode->op[0].val = read_val_ext(env, decode->op[0].ptr,
887 decode->operand_size);
888 cf = (decode->op[0].val >> index) & 0x01;
889
890 switch (flag) {
891 case 0:
892 set_CF(env, cf);
893 return;
894 case 1:
895 decode->op[0].val ^= (1u << index);
896 break;
897 case 2:
898 decode->op[0].val |= (1u << index);
899 break;
900 case 3:
901 decode->op[0].val &= ~(1u << index);
902 break;
903 }
904 write_val_ext(env, decode->op[0].ptr, decode->op[0].val,
905 decode->operand_size);
906 set_CF(env, cf);
907 }
908
909 static void exec_bt(struct CPUX86State *env, struct x86_decode *decode)
910 {
911 do_bt(env, decode, 0);
912 env->eip += decode->len;
913 }
914
915 static void exec_btc(struct CPUX86State *env, struct x86_decode *decode)
916 {
917 do_bt(env, decode, 1);
918 env->eip += decode->len;
919 }
920
921 static void exec_btr(struct CPUX86State *env, struct x86_decode *decode)
922 {
923 do_bt(env, decode, 3);
924 env->eip += decode->len;
925 }
926
927 static void exec_bts(struct CPUX86State *env, struct x86_decode *decode)
928 {
929 do_bt(env, decode, 2);
930 env->eip += decode->len;
931 }
932
933 void exec_shl(struct CPUX86State *env, struct x86_decode *decode)
934 {
935 uint8_t count;
936 int of = 0, cf = 0;
937
938 fetch_operands(env, decode, 2, true, true, false);
939
940 count = decode->op[1].val;
941 count &= 0x1f; /* count is masked to 5 bits*/
942 if (!count) {
943 goto exit;
944 }
945
946 switch (decode->operand_size) {
947 case 1:
948 {
949 uint8_t res = 0;
950 if (count <= 8) {
951 res = (decode->op[0].val << count);
952 cf = (decode->op[0].val >> (8 - count)) & 0x1;
953 of = cf ^ (res >> 7);
954 }
955
956 write_val_ext(env, decode->op[0].ptr, res, 1);
957 SET_FLAGS_OSZAPC_LOGIC8(env, 0, 0, res);
958 SET_FLAGS_OxxxxC(env, of, cf);
959 break;
960 }
961 case 2:
962 {
963 uint16_t res = 0;
964
965 /* from bochs */
966 if (count <= 16) {
967 res = (decode->op[0].val << count);
968 cf = (decode->op[0].val >> (16 - count)) & 0x1;
969 of = cf ^ (res >> 15); /* of = cf ^ result15 */
970 }
971
972 write_val_ext(env, decode->op[0].ptr, res, 2);
973 SET_FLAGS_OSZAPC_LOGIC16(env, 0, 0, res);
974 SET_FLAGS_OxxxxC(env, of, cf);
975 break;
976 }
977 case 4:
978 {
979 uint32_t res = decode->op[0].val << count;
980
981 write_val_ext(env, decode->op[0].ptr, res, 4);
982 SET_FLAGS_OSZAPC_LOGIC32(env, 0, 0, res);
983 cf = (decode->op[0].val >> (32 - count)) & 0x1;
984 of = cf ^ (res >> 31); /* of = cf ^ result31 */
985 SET_FLAGS_OxxxxC(env, of, cf);
986 break;
987 }
988 default:
989 abort();
990 }
991
992 exit:
993 /* lflags_to_rflags(env); */
994 env->eip += decode->len;
995 }
996
997 void exec_movsx(CPUX86State *env, struct x86_decode *decode)
998 {
999 int src_op_size;
1000 int op_size = decode->operand_size;
1001
1002 fetch_operands(env, decode, 2, false, false, false);
1003
1004 if (0xbe == decode->opcode[1]) {
1005 src_op_size = 1;
1006 } else {
1007 src_op_size = 2;
1008 }
1009
1010 decode->operand_size = src_op_size;
1011 calc_modrm_operand(env, decode, &decode->op[1]);
1012 decode->op[1].val = sign(read_val_ext(env, decode->op[1].ptr, src_op_size),
1013 src_op_size);
1014
1015 write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size);
1016
1017 env->eip += decode->len;
1018 }
1019
1020 void exec_ror(struct CPUX86State *env, struct x86_decode *decode)
1021 {
1022 uint8_t count;
1023
1024 fetch_operands(env, decode, 2, true, true, false);
1025 count = decode->op[1].val;
1026
1027 switch (decode->operand_size) {
1028 case 1:
1029 {
1030 uint32_t bit6, bit7;
1031 uint8_t res;
1032
1033 if ((count & 0x07) == 0) {
1034 if (count & 0x18) {
1035 bit6 = ((uint8_t)decode->op[0].val >> 6) & 1;
1036 bit7 = ((uint8_t)decode->op[0].val >> 7) & 1;
1037 SET_FLAGS_OxxxxC(env, bit6 ^ bit7, bit7);
1038 }
1039 } else {
1040 count &= 0x7; /* use only bottom 3 bits */
1041 res = ((uint8_t)decode->op[0].val >> count) |
1042 ((uint8_t)decode->op[0].val << (8 - count));
1043 write_val_ext(env, decode->op[0].ptr, res, 1);
1044 bit6 = (res >> 6) & 1;
1045 bit7 = (res >> 7) & 1;
1046 /* set eflags: ROR count affects the following flags: C, O */
1047 SET_FLAGS_OxxxxC(env, bit6 ^ bit7, bit7);
1048 }
1049 break;
1050 }
1051 case 2:
1052 {
1053 uint32_t bit14, bit15;
1054 uint16_t res;
1055
1056 if ((count & 0x0f) == 0) {
1057 if (count & 0x10) {
1058 bit14 = ((uint16_t)decode->op[0].val >> 14) & 1;
1059 bit15 = ((uint16_t)decode->op[0].val >> 15) & 1;
1060 /* of = result14 ^ result15 */
1061 SET_FLAGS_OxxxxC(env, bit14 ^ bit15, bit15);
1062 }
1063 } else {
1064 count &= 0x0f; /* use only 4 LSB's */
1065 res = ((uint16_t)decode->op[0].val >> count) |
1066 ((uint16_t)decode->op[0].val << (16 - count));
1067 write_val_ext(env, decode->op[0].ptr, res, 2);
1068
1069 bit14 = (res >> 14) & 1;
1070 bit15 = (res >> 15) & 1;
1071 /* of = result14 ^ result15 */
1072 SET_FLAGS_OxxxxC(env, bit14 ^ bit15, bit15);
1073 }
1074 break;
1075 }
1076 case 4:
1077 {
1078 uint32_t bit31, bit30;
1079 uint32_t res;
1080
1081 count &= 0x1f;
1082 if (count) {
1083 res = ((uint32_t)decode->op[0].val >> count) |
1084 ((uint32_t)decode->op[0].val << (32 - count));
1085 write_val_ext(env, decode->op[0].ptr, res, 4);
1086
1087 bit31 = (res >> 31) & 1;
1088 bit30 = (res >> 30) & 1;
1089 /* of = result30 ^ result31 */
1090 SET_FLAGS_OxxxxC(env, bit30 ^ bit31, bit31);
1091 }
1092 break;
1093 }
1094 }
1095 env->eip += decode->len;
1096 }
1097
1098 void exec_rol(struct CPUX86State *env, struct x86_decode *decode)
1099 {
1100 uint8_t count;
1101
1102 fetch_operands(env, decode, 2, true, true, false);
1103 count = decode->op[1].val;
1104
1105 switch (decode->operand_size) {
1106 case 1:
1107 {
1108 uint32_t bit0, bit7;
1109 uint8_t res;
1110
1111 if ((count & 0x07) == 0) {
1112 if (count & 0x18) {
1113 bit0 = ((uint8_t)decode->op[0].val & 1);
1114 bit7 = ((uint8_t)decode->op[0].val >> 7);
1115 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0);
1116 }
1117 } else {
1118 count &= 0x7; /* use only lowest 3 bits */
1119 res = ((uint8_t)decode->op[0].val << count) |
1120 ((uint8_t)decode->op[0].val >> (8 - count));
1121
1122 write_val_ext(env, decode->op[0].ptr, res, 1);
1123 /* set eflags:
1124 * ROL count affects the following flags: C, O
1125 */
1126 bit0 = (res & 1);
1127 bit7 = (res >> 7);
1128 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0);
1129 }
1130 break;
1131 }
1132 case 2:
1133 {
1134 uint32_t bit0, bit15;
1135 uint16_t res;
1136
1137 if ((count & 0x0f) == 0) {
1138 if (count & 0x10) {
1139 bit0 = ((uint16_t)decode->op[0].val & 0x1);
1140 bit15 = ((uint16_t)decode->op[0].val >> 15);
1141 /* of = cf ^ result15 */
1142 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0);
1143 }
1144 } else {
1145 count &= 0x0f; /* only use bottom 4 bits */
1146 res = ((uint16_t)decode->op[0].val << count) |
1147 ((uint16_t)decode->op[0].val >> (16 - count));
1148
1149 write_val_ext(env, decode->op[0].ptr, res, 2);
1150 bit0 = (res & 0x1);
1151 bit15 = (res >> 15);
1152 /* of = cf ^ result15 */
1153 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0);
1154 }
1155 break;
1156 }
1157 case 4:
1158 {
1159 uint32_t bit0, bit31;
1160 uint32_t res;
1161
1162 count &= 0x1f;
1163 if (count) {
1164 res = ((uint32_t)decode->op[0].val << count) |
1165 ((uint32_t)decode->op[0].val >> (32 - count));
1166
1167 write_val_ext(env, decode->op[0].ptr, res, 4);
1168 bit0 = (res & 0x1);
1169 bit31 = (res >> 31);
1170 /* of = cf ^ result31 */
1171 SET_FLAGS_OxxxxC(env, bit0 ^ bit31, bit0);
1172 }
1173 break;
1174 }
1175 }
1176 env->eip += decode->len;
1177 }
1178
1179
1180 void exec_rcl(struct CPUX86State *env, struct x86_decode *decode)
1181 {
1182 uint8_t count;
1183 int of = 0, cf = 0;
1184
1185 fetch_operands(env, decode, 2, true, true, false);
1186 count = decode->op[1].val & 0x1f;
1187
1188 switch (decode->operand_size) {
1189 case 1:
1190 {
1191 uint8_t op1_8 = decode->op[0].val;
1192 uint8_t res;
1193 count %= 9;
1194 if (!count) {
1195 break;
1196 }
1197
1198 if (1 == count) {
1199 res = (op1_8 << 1) | get_CF(env);
1200 } else {
1201 res = (op1_8 << count) | (get_CF(env) << (count - 1)) |
1202 (op1_8 >> (9 - count));
1203 }
1204
1205 write_val_ext(env, decode->op[0].ptr, res, 1);
1206
1207 cf = (op1_8 >> (8 - count)) & 0x01;
1208 of = cf ^ (res >> 7); /* of = cf ^ result7 */
1209 SET_FLAGS_OxxxxC(env, of, cf);
1210 break;
1211 }
1212 case 2:
1213 {
1214 uint16_t res;
1215 uint16_t op1_16 = decode->op[0].val;
1216
1217 count %= 17;
1218 if (!count) {
1219 break;
1220 }
1221
1222 if (1 == count) {
1223 res = (op1_16 << 1) | get_CF(env);
1224 } else if (count == 16) {
1225 res = (get_CF(env) << 15) | (op1_16 >> 1);
1226 } else { /* 2..15 */
1227 res = (op1_16 << count) | (get_CF(env) << (count - 1)) |
1228 (op1_16 >> (17 - count));
1229 }
1230
1231 write_val_ext(env, decode->op[0].ptr, res, 2);
1232
1233 cf = (op1_16 >> (16 - count)) & 0x1;
1234 of = cf ^ (res >> 15); /* of = cf ^ result15 */
1235 SET_FLAGS_OxxxxC(env, of, cf);
1236 break;
1237 }
1238 case 4:
1239 {
1240 uint32_t res;
1241 uint32_t op1_32 = decode->op[0].val;
1242
1243 if (!count) {
1244 break;
1245 }
1246
1247 if (1 == count) {
1248 res = (op1_32 << 1) | get_CF(env);
1249 } else {
1250 res = (op1_32 << count) | (get_CF(env) << (count - 1)) |
1251 (op1_32 >> (33 - count));
1252 }
1253
1254 write_val_ext(env, decode->op[0].ptr, res, 4);
1255
1256 cf = (op1_32 >> (32 - count)) & 0x1;
1257 of = cf ^ (res >> 31); /* of = cf ^ result31 */
1258 SET_FLAGS_OxxxxC(env, of, cf);
1259 break;
1260 }
1261 }
1262 env->eip += decode->len;
1263 }
1264
1265 void exec_rcr(struct CPUX86State *env, struct x86_decode *decode)
1266 {
1267 uint8_t count;
1268 int of = 0, cf = 0;
1269
1270 fetch_operands(env, decode, 2, true, true, false);
1271 count = decode->op[1].val & 0x1f;
1272
1273 switch (decode->operand_size) {
1274 case 1:
1275 {
1276 uint8_t op1_8 = decode->op[0].val;
1277 uint8_t res;
1278
1279 count %= 9;
1280 if (!count) {
1281 break;
1282 }
1283 res = (op1_8 >> count) | (get_CF(env) << (8 - count)) |
1284 (op1_8 << (9 - count));
1285
1286 write_val_ext(env, decode->op[0].ptr, res, 1);
1287
1288 cf = (op1_8 >> (count - 1)) & 0x1;
1289 of = (((res << 1) ^ res) >> 7) & 0x1; /* of = result6 ^ result7 */
1290 SET_FLAGS_OxxxxC(env, of, cf);
1291 break;
1292 }
1293 case 2:
1294 {
1295 uint16_t op1_16 = decode->op[0].val;
1296 uint16_t res;
1297
1298 count %= 17;
1299 if (!count) {
1300 break;
1301 }
1302 res = (op1_16 >> count) | (get_CF(env) << (16 - count)) |
1303 (op1_16 << (17 - count));
1304
1305 write_val_ext(env, decode->op[0].ptr, res, 2);
1306
1307 cf = (op1_16 >> (count - 1)) & 0x1;
1308 of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; /* of = result15 ^
1309 result14 */
1310 SET_FLAGS_OxxxxC(env, of, cf);
1311 break;
1312 }
1313 case 4:
1314 {
1315 uint32_t res;
1316 uint32_t op1_32 = decode->op[0].val;
1317
1318 if (!count) {
1319 break;
1320 }
1321
1322 if (1 == count) {
1323 res = (op1_32 >> 1) | (get_CF(env) << 31);
1324 } else {
1325 res = (op1_32 >> count) | (get_CF(env) << (32 - count)) |
1326 (op1_32 << (33 - count));
1327 }
1328
1329 write_val_ext(env, decode->op[0].ptr, res, 4);
1330
1331 cf = (op1_32 >> (count - 1)) & 0x1;
1332 of = ((res << 1) ^ res) >> 31; /* of = result30 ^ result31 */
1333 SET_FLAGS_OxxxxC(env, of, cf);
1334 break;
1335 }
1336 }
1337 env->eip += decode->len;
1338 }
1339
1340 static void exec_xchg(struct CPUX86State *env, struct x86_decode *decode)
1341 {
1342 fetch_operands(env, decode, 2, true, true, false);
1343
1344 write_val_ext(env, decode->op[0].ptr, decode->op[1].val,
1345 decode->operand_size);
1346 write_val_ext(env, decode->op[1].ptr, decode->op[0].val,
1347 decode->operand_size);
1348
1349 env->eip += decode->len;
1350 }
1351
1352 static void exec_xadd(struct CPUX86State *env, struct x86_decode *decode)
1353 {
1354 EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true);
1355 write_val_ext(env, decode->op[1].ptr, decode->op[0].val,
1356 decode->operand_size);
1357
1358 env->eip += decode->len;
1359 }
1360
1361 static struct cmd_handler {
1362 enum x86_decode_cmd cmd;
1363 void (*handler)(struct CPUX86State *env, struct x86_decode *ins);
1364 } handlers[] = {
1365 {X86_DECODE_CMD_INVL, NULL,},
1366 {X86_DECODE_CMD_MOV, exec_mov},
1367 {X86_DECODE_CMD_ADD, exec_add},
1368 {X86_DECODE_CMD_OR, exec_or},
1369 {X86_DECODE_CMD_ADC, exec_adc},
1370 {X86_DECODE_CMD_SBB, exec_sbb},
1371 {X86_DECODE_CMD_AND, exec_and},
1372 {X86_DECODE_CMD_SUB, exec_sub},
1373 {X86_DECODE_CMD_NEG, exec_neg},
1374 {X86_DECODE_CMD_XOR, exec_xor},
1375 {X86_DECODE_CMD_CMP, exec_cmp},
1376 {X86_DECODE_CMD_INC, exec_inc},
1377 {X86_DECODE_CMD_DEC, exec_dec},
1378 {X86_DECODE_CMD_TST, exec_tst},
1379 {X86_DECODE_CMD_NOT, exec_not},
1380 {X86_DECODE_CMD_MOVZX, exec_movzx},
1381 {X86_DECODE_CMD_OUT, exec_out},
1382 {X86_DECODE_CMD_IN, exec_in},
1383 {X86_DECODE_CMD_INS, exec_ins},
1384 {X86_DECODE_CMD_OUTS, exec_outs},
1385 {X86_DECODE_CMD_RDMSR, exec_rdmsr},
1386 {X86_DECODE_CMD_WRMSR, exec_wrmsr},
1387 {X86_DECODE_CMD_BT, exec_bt},
1388 {X86_DECODE_CMD_BTR, exec_btr},
1389 {X86_DECODE_CMD_BTC, exec_btc},
1390 {X86_DECODE_CMD_BTS, exec_bts},
1391 {X86_DECODE_CMD_SHL, exec_shl},
1392 {X86_DECODE_CMD_ROL, exec_rol},
1393 {X86_DECODE_CMD_ROR, exec_ror},
1394 {X86_DECODE_CMD_RCR, exec_rcr},
1395 {X86_DECODE_CMD_RCL, exec_rcl},
1396 /*{X86_DECODE_CMD_CPUID, exec_cpuid},*/
1397 {X86_DECODE_CMD_MOVS, exec_movs},
1398 {X86_DECODE_CMD_CMPS, exec_cmps},
1399 {X86_DECODE_CMD_STOS, exec_stos},
1400 {X86_DECODE_CMD_SCAS, exec_scas},
1401 {X86_DECODE_CMD_LODS, exec_lods},
1402 {X86_DECODE_CMD_MOVSX, exec_movsx},
1403 {X86_DECODE_CMD_XCHG, exec_xchg},
1404 {X86_DECODE_CMD_XADD, exec_xadd},
1405 };
1406
1407 static struct cmd_handler _cmd_handler[X86_DECODE_CMD_LAST];
1408
1409 static void init_cmd_handler()
1410 {
1411 int i;
1412 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
1413 _cmd_handler[handlers[i].cmd] = handlers[i];
1414 }
1415 }
1416
1417 void load_regs(struct CPUState *cpu)
1418 {
1419 X86CPU *x86_cpu = X86_CPU(cpu);
1420 CPUX86State *env = &x86_cpu->env;
1421
1422 int i = 0;
1423 RRX(env, R_EAX) = rreg(cpu->hvf_fd, HV_X86_RAX);
1424 RRX(env, R_EBX) = rreg(cpu->hvf_fd, HV_X86_RBX);
1425 RRX(env, R_ECX) = rreg(cpu->hvf_fd, HV_X86_RCX);
1426 RRX(env, R_EDX) = rreg(cpu->hvf_fd, HV_X86_RDX);
1427 RRX(env, R_ESI) = rreg(cpu->hvf_fd, HV_X86_RSI);
1428 RRX(env, R_EDI) = rreg(cpu->hvf_fd, HV_X86_RDI);
1429 RRX(env, R_ESP) = rreg(cpu->hvf_fd, HV_X86_RSP);
1430 RRX(env, R_EBP) = rreg(cpu->hvf_fd, HV_X86_RBP);
1431 for (i = 8; i < 16; i++) {
1432 RRX(env, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
1433 }
1434
1435 env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
1436 rflags_to_lflags(env);
1437 env->eip = rreg(cpu->hvf_fd, HV_X86_RIP);
1438 }
1439
1440 void store_regs(struct CPUState *cpu)
1441 {
1442 X86CPU *x86_cpu = X86_CPU(cpu);
1443 CPUX86State *env = &x86_cpu->env;
1444
1445 int i = 0;
1446 wreg(cpu->hvf_fd, HV_X86_RAX, RAX(env));
1447 wreg(cpu->hvf_fd, HV_X86_RBX, RBX(env));
1448 wreg(cpu->hvf_fd, HV_X86_RCX, RCX(env));
1449 wreg(cpu->hvf_fd, HV_X86_RDX, RDX(env));
1450 wreg(cpu->hvf_fd, HV_X86_RSI, RSI(env));
1451 wreg(cpu->hvf_fd, HV_X86_RDI, RDI(env));
1452 wreg(cpu->hvf_fd, HV_X86_RBP, RBP(env));
1453 wreg(cpu->hvf_fd, HV_X86_RSP, RSP(env));
1454 for (i = 8; i < 16; i++) {
1455 wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(env, i));
1456 }
1457
1458 lflags_to_rflags(env);
1459 wreg(cpu->hvf_fd, HV_X86_RFLAGS, env->eflags);
1460 macvm_set_rip(cpu, env->eip);
1461 }
1462
1463 bool exec_instruction(struct CPUX86State *env, struct x86_decode *ins)
1464 {
1465 /*if (hvf_vcpu_id(cpu))
1466 printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,
1467 decode_cmd_to_string(ins->cmd));*/
1468
1469 if (!_cmd_handler[ins->cmd].handler) {
1470 printf("Unimplemented handler (%llx) for %d (%x %x) \n", env->eip,
1471 ins->cmd, ins->opcode[0],
1472 ins->opcode_len > 1 ? ins->opcode[1] : 0);
1473 env->eip += ins->len;
1474 return true;
1475 }
1476
1477 _cmd_handler[ins->cmd].handler(env, ins);
1478 return true;
1479 }
1480
1481 void init_emu()
1482 {
1483 init_cmd_handler();
1484 }
AR7 emulation for QEMU