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target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
[qemu/ar7.git] / target-arm / helper.c
blob50c1017c8a4aca384ead01daa7257a878b4ab25a
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <string.h>
4
5 #include "cpu.h"
6 #include "exec-all.h"
7 #include "gdbstub.h"
8 #include "helpers.h"
9 #include "qemu-common.h"
10 #include "host-utils.h"
11 #if !defined(CONFIG_USER_ONLY)
12 #include "hw/loader.h"
13 #endif
14
15 static uint32_t cortexa9_cp15_c0_c1[8] =
16 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17
18 static uint32_t cortexa9_cp15_c0_c2[8] =
19 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20
21 static uint32_t cortexa8_cp15_c0_c1[8] =
22 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23
24 static uint32_t cortexa8_cp15_c0_c2[8] =
25 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26
27 static uint32_t mpcore_cp15_c0_c1[8] =
28 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29
30 static uint32_t mpcore_cp15_c0_c2[8] =
31 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32
33 static uint32_t arm1136_cp15_c0_c1[8] =
34 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35
36 static uint32_t arm1136_cp15_c0_c2[8] =
37 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
38
39 static uint32_t cpu_arm_find_by_name(const char *name);
40
41 static inline void set_feature(CPUARMState *env, int feature)
42 {
43 env->features |= 1u << feature;
44 }
45
46 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
47 {
48 env->cp15.c0_cpuid = id;
49 switch (id) {
50 case ARM_CPUID_ARM926:
51 set_feature(env, ARM_FEATURE_VFP);
52 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
53 env->cp15.c0_cachetype = 0x1dd20d2;
54 env->cp15.c1_sys = 0x00090078;
55 break;
56 case ARM_CPUID_ARM946:
57 set_feature(env, ARM_FEATURE_MPU);
58 env->cp15.c0_cachetype = 0x0f004006;
59 env->cp15.c1_sys = 0x00000078;
60 break;
61 case ARM_CPUID_ARM1026:
62 set_feature(env, ARM_FEATURE_VFP);
63 set_feature(env, ARM_FEATURE_AUXCR);
64 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
65 env->cp15.c0_cachetype = 0x1dd20d2;
66 env->cp15.c1_sys = 0x00090078;
67 break;
68 case ARM_CPUID_ARM1136_R2:
69 case ARM_CPUID_ARM1136:
70 set_feature(env, ARM_FEATURE_V6);
71 set_feature(env, ARM_FEATURE_VFP);
72 set_feature(env, ARM_FEATURE_AUXCR);
73 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
74 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
75 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
76 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
77 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
78 env->cp15.c0_cachetype = 0x1dd20d2;
79 env->cp15.c1_sys = 0x00050078;
80 break;
81 case ARM_CPUID_ARM11MPCORE:
82 set_feature(env, ARM_FEATURE_V6);
83 set_feature(env, ARM_FEATURE_V6K);
84 set_feature(env, ARM_FEATURE_VFP);
85 set_feature(env, ARM_FEATURE_AUXCR);
86 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
87 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
88 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
89 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
90 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
91 env->cp15.c0_cachetype = 0x1dd20d2;
92 break;
93 case ARM_CPUID_CORTEXA8:
94 set_feature(env, ARM_FEATURE_V6);
95 set_feature(env, ARM_FEATURE_V6K);
96 set_feature(env, ARM_FEATURE_V7);
97 set_feature(env, ARM_FEATURE_AUXCR);
98 set_feature(env, ARM_FEATURE_THUMB2);
99 set_feature(env, ARM_FEATURE_VFP);
100 set_feature(env, ARM_FEATURE_VFP3);
101 set_feature(env, ARM_FEATURE_NEON);
102 set_feature(env, ARM_FEATURE_THUMB2EE);
103 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
104 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
105 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
106 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
107 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
108 env->cp15.c0_cachetype = 0x82048004;
109 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
110 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
111 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
112 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
113 env->cp15.c1_sys = 0x00c50078;
114 break;
115 case ARM_CPUID_CORTEXA9:
116 set_feature(env, ARM_FEATURE_V6);
117 set_feature(env, ARM_FEATURE_V6K);
118 set_feature(env, ARM_FEATURE_V7);
119 set_feature(env, ARM_FEATURE_AUXCR);
120 set_feature(env, ARM_FEATURE_THUMB2);
121 set_feature(env, ARM_FEATURE_VFP);
122 set_feature(env, ARM_FEATURE_VFP3);
123 set_feature(env, ARM_FEATURE_VFP_FP16);
124 set_feature(env, ARM_FEATURE_NEON);
125 set_feature(env, ARM_FEATURE_THUMB2EE);
126 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
127 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
128 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
129 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
130 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
131 env->cp15.c0_cachetype = 0x80038003;
132 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
133 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
134 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
135 env->cp15.c1_sys = 0x00c50078;
136 break;
137 case ARM_CPUID_CORTEXM3:
138 set_feature(env, ARM_FEATURE_V6);
139 set_feature(env, ARM_FEATURE_THUMB2);
140 set_feature(env, ARM_FEATURE_V7);
141 set_feature(env, ARM_FEATURE_M);
142 set_feature(env, ARM_FEATURE_DIV);
143 break;
144 case ARM_CPUID_ANY: /* For userspace emulation. */
145 set_feature(env, ARM_FEATURE_V6);
146 set_feature(env, ARM_FEATURE_V6K);
147 set_feature(env, ARM_FEATURE_V7);
148 set_feature(env, ARM_FEATURE_THUMB2);
149 set_feature(env, ARM_FEATURE_VFP);
150 set_feature(env, ARM_FEATURE_VFP3);
151 set_feature(env, ARM_FEATURE_VFP_FP16);
152 set_feature(env, ARM_FEATURE_NEON);
153 set_feature(env, ARM_FEATURE_THUMB2EE);
154 set_feature(env, ARM_FEATURE_DIV);
155 break;
156 case ARM_CPUID_TI915T:
157 case ARM_CPUID_TI925T:
158 set_feature(env, ARM_FEATURE_OMAPCP);
159 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
160 env->cp15.c0_cachetype = 0x5109149;
161 env->cp15.c1_sys = 0x00000070;
162 env->cp15.c15_i_max = 0x000;
163 env->cp15.c15_i_min = 0xff0;
164 break;
165 case ARM_CPUID_PXA250:
166 case ARM_CPUID_PXA255:
167 case ARM_CPUID_PXA260:
168 case ARM_CPUID_PXA261:
169 case ARM_CPUID_PXA262:
170 set_feature(env, ARM_FEATURE_XSCALE);
171 /* JTAG_ID is ((id << 28) | 0x09265013) */
172 env->cp15.c0_cachetype = 0xd172172;
173 env->cp15.c1_sys = 0x00000078;
174 break;
175 case ARM_CPUID_PXA270_A0:
176 case ARM_CPUID_PXA270_A1:
177 case ARM_CPUID_PXA270_B0:
178 case ARM_CPUID_PXA270_B1:
179 case ARM_CPUID_PXA270_C0:
180 case ARM_CPUID_PXA270_C5:
181 set_feature(env, ARM_FEATURE_XSCALE);
182 /* JTAG_ID is ((id << 28) | 0x09265013) */
183 set_feature(env, ARM_FEATURE_IWMMXT);
184 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
185 env->cp15.c0_cachetype = 0xd172172;
186 env->cp15.c1_sys = 0x00000078;
187 break;
188 default:
189 cpu_abort(env, "Bad CPU ID: %x\n", id);
190 break;
191 }
192 }
193
194 void cpu_reset(CPUARMState *env)
195 {
196 uint32_t id;
197
198 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
199 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
200 log_cpu_state(env, 0);
201 }
202
203 id = env->cp15.c0_cpuid;
204 memset(env, 0, offsetof(CPUARMState, breakpoints));
205 if (id)
206 cpu_reset_model_id(env, id);
207 #if defined (CONFIG_USER_ONLY)
208 env->uncached_cpsr = ARM_CPU_MODE_USR;
209 /* For user mode we must enable access to coprocessors */
210 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
211 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
212 env->cp15.c15_cpar = 3;
213 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
214 env->cp15.c15_cpar = 1;
215 }
216 #else
217 /* SVC mode with interrupts disabled. */
218 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
219 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
220 clear at reset. Initial SP and PC are loaded from ROM. */
221 if (IS_M(env)) {
222 uint32_t pc;
223 uint8_t *rom;
224 env->uncached_cpsr &= ~CPSR_I;
225 rom = rom_ptr(0);
226 if (rom) {
227 /* We should really use ldl_phys here, in case the guest
228 modified flash and reset itself. However images
229 loaded via -kenrel have not been copied yet, so load the
230 values directly from there. */
231 env->regs[13] = ldl_p(rom);
232 pc = ldl_p(rom + 4);
233 env->thumb = pc & 1;
234 env->regs[15] = pc & ~1;
235 }
236 }
237 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
238 env->cp15.c2_base_mask = 0xffffc000u;
239 #endif
240 tlb_flush(env, 1);
241 }
242
243 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
244 {
245 int nregs;
246
247 /* VFP data registers are always little-endian. */
248 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
249 if (reg < nregs) {
250 stfq_le_p(buf, env->vfp.regs[reg]);
251 return 8;
252 }
253 if (arm_feature(env, ARM_FEATURE_NEON)) {
254 /* Aliases for Q regs. */
255 nregs += 16;
256 if (reg < nregs) {
257 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
258 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
259 return 16;
260 }
261 }
262 switch (reg - nregs) {
263 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
264 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
265 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
266 }
267 return 0;
268 }
269
270 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
271 {
272 int nregs;
273
274 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
275 if (reg < nregs) {
276 env->vfp.regs[reg] = ldfq_le_p(buf);
277 return 8;
278 }
279 if (arm_feature(env, ARM_FEATURE_NEON)) {
280 nregs += 16;
281 if (reg < nregs) {
282 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
283 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
284 return 16;
285 }
286 }
287 switch (reg - nregs) {
288 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
289 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
290 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
291 }
292 return 0;
293 }
294
295 CPUARMState *cpu_arm_init(const char *cpu_model)
296 {
297 CPUARMState *env;
298 uint32_t id;
299 static int inited = 0;
300
301 id = cpu_arm_find_by_name(cpu_model);
302 if (id == 0)
303 return NULL;
304 env = qemu_mallocz(sizeof(CPUARMState));
305 cpu_exec_init(env);
306 if (!inited) {
307 inited = 1;
308 arm_translate_init();
309 }
310
311 env->cpu_model_str = cpu_model;
312 env->cp15.c0_cpuid = id;
313 cpu_reset(env);
314 if (arm_feature(env, ARM_FEATURE_NEON)) {
315 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
316 51, "arm-neon.xml", 0);
317 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
318 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
319 35, "arm-vfp3.xml", 0);
320 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
321 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
322 19, "arm-vfp.xml", 0);
323 }
324 qemu_init_vcpu(env);
325 return env;
326 }
327
328 struct arm_cpu_t {
329 uint32_t id;
330 const char *name;
331 };
332
333 static const struct arm_cpu_t arm_cpu_names[] = {
334 { ARM_CPUID_ARM926, "arm926"},
335 { ARM_CPUID_ARM946, "arm946"},
336 { ARM_CPUID_ARM1026, "arm1026"},
337 { ARM_CPUID_ARM1136, "arm1136"},
338 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
339 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
340 { ARM_CPUID_CORTEXM3, "cortex-m3"},
341 { ARM_CPUID_CORTEXA8, "cortex-a8"},
342 { ARM_CPUID_CORTEXA9, "cortex-a9"},
343 { ARM_CPUID_TI925T, "ti925t" },
344 { ARM_CPUID_PXA250, "pxa250" },
345 { ARM_CPUID_PXA255, "pxa255" },
346 { ARM_CPUID_PXA260, "pxa260" },
347 { ARM_CPUID_PXA261, "pxa261" },
348 { ARM_CPUID_PXA262, "pxa262" },
349 { ARM_CPUID_PXA270, "pxa270" },
350 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
351 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
352 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
353 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
354 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
355 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
356 { ARM_CPUID_ANY, "any"},
357 { 0, NULL}
358 };
359
360 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
361 {
362 int i;
363
364 (*cpu_fprintf)(f, "Available CPUs:\n");
365 for (i = 0; arm_cpu_names[i].name; i++) {
366 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
367 }
368 }
369
370 /* return 0 if not found */
371 static uint32_t cpu_arm_find_by_name(const char *name)
372 {
373 int i;
374 uint32_t id;
375
376 id = 0;
377 for (i = 0; arm_cpu_names[i].name; i++) {
378 if (strcmp(name, arm_cpu_names[i].name) == 0) {
379 id = arm_cpu_names[i].id;
380 break;
381 }
382 }
383 return id;
384 }
385
386 void cpu_arm_close(CPUARMState *env)
387 {
388 free(env);
389 }
390
391 uint32_t cpsr_read(CPUARMState *env)
392 {
393 int ZF;
394 ZF = (env->ZF == 0);
395 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
396 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
397 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
398 | ((env->condexec_bits & 0xfc) << 8)
399 | (env->GE << 16);
400 }
401
402 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
403 {
404 if (mask & CPSR_NZCV) {
405 env->ZF = (~val) & CPSR_Z;
406 env->NF = val;
407 env->CF = (val >> 29) & 1;
408 env->VF = (val << 3) & 0x80000000;
409 }
410 if (mask & CPSR_Q)
411 env->QF = ((val & CPSR_Q) != 0);
412 if (mask & CPSR_T)
413 env->thumb = ((val & CPSR_T) != 0);
414 if (mask & CPSR_IT_0_1) {
415 env->condexec_bits &= ~3;
416 env->condexec_bits |= (val >> 25) & 3;
417 }
418 if (mask & CPSR_IT_2_7) {
419 env->condexec_bits &= 3;
420 env->condexec_bits |= (val >> 8) & 0xfc;
421 }
422 if (mask & CPSR_GE) {
423 env->GE = (val >> 16) & 0xf;
424 }
425
426 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
427 switch_mode(env, val & CPSR_M);
428 }
429 mask &= ~CACHED_CPSR_BITS;
430 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
431 }
432
433 /* Sign/zero extend */
434 uint32_t HELPER(sxtb16)(uint32_t x)
435 {
436 uint32_t res;
437 res = (uint16_t)(int8_t)x;
438 res |= (uint32_t)(int8_t)(x >> 16) << 16;
439 return res;
440 }
441
442 uint32_t HELPER(uxtb16)(uint32_t x)
443 {
444 uint32_t res;
445 res = (uint16_t)(uint8_t)x;
446 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
447 return res;
448 }
449
450 uint32_t HELPER(clz)(uint32_t x)
451 {
452 return clz32(x);
453 }
454
455 int32_t HELPER(sdiv)(int32_t num, int32_t den)
456 {
457 if (den == 0)
458 return 0;
459 if (num == INT_MIN && den == -1)
460 return INT_MIN;
461 return num / den;
462 }
463
464 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
465 {
466 if (den == 0)
467 return 0;
468 return num / den;
469 }
470
471 uint32_t HELPER(rbit)(uint32_t x)
472 {
473 x = ((x & 0xff000000) >> 24)
474 | ((x & 0x00ff0000) >> 8)
475 | ((x & 0x0000ff00) << 8)
476 | ((x & 0x000000ff) << 24);
477 x = ((x & 0xf0f0f0f0) >> 4)
478 | ((x & 0x0f0f0f0f) << 4);
479 x = ((x & 0x88888888) >> 3)
480 | ((x & 0x44444444) >> 1)
481 | ((x & 0x22222222) << 1)
482 | ((x & 0x11111111) << 3);
483 return x;
484 }
485
486 uint32_t HELPER(abs)(uint32_t x)
487 {
488 return ((int32_t)x < 0) ? -x : x;
489 }
490
491 #if defined(CONFIG_USER_ONLY)
492
493 void do_interrupt (CPUState *env)
494 {
495 env->exception_index = -1;
496 }
497
498 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
499 int mmu_idx, int is_softmmu)
500 {
501 if (rw == 2) {
502 env->exception_index = EXCP_PREFETCH_ABORT;
503 env->cp15.c6_insn = address;
504 } else {
505 env->exception_index = EXCP_DATA_ABORT;
506 env->cp15.c6_data = address;
507 }
508 return 1;
509 }
510
511 /* These should probably raise undefined insn exceptions. */
512 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
513 {
514 int op1 = (insn >> 8) & 0xf;
515 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
516 return;
517 }
518
519 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
520 {
521 int op1 = (insn >> 8) & 0xf;
522 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
523 return 0;
524 }
525
526 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
527 {
528 cpu_abort(env, "cp15 insn %08x\n", insn);
529 }
530
531 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
532 {
533 cpu_abort(env, "cp15 insn %08x\n", insn);
534 }
535
536 /* These should probably raise undefined insn exceptions. */
537 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
538 {
539 cpu_abort(env, "v7m_mrs %d\n", reg);
540 }
541
542 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
543 {
544 cpu_abort(env, "v7m_mrs %d\n", reg);
545 return 0;
546 }
547
548 void switch_mode(CPUState *env, int mode)
549 {
550 if (mode != ARM_CPU_MODE_USR)
551 cpu_abort(env, "Tried to switch out of user mode\n");
552 }
553
554 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
555 {
556 cpu_abort(env, "banked r13 write\n");
557 }
558
559 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
560 {
561 cpu_abort(env, "banked r13 read\n");
562 return 0;
563 }
564
565 #else
566
567 extern int semihosting_enabled;
568
569 /* Map CPU modes onto saved register banks. */
570 static inline int bank_number (int mode)
571 {
572 switch (mode) {
573 case ARM_CPU_MODE_USR:
574 case ARM_CPU_MODE_SYS:
575 return 0;
576 case ARM_CPU_MODE_SVC:
577 return 1;
578 case ARM_CPU_MODE_ABT:
579 return 2;
580 case ARM_CPU_MODE_UND:
581 return 3;
582 case ARM_CPU_MODE_IRQ:
583 return 4;
584 case ARM_CPU_MODE_FIQ:
585 return 5;
586 }
587 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
588 return -1;
589 }
590
591 void switch_mode(CPUState *env, int mode)
592 {
593 int old_mode;
594 int i;
595
596 old_mode = env->uncached_cpsr & CPSR_M;
597 if (mode == old_mode)
598 return;
599
600 if (old_mode == ARM_CPU_MODE_FIQ) {
601 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
602 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
603 } else if (mode == ARM_CPU_MODE_FIQ) {
604 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
605 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
606 }
607
608 i = bank_number(old_mode);
609 env->banked_r13[i] = env->regs[13];
610 env->banked_r14[i] = env->regs[14];
611 env->banked_spsr[i] = env->spsr;
612
613 i = bank_number(mode);
614 env->regs[13] = env->banked_r13[i];
615 env->regs[14] = env->banked_r14[i];
616 env->spsr = env->banked_spsr[i];
617 }
618
619 static void v7m_push(CPUARMState *env, uint32_t val)
620 {
621 env->regs[13] -= 4;
622 stl_phys(env->regs[13], val);
623 }
624
625 static uint32_t v7m_pop(CPUARMState *env)
626 {
627 uint32_t val;
628 val = ldl_phys(env->regs[13]);
629 env->regs[13] += 4;
630 return val;
631 }
632
633 /* Switch to V7M main or process stack pointer. */
634 static void switch_v7m_sp(CPUARMState *env, int process)
635 {
636 uint32_t tmp;
637 if (env->v7m.current_sp != process) {
638 tmp = env->v7m.other_sp;
639 env->v7m.other_sp = env->regs[13];
640 env->regs[13] = tmp;
641 env->v7m.current_sp = process;
642 }
643 }
644
645 static void do_v7m_exception_exit(CPUARMState *env)
646 {
647 uint32_t type;
648 uint32_t xpsr;
649
650 type = env->regs[15];
651 if (env->v7m.exception != 0)
652 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
653
654 /* Switch to the target stack. */
655 switch_v7m_sp(env, (type & 4) != 0);
656 /* Pop registers. */
657 env->regs[0] = v7m_pop(env);
658 env->regs[1] = v7m_pop(env);
659 env->regs[2] = v7m_pop(env);
660 env->regs[3] = v7m_pop(env);
661 env->regs[12] = v7m_pop(env);
662 env->regs[14] = v7m_pop(env);
663 env->regs[15] = v7m_pop(env);
664 xpsr = v7m_pop(env);
665 xpsr_write(env, xpsr, 0xfffffdff);
666 /* Undo stack alignment. */
667 if (xpsr & 0x200)
668 env->regs[13] |= 4;
669 /* ??? The exception return type specifies Thread/Handler mode. However
670 this is also implied by the xPSR value. Not sure what to do
671 if there is a mismatch. */
672 /* ??? Likewise for mismatches between the CONTROL register and the stack
673 pointer. */
674 }
675
676 static void do_interrupt_v7m(CPUARMState *env)
677 {
678 uint32_t xpsr = xpsr_read(env);
679 uint32_t lr;
680 uint32_t addr;
681
682 lr = 0xfffffff1;
683 if (env->v7m.current_sp)
684 lr |= 4;
685 if (env->v7m.exception == 0)
686 lr |= 8;
687
688 /* For exceptions we just mark as pending on the NVIC, and let that
689 handle it. */
690 /* TODO: Need to escalate if the current priority is higher than the
691 one we're raising. */
692 switch (env->exception_index) {
693 case EXCP_UDEF:
694 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
695 return;
696 case EXCP_SWI:
697 env->regs[15] += 2;
698 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
699 return;
700 case EXCP_PREFETCH_ABORT:
701 case EXCP_DATA_ABORT:
702 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
703 return;
704 case EXCP_BKPT:
705 if (semihosting_enabled) {
706 int nr;
707 nr = lduw_code(env->regs[15]) & 0xff;
708 if (nr == 0xab) {
709 env->regs[15] += 2;
710 env->regs[0] = do_arm_semihosting(env);
711 return;
712 }
713 }
714 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
715 return;
716 case EXCP_IRQ:
717 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
718 break;
719 case EXCP_EXCEPTION_EXIT:
720 do_v7m_exception_exit(env);
721 return;
722 default:
723 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
724 return; /* Never happens. Keep compiler happy. */
725 }
726
727 /* Align stack pointer. */
728 /* ??? Should only do this if Configuration Control Register
729 STACKALIGN bit is set. */
730 if (env->regs[13] & 4) {
731 env->regs[13] -= 4;
732 xpsr |= 0x200;
733 }
734 /* Switch to the handler mode. */
735 v7m_push(env, xpsr);
736 v7m_push(env, env->regs[15]);
737 v7m_push(env, env->regs[14]);
738 v7m_push(env, env->regs[12]);
739 v7m_push(env, env->regs[3]);
740 v7m_push(env, env->regs[2]);
741 v7m_push(env, env->regs[1]);
742 v7m_push(env, env->regs[0]);
743 switch_v7m_sp(env, 0);
744 env->uncached_cpsr &= ~CPSR_IT;
745 env->regs[14] = lr;
746 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
747 env->regs[15] = addr & 0xfffffffe;
748 env->thumb = addr & 1;
749 }
750
751 /* Handle a CPU exception. */
752 void do_interrupt(CPUARMState *env)
753 {
754 uint32_t addr;
755 uint32_t mask;
756 int new_mode;
757 uint32_t offset;
758
759 if (IS_M(env)) {
760 do_interrupt_v7m(env);
761 return;
762 }
763 /* TODO: Vectored interrupt controller. */
764 switch (env->exception_index) {
765 case EXCP_UDEF:
766 new_mode = ARM_CPU_MODE_UND;
767 addr = 0x04;
768 mask = CPSR_I;
769 if (env->thumb)
770 offset = 2;
771 else
772 offset = 4;
773 break;
774 case EXCP_SWI:
775 if (semihosting_enabled) {
776 /* Check for semihosting interrupt. */
777 if (env->thumb) {
778 mask = lduw_code(env->regs[15] - 2) & 0xff;
779 } else {
780 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
781 }
782 /* Only intercept calls from privileged modes, to provide some
783 semblance of security. */
784 if (((mask == 0x123456 && !env->thumb)
785 || (mask == 0xab && env->thumb))
786 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
787 env->regs[0] = do_arm_semihosting(env);
788 return;
789 }
790 }
791 new_mode = ARM_CPU_MODE_SVC;
792 addr = 0x08;
793 mask = CPSR_I;
794 /* The PC already points to the next instruction. */
795 offset = 0;
796 break;
797 case EXCP_BKPT:
798 /* See if this is a semihosting syscall. */
799 if (env->thumb && semihosting_enabled) {
800 mask = lduw_code(env->regs[15]) & 0xff;
801 if (mask == 0xab
802 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
803 env->regs[15] += 2;
804 env->regs[0] = do_arm_semihosting(env);
805 return;
806 }
807 }
808 /* Fall through to prefetch abort. */
809 case EXCP_PREFETCH_ABORT:
810 new_mode = ARM_CPU_MODE_ABT;
811 addr = 0x0c;
812 mask = CPSR_A | CPSR_I;
813 offset = 4;
814 break;
815 case EXCP_DATA_ABORT:
816 new_mode = ARM_CPU_MODE_ABT;
817 addr = 0x10;
818 mask = CPSR_A | CPSR_I;
819 offset = 8;
820 break;
821 case EXCP_IRQ:
822 new_mode = ARM_CPU_MODE_IRQ;
823 addr = 0x18;
824 /* Disable IRQ and imprecise data aborts. */
825 mask = CPSR_A | CPSR_I;
826 offset = 4;
827 break;
828 case EXCP_FIQ:
829 new_mode = ARM_CPU_MODE_FIQ;
830 addr = 0x1c;
831 /* Disable FIQ, IRQ and imprecise data aborts. */
832 mask = CPSR_A | CPSR_I | CPSR_F;
833 offset = 4;
834 break;
835 default:
836 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
837 return; /* Never happens. Keep compiler happy. */
838 }
839 /* High vectors. */
840 if (env->cp15.c1_sys & (1 << 13)) {
841 addr += 0xffff0000;
842 }
843 switch_mode (env, new_mode);
844 env->spsr = cpsr_read(env);
845 /* Clear IT bits. */
846 env->condexec_bits = 0;
847 /* Switch to the new mode, and to the correct instruction set. */
848 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
849 env->uncached_cpsr |= mask;
850 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
851 env->regs[14] = env->regs[15] + offset;
852 env->regs[15] = addr;
853 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
854 }
855
856 /* Check section/page access permissions.
857 Returns the page protection flags, or zero if the access is not
858 permitted. */
859 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
860 int is_user)
861 {
862 int prot_ro;
863
864 if (domain == 3)
865 return PAGE_READ | PAGE_WRITE;
866
867 if (access_type == 1)
868 prot_ro = 0;
869 else
870 prot_ro = PAGE_READ;
871
872 switch (ap) {
873 case 0:
874 if (access_type == 1)
875 return 0;
876 switch ((env->cp15.c1_sys >> 8) & 3) {
877 case 1:
878 return is_user ? 0 : PAGE_READ;
879 case 2:
880 return PAGE_READ;
881 default:
882 return 0;
883 }
884 case 1:
885 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
886 case 2:
887 if (is_user)
888 return prot_ro;
889 else
890 return PAGE_READ | PAGE_WRITE;
891 case 3:
892 return PAGE_READ | PAGE_WRITE;
893 case 4: /* Reserved. */
894 return 0;
895 case 5:
896 return is_user ? 0 : prot_ro;
897 case 6:
898 return prot_ro;
899 case 7:
900 if (!arm_feature (env, ARM_FEATURE_V7))
901 return 0;
902 return prot_ro;
903 default:
904 abort();
905 }
906 }
907
908 static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
909 {
910 uint32_t table;
911
912 if (address & env->cp15.c2_mask)
913 table = env->cp15.c2_base1 & 0xffffc000;
914 else
915 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
916
917 table |= (address >> 18) & 0x3ffc;
918 return table;
919 }
920
921 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
922 int is_user, uint32_t *phys_ptr, int *prot,
923 target_ulong *page_size)
924 {
925 int code;
926 uint32_t table;
927 uint32_t desc;
928 int type;
929 int ap;
930 int domain;
931 uint32_t phys_addr;
932
933 /* Pagetable walk. */
934 /* Lookup l1 descriptor. */
935 table = get_level1_table_address(env, address);
936 desc = ldl_phys(table);
937 type = (desc & 3);
938 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
939 if (type == 0) {
940 /* Section translation fault. */
941 code = 5;
942 goto do_fault;
943 }
944 if (domain == 0 || domain == 2) {
945 if (type == 2)
946 code = 9; /* Section domain fault. */
947 else
948 code = 11; /* Page domain fault. */
949 goto do_fault;
950 }
951 if (type == 2) {
952 /* 1Mb section. */
953 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
954 ap = (desc >> 10) & 3;
955 code = 13;
956 *page_size = 1024 * 1024;
957 } else {
958 /* Lookup l2 entry. */
959 if (type == 1) {
960 /* Coarse pagetable. */
961 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
962 } else {
963 /* Fine pagetable. */
964 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
965 }
966 desc = ldl_phys(table);
967 switch (desc & 3) {
968 case 0: /* Page translation fault. */
969 code = 7;
970 goto do_fault;
971 case 1: /* 64k page. */
972 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
973 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
974 *page_size = 0x10000;
975 break;
976 case 2: /* 4k page. */
977 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
978 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
979 *page_size = 0x1000;
980 break;
981 case 3: /* 1k page. */
982 if (type == 1) {
983 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
984 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
985 } else {
986 /* Page translation fault. */
987 code = 7;
988 goto do_fault;
989 }
990 } else {
991 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
992 }
993 ap = (desc >> 4) & 3;
994 *page_size = 0x400;
995 break;
996 default:
997 /* Never happens, but compiler isn't smart enough to tell. */
998 abort();
999 }
1000 code = 15;
1001 }
1002 *prot = check_ap(env, ap, domain, access_type, is_user);
1003 if (!*prot) {
1004 /* Access permission fault. */
1005 goto do_fault;
1006 }
1007 *prot |= PAGE_EXEC;
1008 *phys_ptr = phys_addr;
1009 return 0;
1010 do_fault:
1011 return code | (domain << 4);
1012 }
1013
1014 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1015 int is_user, uint32_t *phys_ptr, int *prot,
1016 target_ulong *page_size)
1017 {
1018 int code;
1019 uint32_t table;
1020 uint32_t desc;
1021 uint32_t xn;
1022 int type;
1023 int ap;
1024 int domain;
1025 uint32_t phys_addr;
1026
1027 /* Pagetable walk. */
1028 /* Lookup l1 descriptor. */
1029 table = get_level1_table_address(env, address);
1030 desc = ldl_phys(table);
1031 type = (desc & 3);
1032 if (type == 0) {
1033 /* Section translation fault. */
1034 code = 5;
1035 domain = 0;
1036 goto do_fault;
1037 } else if (type == 2 && (desc & (1 << 18))) {
1038 /* Supersection. */
1039 domain = 0;
1040 } else {
1041 /* Section or page. */
1042 domain = (desc >> 4) & 0x1e;
1043 }
1044 domain = (env->cp15.c3 >> domain) & 3;
1045 if (domain == 0 || domain == 2) {
1046 if (type == 2)
1047 code = 9; /* Section domain fault. */
1048 else
1049 code = 11; /* Page domain fault. */
1050 goto do_fault;
1051 }
1052 if (type == 2) {
1053 if (desc & (1 << 18)) {
1054 /* Supersection. */
1055 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
1056 *page_size = 0x1000000;
1057 } else {
1058 /* Section. */
1059 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1060 *page_size = 0x100000;
1061 }
1062 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1063 xn = desc & (1 << 4);
1064 code = 13;
1065 } else {
1066 /* Lookup l2 entry. */
1067 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1068 desc = ldl_phys(table);
1069 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1070 switch (desc & 3) {
1071 case 0: /* Page translation fault. */
1072 code = 7;
1073 goto do_fault;
1074 case 1: /* 64k page. */
1075 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1076 xn = desc & (1 << 15);
1077 *page_size = 0x10000;
1078 break;
1079 case 2: case 3: /* 4k page. */
1080 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1081 xn = desc & 1;
1082 *page_size = 0x1000;
1083 break;
1084 default:
1085 /* Never happens, but compiler isn't smart enough to tell. */
1086 abort();
1087 }
1088 code = 15;
1089 }
1090 if (domain == 3) {
1091 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1092 } else {
1093 if (xn && access_type == 2)
1094 goto do_fault;
1095
1096 /* The simplified model uses AP[0] as an access control bit. */
1097 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1098 /* Access flag fault. */
1099 code = (code == 15) ? 6 : 3;
1100 goto do_fault;
1101 }
1102 *prot = check_ap(env, ap, domain, access_type, is_user);
1103 if (!*prot) {
1104 /* Access permission fault. */
1105 goto do_fault;
1106 }
1107 if (!xn) {
1108 *prot |= PAGE_EXEC;
1109 }
1110 }
1111 *phys_ptr = phys_addr;
1112 return 0;
1113 do_fault:
1114 return code | (domain << 4);
1115 }
1116
1117 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1118 int is_user, uint32_t *phys_ptr, int *prot)
1119 {
1120 int n;
1121 uint32_t mask;
1122 uint32_t base;
1123
1124 *phys_ptr = address;
1125 for (n = 7; n >= 0; n--) {
1126 base = env->cp15.c6_region[n];
1127 if ((base & 1) == 0)
1128 continue;
1129 mask = 1 << ((base >> 1) & 0x1f);
1130 /* Keep this shift separate from the above to avoid an
1131 (undefined) << 32. */
1132 mask = (mask << 1) - 1;
1133 if (((base ^ address) & ~mask) == 0)
1134 break;
1135 }
1136 if (n < 0)
1137 return 2;
1138
1139 if (access_type == 2) {
1140 mask = env->cp15.c5_insn;
1141 } else {
1142 mask = env->cp15.c5_data;
1143 }
1144 mask = (mask >> (n * 4)) & 0xf;
1145 switch (mask) {
1146 case 0:
1147 return 1;
1148 case 1:
1149 if (is_user)
1150 return 1;
1151 *prot = PAGE_READ | PAGE_WRITE;
1152 break;
1153 case 2:
1154 *prot = PAGE_READ;
1155 if (!is_user)
1156 *prot |= PAGE_WRITE;
1157 break;
1158 case 3:
1159 *prot = PAGE_READ | PAGE_WRITE;
1160 break;
1161 case 5:
1162 if (is_user)
1163 return 1;
1164 *prot = PAGE_READ;
1165 break;
1166 case 6:
1167 *prot = PAGE_READ;
1168 break;
1169 default:
1170 /* Bad permission. */
1171 return 1;
1172 }
1173 *prot |= PAGE_EXEC;
1174 return 0;
1175 }
1176
1177 static inline int get_phys_addr(CPUState *env, uint32_t address,
1178 int access_type, int is_user,
1179 uint32_t *phys_ptr, int *prot,
1180 target_ulong *page_size)
1181 {
1182 /* Fast Context Switch Extension. */
1183 if (address < 0x02000000)
1184 address += env->cp15.c13_fcse;
1185
1186 if ((env->cp15.c1_sys & 1) == 0) {
1187 /* MMU/MPU disabled. */
1188 *phys_ptr = address;
1189 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1190 *page_size = TARGET_PAGE_SIZE;
1191 return 0;
1192 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1193 *page_size = TARGET_PAGE_SIZE;
1194 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1195 prot);
1196 } else if (env->cp15.c1_sys & (1 << 23)) {
1197 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1198 prot, page_size);
1199 } else {
1200 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1201 prot, page_size);
1202 }
1203 }
1204
1205 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1206 int access_type, int mmu_idx, int is_softmmu)
1207 {
1208 uint32_t phys_addr;
1209 target_ulong page_size;
1210 int prot;
1211 int ret, is_user;
1212
1213 is_user = mmu_idx == MMU_USER_IDX;
1214 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1215 &page_size);
1216 if (ret == 0) {
1217 /* Map a single [sub]page. */
1218 phys_addr &= ~(uint32_t)0x3ff;
1219 address &= ~(uint32_t)0x3ff;
1220 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
1221 return 0;
1222 }
1223
1224 if (access_type == 2) {
1225 env->cp15.c5_insn = ret;
1226 env->cp15.c6_insn = address;
1227 env->exception_index = EXCP_PREFETCH_ABORT;
1228 } else {
1229 env->cp15.c5_data = ret;
1230 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1231 env->cp15.c5_data |= (1 << 11);
1232 env->cp15.c6_data = address;
1233 env->exception_index = EXCP_DATA_ABORT;
1234 }
1235 return 1;
1236 }
1237
1238 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1239 {
1240 uint32_t phys_addr;
1241 target_ulong page_size;
1242 int prot;
1243 int ret;
1244
1245 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
1246
1247 if (ret != 0)
1248 return -1;
1249
1250 return phys_addr;
1251 }
1252
1253 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1254 {
1255 int cp_num = (insn >> 8) & 0xf;
1256 int cp_info = (insn >> 5) & 7;
1257 int src = (insn >> 16) & 0xf;
1258 int operand = insn & 0xf;
1259
1260 if (env->cp[cp_num].cp_write)
1261 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1262 cp_info, src, operand, val);
1263 }
1264
1265 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
1266 {
1267 int cp_num = (insn >> 8) & 0xf;
1268 int cp_info = (insn >> 5) & 7;
1269 int dest = (insn >> 16) & 0xf;
1270 int operand = insn & 0xf;
1271
1272 if (env->cp[cp_num].cp_read)
1273 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1274 cp_info, dest, operand);
1275 return 0;
1276 }
1277
1278 /* Return basic MPU access permission bits. */
1279 static uint32_t simple_mpu_ap_bits(uint32_t val)
1280 {
1281 uint32_t ret;
1282 uint32_t mask;
1283 int i;
1284 ret = 0;
1285 mask = 3;
1286 for (i = 0; i < 16; i += 2) {
1287 ret |= (val >> i) & mask;
1288 mask <<= 2;
1289 }
1290 return ret;
1291 }
1292
1293 /* Pad basic MPU access permission bits to extended format. */
1294 static uint32_t extended_mpu_ap_bits(uint32_t val)
1295 {
1296 uint32_t ret;
1297 uint32_t mask;
1298 int i;
1299 ret = 0;
1300 mask = 3;
1301 for (i = 0; i < 16; i += 2) {
1302 ret |= (val & mask) << i;
1303 mask <<= 2;
1304 }
1305 return ret;
1306 }
1307
1308 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1309 {
1310 int op1;
1311 int op2;
1312 int crm;
1313
1314 op1 = (insn >> 21) & 7;
1315 op2 = (insn >> 5) & 7;
1316 crm = insn & 0xf;
1317 switch ((insn >> 16) & 0xf) {
1318 case 0:
1319 /* ID codes. */
1320 if (arm_feature(env, ARM_FEATURE_XSCALE))
1321 break;
1322 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1323 break;
1324 if (arm_feature(env, ARM_FEATURE_V7)
1325 && op1 == 2 && crm == 0 && op2 == 0) {
1326 env->cp15.c0_cssel = val & 0xf;
1327 break;
1328 }
1329 goto bad_reg;
1330 case 1: /* System configuration. */
1331 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1332 op2 = 0;
1333 switch (op2) {
1334 case 0:
1335 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1336 env->cp15.c1_sys = val;
1337 /* ??? Lots of these bits are not implemented. */
1338 /* This may enable/disable the MMU, so do a TLB flush. */
1339 tlb_flush(env, 1);
1340 break;
1341 case 1: /* Auxiliary cotrol register. */
1342 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1343 env->cp15.c1_xscaleauxcr = val;
1344 break;
1345 }
1346 /* Not implemented. */
1347 break;
1348 case 2:
1349 if (arm_feature(env, ARM_FEATURE_XSCALE))
1350 goto bad_reg;
1351 if (env->cp15.c1_coproc != val) {
1352 env->cp15.c1_coproc = val;
1353 /* ??? Is this safe when called from within a TB? */
1354 tb_flush(env);
1355 }
1356 break;
1357 default:
1358 goto bad_reg;
1359 }
1360 break;
1361 case 2: /* MMU Page table control / MPU cache control. */
1362 if (arm_feature(env, ARM_FEATURE_MPU)) {
1363 switch (op2) {
1364 case 0:
1365 env->cp15.c2_data = val;
1366 break;
1367 case 1:
1368 env->cp15.c2_insn = val;
1369 break;
1370 default:
1371 goto bad_reg;
1372 }
1373 } else {
1374 switch (op2) {
1375 case 0:
1376 env->cp15.c2_base0 = val;
1377 break;
1378 case 1:
1379 env->cp15.c2_base1 = val;
1380 break;
1381 case 2:
1382 val &= 7;
1383 env->cp15.c2_control = val;
1384 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1385 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1386 break;
1387 default:
1388 goto bad_reg;
1389 }
1390 }
1391 break;
1392 case 3: /* MMU Domain access control / MPU write buffer control. */
1393 env->cp15.c3 = val;
1394 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1395 break;
1396 case 4: /* Reserved. */
1397 goto bad_reg;
1398 case 5: /* MMU Fault status / MPU access permission. */
1399 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1400 op2 = 0;
1401 switch (op2) {
1402 case 0:
1403 if (arm_feature(env, ARM_FEATURE_MPU))
1404 val = extended_mpu_ap_bits(val);
1405 env->cp15.c5_data = val;
1406 break;
1407 case 1:
1408 if (arm_feature(env, ARM_FEATURE_MPU))
1409 val = extended_mpu_ap_bits(val);
1410 env->cp15.c5_insn = val;
1411 break;
1412 case 2:
1413 if (!arm_feature(env, ARM_FEATURE_MPU))
1414 goto bad_reg;
1415 env->cp15.c5_data = val;
1416 break;
1417 case 3:
1418 if (!arm_feature(env, ARM_FEATURE_MPU))
1419 goto bad_reg;
1420 env->cp15.c5_insn = val;
1421 break;
1422 default:
1423 goto bad_reg;
1424 }
1425 break;
1426 case 6: /* MMU Fault address / MPU base/size. */
1427 if (arm_feature(env, ARM_FEATURE_MPU)) {
1428 if (crm >= 8)
1429 goto bad_reg;
1430 env->cp15.c6_region[crm] = val;
1431 } else {
1432 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1433 op2 = 0;
1434 switch (op2) {
1435 case 0:
1436 env->cp15.c6_data = val;
1437 break;
1438 case 1: /* ??? This is WFAR on armv6 */
1439 case 2:
1440 env->cp15.c6_insn = val;
1441 break;
1442 default:
1443 goto bad_reg;
1444 }
1445 }
1446 break;
1447 case 7: /* Cache control. */
1448 env->cp15.c15_i_max = 0x000;
1449 env->cp15.c15_i_min = 0xff0;
1450 /* No cache, so nothing to do. */
1451 /* ??? MPCore has VA to PA translation functions. */
1452 break;
1453 case 8: /* MMU TLB control. */
1454 switch (op2) {
1455 case 0: /* Invalidate all. */
1456 tlb_flush(env, 0);
1457 break;
1458 case 1: /* Invalidate single TLB entry. */
1459 tlb_flush_page(env, val & TARGET_PAGE_MASK);
1460 break;
1461 case 2: /* Invalidate on ASID. */
1462 tlb_flush(env, val == 0);
1463 break;
1464 case 3: /* Invalidate single entry on MVA. */
1465 /* ??? This is like case 1, but ignores ASID. */
1466 tlb_flush(env, 1);
1467 break;
1468 default:
1469 goto bad_reg;
1470 }
1471 break;
1472 case 9:
1473 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1474 break;
1475 switch (crm) {
1476 case 0: /* Cache lockdown. */
1477 switch (op1) {
1478 case 0: /* L1 cache. */
1479 switch (op2) {
1480 case 0:
1481 env->cp15.c9_data = val;
1482 break;
1483 case 1:
1484 env->cp15.c9_insn = val;
1485 break;
1486 default:
1487 goto bad_reg;
1488 }
1489 break;
1490 case 1: /* L2 cache. */
1491 /* Ignore writes to L2 lockdown/auxiliary registers. */
1492 break;
1493 default:
1494 goto bad_reg;
1495 }
1496 break;
1497 case 1: /* TCM memory region registers. */
1498 /* Not implemented. */
1499 goto bad_reg;
1500 default:
1501 goto bad_reg;
1502 }
1503 break;
1504 case 10: /* MMU TLB lockdown. */
1505 /* ??? TLB lockdown not implemented. */
1506 break;
1507 case 12: /* Reserved. */
1508 goto bad_reg;
1509 case 13: /* Process ID. */
1510 switch (op2) {
1511 case 0:
1512 /* Unlike real hardware the qemu TLB uses virtual addresses,
1513 not modified virtual addresses, so this causes a TLB flush.
1514 */
1515 if (env->cp15.c13_fcse != val)
1516 tlb_flush(env, 1);
1517 env->cp15.c13_fcse = val;
1518 break;
1519 case 1:
1520 /* This changes the ASID, so do a TLB flush. */
1521 if (env->cp15.c13_context != val
1522 && !arm_feature(env, ARM_FEATURE_MPU))
1523 tlb_flush(env, 0);
1524 env->cp15.c13_context = val;
1525 break;
1526 default:
1527 goto bad_reg;
1528 }
1529 break;
1530 case 14: /* Reserved. */
1531 goto bad_reg;
1532 case 15: /* Implementation specific. */
1533 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1534 if (op2 == 0 && crm == 1) {
1535 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1536 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1537 tb_flush(env);
1538 env->cp15.c15_cpar = val & 0x3fff;
1539 }
1540 break;
1541 }
1542 goto bad_reg;
1543 }
1544 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1545 switch (crm) {
1546 case 0:
1547 break;
1548 case 1: /* Set TI925T configuration. */
1549 env->cp15.c15_ticonfig = val & 0xe7;
1550 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1551 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1552 break;
1553 case 2: /* Set I_max. */
1554 env->cp15.c15_i_max = val;
1555 break;
1556 case 3: /* Set I_min. */
1557 env->cp15.c15_i_min = val;
1558 break;
1559 case 4: /* Set thread-ID. */
1560 env->cp15.c15_threadid = val & 0xffff;
1561 break;
1562 case 8: /* Wait-for-interrupt (deprecated). */
1563 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1564 break;
1565 default:
1566 goto bad_reg;
1567 }
1568 }
1569 break;
1570 }
1571 return;
1572 bad_reg:
1573 /* ??? For debugging only. Should raise illegal instruction exception. */
1574 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1575 (insn >> 16) & 0xf, crm, op1, op2);
1576 }
1577
1578 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1579 {
1580 int op1;
1581 int op2;
1582 int crm;
1583
1584 op1 = (insn >> 21) & 7;
1585 op2 = (insn >> 5) & 7;
1586 crm = insn & 0xf;
1587 switch ((insn >> 16) & 0xf) {
1588 case 0: /* ID codes. */
1589 switch (op1) {
1590 case 0:
1591 switch (crm) {
1592 case 0:
1593 switch (op2) {
1594 case 0: /* Device ID. */
1595 return env->cp15.c0_cpuid;
1596 case 1: /* Cache Type. */
1597 return env->cp15.c0_cachetype;
1598 case 2: /* TCM status. */
1599 return 0;
1600 case 3: /* TLB type register. */
1601 return 0; /* No lockable TLB entries. */
1602 case 5: /* CPU ID */
1603 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1604 return env->cpu_index | 0x80000900;
1605 } else {
1606 return env->cpu_index;
1607 }
1608 default:
1609 goto bad_reg;
1610 }
1611 case 1:
1612 if (!arm_feature(env, ARM_FEATURE_V6))
1613 goto bad_reg;
1614 return env->cp15.c0_c1[op2];
1615 case 2:
1616 if (!arm_feature(env, ARM_FEATURE_V6))
1617 goto bad_reg;
1618 return env->cp15.c0_c2[op2];
1619 case 3: case 4: case 5: case 6: case 7:
1620 return 0;
1621 default:
1622 goto bad_reg;
1623 }
1624 case 1:
1625 /* These registers aren't documented on arm11 cores. However
1626 Linux looks at them anyway. */
1627 if (!arm_feature(env, ARM_FEATURE_V6))
1628 goto bad_reg;
1629 if (crm != 0)
1630 goto bad_reg;
1631 if (!arm_feature(env, ARM_FEATURE_V7))
1632 return 0;
1633
1634 switch (op2) {
1635 case 0:
1636 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1637 case 1:
1638 return env->cp15.c0_clid;
1639 case 7:
1640 return 0;
1641 }
1642 goto bad_reg;
1643 case 2:
1644 if (op2 != 0 || crm != 0)
1645 goto bad_reg;
1646 return env->cp15.c0_cssel;
1647 default:
1648 goto bad_reg;
1649 }
1650 case 1: /* System configuration. */
1651 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1652 op2 = 0;
1653 switch (op2) {
1654 case 0: /* Control register. */
1655 return env->cp15.c1_sys;
1656 case 1: /* Auxiliary control register. */
1657 if (arm_feature(env, ARM_FEATURE_XSCALE))
1658 return env->cp15.c1_xscaleauxcr;
1659 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1660 goto bad_reg;
1661 switch (ARM_CPUID(env)) {
1662 case ARM_CPUID_ARM1026:
1663 return 1;
1664 case ARM_CPUID_ARM1136:
1665 case ARM_CPUID_ARM1136_R2:
1666 return 7;
1667 case ARM_CPUID_ARM11MPCORE:
1668 return 1;
1669 case ARM_CPUID_CORTEXA8:
1670 return 2;
1671 case ARM_CPUID_CORTEXA9:
1672 return 0;
1673 default:
1674 goto bad_reg;
1675 }
1676 case 2: /* Coprocessor access register. */
1677 if (arm_feature(env, ARM_FEATURE_XSCALE))
1678 goto bad_reg;
1679 return env->cp15.c1_coproc;
1680 default:
1681 goto bad_reg;
1682 }
1683 case 2: /* MMU Page table control / MPU cache control. */
1684 if (arm_feature(env, ARM_FEATURE_MPU)) {
1685 switch (op2) {
1686 case 0:
1687 return env->cp15.c2_data;
1688 break;
1689 case 1:
1690 return env->cp15.c2_insn;
1691 break;
1692 default:
1693 goto bad_reg;
1694 }
1695 } else {
1696 switch (op2) {
1697 case 0:
1698 return env->cp15.c2_base0;
1699 case 1:
1700 return env->cp15.c2_base1;
1701 case 2:
1702 return env->cp15.c2_control;
1703 default:
1704 goto bad_reg;
1705 }
1706 }
1707 case 3: /* MMU Domain access control / MPU write buffer control. */
1708 return env->cp15.c3;
1709 case 4: /* Reserved. */
1710 goto bad_reg;
1711 case 5: /* MMU Fault status / MPU access permission. */
1712 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1713 op2 = 0;
1714 switch (op2) {
1715 case 0:
1716 if (arm_feature(env, ARM_FEATURE_MPU))
1717 return simple_mpu_ap_bits(env->cp15.c5_data);
1718 return env->cp15.c5_data;
1719 case 1:
1720 if (arm_feature(env, ARM_FEATURE_MPU))
1721 return simple_mpu_ap_bits(env->cp15.c5_data);
1722 return env->cp15.c5_insn;
1723 case 2:
1724 if (!arm_feature(env, ARM_FEATURE_MPU))
1725 goto bad_reg;
1726 return env->cp15.c5_data;
1727 case 3:
1728 if (!arm_feature(env, ARM_FEATURE_MPU))
1729 goto bad_reg;
1730 return env->cp15.c5_insn;
1731 default:
1732 goto bad_reg;
1733 }
1734 case 6: /* MMU Fault address. */
1735 if (arm_feature(env, ARM_FEATURE_MPU)) {
1736 if (crm >= 8)
1737 goto bad_reg;
1738 return env->cp15.c6_region[crm];
1739 } else {
1740 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1741 op2 = 0;
1742 switch (op2) {
1743 case 0:
1744 return env->cp15.c6_data;
1745 case 1:
1746 if (arm_feature(env, ARM_FEATURE_V6)) {
1747 /* Watchpoint Fault Adrress. */
1748 return 0; /* Not implemented. */
1749 } else {
1750 /* Instruction Fault Adrress. */
1751 /* Arm9 doesn't have an IFAR, but implementing it anyway
1752 shouldn't do any harm. */
1753 return env->cp15.c6_insn;
1754 }
1755 case 2:
1756 if (arm_feature(env, ARM_FEATURE_V6)) {
1757 /* Instruction Fault Adrress. */
1758 return env->cp15.c6_insn;
1759 } else {
1760 goto bad_reg;
1761 }
1762 default:
1763 goto bad_reg;
1764 }
1765 }
1766 case 7: /* Cache control. */
1767 /* FIXME: Should only clear Z flag if destination is r15. */
1768 env->ZF = 0;
1769 return 0;
1770 case 8: /* MMU TLB control. */
1771 goto bad_reg;
1772 case 9: /* Cache lockdown. */
1773 switch (op1) {
1774 case 0: /* L1 cache. */
1775 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1776 return 0;
1777 switch (op2) {
1778 case 0:
1779 return env->cp15.c9_data;
1780 case 1:
1781 return env->cp15.c9_insn;
1782 default:
1783 goto bad_reg;
1784 }
1785 case 1: /* L2 cache */
1786 if (crm != 0)
1787 goto bad_reg;
1788 /* L2 Lockdown and Auxiliary control. */
1789 return 0;
1790 default:
1791 goto bad_reg;
1792 }
1793 case 10: /* MMU TLB lockdown. */
1794 /* ??? TLB lockdown not implemented. */
1795 return 0;
1796 case 11: /* TCM DMA control. */
1797 case 12: /* Reserved. */
1798 goto bad_reg;
1799 case 13: /* Process ID. */
1800 switch (op2) {
1801 case 0:
1802 return env->cp15.c13_fcse;
1803 case 1:
1804 return env->cp15.c13_context;
1805 default:
1806 goto bad_reg;
1807 }
1808 case 14: /* Reserved. */
1809 goto bad_reg;
1810 case 15: /* Implementation specific. */
1811 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1812 if (op2 == 0 && crm == 1)
1813 return env->cp15.c15_cpar;
1814
1815 goto bad_reg;
1816 }
1817 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1818 switch (crm) {
1819 case 0:
1820 return 0;
1821 case 1: /* Read TI925T configuration. */
1822 return env->cp15.c15_ticonfig;
1823 case 2: /* Read I_max. */
1824 return env->cp15.c15_i_max;
1825 case 3: /* Read I_min. */
1826 return env->cp15.c15_i_min;
1827 case 4: /* Read thread-ID. */
1828 return env->cp15.c15_threadid;
1829 case 8: /* TI925T_status */
1830 return 0;
1831 }
1832 /* TODO: Peripheral port remap register:
1833 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1834 * controller base address at $rn & ~0xfff and map size of
1835 * 0x200 << ($rn & 0xfff), when MMU is off. */
1836 goto bad_reg;
1837 }
1838 return 0;
1839 }
1840 bad_reg:
1841 /* ??? For debugging only. Should raise illegal instruction exception. */
1842 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1843 (insn >> 16) & 0xf, crm, op1, op2);
1844 return 0;
1845 }
1846
1847 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
1848 {
1849 env->banked_r13[bank_number(mode)] = val;
1850 }
1851
1852 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
1853 {
1854 return env->banked_r13[bank_number(mode)];
1855 }
1856
1857 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
1858 {
1859 switch (reg) {
1860 case 0: /* APSR */
1861 return xpsr_read(env) & 0xf8000000;
1862 case 1: /* IAPSR */
1863 return xpsr_read(env) & 0xf80001ff;
1864 case 2: /* EAPSR */
1865 return xpsr_read(env) & 0xff00fc00;
1866 case 3: /* xPSR */
1867 return xpsr_read(env) & 0xff00fdff;
1868 case 5: /* IPSR */
1869 return xpsr_read(env) & 0x000001ff;
1870 case 6: /* EPSR */
1871 return xpsr_read(env) & 0x0700fc00;
1872 case 7: /* IEPSR */
1873 return xpsr_read(env) & 0x0700edff;
1874 case 8: /* MSP */
1875 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1876 case 9: /* PSP */
1877 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1878 case 16: /* PRIMASK */
1879 return (env->uncached_cpsr & CPSR_I) != 0;
1880 case 17: /* FAULTMASK */
1881 return (env->uncached_cpsr & CPSR_F) != 0;
1882 case 18: /* BASEPRI */
1883 case 19: /* BASEPRI_MAX */
1884 return env->v7m.basepri;
1885 case 20: /* CONTROL */
1886 return env->v7m.control;
1887 default:
1888 /* ??? For debugging only. */
1889 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1890 return 0;
1891 }
1892 }
1893
1894 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
1895 {
1896 switch (reg) {
1897 case 0: /* APSR */
1898 xpsr_write(env, val, 0xf8000000);
1899 break;
1900 case 1: /* IAPSR */
1901 xpsr_write(env, val, 0xf8000000);
1902 break;
1903 case 2: /* EAPSR */
1904 xpsr_write(env, val, 0xfe00fc00);
1905 break;
1906 case 3: /* xPSR */
1907 xpsr_write(env, val, 0xfe00fc00);
1908 break;
1909 case 5: /* IPSR */
1910 /* IPSR bits are readonly. */
1911 break;
1912 case 6: /* EPSR */
1913 xpsr_write(env, val, 0x0600fc00);
1914 break;
1915 case 7: /* IEPSR */
1916 xpsr_write(env, val, 0x0600fc00);
1917 break;
1918 case 8: /* MSP */
1919 if (env->v7m.current_sp)
1920 env->v7m.other_sp = val;
1921 else
1922 env->regs[13] = val;
1923 break;
1924 case 9: /* PSP */
1925 if (env->v7m.current_sp)
1926 env->regs[13] = val;
1927 else
1928 env->v7m.other_sp = val;
1929 break;
1930 case 16: /* PRIMASK */
1931 if (val & 1)
1932 env->uncached_cpsr |= CPSR_I;
1933 else
1934 env->uncached_cpsr &= ~CPSR_I;
1935 break;
1936 case 17: /* FAULTMASK */
1937 if (val & 1)
1938 env->uncached_cpsr |= CPSR_F;
1939 else
1940 env->uncached_cpsr &= ~CPSR_F;
1941 break;
1942 case 18: /* BASEPRI */
1943 env->v7m.basepri = val & 0xff;
1944 break;
1945 case 19: /* BASEPRI_MAX */
1946 val &= 0xff;
1947 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1948 env->v7m.basepri = val;
1949 break;
1950 case 20: /* CONTROL */
1951 env->v7m.control = val & 3;
1952 switch_v7m_sp(env, (val & 2) != 0);
1953 break;
1954 default:
1955 /* ??? For debugging only. */
1956 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1957 return;
1958 }
1959 }
1960
1961 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1962 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1963 void *opaque)
1964 {
1965 if (cpnum < 0 || cpnum > 14) {
1966 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1967 return;
1968 }
1969
1970 env->cp[cpnum].cp_read = cp_read;
1971 env->cp[cpnum].cp_write = cp_write;
1972 env->cp[cpnum].opaque = opaque;
1973 }
1974
1975 #endif
1976
1977 /* Note that signed overflow is undefined in C. The following routines are
1978 careful to use unsigned types where modulo arithmetic is required.
1979 Failure to do so _will_ break on newer gcc. */
1980
1981 /* Signed saturating arithmetic. */
1982
1983 /* Perform 16-bit signed saturating addition. */
1984 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
1985 {
1986 uint16_t res;
1987
1988 res = a + b;
1989 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
1990 if (a & 0x8000)
1991 res = 0x8000;
1992 else
1993 res = 0x7fff;
1994 }
1995 return res;
1996 }
1997
1998 /* Perform 8-bit signed saturating addition. */
1999 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2000 {
2001 uint8_t res;
2002
2003 res = a + b;
2004 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2005 if (a & 0x80)
2006 res = 0x80;
2007 else
2008 res = 0x7f;
2009 }
2010 return res;
2011 }
2012
2013 /* Perform 16-bit signed saturating subtraction. */
2014 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2015 {
2016 uint16_t res;
2017
2018 res = a - b;
2019 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2020 if (a & 0x8000)
2021 res = 0x8000;
2022 else
2023 res = 0x7fff;
2024 }
2025 return res;
2026 }
2027
2028 /* Perform 8-bit signed saturating subtraction. */
2029 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2030 {
2031 uint8_t res;
2032
2033 res = a - b;
2034 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2035 if (a & 0x80)
2036 res = 0x80;
2037 else
2038 res = 0x7f;
2039 }
2040 return res;
2041 }
2042
2043 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2044 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2045 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2046 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2047 #define PFX q
2048
2049 #include "op_addsub.h"
2050
2051 /* Unsigned saturating arithmetic. */
2052 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2053 {
2054 uint16_t res;
2055 res = a + b;
2056 if (res < a)
2057 res = 0xffff;
2058 return res;
2059 }
2060
2061 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2062 {
2063 if (a > b)
2064 return a - b;
2065 else
2066 return 0;
2067 }
2068
2069 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2070 {
2071 uint8_t res;
2072 res = a + b;
2073 if (res < a)
2074 res = 0xff;
2075 return res;
2076 }
2077
2078 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2079 {
2080 if (a > b)
2081 return a - b;
2082 else
2083 return 0;
2084 }
2085
2086 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2087 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2088 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2089 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2090 #define PFX uq
2091
2092 #include "op_addsub.h"
2093
2094 /* Signed modulo arithmetic. */
2095 #define SARITH16(a, b, n, op) do { \
2096 int32_t sum; \
2097 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2098 RESULT(sum, n, 16); \
2099 if (sum >= 0) \
2100 ge |= 3 << (n * 2); \
2101 } while(0)
2102
2103 #define SARITH8(a, b, n, op) do { \
2104 int32_t sum; \
2105 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2106 RESULT(sum, n, 8); \
2107 if (sum >= 0) \
2108 ge |= 1 << n; \
2109 } while(0)
2110
2111
2112 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2113 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2114 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2115 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2116 #define PFX s
2117 #define ARITH_GE
2118
2119 #include "op_addsub.h"
2120
2121 /* Unsigned modulo arithmetic. */
2122 #define ADD16(a, b, n) do { \
2123 uint32_t sum; \
2124 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2125 RESULT(sum, n, 16); \
2126 if ((sum >> 16) == 1) \
2127 ge |= 3 << (n * 2); \
2128 } while(0)
2129
2130 #define ADD8(a, b, n) do { \
2131 uint32_t sum; \
2132 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2133 RESULT(sum, n, 8); \
2134 if ((sum >> 8) == 1) \
2135 ge |= 1 << n; \
2136 } while(0)
2137
2138 #define SUB16(a, b, n) do { \
2139 uint32_t sum; \
2140 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2141 RESULT(sum, n, 16); \
2142 if ((sum >> 16) == 0) \
2143 ge |= 3 << (n * 2); \
2144 } while(0)
2145
2146 #define SUB8(a, b, n) do { \
2147 uint32_t sum; \
2148 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2149 RESULT(sum, n, 8); \
2150 if ((sum >> 8) == 0) \
2151 ge |= 1 << n; \
2152 } while(0)
2153
2154 #define PFX u
2155 #define ARITH_GE
2156
2157 #include "op_addsub.h"
2158
2159 /* Halved signed arithmetic. */
2160 #define ADD16(a, b, n) \
2161 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2162 #define SUB16(a, b, n) \
2163 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2164 #define ADD8(a, b, n) \
2165 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2166 #define SUB8(a, b, n) \
2167 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2168 #define PFX sh
2169
2170 #include "op_addsub.h"
2171
2172 /* Halved unsigned arithmetic. */
2173 #define ADD16(a, b, n) \
2174 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2175 #define SUB16(a, b, n) \
2176 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2177 #define ADD8(a, b, n) \
2178 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2179 #define SUB8(a, b, n) \
2180 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2181 #define PFX uh
2182
2183 #include "op_addsub.h"
2184
2185 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2186 {
2187 if (a > b)
2188 return a - b;
2189 else
2190 return b - a;
2191 }
2192
2193 /* Unsigned sum of absolute byte differences. */
2194 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2195 {
2196 uint32_t sum;
2197 sum = do_usad(a, b);
2198 sum += do_usad(a >> 8, b >> 8);
2199 sum += do_usad(a >> 16, b >>16);
2200 sum += do_usad(a >> 24, b >> 24);
2201 return sum;
2202 }
2203
2204 /* For ARMv6 SEL instruction. */
2205 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2206 {
2207 uint32_t mask;
2208
2209 mask = 0;
2210 if (flags & 1)
2211 mask |= 0xff;
2212 if (flags & 2)
2213 mask |= 0xff00;
2214 if (flags & 4)
2215 mask |= 0xff0000;
2216 if (flags & 8)
2217 mask |= 0xff000000;
2218 return (a & mask) | (b & ~mask);
2219 }
2220
2221 uint32_t HELPER(logicq_cc)(uint64_t val)
2222 {
2223 return (val >> 32) | (val != 0);
2224 }
2225
2226 /* VFP support. We follow the convention used for VFP instrunctions:
2227 Single precition routines have a "s" suffix, double precision a
2228 "d" suffix. */
2229
2230 /* Convert host exception flags to vfp form. */
2231 static inline int vfp_exceptbits_from_host(int host_bits)
2232 {
2233 int target_bits = 0;
2234
2235 if (host_bits & float_flag_invalid)
2236 target_bits |= 1;
2237 if (host_bits & float_flag_divbyzero)
2238 target_bits |= 2;
2239 if (host_bits & float_flag_overflow)
2240 target_bits |= 4;
2241 if (host_bits & float_flag_underflow)
2242 target_bits |= 8;
2243 if (host_bits & float_flag_inexact)
2244 target_bits |= 0x10;
2245 return target_bits;
2246 }
2247
2248 uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2249 {
2250 int i;
2251 uint32_t fpscr;
2252
2253 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2254 | (env->vfp.vec_len << 16)
2255 | (env->vfp.vec_stride << 20);
2256 i = get_float_exception_flags(&env->vfp.fp_status);
2257 fpscr |= vfp_exceptbits_from_host(i);
2258 return fpscr;
2259 }
2260
2261 uint32_t vfp_get_fpscr(CPUState *env)
2262 {
2263 return HELPER(vfp_get_fpscr)(env);
2264 }
2265
2266 /* Convert vfp exception flags to target form. */
2267 static inline int vfp_exceptbits_to_host(int target_bits)
2268 {
2269 int host_bits = 0;
2270
2271 if (target_bits & 1)
2272 host_bits |= float_flag_invalid;
2273 if (target_bits & 2)
2274 host_bits |= float_flag_divbyzero;
2275 if (target_bits & 4)
2276 host_bits |= float_flag_overflow;
2277 if (target_bits & 8)
2278 host_bits |= float_flag_underflow;
2279 if (target_bits & 0x10)
2280 host_bits |= float_flag_inexact;
2281 return host_bits;
2282 }
2283
2284 void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2285 {
2286 int i;
2287 uint32_t changed;
2288
2289 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2290 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2291 env->vfp.vec_len = (val >> 16) & 7;
2292 env->vfp.vec_stride = (val >> 20) & 3;
2293
2294 changed ^= val;
2295 if (changed & (3 << 22)) {
2296 i = (val >> 22) & 3;
2297 switch (i) {
2298 case 0:
2299 i = float_round_nearest_even;
2300 break;
2301 case 1:
2302 i = float_round_up;
2303 break;
2304 case 2:
2305 i = float_round_down;
2306 break;
2307 case 3:
2308 i = float_round_to_zero;
2309 break;
2310 }
2311 set_float_rounding_mode(i, &env->vfp.fp_status);
2312 }
2313 if (changed & (1 << 24))
2314 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2315 if (changed & (1 << 25))
2316 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2317
2318 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2319 set_float_exception_flags(i, &env->vfp.fp_status);
2320 }
2321
2322 void vfp_set_fpscr(CPUState *env, uint32_t val)
2323 {
2324 HELPER(vfp_set_fpscr)(env, val);
2325 }
2326
2327 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2328
2329 #define VFP_BINOP(name) \
2330 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2331 { \
2332 return float32_ ## name (a, b, &env->vfp.fp_status); \
2333 } \
2334 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2335 { \
2336 return float64_ ## name (a, b, &env->vfp.fp_status); \
2337 }
2338 VFP_BINOP(add)
2339 VFP_BINOP(sub)
2340 VFP_BINOP(mul)
2341 VFP_BINOP(div)
2342 #undef VFP_BINOP
2343
2344 float32 VFP_HELPER(neg, s)(float32 a)
2345 {
2346 return float32_chs(a);
2347 }
2348
2349 float64 VFP_HELPER(neg, d)(float64 a)
2350 {
2351 return float64_chs(a);
2352 }
2353
2354 float32 VFP_HELPER(abs, s)(float32 a)
2355 {
2356 return float32_abs(a);
2357 }
2358
2359 float64 VFP_HELPER(abs, d)(float64 a)
2360 {
2361 return float64_abs(a);
2362 }
2363
2364 float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2365 {
2366 return float32_sqrt(a, &env->vfp.fp_status);
2367 }
2368
2369 float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2370 {
2371 return float64_sqrt(a, &env->vfp.fp_status);
2372 }
2373
2374 /* XXX: check quiet/signaling case */
2375 #define DO_VFP_cmp(p, type) \
2376 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2377 { \
2378 uint32_t flags; \
2379 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2380 case 0: flags = 0x6; break; \
2381 case -1: flags = 0x8; break; \
2382 case 1: flags = 0x2; break; \
2383 default: case 2: flags = 0x3; break; \
2384 } \
2385 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2386 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2387 } \
2388 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2389 { \
2390 uint32_t flags; \
2391 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2392 case 0: flags = 0x6; break; \
2393 case -1: flags = 0x8; break; \
2394 case 1: flags = 0x2; break; \
2395 default: case 2: flags = 0x3; break; \
2396 } \
2397 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2398 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2399 }
2400 DO_VFP_cmp(s, float32)
2401 DO_VFP_cmp(d, float64)
2402 #undef DO_VFP_cmp
2403
2404 /* Helper routines to perform bitwise copies between float and int. */
2405 static inline float32 vfp_itos(uint32_t i)
2406 {
2407 union {
2408 uint32_t i;
2409 float32 s;
2410 } v;
2411
2412 v.i = i;
2413 return v.s;
2414 }
2415
2416 static inline uint32_t vfp_stoi(float32 s)
2417 {
2418 union {
2419 uint32_t i;
2420 float32 s;
2421 } v;
2422
2423 v.s = s;
2424 return v.i;
2425 }
2426
2427 static inline float64 vfp_itod(uint64_t i)
2428 {
2429 union {
2430 uint64_t i;
2431 float64 d;
2432 } v;
2433
2434 v.i = i;
2435 return v.d;
2436 }
2437
2438 static inline uint64_t vfp_dtoi(float64 d)
2439 {
2440 union {
2441 uint64_t i;
2442 float64 d;
2443 } v;
2444
2445 v.d = d;
2446 return v.i;
2447 }
2448
2449 /* Integer to float conversion. */
2450 float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2451 {
2452 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2453 }
2454
2455 float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2456 {
2457 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2458 }
2459
2460 float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2461 {
2462 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2463 }
2464
2465 float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2466 {
2467 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2468 }
2469
2470 /* Float to integer conversion. */
2471 float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2472 {
2473 if (float32_is_any_nan(x)) {
2474 return float32_zero;
2475 }
2476 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2477 }
2478
2479 float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2480 {
2481 if (float64_is_any_nan(x)) {
2482 return float32_zero;
2483 }
2484 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2485 }
2486
2487 float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2488 {
2489 if (float32_is_any_nan(x)) {
2490 return float32_zero;
2491 }
2492 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2493 }
2494
2495 float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2496 {
2497 if (float64_is_any_nan(x)) {
2498 return float32_zero;
2499 }
2500 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2501 }
2502
2503 float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2504 {
2505 if (float32_is_any_nan(x)) {
2506 return float32_zero;
2507 }
2508 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2509 }
2510
2511 float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2512 {
2513 if (float64_is_any_nan(x)) {
2514 return float32_zero;
2515 }
2516 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2517 }
2518
2519 float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2520 {
2521 if (float32_is_any_nan(x)) {
2522 return float32_zero;
2523 }
2524 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2525 }
2526
2527 float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2528 {
2529 if (float64_is_any_nan(x)) {
2530 return float32_zero;
2531 }
2532 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2533 }
2534
2535 /* floating point conversion */
2536 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2537 {
2538 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2539 /* ARM requires that S<->D conversion of any kind of NaN generates
2540 * a quiet NaN by forcing the most significant frac bit to 1.
2541 */
2542 return float64_maybe_silence_nan(r);
2543 }
2544
2545 float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2546 {
2547 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2548 /* ARM requires that S<->D conversion of any kind of NaN generates
2549 * a quiet NaN by forcing the most significant frac bit to 1.
2550 */
2551 return float32_maybe_silence_nan(r);
2552 }
2553
2554 /* VFP3 fixed point conversion. */
2555 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2556 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2557 { \
2558 ftype tmp; \
2559 tmp = sign##int32_to_##ftype ((itype##_t)vfp_##p##toi(x), \
2560 &env->vfp.fp_status); \
2561 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2562 } \
2563 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2564 { \
2565 ftype tmp; \
2566 if (ftype##_is_any_nan(x)) { \
2567 return ftype##_zero; \
2568 } \
2569 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2570 return vfp_ito##p(ftype##_to_##itype##_round_to_zero(tmp, \
2571 &env->vfp.fp_status)); \
2572 }
2573
2574 VFP_CONV_FIX(sh, d, float64, int16, )
2575 VFP_CONV_FIX(sl, d, float64, int32, )
2576 VFP_CONV_FIX(uh, d, float64, uint16, u)
2577 VFP_CONV_FIX(ul, d, float64, uint32, u)
2578 VFP_CONV_FIX(sh, s, float32, int16, )
2579 VFP_CONV_FIX(sl, s, float32, int32, )
2580 VFP_CONV_FIX(uh, s, float32, uint16, u)
2581 VFP_CONV_FIX(ul, s, float32, uint32, u)
2582 #undef VFP_CONV_FIX
2583
2584 /* Half precision conversions. */
2585 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2586 {
2587 float_status *s = &env->vfp.fp_status;
2588 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2589 return float16_to_float32(a, ieee, s);
2590 }
2591
2592 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2593 {
2594 float_status *s = &env->vfp.fp_status;
2595 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2596 return float32_to_float16(a, ieee, s);
2597 }
2598
2599 float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2600 {
2601 float_status *s = &env->vfp.fp_status;
2602 float32 two = int32_to_float32(2, s);
2603 return float32_sub(two, float32_mul(a, b, s), s);
2604 }
2605
2606 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2607 {
2608 float_status *s = &env->vfp.fp_status;
2609 float32 three = int32_to_float32(3, s);
2610 return float32_sub(three, float32_mul(a, b, s), s);
2611 }
2612
2613 /* NEON helpers. */
2614
2615 /* TODO: The architecture specifies the value that the estimate functions
2616 should return. We return the exact reciprocal/root instead. */
2617 float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2618 {
2619 float_status *s = &env->vfp.fp_status;
2620 float32 one = int32_to_float32(1, s);
2621 return float32_div(one, a, s);
2622 }
2623
2624 float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2625 {
2626 float_status *s = &env->vfp.fp_status;
2627 float32 one = int32_to_float32(1, s);
2628 return float32_div(one, float32_sqrt(a, s), s);
2629 }
2630
2631 uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2632 {
2633 float_status *s = &env->vfp.fp_status;
2634 float32 tmp;
2635 tmp = int32_to_float32(a, s);
2636 tmp = float32_scalbn(tmp, -32, s);
2637 tmp = helper_recpe_f32(tmp, env);
2638 tmp = float32_scalbn(tmp, 31, s);
2639 return float32_to_int32(tmp, s);
2640 }
2641
2642 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2643 {
2644 float_status *s = &env->vfp.fp_status;
2645 float32 tmp;
2646 tmp = int32_to_float32(a, s);
2647 tmp = float32_scalbn(tmp, -32, s);
2648 tmp = helper_rsqrte_f32(tmp, env);
2649 tmp = float32_scalbn(tmp, 31, s);
2650 return float32_to_int32(tmp, s);
2651 }
2652
2653 void HELPER(set_teecr)(CPUState *env, uint32_t val)
2654 {
2655 val &= 1;
2656 if (env->teecr != val) {
2657 env->teecr = val;
2658 tb_flush(env);
2659 }
2660 }
AR7 emulation for QEMU