2 * TriCore emulation for qemu: main translation routines.
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "tricore-opcodes.h"
39 static TCGv cpu_gpr_a
[16];
40 static TCGv cpu_gpr_d
[16];
42 static TCGv cpu_PSW_C
;
43 static TCGv cpu_PSW_V
;
44 static TCGv cpu_PSW_SV
;
45 static TCGv cpu_PSW_AV
;
46 static TCGv cpu_PSW_SAV
;
48 static TCGv_ptr cpu_env
;
50 #include "exec/gen-icount.h"
52 static const char *regnames_a
[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
58 static const char *regnames_d
[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
64 typedef struct DisasContext
{
65 struct TranslationBlock
*tb
;
66 target_ulong pc
, saved_pc
, next_pc
;
68 int singlestep_enabled
;
69 /* Routine used to access memory */
71 uint32_t hflags
, saved_hflags
;
90 void tricore_cpu_dump_state(CPUState
*cs
, FILE *f
,
91 fprintf_function cpu_fprintf
, int flags
)
93 TriCoreCPU
*cpu
= TRICORE_CPU(cs
);
94 CPUTriCoreState
*env
= &cpu
->env
;
100 cpu_fprintf(f
, "PC: " TARGET_FMT_lx
, env
->PC
);
101 cpu_fprintf(f
, " PSW: " TARGET_FMT_lx
, psw
);
102 cpu_fprintf(f
, " ICR: " TARGET_FMT_lx
, env
->ICR
);
103 cpu_fprintf(f
, "\nPCXI: " TARGET_FMT_lx
, env
->PCXI
);
104 cpu_fprintf(f
, " FCX: " TARGET_FMT_lx
, env
->FCX
);
105 cpu_fprintf(f
, " LCX: " TARGET_FMT_lx
, env
->LCX
);
107 for (i
= 0; i
< 16; ++i
) {
109 cpu_fprintf(f
, "\nGPR A%02d:", i
);
111 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gpr_a
[i
]);
113 for (i
= 0; i
< 16; ++i
) {
115 cpu_fprintf(f
, "\nGPR D%02d:", i
);
117 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gpr_d
[i
]);
119 cpu_fprintf(f
, "\n");
123 * Functions to generate micro-ops
126 /* Makros for generating helpers */
128 #define gen_helper_1arg(name, arg) do { \
129 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
130 gen_helper_##name(cpu_env, helper_tmp); \
131 tcg_temp_free_i32(helper_tmp); \
134 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
135 TCGv arg00 = tcg_temp_new(); \
136 TCGv arg01 = tcg_temp_new(); \
137 TCGv arg11 = tcg_temp_new(); \
138 tcg_gen_sari_tl(arg00, arg0, 16); \
139 tcg_gen_ext16s_tl(arg01, arg0); \
140 tcg_gen_ext16s_tl(arg11, arg1); \
141 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
142 tcg_temp_free(arg00); \
143 tcg_temp_free(arg01); \
144 tcg_temp_free(arg11); \
147 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
148 TCGv arg00 = tcg_temp_new(); \
149 TCGv arg01 = tcg_temp_new(); \
150 TCGv arg10 = tcg_temp_new(); \
151 TCGv arg11 = tcg_temp_new(); \
152 tcg_gen_sari_tl(arg00, arg0, 16); \
153 tcg_gen_ext16s_tl(arg01, arg0); \
154 tcg_gen_sari_tl(arg11, arg1, 16); \
155 tcg_gen_ext16s_tl(arg10, arg1); \
156 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
157 tcg_temp_free(arg00); \
158 tcg_temp_free(arg01); \
159 tcg_temp_free(arg10); \
160 tcg_temp_free(arg11); \
163 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
164 TCGv arg00 = tcg_temp_new(); \
165 TCGv arg01 = tcg_temp_new(); \
166 TCGv arg10 = tcg_temp_new(); \
167 TCGv arg11 = tcg_temp_new(); \
168 tcg_gen_sari_tl(arg00, arg0, 16); \
169 tcg_gen_ext16s_tl(arg01, arg0); \
170 tcg_gen_sari_tl(arg10, arg1, 16); \
171 tcg_gen_ext16s_tl(arg11, arg1); \
172 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
173 tcg_temp_free(arg00); \
174 tcg_temp_free(arg01); \
175 tcg_temp_free(arg10); \
176 tcg_temp_free(arg11); \
179 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
180 TCGv arg00 = tcg_temp_new(); \
181 TCGv arg01 = tcg_temp_new(); \
182 TCGv arg11 = tcg_temp_new(); \
183 tcg_gen_sari_tl(arg01, arg0, 16); \
184 tcg_gen_ext16s_tl(arg00, arg0); \
185 tcg_gen_sari_tl(arg11, arg1, 16); \
186 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
187 tcg_temp_free(arg00); \
188 tcg_temp_free(arg01); \
189 tcg_temp_free(arg11); \
192 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
193 TCGv_i64 ret = tcg_temp_new_i64(); \
194 TCGv_i64 arg1 = tcg_temp_new_i64(); \
196 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
197 gen_helper_##name(ret, arg1, arg2); \
198 tcg_gen_extr_i64_i32(rl, rh, ret); \
200 tcg_temp_free_i64(ret); \
201 tcg_temp_free_i64(arg1); \
204 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
205 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
206 ((offset & 0x0fffff) << 1))
208 /* Functions for load/save to/from memory */
210 static inline void gen_offset_ld(DisasContext
*ctx
, TCGv r1
, TCGv r2
,
211 int16_t con
, TCGMemOp mop
)
213 TCGv temp
= tcg_temp_new();
214 tcg_gen_addi_tl(temp
, r2
, con
);
215 tcg_gen_qemu_ld_tl(r1
, temp
, ctx
->mem_idx
, mop
);
219 static inline void gen_offset_st(DisasContext
*ctx
, TCGv r1
, TCGv r2
,
220 int16_t con
, TCGMemOp mop
)
222 TCGv temp
= tcg_temp_new();
223 tcg_gen_addi_tl(temp
, r2
, con
);
224 tcg_gen_qemu_st_tl(r1
, temp
, ctx
->mem_idx
, mop
);
228 static void gen_st_2regs_64(TCGv rh
, TCGv rl
, TCGv address
, DisasContext
*ctx
)
230 TCGv_i64 temp
= tcg_temp_new_i64();
232 tcg_gen_concat_i32_i64(temp
, rl
, rh
);
233 tcg_gen_qemu_st_i64(temp
, address
, ctx
->mem_idx
, MO_LEQ
);
235 tcg_temp_free_i64(temp
);
238 static void gen_offset_st_2regs(TCGv rh
, TCGv rl
, TCGv base
, int16_t con
,
241 TCGv temp
= tcg_temp_new();
242 tcg_gen_addi_tl(temp
, base
, con
);
243 gen_st_2regs_64(rh
, rl
, temp
, ctx
);
247 static void gen_ld_2regs_64(TCGv rh
, TCGv rl
, TCGv address
, DisasContext
*ctx
)
249 TCGv_i64 temp
= tcg_temp_new_i64();
251 tcg_gen_qemu_ld_i64(temp
, address
, ctx
->mem_idx
, MO_LEQ
);
252 /* write back to two 32 bit regs */
253 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
255 tcg_temp_free_i64(temp
);
258 static void gen_offset_ld_2regs(TCGv rh
, TCGv rl
, TCGv base
, int16_t con
,
261 TCGv temp
= tcg_temp_new();
262 tcg_gen_addi_tl(temp
, base
, con
);
263 gen_ld_2regs_64(rh
, rl
, temp
, ctx
);
267 static void gen_st_preincr(DisasContext
*ctx
, TCGv r1
, TCGv r2
, int16_t off
,
270 TCGv temp
= tcg_temp_new();
271 tcg_gen_addi_tl(temp
, r2
, off
);
272 tcg_gen_qemu_st_tl(r1
, temp
, ctx
->mem_idx
, mop
);
273 tcg_gen_mov_tl(r2
, temp
);
277 static void gen_ld_preincr(DisasContext
*ctx
, TCGv r1
, TCGv r2
, int16_t off
,
280 TCGv temp
= tcg_temp_new();
281 tcg_gen_addi_tl(temp
, r2
, off
);
282 tcg_gen_qemu_ld_tl(r1
, temp
, ctx
->mem_idx
, mop
);
283 tcg_gen_mov_tl(r2
, temp
);
287 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
288 static void gen_ldmst(DisasContext
*ctx
, int ereg
, TCGv ea
)
290 TCGv temp
= tcg_temp_new();
291 TCGv temp2
= tcg_temp_new();
293 /* temp = (M(EA, word) */
294 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
295 /* temp = temp & ~E[a][63:32]) */
296 tcg_gen_andc_tl(temp
, temp
, cpu_gpr_d
[ereg
+1]);
297 /* temp2 = (E[a][31:0] & E[a][63:32]); */
298 tcg_gen_and_tl(temp2
, cpu_gpr_d
[ereg
], cpu_gpr_d
[ereg
+1]);
299 /* temp = temp | temp2; */
300 tcg_gen_or_tl(temp
, temp
, temp2
);
301 /* M(EA, word) = temp; */
302 tcg_gen_qemu_st_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
305 tcg_temp_free(temp2
);
308 /* tmp = M(EA, word);
311 static void gen_swap(DisasContext
*ctx
, int reg
, TCGv ea
)
313 TCGv temp
= tcg_temp_new();
315 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
316 tcg_gen_qemu_st_tl(cpu_gpr_d
[reg
], ea
, ctx
->mem_idx
, MO_LEUL
);
317 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
322 /* We generate loads and store to core special function register (csfr) through
323 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
324 makros R, A and E, which allow read-only, all and endinit protected access.
325 These makros also specify in which ISA version the csfr was introduced. */
326 #define R(ADDRESS, REG, FEATURE) \
328 if (tricore_feature(env, FEATURE)) { \
329 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
332 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
333 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
334 static inline void gen_mfcr(CPUTriCoreState
*env
, TCGv ret
, int32_t offset
)
336 /* since we're caching PSW make this a special case */
337 if (offset
== 0xfe04) {
338 gen_helper_psw_read(ret
, cpu_env
);
349 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
350 since no execption occurs */
351 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
353 if (tricore_feature(env, FEATURE)) { \
354 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
357 /* Endinit protected registers
358 TODO: Since the endinit bit is in a register of a not yet implemented
359 watchdog device, we handle endinit protected registers like
360 all-access registers for now. */
361 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
362 static inline void gen_mtcr(CPUTriCoreState
*env
, DisasContext
*ctx
, TCGv r1
,
365 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
) {
366 /* since we're caching PSW make this a special case */
367 if (offset
== 0xfe04) {
368 gen_helper_psw_write(cpu_env
, r1
);
375 /* generate privilege trap */
379 /* Functions for arithmetic instructions */
381 static inline void gen_add_d(TCGv ret
, TCGv r1
, TCGv r2
)
383 TCGv t0
= tcg_temp_new_i32();
384 TCGv result
= tcg_temp_new_i32();
385 /* Addition and set V/SV bits */
386 tcg_gen_add_tl(result
, r1
, r2
);
388 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
389 tcg_gen_xor_tl(t0
, r1
, r2
);
390 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
392 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
393 /* Calc AV/SAV bits */
394 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
395 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
397 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
398 /* write back result */
399 tcg_gen_mov_tl(ret
, result
);
401 tcg_temp_free(result
);
406 gen_add64_d(TCGv_i64 ret
, TCGv_i64 r1
, TCGv_i64 r2
)
408 TCGv temp
= tcg_temp_new();
409 TCGv_i64 t0
= tcg_temp_new_i64();
410 TCGv_i64 t1
= tcg_temp_new_i64();
411 TCGv_i64 result
= tcg_temp_new_i64();
413 tcg_gen_add_i64(result
, r1
, r2
);
415 tcg_gen_xor_i64(t1
, result
, r1
);
416 tcg_gen_xor_i64(t0
, r1
, r2
);
417 tcg_gen_andc_i64(t1
, t1
, t0
);
418 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V
, t1
, 32);
420 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
421 /* calc AV/SAV bits */
422 tcg_gen_trunc_shr_i64_i32(temp
, result
, 32);
423 tcg_gen_add_tl(cpu_PSW_AV
, temp
, temp
);
424 tcg_gen_xor_tl(cpu_PSW_AV
, temp
, cpu_PSW_AV
);
426 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
427 /* write back result */
428 tcg_gen_mov_i64(ret
, result
);
431 tcg_temp_free_i64(result
);
432 tcg_temp_free_i64(t0
);
433 tcg_temp_free_i64(t1
);
437 gen_addsub64_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
438 TCGv r3
, void(*op1
)(TCGv
, TCGv
, TCGv
),
439 void(*op2
)(TCGv
, TCGv
, TCGv
))
441 TCGv temp
= tcg_temp_new();
442 TCGv temp2
= tcg_temp_new();
443 TCGv temp3
= tcg_temp_new();
444 TCGv temp4
= tcg_temp_new();
446 (*op1
)(temp
, r1_low
, r2
);
448 tcg_gen_xor_tl(temp2
, temp
, r1_low
);
449 tcg_gen_xor_tl(temp3
, r1_low
, r2
);
450 if (op1
== tcg_gen_add_tl
) {
451 tcg_gen_andc_tl(temp2
, temp2
, temp3
);
453 tcg_gen_and_tl(temp2
, temp2
, temp3
);
456 (*op2
)(temp3
, r1_high
, r3
);
458 tcg_gen_xor_tl(cpu_PSW_V
, temp3
, r1_high
);
459 tcg_gen_xor_tl(temp4
, r1_high
, r3
);
460 if (op2
== tcg_gen_add_tl
) {
461 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, temp4
);
463 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp4
);
465 /* combine V0/V1 bits */
466 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp2
);
468 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
470 tcg_gen_mov_tl(ret_low
, temp
);
471 tcg_gen_mov_tl(ret_high
, temp3
);
473 tcg_gen_add_tl(temp
, ret_low
, ret_low
);
474 tcg_gen_xor_tl(temp
, temp
, ret_low
);
475 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
476 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_PSW_AV
, ret_high
);
477 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
479 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
482 tcg_temp_free(temp2
);
483 tcg_temp_free(temp3
);
484 tcg_temp_free(temp4
);
487 /* ret = r2 + (r1 * r3); */
488 static inline void gen_madd32_d(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
)
490 TCGv_i64 t1
= tcg_temp_new_i64();
491 TCGv_i64 t2
= tcg_temp_new_i64();
492 TCGv_i64 t3
= tcg_temp_new_i64();
494 tcg_gen_ext_i32_i64(t1
, r1
);
495 tcg_gen_ext_i32_i64(t2
, r2
);
496 tcg_gen_ext_i32_i64(t3
, r3
);
498 tcg_gen_mul_i64(t1
, t1
, t3
);
499 tcg_gen_add_i64(t1
, t2
, t1
);
501 tcg_gen_trunc_i64_i32(ret
, t1
);
504 tcg_gen_setcondi_i64(TCG_COND_GT
, t3
, t1
, 0x7fffffffLL
);
505 /* t1 < -0x80000000 */
506 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t1
, -0x80000000LL
);
507 tcg_gen_or_i64(t2
, t2
, t3
);
508 tcg_gen_trunc_i64_i32(cpu_PSW_V
, t2
);
509 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
511 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
512 /* Calc AV/SAV bits */
513 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
514 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
516 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
518 tcg_temp_free_i64(t1
);
519 tcg_temp_free_i64(t2
);
520 tcg_temp_free_i64(t3
);
523 static inline void gen_maddi32_d(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
525 TCGv temp
= tcg_const_i32(con
);
526 gen_madd32_d(ret
, r1
, r2
, temp
);
531 gen_madd64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
534 TCGv t1
= tcg_temp_new();
535 TCGv t2
= tcg_temp_new();
536 TCGv t3
= tcg_temp_new();
537 TCGv t4
= tcg_temp_new();
539 tcg_gen_muls2_tl(t1
, t2
, r1
, r3
);
540 /* only the add can overflow */
541 tcg_gen_add2_tl(t3
, t4
, r2_low
, r2_high
, t1
, t2
);
543 tcg_gen_xor_tl(cpu_PSW_V
, t4
, r2_high
);
544 tcg_gen_xor_tl(t1
, r2_high
, t2
);
545 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t1
);
547 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
548 /* Calc AV/SAV bits */
549 tcg_gen_add_tl(cpu_PSW_AV
, t4
, t4
);
550 tcg_gen_xor_tl(cpu_PSW_AV
, t4
, cpu_PSW_AV
);
552 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
553 /* write back the result */
554 tcg_gen_mov_tl(ret_low
, t3
);
555 tcg_gen_mov_tl(ret_high
, t4
);
564 gen_maddu64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
567 TCGv_i64 t1
= tcg_temp_new_i64();
568 TCGv_i64 t2
= tcg_temp_new_i64();
569 TCGv_i64 t3
= tcg_temp_new_i64();
571 tcg_gen_extu_i32_i64(t1
, r1
);
572 tcg_gen_concat_i32_i64(t2
, r2_low
, r2_high
);
573 tcg_gen_extu_i32_i64(t3
, r3
);
575 tcg_gen_mul_i64(t1
, t1
, t3
);
576 tcg_gen_add_i64(t2
, t2
, t1
);
577 /* write back result */
578 tcg_gen_extr_i64_i32(ret_low
, ret_high
, t2
);
579 /* only the add overflows, if t2 < t1
581 tcg_gen_setcond_i64(TCG_COND_LTU
, t2
, t2
, t1
);
582 tcg_gen_trunc_i64_i32(cpu_PSW_V
, t2
);
583 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
585 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
586 /* Calc AV/SAV bits */
587 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
588 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
590 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
592 tcg_temp_free_i64(t1
);
593 tcg_temp_free_i64(t2
);
594 tcg_temp_free_i64(t3
);
598 gen_maddi64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
601 TCGv temp
= tcg_const_i32(con
);
602 gen_madd64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
607 gen_maddui64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
610 TCGv temp
= tcg_const_i32(con
);
611 gen_maddu64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
616 gen_madd_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
617 TCGv r3
, uint32_t n
, uint32_t mode
)
619 TCGv temp
= tcg_const_i32(n
);
620 TCGv temp2
= tcg_temp_new();
621 TCGv_i64 temp64
= tcg_temp_new_i64();
624 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
627 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
630 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
633 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
636 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
637 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
638 tcg_gen_add_tl
, tcg_gen_add_tl
);
640 tcg_temp_free(temp2
);
641 tcg_temp_free_i64(temp64
);
645 gen_maddsu_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
646 TCGv r3
, uint32_t n
, uint32_t mode
)
648 TCGv temp
= tcg_const_i32(n
);
649 TCGv temp2
= tcg_temp_new();
650 TCGv_i64 temp64
= tcg_temp_new_i64();
653 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
656 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
659 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
662 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
665 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
666 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
667 tcg_gen_sub_tl
, tcg_gen_add_tl
);
669 tcg_temp_free(temp2
);
670 tcg_temp_free_i64(temp64
);
674 gen_maddsum_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
675 TCGv r3
, uint32_t n
, uint32_t mode
)
677 TCGv temp
= tcg_const_i32(n
);
678 TCGv_i64 temp64
= tcg_temp_new_i64();
679 TCGv_i64 temp64_2
= tcg_temp_new_i64();
680 TCGv_i64 temp64_3
= tcg_temp_new_i64();
683 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
686 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
689 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
692 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
695 tcg_gen_concat_i32_i64(temp64_3
, r1_low
, r1_high
);
696 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
697 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
698 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
699 tcg_gen_shli_i64(temp64
, temp64
, 16);
701 gen_add64_d(temp64_2
, temp64_3
, temp64
);
702 /* write back result */
703 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_2
);
706 tcg_temp_free_i64(temp64
);
707 tcg_temp_free_i64(temp64_2
);
708 tcg_temp_free_i64(temp64_3
);
711 static inline void gen_adds(TCGv ret
, TCGv r1
, TCGv r2
);
714 gen_madds_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
715 TCGv r3
, uint32_t n
, uint32_t mode
)
717 TCGv temp
= tcg_const_i32(n
);
718 TCGv temp2
= tcg_temp_new();
719 TCGv temp3
= tcg_temp_new();
720 TCGv_i64 temp64
= tcg_temp_new_i64();
724 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
727 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
730 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
733 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
736 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
737 gen_adds(ret_low
, r1_low
, temp
);
738 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
739 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
740 gen_adds(ret_high
, r1_high
, temp2
);
742 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
743 /* combine av bits */
744 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
747 tcg_temp_free(temp2
);
748 tcg_temp_free(temp3
);
749 tcg_temp_free_i64(temp64
);
753 static inline void gen_subs(TCGv ret
, TCGv r1
, TCGv r2
);
756 gen_maddsus_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
757 TCGv r3
, uint32_t n
, uint32_t mode
)
759 TCGv temp
= tcg_const_i32(n
);
760 TCGv temp2
= tcg_temp_new();
761 TCGv temp3
= tcg_temp_new();
762 TCGv_i64 temp64
= tcg_temp_new_i64();
766 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
769 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
772 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
775 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
778 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
779 gen_subs(ret_low
, r1_low
, temp
);
780 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
781 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
782 gen_adds(ret_high
, r1_high
, temp2
);
784 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
785 /* combine av bits */
786 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
789 tcg_temp_free(temp2
);
790 tcg_temp_free(temp3
);
791 tcg_temp_free_i64(temp64
);
796 gen_maddsums_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
797 TCGv r3
, uint32_t n
, uint32_t mode
)
799 TCGv temp
= tcg_const_i32(n
);
800 TCGv_i64 temp64
= tcg_temp_new_i64();
801 TCGv_i64 temp64_2
= tcg_temp_new_i64();
805 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
808 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
811 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
814 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
817 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
818 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
819 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
820 tcg_gen_shli_i64(temp64
, temp64
, 16);
821 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
823 gen_helper_add64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
824 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
827 tcg_temp_free_i64(temp64
);
828 tcg_temp_free_i64(temp64_2
);
833 gen_maddm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
834 TCGv r3
, uint32_t n
, uint32_t mode
)
836 TCGv temp
= tcg_const_i32(n
);
837 TCGv_i64 temp64
= tcg_temp_new_i64();
838 TCGv_i64 temp64_2
= tcg_temp_new_i64();
839 TCGv_i64 temp64_3
= tcg_temp_new_i64();
842 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
845 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
848 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
851 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
854 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
855 gen_add64_d(temp64_3
, temp64_2
, temp64
);
856 /* write back result */
857 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_3
);
860 tcg_temp_free_i64(temp64
);
861 tcg_temp_free_i64(temp64_2
);
862 tcg_temp_free_i64(temp64_3
);
866 gen_maddms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
867 TCGv r3
, uint32_t n
, uint32_t mode
)
869 TCGv temp
= tcg_const_i32(n
);
870 TCGv_i64 temp64
= tcg_temp_new_i64();
871 TCGv_i64 temp64_2
= tcg_temp_new_i64();
874 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
877 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
880 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
883 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
886 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
887 gen_helper_add64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
888 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
891 tcg_temp_free_i64(temp64
);
892 tcg_temp_free_i64(temp64_2
);
896 gen_maddr64_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
, uint32_t n
,
899 TCGv temp
= tcg_const_i32(n
);
900 TCGv_i64 temp64
= tcg_temp_new_i64();
903 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
906 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
909 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
912 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
915 gen_helper_addr_h(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
918 tcg_temp_free_i64(temp64
);
922 gen_maddr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
924 TCGv temp
= tcg_temp_new();
925 TCGv temp2
= tcg_temp_new();
927 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
928 tcg_gen_shli_tl(temp
, r1
, 16);
929 gen_maddr64_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
932 tcg_temp_free(temp2
);
936 gen_maddsur32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
938 TCGv temp
= tcg_const_i32(n
);
939 TCGv temp2
= tcg_temp_new();
940 TCGv_i64 temp64
= tcg_temp_new_i64();
943 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
946 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
949 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
952 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
955 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
956 tcg_gen_shli_tl(temp
, r1
, 16);
957 gen_helper_addsur_h(ret
, cpu_env
, temp64
, temp
, temp2
);
960 tcg_temp_free(temp2
);
961 tcg_temp_free_i64(temp64
);
966 gen_maddr64s_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
,
967 uint32_t n
, uint32_t mode
)
969 TCGv temp
= tcg_const_i32(n
);
970 TCGv_i64 temp64
= tcg_temp_new_i64();
973 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
976 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
979 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
982 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
985 gen_helper_addr_h_ssov(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
988 tcg_temp_free_i64(temp64
);
992 gen_maddr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
994 TCGv temp
= tcg_temp_new();
995 TCGv temp2
= tcg_temp_new();
997 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
998 tcg_gen_shli_tl(temp
, r1
, 16);
999 gen_maddr64s_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1001 tcg_temp_free(temp
);
1002 tcg_temp_free(temp2
);
1006 gen_maddsur32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1008 TCGv temp
= tcg_const_i32(n
);
1009 TCGv temp2
= tcg_temp_new();
1010 TCGv_i64 temp64
= tcg_temp_new_i64();
1013 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1016 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1019 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1022 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1025 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1026 tcg_gen_shli_tl(temp
, r1
, 16);
1027 gen_helper_addsur_h_ssov(ret
, cpu_env
, temp64
, temp
, temp2
);
1029 tcg_temp_free(temp
);
1030 tcg_temp_free(temp2
);
1031 tcg_temp_free_i64(temp64
);
1035 gen_maddr_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1037 TCGv temp
= tcg_const_i32(n
);
1038 gen_helper_maddr_q(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1039 tcg_temp_free(temp
);
1043 gen_maddrs_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1045 TCGv temp
= tcg_const_i32(n
);
1046 gen_helper_maddr_q_ssov(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1047 tcg_temp_free(temp
);
1051 gen_madd32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1052 uint32_t up_shift
, CPUTriCoreState
*env
)
1054 TCGv temp
= tcg_temp_new();
1055 TCGv temp2
= tcg_temp_new();
1056 TCGv temp3
= tcg_temp_new();
1057 TCGv_i64 t1
= tcg_temp_new_i64();
1058 TCGv_i64 t2
= tcg_temp_new_i64();
1059 TCGv_i64 t3
= tcg_temp_new_i64();
1061 tcg_gen_ext_i32_i64(t2
, arg2
);
1062 tcg_gen_ext_i32_i64(t3
, arg3
);
1064 tcg_gen_mul_i64(t2
, t2
, t3
);
1065 tcg_gen_shli_i64(t2
, t2
, n
);
1067 tcg_gen_ext_i32_i64(t1
, arg1
);
1068 tcg_gen_sari_i64(t2
, t2
, up_shift
);
1070 tcg_gen_add_i64(t3
, t1
, t2
);
1071 tcg_gen_trunc_i64_i32(temp3
, t3
);
1073 tcg_gen_setcondi_i64(TCG_COND_GT
, t1
, t3
, 0x7fffffffLL
);
1074 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t3
, -0x80000000LL
);
1075 tcg_gen_or_i64(t1
, t1
, t2
);
1076 tcg_gen_trunc_i64_i32(cpu_PSW_V
, t1
);
1077 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1078 /* We produce an overflow on the host if the mul before was
1079 (0x80000000 * 0x80000000) << 1). If this is the
1080 case, we negate the ovf. */
1082 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
1083 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
1084 tcg_gen_and_tl(temp
, temp
, temp2
);
1085 tcg_gen_shli_tl(temp
, temp
, 31);
1086 /* negate v bit, if special condition */
1087 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1090 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1091 /* Calc AV/SAV bits */
1092 tcg_gen_add_tl(cpu_PSW_AV
, temp3
, temp3
);
1093 tcg_gen_xor_tl(cpu_PSW_AV
, temp3
, cpu_PSW_AV
);
1095 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1096 /* write back result */
1097 tcg_gen_mov_tl(ret
, temp3
);
1099 tcg_temp_free(temp
);
1100 tcg_temp_free(temp2
);
1101 tcg_temp_free(temp3
);
1102 tcg_temp_free_i64(t1
);
1103 tcg_temp_free_i64(t2
);
1104 tcg_temp_free_i64(t3
);
1108 gen_m16add32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
1110 TCGv temp
= tcg_temp_new();
1111 TCGv temp2
= tcg_temp_new();
1113 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1114 } else { /* n is exspected to be 1 */
1115 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1116 tcg_gen_shli_tl(temp
, temp
, 1);
1117 /* catch special case r1 = r2 = 0x8000 */
1118 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1119 tcg_gen_sub_tl(temp
, temp
, temp2
);
1121 gen_add_d(ret
, arg1
, temp
);
1123 tcg_temp_free(temp
);
1124 tcg_temp_free(temp2
);
1128 gen_m16adds32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
1130 TCGv temp
= tcg_temp_new();
1131 TCGv temp2
= tcg_temp_new();
1133 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1134 } else { /* n is exspected to be 1 */
1135 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1136 tcg_gen_shli_tl(temp
, temp
, 1);
1137 /* catch special case r1 = r2 = 0x8000 */
1138 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1139 tcg_gen_sub_tl(temp
, temp
, temp2
);
1141 gen_adds(ret
, arg1
, temp
);
1143 tcg_temp_free(temp
);
1144 tcg_temp_free(temp2
);
1148 gen_m16add64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1149 TCGv arg3
, uint32_t n
)
1151 TCGv temp
= tcg_temp_new();
1152 TCGv temp2
= tcg_temp_new();
1153 TCGv_i64 t1
= tcg_temp_new_i64();
1154 TCGv_i64 t2
= tcg_temp_new_i64();
1155 TCGv_i64 t3
= tcg_temp_new_i64();
1158 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1159 } else { /* n is exspected to be 1 */
1160 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1161 tcg_gen_shli_tl(temp
, temp
, 1);
1162 /* catch special case r1 = r2 = 0x8000 */
1163 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1164 tcg_gen_sub_tl(temp
, temp
, temp2
);
1166 tcg_gen_ext_i32_i64(t2
, temp
);
1167 tcg_gen_shli_i64(t2
, t2
, 16);
1168 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1169 gen_add64_d(t3
, t1
, t2
);
1170 /* write back result */
1171 tcg_gen_extr_i64_i32(rl
, rh
, t3
);
1173 tcg_temp_free_i64(t1
);
1174 tcg_temp_free_i64(t2
);
1175 tcg_temp_free_i64(t3
);
1176 tcg_temp_free(temp
);
1177 tcg_temp_free(temp2
);
1181 gen_m16adds64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1182 TCGv arg3
, uint32_t n
)
1184 TCGv temp
= tcg_temp_new();
1185 TCGv temp2
= tcg_temp_new();
1186 TCGv_i64 t1
= tcg_temp_new_i64();
1187 TCGv_i64 t2
= tcg_temp_new_i64();
1190 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1191 } else { /* n is exspected to be 1 */
1192 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1193 tcg_gen_shli_tl(temp
, temp
, 1);
1194 /* catch special case r1 = r2 = 0x8000 */
1195 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1196 tcg_gen_sub_tl(temp
, temp
, temp2
);
1198 tcg_gen_ext_i32_i64(t2
, temp
);
1199 tcg_gen_shli_i64(t2
, t2
, 16);
1200 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1202 gen_helper_add64_ssov(t1
, cpu_env
, t1
, t2
);
1203 tcg_gen_extr_i64_i32(rl
, rh
, t1
);
1205 tcg_temp_free(temp
);
1206 tcg_temp_free(temp2
);
1207 tcg_temp_free_i64(t1
);
1208 tcg_temp_free_i64(t2
);
1212 gen_madd64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1213 TCGv arg3
, uint32_t n
, CPUTriCoreState
*env
)
1215 TCGv_i64 t1
= tcg_temp_new_i64();
1216 TCGv_i64 t2
= tcg_temp_new_i64();
1217 TCGv_i64 t3
= tcg_temp_new_i64();
1218 TCGv_i64 t4
= tcg_temp_new_i64();
1221 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1222 tcg_gen_ext_i32_i64(t2
, arg2
);
1223 tcg_gen_ext_i32_i64(t3
, arg3
);
1225 tcg_gen_mul_i64(t2
, t2
, t3
);
1227 tcg_gen_shli_i64(t2
, t2
, 1);
1229 tcg_gen_add_i64(t4
, t1
, t2
);
1231 tcg_gen_xor_i64(t3
, t4
, t1
);
1232 tcg_gen_xor_i64(t2
, t1
, t2
);
1233 tcg_gen_andc_i64(t3
, t3
, t2
);
1234 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V
, t3
, 32);
1235 /* We produce an overflow on the host if the mul before was
1236 (0x80000000 * 0x80000000) << 1). If this is the
1237 case, we negate the ovf. */
1239 temp
= tcg_temp_new();
1240 temp2
= tcg_temp_new();
1241 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
1242 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
1243 tcg_gen_and_tl(temp
, temp
, temp2
);
1244 tcg_gen_shli_tl(temp
, temp
, 31);
1245 /* negate v bit, if special condition */
1246 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1248 tcg_temp_free(temp
);
1249 tcg_temp_free(temp2
);
1251 /* write back result */
1252 tcg_gen_extr_i64_i32(rl
, rh
, t4
);
1254 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1255 /* Calc AV/SAV bits */
1256 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
1257 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
1259 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1261 tcg_temp_free_i64(t1
);
1262 tcg_temp_free_i64(t2
);
1263 tcg_temp_free_i64(t3
);
1264 tcg_temp_free_i64(t4
);
1268 gen_madds32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1271 TCGv_i64 t1
= tcg_temp_new_i64();
1272 TCGv_i64 t2
= tcg_temp_new_i64();
1273 TCGv_i64 t3
= tcg_temp_new_i64();
1275 tcg_gen_ext_i32_i64(t1
, arg1
);
1276 tcg_gen_ext_i32_i64(t2
, arg2
);
1277 tcg_gen_ext_i32_i64(t3
, arg3
);
1279 tcg_gen_mul_i64(t2
, t2
, t3
);
1280 tcg_gen_sari_i64(t2
, t2
, up_shift
- n
);
1282 gen_helper_madd32_q_add_ssov(ret
, cpu_env
, t1
, t2
);
1284 tcg_temp_free_i64(t1
);
1285 tcg_temp_free_i64(t2
);
1286 tcg_temp_free_i64(t3
);
1290 gen_madds64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1291 TCGv arg3
, uint32_t n
)
1293 TCGv_i64 r1
= tcg_temp_new_i64();
1294 TCGv temp
= tcg_const_i32(n
);
1296 tcg_gen_concat_i32_i64(r1
, arg1_low
, arg1_high
);
1297 gen_helper_madd64_q_ssov(r1
, cpu_env
, r1
, arg2
, arg3
, temp
);
1298 tcg_gen_extr_i64_i32(rl
, rh
, r1
);
1300 tcg_temp_free_i64(r1
);
1301 tcg_temp_free(temp
);
1303 /* ret = r2 - (r1 * r3); */
1304 static inline void gen_msub32_d(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
)
1306 TCGv_i64 t1
= tcg_temp_new_i64();
1307 TCGv_i64 t2
= tcg_temp_new_i64();
1308 TCGv_i64 t3
= tcg_temp_new_i64();
1310 tcg_gen_ext_i32_i64(t1
, r1
);
1311 tcg_gen_ext_i32_i64(t2
, r2
);
1312 tcg_gen_ext_i32_i64(t3
, r3
);
1314 tcg_gen_mul_i64(t1
, t1
, t3
);
1315 tcg_gen_sub_i64(t1
, t2
, t1
);
1317 tcg_gen_trunc_i64_i32(ret
, t1
);
1320 tcg_gen_setcondi_i64(TCG_COND_GT
, t3
, t1
, 0x7fffffffLL
);
1321 /* result < -0x80000000 */
1322 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t1
, -0x80000000LL
);
1323 tcg_gen_or_i64(t2
, t2
, t3
);
1324 tcg_gen_trunc_i64_i32(cpu_PSW_V
, t2
);
1325 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1328 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1329 /* Calc AV/SAV bits */
1330 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1331 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1333 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1335 tcg_temp_free_i64(t1
);
1336 tcg_temp_free_i64(t2
);
1337 tcg_temp_free_i64(t3
);
1340 static inline void gen_msubi32_d(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1342 TCGv temp
= tcg_const_i32(con
);
1343 gen_msub32_d(ret
, r1
, r2
, temp
);
1344 tcg_temp_free(temp
);
1348 gen_msub64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1351 TCGv t1
= tcg_temp_new();
1352 TCGv t2
= tcg_temp_new();
1353 TCGv t3
= tcg_temp_new();
1354 TCGv t4
= tcg_temp_new();
1356 tcg_gen_muls2_tl(t1
, t2
, r1
, r3
);
1357 /* only the sub can overflow */
1358 tcg_gen_sub2_tl(t3
, t4
, r2_low
, r2_high
, t1
, t2
);
1360 tcg_gen_xor_tl(cpu_PSW_V
, t4
, r2_high
);
1361 tcg_gen_xor_tl(t1
, r2_high
, t2
);
1362 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, t1
);
1364 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1365 /* Calc AV/SAV bits */
1366 tcg_gen_add_tl(cpu_PSW_AV
, t4
, t4
);
1367 tcg_gen_xor_tl(cpu_PSW_AV
, t4
, cpu_PSW_AV
);
1369 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1370 /* write back the result */
1371 tcg_gen_mov_tl(ret_low
, t3
);
1372 tcg_gen_mov_tl(ret_high
, t4
);
1381 gen_msubi64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1384 TCGv temp
= tcg_const_i32(con
);
1385 gen_msub64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1386 tcg_temp_free(temp
);
1390 gen_msubu64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1393 TCGv_i64 t1
= tcg_temp_new_i64();
1394 TCGv_i64 t2
= tcg_temp_new_i64();
1395 TCGv_i64 t3
= tcg_temp_new_i64();
1397 tcg_gen_extu_i32_i64(t1
, r1
);
1398 tcg_gen_concat_i32_i64(t2
, r2_low
, r2_high
);
1399 tcg_gen_extu_i32_i64(t3
, r3
);
1401 tcg_gen_mul_i64(t1
, t1
, t3
);
1402 tcg_gen_sub_i64(t3
, t2
, t1
);
1403 tcg_gen_extr_i64_i32(ret_low
, ret_high
, t3
);
1404 /* calc V bit, only the sub can overflow, if t1 > t2 */
1405 tcg_gen_setcond_i64(TCG_COND_GTU
, t1
, t1
, t2
);
1406 tcg_gen_trunc_i64_i32(cpu_PSW_V
, t1
);
1407 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1409 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1410 /* Calc AV/SAV bits */
1411 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
1412 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
1414 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1416 tcg_temp_free_i64(t1
);
1417 tcg_temp_free_i64(t2
);
1418 tcg_temp_free_i64(t3
);
1422 gen_msubui64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1425 TCGv temp
= tcg_const_i32(con
);
1426 gen_msubu64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1427 tcg_temp_free(temp
);
1430 static inline void gen_addi_d(TCGv ret
, TCGv r1
, target_ulong r2
)
1432 TCGv temp
= tcg_const_i32(r2
);
1433 gen_add_d(ret
, r1
, temp
);
1434 tcg_temp_free(temp
);
1436 /* calculate the carry bit too */
1437 static inline void gen_add_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1439 TCGv t0
= tcg_temp_new_i32();
1440 TCGv result
= tcg_temp_new_i32();
1442 tcg_gen_movi_tl(t0
, 0);
1443 /* Addition and set C/V/SV bits */
1444 tcg_gen_add2_i32(result
, cpu_PSW_C
, r1
, t0
, r2
, t0
);
1446 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1447 tcg_gen_xor_tl(t0
, r1
, r2
);
1448 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
1450 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1451 /* Calc AV/SAV bits */
1452 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1453 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1455 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1456 /* write back result */
1457 tcg_gen_mov_tl(ret
, result
);
1459 tcg_temp_free(result
);
1463 static inline void gen_addi_CC(TCGv ret
, TCGv r1
, int32_t con
)
1465 TCGv temp
= tcg_const_i32(con
);
1466 gen_add_CC(ret
, r1
, temp
);
1467 tcg_temp_free(temp
);
1470 static inline void gen_addc_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1472 TCGv carry
= tcg_temp_new_i32();
1473 TCGv t0
= tcg_temp_new_i32();
1474 TCGv result
= tcg_temp_new_i32();
1476 tcg_gen_movi_tl(t0
, 0);
1477 tcg_gen_setcondi_tl(TCG_COND_NE
, carry
, cpu_PSW_C
, 0);
1478 /* Addition, carry and set C/V/SV bits */
1479 tcg_gen_add2_i32(result
, cpu_PSW_C
, r1
, t0
, carry
, t0
);
1480 tcg_gen_add2_i32(result
, cpu_PSW_C
, result
, cpu_PSW_C
, r2
, t0
);
1482 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1483 tcg_gen_xor_tl(t0
, r1
, r2
);
1484 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
1486 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1487 /* Calc AV/SAV bits */
1488 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1489 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1491 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1492 /* write back result */
1493 tcg_gen_mov_tl(ret
, result
);
1495 tcg_temp_free(result
);
1497 tcg_temp_free(carry
);
1500 static inline void gen_addci_CC(TCGv ret
, TCGv r1
, int32_t con
)
1502 TCGv temp
= tcg_const_i32(con
);
1503 gen_addc_CC(ret
, r1
, temp
);
1504 tcg_temp_free(temp
);
1507 static inline void gen_cond_add(TCGCond cond
, TCGv r1
, TCGv r2
, TCGv r3
,
1510 TCGv temp
= tcg_temp_new();
1511 TCGv temp2
= tcg_temp_new();
1512 TCGv result
= tcg_temp_new();
1513 TCGv mask
= tcg_temp_new();
1514 TCGv t0
= tcg_const_i32(0);
1516 /* create mask for sticky bits */
1517 tcg_gen_setcond_tl(cond
, mask
, r4
, t0
);
1518 tcg_gen_shli_tl(mask
, mask
, 31);
1520 tcg_gen_add_tl(result
, r1
, r2
);
1522 tcg_gen_xor_tl(temp
, result
, r1
);
1523 tcg_gen_xor_tl(temp2
, r1
, r2
);
1524 tcg_gen_andc_tl(temp
, temp
, temp2
);
1525 tcg_gen_movcond_tl(cond
, cpu_PSW_V
, r4
, t0
, temp
, cpu_PSW_V
);
1527 tcg_gen_and_tl(temp
, temp
, mask
);
1528 tcg_gen_or_tl(cpu_PSW_SV
, temp
, cpu_PSW_SV
);
1530 tcg_gen_add_tl(temp
, result
, result
);
1531 tcg_gen_xor_tl(temp
, temp
, result
);
1532 tcg_gen_movcond_tl(cond
, cpu_PSW_AV
, r4
, t0
, temp
, cpu_PSW_AV
);
1534 tcg_gen_and_tl(temp
, temp
, mask
);
1535 tcg_gen_or_tl(cpu_PSW_SAV
, temp
, cpu_PSW_SAV
);
1536 /* write back result */
1537 tcg_gen_movcond_tl(cond
, r3
, r4
, t0
, result
, r1
);
1540 tcg_temp_free(temp
);
1541 tcg_temp_free(temp2
);
1542 tcg_temp_free(result
);
1543 tcg_temp_free(mask
);
1546 static inline void gen_condi_add(TCGCond cond
, TCGv r1
, int32_t r2
,
1549 TCGv temp
= tcg_const_i32(r2
);
1550 gen_cond_add(cond
, r1
, temp
, r3
, r4
);
1551 tcg_temp_free(temp
);
1554 static inline void gen_sub_d(TCGv ret
, TCGv r1
, TCGv r2
)
1556 TCGv temp
= tcg_temp_new_i32();
1557 TCGv result
= tcg_temp_new_i32();
1559 tcg_gen_sub_tl(result
, r1
, r2
);
1561 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1562 tcg_gen_xor_tl(temp
, r1
, r2
);
1563 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1565 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1567 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1568 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1570 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1571 /* write back result */
1572 tcg_gen_mov_tl(ret
, result
);
1574 tcg_temp_free(temp
);
1575 tcg_temp_free(result
);
1578 static inline void gen_sub_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1580 TCGv result
= tcg_temp_new();
1581 TCGv temp
= tcg_temp_new();
1583 tcg_gen_sub_tl(result
, r1
, r2
);
1585 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_PSW_C
, r1
, r2
);
1587 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1588 tcg_gen_xor_tl(temp
, r1
, r2
);
1589 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1591 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1593 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1594 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1596 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1597 /* write back result */
1598 tcg_gen_mov_tl(ret
, result
);
1600 tcg_temp_free(result
);
1601 tcg_temp_free(temp
);
1604 static inline void gen_subc_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1606 TCGv temp
= tcg_temp_new();
1607 tcg_gen_not_tl(temp
, r2
);
1608 gen_addc_CC(ret
, r1
, temp
);
1609 tcg_temp_free(temp
);
1612 static inline void gen_cond_sub(TCGCond cond
, TCGv r1
, TCGv r2
, TCGv r3
,
1615 TCGv temp
= tcg_temp_new();
1616 TCGv temp2
= tcg_temp_new();
1617 TCGv result
= tcg_temp_new();
1618 TCGv mask
= tcg_temp_new();
1619 TCGv t0
= tcg_const_i32(0);
1621 /* create mask for sticky bits */
1622 tcg_gen_setcond_tl(cond
, mask
, r4
, t0
);
1623 tcg_gen_shli_tl(mask
, mask
, 31);
1625 tcg_gen_sub_tl(result
, r1
, r2
);
1627 tcg_gen_xor_tl(temp
, result
, r1
);
1628 tcg_gen_xor_tl(temp2
, r1
, r2
);
1629 tcg_gen_and_tl(temp
, temp
, temp2
);
1630 tcg_gen_movcond_tl(cond
, cpu_PSW_V
, r4
, t0
, temp
, cpu_PSW_V
);
1632 tcg_gen_and_tl(temp
, temp
, mask
);
1633 tcg_gen_or_tl(cpu_PSW_SV
, temp
, cpu_PSW_SV
);
1635 tcg_gen_add_tl(temp
, result
, result
);
1636 tcg_gen_xor_tl(temp
, temp
, result
);
1637 tcg_gen_movcond_tl(cond
, cpu_PSW_AV
, r4
, t0
, temp
, cpu_PSW_AV
);
1639 tcg_gen_and_tl(temp
, temp
, mask
);
1640 tcg_gen_or_tl(cpu_PSW_SAV
, temp
, cpu_PSW_SAV
);
1641 /* write back result */
1642 tcg_gen_movcond_tl(cond
, r3
, r4
, t0
, result
, r1
);
1645 tcg_temp_free(temp
);
1646 tcg_temp_free(temp2
);
1647 tcg_temp_free(result
);
1648 tcg_temp_free(mask
);
1651 static inline void gen_abs(TCGv ret
, TCGv r1
)
1653 TCGv temp
= tcg_temp_new();
1654 TCGv t0
= tcg_const_i32(0);
1656 tcg_gen_neg_tl(temp
, r1
);
1657 tcg_gen_movcond_tl(TCG_COND_GE
, ret
, r1
, t0
, r1
, temp
);
1658 /* overflow can only happen, if r1 = 0x80000000 */
1659 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, r1
, 0x80000000);
1660 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1662 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1664 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1665 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1667 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1669 tcg_temp_free(temp
);
1673 static inline void gen_absdif(TCGv ret
, TCGv r1
, TCGv r2
)
1675 TCGv temp
= tcg_temp_new_i32();
1676 TCGv result
= tcg_temp_new_i32();
1678 tcg_gen_sub_tl(result
, r1
, r2
);
1679 tcg_gen_sub_tl(temp
, r2
, r1
);
1680 tcg_gen_movcond_tl(TCG_COND_GT
, result
, r1
, r2
, result
, temp
);
1683 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1684 tcg_gen_xor_tl(temp
, result
, r2
);
1685 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_PSW_V
, r1
, r2
, cpu_PSW_V
, temp
);
1686 tcg_gen_xor_tl(temp
, r1
, r2
);
1687 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1689 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1691 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1692 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1694 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1695 /* write back result */
1696 tcg_gen_mov_tl(ret
, result
);
1698 tcg_temp_free(temp
);
1699 tcg_temp_free(result
);
1702 static inline void gen_absdifi(TCGv ret
, TCGv r1
, int32_t con
)
1704 TCGv temp
= tcg_const_i32(con
);
1705 gen_absdif(ret
, r1
, temp
);
1706 tcg_temp_free(temp
);
1709 static inline void gen_absdifsi(TCGv ret
, TCGv r1
, int32_t con
)
1711 TCGv temp
= tcg_const_i32(con
);
1712 gen_helper_absdif_ssov(ret
, cpu_env
, r1
, temp
);
1713 tcg_temp_free(temp
);
1716 static inline void gen_mul_i32s(TCGv ret
, TCGv r1
, TCGv r2
)
1718 TCGv high
= tcg_temp_new();
1719 TCGv low
= tcg_temp_new();
1721 tcg_gen_muls2_tl(low
, high
, r1
, r2
);
1722 tcg_gen_mov_tl(ret
, low
);
1724 tcg_gen_sari_tl(low
, low
, 31);
1725 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_PSW_V
, high
, low
);
1726 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1728 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1730 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1731 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1733 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1735 tcg_temp_free(high
);
1739 static inline void gen_muli_i32s(TCGv ret
, TCGv r1
, int32_t con
)
1741 TCGv temp
= tcg_const_i32(con
);
1742 gen_mul_i32s(ret
, r1
, temp
);
1743 tcg_temp_free(temp
);
1746 static inline void gen_mul_i64s(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2
)
1748 tcg_gen_muls2_tl(ret_low
, ret_high
, r1
, r2
);
1750 tcg_gen_movi_tl(cpu_PSW_V
, 0);
1752 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1754 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
1755 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
1757 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1760 static inline void gen_muli_i64s(TCGv ret_low
, TCGv ret_high
, TCGv r1
,
1763 TCGv temp
= tcg_const_i32(con
);
1764 gen_mul_i64s(ret_low
, ret_high
, r1
, temp
);
1765 tcg_temp_free(temp
);
1768 static inline void gen_mul_i64u(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2
)
1770 tcg_gen_mulu2_tl(ret_low
, ret_high
, r1
, r2
);
1772 tcg_gen_movi_tl(cpu_PSW_V
, 0);
1774 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1776 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
1777 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
1779 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1782 static inline void gen_muli_i64u(TCGv ret_low
, TCGv ret_high
, TCGv r1
,
1785 TCGv temp
= tcg_const_i32(con
);
1786 gen_mul_i64u(ret_low
, ret_high
, r1
, temp
);
1787 tcg_temp_free(temp
);
1790 static inline void gen_mulsi_i32(TCGv ret
, TCGv r1
, int32_t con
)
1792 TCGv temp
= tcg_const_i32(con
);
1793 gen_helper_mul_ssov(ret
, cpu_env
, r1
, temp
);
1794 tcg_temp_free(temp
);
1797 static inline void gen_mulsui_i32(TCGv ret
, TCGv r1
, int32_t con
)
1799 TCGv temp
= tcg_const_i32(con
);
1800 gen_helper_mul_suov(ret
, cpu_env
, r1
, temp
);
1801 tcg_temp_free(temp
);
1803 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
1804 static inline void gen_maddsi_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1806 TCGv temp
= tcg_const_i32(con
);
1807 gen_helper_madd32_ssov(ret
, cpu_env
, r1
, r2
, temp
);
1808 tcg_temp_free(temp
);
1811 static inline void gen_maddsui_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1813 TCGv temp
= tcg_const_i32(con
);
1814 gen_helper_madd32_suov(ret
, cpu_env
, r1
, r2
, temp
);
1815 tcg_temp_free(temp
);
1819 gen_mul_q(TCGv rl
, TCGv rh
, TCGv arg1
, TCGv arg2
, uint32_t n
, uint32_t up_shift
)
1821 TCGv temp
= tcg_temp_new();
1822 TCGv_i64 temp_64
= tcg_temp_new_i64();
1823 TCGv_i64 temp2_64
= tcg_temp_new_i64();
1826 if (up_shift
== 32) {
1827 tcg_gen_muls2_tl(rh
, rl
, arg1
, arg2
);
1828 } else if (up_shift
== 16) {
1829 tcg_gen_ext_i32_i64(temp_64
, arg1
);
1830 tcg_gen_ext_i32_i64(temp2_64
, arg2
);
1832 tcg_gen_mul_i64(temp_64
, temp_64
, temp2_64
);
1833 tcg_gen_shri_i64(temp_64
, temp_64
, up_shift
);
1834 tcg_gen_extr_i64_i32(rl
, rh
, temp_64
);
1836 tcg_gen_muls2_tl(rl
, rh
, arg1
, arg2
);
1839 tcg_gen_movi_tl(cpu_PSW_V
, 0);
1840 } else { /* n is exspected to be 1 */
1841 tcg_gen_ext_i32_i64(temp_64
, arg1
);
1842 tcg_gen_ext_i32_i64(temp2_64
, arg2
);
1844 tcg_gen_mul_i64(temp_64
, temp_64
, temp2_64
);
1846 if (up_shift
== 0) {
1847 tcg_gen_shli_i64(temp_64
, temp_64
, 1);
1849 tcg_gen_shri_i64(temp_64
, temp_64
, up_shift
- 1);
1851 tcg_gen_extr_i64_i32(rl
, rh
, temp_64
);
1852 /* overflow only occours if r1 = r2 = 0x8000 */
1853 if (up_shift
== 0) {/* result is 64 bit */
1854 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, rh
,
1856 } else { /* result is 32 bit */
1857 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, rl
,
1860 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1861 /* calc sv overflow bit */
1862 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1864 /* calc av overflow bit */
1865 if (up_shift
== 0) {
1866 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
1867 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
1869 tcg_gen_add_tl(cpu_PSW_AV
, rl
, rl
);
1870 tcg_gen_xor_tl(cpu_PSW_AV
, rl
, cpu_PSW_AV
);
1872 /* calc sav overflow bit */
1873 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1874 tcg_temp_free(temp
);
1875 tcg_temp_free_i64(temp_64
);
1876 tcg_temp_free_i64(temp2_64
);
1880 gen_mul_q_16(TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t n
)
1882 TCGv temp
= tcg_temp_new();
1884 tcg_gen_mul_tl(ret
, arg1
, arg2
);
1885 } else { /* n is exspected to be 1 */
1886 tcg_gen_mul_tl(ret
, arg1
, arg2
);
1887 tcg_gen_shli_tl(ret
, ret
, 1);
1888 /* catch special case r1 = r2 = 0x8000 */
1889 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, ret
, 0x80000000);
1890 tcg_gen_sub_tl(ret
, ret
, temp
);
1893 tcg_gen_movi_tl(cpu_PSW_V
, 0);
1894 /* calc av overflow bit */
1895 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1896 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1897 /* calc sav overflow bit */
1898 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1900 tcg_temp_free(temp
);
1903 static void gen_mulr_q(TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t n
)
1905 TCGv temp
= tcg_temp_new();
1907 tcg_gen_mul_tl(ret
, arg1
, arg2
);
1908 tcg_gen_addi_tl(ret
, ret
, 0x8000);
1910 tcg_gen_mul_tl(ret
, arg1
, arg2
);
1911 tcg_gen_shli_tl(ret
, ret
, 1);
1912 tcg_gen_addi_tl(ret
, ret
, 0x8000);
1913 /* catch special case r1 = r2 = 0x8000 */
1914 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, ret
, 0x80008000);
1915 tcg_gen_muli_tl(temp
, temp
, 0x8001);
1916 tcg_gen_sub_tl(ret
, ret
, temp
);
1919 tcg_gen_movi_tl(cpu_PSW_V
, 0);
1920 /* calc av overflow bit */
1921 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1922 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1923 /* calc sav overflow bit */
1924 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1925 /* cut halfword off */
1926 tcg_gen_andi_tl(ret
, ret
, 0xffff0000);
1928 tcg_temp_free(temp
);
1932 gen_madds_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1935 TCGv_i64 temp64
= tcg_temp_new_i64();
1936 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
1937 gen_helper_madd64_ssov(temp64
, cpu_env
, r1
, temp64
, r3
);
1938 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
1939 tcg_temp_free_i64(temp64
);
1943 gen_maddsi_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1946 TCGv temp
= tcg_const_i32(con
);
1947 gen_madds_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1948 tcg_temp_free(temp
);
1952 gen_maddsu_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1955 TCGv_i64 temp64
= tcg_temp_new_i64();
1956 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
1957 gen_helper_madd64_suov(temp64
, cpu_env
, r1
, temp64
, r3
);
1958 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
1959 tcg_temp_free_i64(temp64
);
1963 gen_maddsui_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1966 TCGv temp
= tcg_const_i32(con
);
1967 gen_maddsu_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1968 tcg_temp_free(temp
);
1971 static inline void gen_msubsi_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1973 TCGv temp
= tcg_const_i32(con
);
1974 gen_helper_msub32_ssov(ret
, cpu_env
, r1
, r2
, temp
);
1975 tcg_temp_free(temp
);
1978 static inline void gen_msubsui_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1980 TCGv temp
= tcg_const_i32(con
);
1981 gen_helper_msub32_suov(ret
, cpu_env
, r1
, r2
, temp
);
1982 tcg_temp_free(temp
);
1986 gen_msubs_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1989 TCGv_i64 temp64
= tcg_temp_new_i64();
1990 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
1991 gen_helper_msub64_ssov(temp64
, cpu_env
, r1
, temp64
, r3
);
1992 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
1993 tcg_temp_free_i64(temp64
);
1997 gen_msubsi_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2000 TCGv temp
= tcg_const_i32(con
);
2001 gen_msubs_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2002 tcg_temp_free(temp
);
2006 gen_msubsu_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2009 TCGv_i64 temp64
= tcg_temp_new_i64();
2010 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2011 gen_helper_msub64_suov(temp64
, cpu_env
, r1
, temp64
, r3
);
2012 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2013 tcg_temp_free_i64(temp64
);
2017 gen_msubsui_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2020 TCGv temp
= tcg_const_i32(con
);
2021 gen_msubsu_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2022 tcg_temp_free(temp
);
2025 static void gen_saturate(TCGv ret
, TCGv arg
, int32_t up
, int32_t low
)
2027 TCGv sat_neg
= tcg_const_i32(low
);
2028 TCGv temp
= tcg_const_i32(up
);
2030 /* sat_neg = (arg < low ) ? low : arg; */
2031 tcg_gen_movcond_tl(TCG_COND_LT
, sat_neg
, arg
, sat_neg
, sat_neg
, arg
);
2033 /* ret = (sat_neg > up ) ? up : sat_neg; */
2034 tcg_gen_movcond_tl(TCG_COND_GT
, ret
, sat_neg
, temp
, temp
, sat_neg
);
2036 tcg_temp_free(sat_neg
);
2037 tcg_temp_free(temp
);
2040 static void gen_saturate_u(TCGv ret
, TCGv arg
, int32_t up
)
2042 TCGv temp
= tcg_const_i32(up
);
2043 /* sat_neg = (arg > up ) ? up : arg; */
2044 tcg_gen_movcond_tl(TCG_COND_GTU
, ret
, arg
, temp
, temp
, arg
);
2045 tcg_temp_free(temp
);
2048 static void gen_shi(TCGv ret
, TCGv r1
, int32_t shift_count
)
2050 if (shift_count
== -32) {
2051 tcg_gen_movi_tl(ret
, 0);
2052 } else if (shift_count
>= 0) {
2053 tcg_gen_shli_tl(ret
, r1
, shift_count
);
2055 tcg_gen_shri_tl(ret
, r1
, -shift_count
);
2059 static void gen_sh_hi(TCGv ret
, TCGv r1
, int32_t shiftcount
)
2061 TCGv temp_low
, temp_high
;
2063 if (shiftcount
== -16) {
2064 tcg_gen_movi_tl(ret
, 0);
2066 temp_high
= tcg_temp_new();
2067 temp_low
= tcg_temp_new();
2069 tcg_gen_andi_tl(temp_low
, r1
, 0xffff);
2070 tcg_gen_andi_tl(temp_high
, r1
, 0xffff0000);
2071 gen_shi(temp_low
, temp_low
, shiftcount
);
2072 gen_shi(ret
, temp_high
, shiftcount
);
2073 tcg_gen_deposit_tl(ret
, ret
, temp_low
, 0, 16);
2075 tcg_temp_free(temp_low
);
2076 tcg_temp_free(temp_high
);
2080 static void gen_shaci(TCGv ret
, TCGv r1
, int32_t shift_count
)
2082 uint32_t msk
, msk_start
;
2083 TCGv temp
= tcg_temp_new();
2084 TCGv temp2
= tcg_temp_new();
2085 TCGv t_0
= tcg_const_i32(0);
2087 if (shift_count
== 0) {
2088 /* Clear PSW.C and PSW.V */
2089 tcg_gen_movi_tl(cpu_PSW_C
, 0);
2090 tcg_gen_mov_tl(cpu_PSW_V
, cpu_PSW_C
);
2091 tcg_gen_mov_tl(ret
, r1
);
2092 } else if (shift_count
== -32) {
2094 tcg_gen_mov_tl(cpu_PSW_C
, r1
);
2095 /* fill ret completly with sign bit */
2096 tcg_gen_sari_tl(ret
, r1
, 31);
2098 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2099 } else if (shift_count
> 0) {
2100 TCGv t_max
= tcg_const_i32(0x7FFFFFFF >> shift_count
);
2101 TCGv t_min
= tcg_const_i32(((int32_t) -0x80000000) >> shift_count
);
2104 msk_start
= 32 - shift_count
;
2105 msk
= ((1 << shift_count
) - 1) << msk_start
;
2106 tcg_gen_andi_tl(cpu_PSW_C
, r1
, msk
);
2107 /* calc v/sv bits */
2108 tcg_gen_setcond_tl(TCG_COND_GT
, temp
, r1
, t_max
);
2109 tcg_gen_setcond_tl(TCG_COND_LT
, temp2
, r1
, t_min
);
2110 tcg_gen_or_tl(cpu_PSW_V
, temp
, temp2
);
2111 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2113 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_V
, cpu_PSW_SV
);
2115 tcg_gen_shli_tl(ret
, r1
, shift_count
);
2117 tcg_temp_free(t_max
);
2118 tcg_temp_free(t_min
);
2121 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2123 msk
= (1 << -shift_count
) - 1;
2124 tcg_gen_andi_tl(cpu_PSW_C
, r1
, msk
);
2126 tcg_gen_sari_tl(ret
, r1
, -shift_count
);
2128 /* calc av overflow bit */
2129 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2130 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2131 /* calc sav overflow bit */
2132 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2134 tcg_temp_free(temp
);
2135 tcg_temp_free(temp2
);
2139 static void gen_shas(TCGv ret
, TCGv r1
, TCGv r2
)
2141 gen_helper_sha_ssov(ret
, cpu_env
, r1
, r2
);
2144 static void gen_shasi(TCGv ret
, TCGv r1
, int32_t con
)
2146 TCGv temp
= tcg_const_i32(con
);
2147 gen_shas(ret
, r1
, temp
);
2148 tcg_temp_free(temp
);
2151 static void gen_sha_hi(TCGv ret
, TCGv r1
, int32_t shift_count
)
2155 if (shift_count
== 0) {
2156 tcg_gen_mov_tl(ret
, r1
);
2157 } else if (shift_count
> 0) {
2158 low
= tcg_temp_new();
2159 high
= tcg_temp_new();
2161 tcg_gen_andi_tl(high
, r1
, 0xffff0000);
2162 tcg_gen_shli_tl(low
, r1
, shift_count
);
2163 tcg_gen_shli_tl(ret
, high
, shift_count
);
2164 tcg_gen_deposit_tl(ret
, ret
, low
, 0, 16);
2167 tcg_temp_free(high
);
2169 low
= tcg_temp_new();
2170 high
= tcg_temp_new();
2172 tcg_gen_ext16s_tl(low
, r1
);
2173 tcg_gen_sari_tl(low
, low
, -shift_count
);
2174 tcg_gen_sari_tl(ret
, r1
, -shift_count
);
2175 tcg_gen_deposit_tl(ret
, ret
, low
, 0, 16);
2178 tcg_temp_free(high
);
2183 /* ret = {ret[30:0], (r1 cond r2)}; */
2184 static void gen_sh_cond(int cond
, TCGv ret
, TCGv r1
, TCGv r2
)
2186 TCGv temp
= tcg_temp_new();
2187 TCGv temp2
= tcg_temp_new();
2189 tcg_gen_shli_tl(temp
, ret
, 1);
2190 tcg_gen_setcond_tl(cond
, temp2
, r1
, r2
);
2191 tcg_gen_or_tl(ret
, temp
, temp2
);
2193 tcg_temp_free(temp
);
2194 tcg_temp_free(temp2
);
2197 static void gen_sh_condi(int cond
, TCGv ret
, TCGv r1
, int32_t con
)
2199 TCGv temp
= tcg_const_i32(con
);
2200 gen_sh_cond(cond
, ret
, r1
, temp
);
2201 tcg_temp_free(temp
);
2204 static inline void gen_adds(TCGv ret
, TCGv r1
, TCGv r2
)
2206 gen_helper_add_ssov(ret
, cpu_env
, r1
, r2
);
2209 static inline void gen_addsi(TCGv ret
, TCGv r1
, int32_t con
)
2211 TCGv temp
= tcg_const_i32(con
);
2212 gen_helper_add_ssov(ret
, cpu_env
, r1
, temp
);
2213 tcg_temp_free(temp
);
2216 static inline void gen_addsui(TCGv ret
, TCGv r1
, int32_t con
)
2218 TCGv temp
= tcg_const_i32(con
);
2219 gen_helper_add_suov(ret
, cpu_env
, r1
, temp
);
2220 tcg_temp_free(temp
);
2223 static inline void gen_subs(TCGv ret
, TCGv r1
, TCGv r2
)
2225 gen_helper_sub_ssov(ret
, cpu_env
, r1
, r2
);
2228 static inline void gen_subsu(TCGv ret
, TCGv r1
, TCGv r2
)
2230 gen_helper_sub_suov(ret
, cpu_env
, r1
, r2
);
2233 static inline void gen_bit_2op(TCGv ret
, TCGv r1
, TCGv r2
,
2235 void(*op1
)(TCGv
, TCGv
, TCGv
),
2236 void(*op2
)(TCGv
, TCGv
, TCGv
))
2240 temp1
= tcg_temp_new();
2241 temp2
= tcg_temp_new();
2243 tcg_gen_shri_tl(temp2
, r2
, pos2
);
2244 tcg_gen_shri_tl(temp1
, r1
, pos1
);
2246 (*op1
)(temp1
, temp1
, temp2
);
2247 (*op2
)(temp1
, ret
, temp1
);
2249 tcg_gen_deposit_tl(ret
, ret
, temp1
, 0, 1);
2251 tcg_temp_free(temp1
);
2252 tcg_temp_free(temp2
);
2255 /* ret = r1[pos1] op1 r2[pos2]; */
2256 static inline void gen_bit_1op(TCGv ret
, TCGv r1
, TCGv r2
,
2258 void(*op1
)(TCGv
, TCGv
, TCGv
))
2262 temp1
= tcg_temp_new();
2263 temp2
= tcg_temp_new();
2265 tcg_gen_shri_tl(temp2
, r2
, pos2
);
2266 tcg_gen_shri_tl(temp1
, r1
, pos1
);
2268 (*op1
)(ret
, temp1
, temp2
);
2270 tcg_gen_andi_tl(ret
, ret
, 0x1);
2272 tcg_temp_free(temp1
);
2273 tcg_temp_free(temp2
);
2276 static inline void gen_accumulating_cond(int cond
, TCGv ret
, TCGv r1
, TCGv r2
,
2277 void(*op
)(TCGv
, TCGv
, TCGv
))
2279 TCGv temp
= tcg_temp_new();
2280 TCGv temp2
= tcg_temp_new();
2281 /* temp = (arg1 cond arg2 )*/
2282 tcg_gen_setcond_tl(cond
, temp
, r1
, r2
);
2284 tcg_gen_andi_tl(temp2
, ret
, 0x1);
2285 /* temp = temp insn temp2 */
2286 (*op
)(temp
, temp
, temp2
);
2287 /* ret = {ret[31:1], temp} */
2288 tcg_gen_deposit_tl(ret
, ret
, temp
, 0, 1);
2290 tcg_temp_free(temp
);
2291 tcg_temp_free(temp2
);
2295 gen_accumulating_condi(int cond
, TCGv ret
, TCGv r1
, int32_t con
,
2296 void(*op
)(TCGv
, TCGv
, TCGv
))
2298 TCGv temp
= tcg_const_i32(con
);
2299 gen_accumulating_cond(cond
, ret
, r1
, temp
, op
);
2300 tcg_temp_free(temp
);
2303 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
2304 static inline void gen_cond_w(TCGCond cond
, TCGv ret
, TCGv r1
, TCGv r2
)
2306 tcg_gen_setcond_tl(cond
, ret
, r1
, r2
);
2307 tcg_gen_neg_tl(ret
, ret
);
2310 static inline void gen_eqany_bi(TCGv ret
, TCGv r1
, int32_t con
)
2312 TCGv b0
= tcg_temp_new();
2313 TCGv b1
= tcg_temp_new();
2314 TCGv b2
= tcg_temp_new();
2315 TCGv b3
= tcg_temp_new();
2318 tcg_gen_andi_tl(b0
, r1
, 0xff);
2319 tcg_gen_setcondi_tl(TCG_COND_EQ
, b0
, b0
, con
& 0xff);
2322 tcg_gen_andi_tl(b1
, r1
, 0xff00);
2323 tcg_gen_setcondi_tl(TCG_COND_EQ
, b1
, b1
, con
& 0xff00);
2326 tcg_gen_andi_tl(b2
, r1
, 0xff0000);
2327 tcg_gen_setcondi_tl(TCG_COND_EQ
, b2
, b2
, con
& 0xff0000);
2330 tcg_gen_andi_tl(b3
, r1
, 0xff000000);
2331 tcg_gen_setcondi_tl(TCG_COND_EQ
, b3
, b3
, con
& 0xff000000);
2334 tcg_gen_or_tl(ret
, b0
, b1
);
2335 tcg_gen_or_tl(ret
, ret
, b2
);
2336 tcg_gen_or_tl(ret
, ret
, b3
);
2344 static inline void gen_eqany_hi(TCGv ret
, TCGv r1
, int32_t con
)
2346 TCGv h0
= tcg_temp_new();
2347 TCGv h1
= tcg_temp_new();
2350 tcg_gen_andi_tl(h0
, r1
, 0xffff);
2351 tcg_gen_setcondi_tl(TCG_COND_EQ
, h0
, h0
, con
& 0xffff);
2354 tcg_gen_andi_tl(h1
, r1
, 0xffff0000);
2355 tcg_gen_setcondi_tl(TCG_COND_EQ
, h1
, h1
, con
& 0xffff0000);
2358 tcg_gen_or_tl(ret
, h0
, h1
);
2363 /* mask = ((1 << width) -1) << pos;
2364 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2365 static inline void gen_insert(TCGv ret
, TCGv r1
, TCGv r2
, TCGv width
, TCGv pos
)
2367 TCGv mask
= tcg_temp_new();
2368 TCGv temp
= tcg_temp_new();
2369 TCGv temp2
= tcg_temp_new();
2371 tcg_gen_movi_tl(mask
, 1);
2372 tcg_gen_shl_tl(mask
, mask
, width
);
2373 tcg_gen_subi_tl(mask
, mask
, 1);
2374 tcg_gen_shl_tl(mask
, mask
, pos
);
2376 tcg_gen_shl_tl(temp
, r2
, pos
);
2377 tcg_gen_and_tl(temp
, temp
, mask
);
2378 tcg_gen_andc_tl(temp2
, r1
, mask
);
2379 tcg_gen_or_tl(ret
, temp
, temp2
);
2381 tcg_temp_free(mask
);
2382 tcg_temp_free(temp
);
2383 tcg_temp_free(temp2
);
2386 static inline void gen_bsplit(TCGv rl
, TCGv rh
, TCGv r1
)
2388 TCGv_i64 temp
= tcg_temp_new_i64();
2390 gen_helper_bsplit(temp
, r1
);
2391 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
2393 tcg_temp_free_i64(temp
);
2396 static inline void gen_unpack(TCGv rl
, TCGv rh
, TCGv r1
)
2398 TCGv_i64 temp
= tcg_temp_new_i64();
2400 gen_helper_unpack(temp
, r1
);
2401 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
2403 tcg_temp_free_i64(temp
);
2407 gen_dvinit_b(CPUTriCoreState
*env
, TCGv rl
, TCGv rh
, TCGv r1
, TCGv r2
)
2409 TCGv_i64 ret
= tcg_temp_new_i64();
2411 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
2412 gen_helper_dvinit_b_13(ret
, cpu_env
, r1
, r2
);
2414 gen_helper_dvinit_b_131(ret
, cpu_env
, r1
, r2
);
2416 tcg_gen_extr_i64_i32(rl
, rh
, ret
);
2418 tcg_temp_free_i64(ret
);
2422 gen_dvinit_h(CPUTriCoreState
*env
, TCGv rl
, TCGv rh
, TCGv r1
, TCGv r2
)
2424 TCGv_i64 ret
= tcg_temp_new_i64();
2426 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
2427 gen_helper_dvinit_h_13(ret
, cpu_env
, r1
, r2
);
2429 gen_helper_dvinit_h_131(ret
, cpu_env
, r1
, r2
);
2431 tcg_gen_extr_i64_i32(rl
, rh
, ret
);
2433 tcg_temp_free_i64(ret
);
2436 static void gen_calc_usb_mul_h(TCGv arg_low
, TCGv arg_high
)
2438 TCGv temp
= tcg_temp_new();
2440 tcg_gen_add_tl(temp
, arg_low
, arg_low
);
2441 tcg_gen_xor_tl(temp
, temp
, arg_low
);
2442 tcg_gen_add_tl(cpu_PSW_AV
, arg_high
, arg_high
);
2443 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_PSW_AV
, arg_high
);
2444 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
2446 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2447 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2448 tcg_temp_free(temp
);
2451 static void gen_calc_usb_mulr_h(TCGv arg
)
2453 TCGv temp
= tcg_temp_new();
2455 tcg_gen_add_tl(temp
, arg
, arg
);
2456 tcg_gen_xor_tl(temp
, temp
, arg
);
2457 tcg_gen_shli_tl(cpu_PSW_AV
, temp
, 16);
2458 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
2460 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2462 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2463 tcg_temp_free(temp
);
2466 /* helpers for generating program flow micro-ops */
2468 static inline void gen_save_pc(target_ulong pc
)
2470 tcg_gen_movi_tl(cpu_PC
, pc
);
2473 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2475 TranslationBlock
*tb
;
2477 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
2478 likely(!ctx
->singlestep_enabled
)) {
2481 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
2484 if (ctx
->singlestep_enabled
) {
2485 /* raise exception debug */
2491 static inline void gen_branch_cond(DisasContext
*ctx
, TCGCond cond
, TCGv r1
,
2492 TCGv r2
, int16_t address
)
2495 jumpLabel
= gen_new_label();
2496 tcg_gen_brcond_tl(cond
, r1
, r2
, jumpLabel
);
2498 gen_goto_tb(ctx
, 1, ctx
->next_pc
);
2500 gen_set_label(jumpLabel
);
2501 gen_goto_tb(ctx
, 0, ctx
->pc
+ address
* 2);
2504 static inline void gen_branch_condi(DisasContext
*ctx
, TCGCond cond
, TCGv r1
,
2505 int r2
, int16_t address
)
2507 TCGv temp
= tcg_const_i32(r2
);
2508 gen_branch_cond(ctx
, cond
, r1
, temp
, address
);
2509 tcg_temp_free(temp
);
2512 static void gen_loop(DisasContext
*ctx
, int r1
, int32_t offset
)
2515 l1
= gen_new_label();
2517 tcg_gen_subi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], 1);
2518 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr_a
[r1
], -1, l1
);
2519 gen_goto_tb(ctx
, 1, ctx
->pc
+ offset
);
2521 gen_goto_tb(ctx
, 0, ctx
->next_pc
);
2524 static void gen_compute_branch(DisasContext
*ctx
, uint32_t opc
, int r1
,
2525 int r2
, int32_t constant
, int32_t offset
)
2531 /* SB-format jumps */
2534 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
2536 case OPC1_32_B_CALL
:
2537 case OPC1_16_SB_CALL
:
2538 gen_helper_1arg(call
, ctx
->next_pc
);
2539 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
2542 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], 0, offset
);
2544 case OPC1_16_SB_JNZ
:
2545 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15], 0, offset
);
2547 /* SBC-format jumps */
2548 case OPC1_16_SBC_JEQ
:
2549 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], constant
, offset
);
2551 case OPC1_16_SBC_JNE
:
2552 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15], constant
, offset
);
2554 /* SBRN-format jumps */
2555 case OPC1_16_SBRN_JZ_T
:
2556 temp
= tcg_temp_new();
2557 tcg_gen_andi_tl(temp
, cpu_gpr_d
[15], 0x1u
<< constant
);
2558 gen_branch_condi(ctx
, TCG_COND_EQ
, temp
, 0, offset
);
2559 tcg_temp_free(temp
);
2561 case OPC1_16_SBRN_JNZ_T
:
2562 temp
= tcg_temp_new();
2563 tcg_gen_andi_tl(temp
, cpu_gpr_d
[15], 0x1u
<< constant
);
2564 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, 0, offset
);
2565 tcg_temp_free(temp
);
2567 /* SBR-format jumps */
2568 case OPC1_16_SBR_JEQ
:
2569 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15],
2572 case OPC1_16_SBR_JNE
:
2573 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15],
2576 case OPC1_16_SBR_JNZ
:
2577 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], 0, offset
);
2579 case OPC1_16_SBR_JNZ_A
:
2580 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], 0, offset
);
2582 case OPC1_16_SBR_JGEZ
:
2583 gen_branch_condi(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], 0, offset
);
2585 case OPC1_16_SBR_JGTZ
:
2586 gen_branch_condi(ctx
, TCG_COND_GT
, cpu_gpr_d
[r1
], 0, offset
);
2588 case OPC1_16_SBR_JLEZ
:
2589 gen_branch_condi(ctx
, TCG_COND_LE
, cpu_gpr_d
[r1
], 0, offset
);
2591 case OPC1_16_SBR_JLTZ
:
2592 gen_branch_condi(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], 0, offset
);
2594 case OPC1_16_SBR_JZ
:
2595 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], 0, offset
);
2597 case OPC1_16_SBR_JZ_A
:
2598 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], 0, offset
);
2600 case OPC1_16_SBR_LOOP
:
2601 gen_loop(ctx
, r1
, offset
* 2 - 32);
2603 /* SR-format jumps */
2605 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], 0xfffffffe);
2608 case OPC2_16_SR_RET
:
2609 gen_helper_ret(cpu_env
);
2613 case OPC1_32_B_CALLA
:
2614 gen_helper_1arg(call
, ctx
->next_pc
);
2615 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
2618 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
2621 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
2624 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
2625 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
2628 case OPCM_32_BRC_EQ_NEQ
:
2629 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JEQ
) {
2630 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], constant
, offset
);
2632 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], constant
, offset
);
2635 case OPCM_32_BRC_GE
:
2636 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OP2_32_BRC_JGE
) {
2637 gen_branch_condi(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], constant
, offset
);
2639 constant
= MASK_OP_BRC_CONST4(ctx
->opcode
);
2640 gen_branch_condi(ctx
, TCG_COND_GEU
, cpu_gpr_d
[r1
], constant
,
2644 case OPCM_32_BRC_JLT
:
2645 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JLT
) {
2646 gen_branch_condi(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], constant
, offset
);
2648 constant
= MASK_OP_BRC_CONST4(ctx
->opcode
);
2649 gen_branch_condi(ctx
, TCG_COND_LTU
, cpu_gpr_d
[r1
], constant
,
2653 case OPCM_32_BRC_JNE
:
2654 temp
= tcg_temp_new();
2655 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JNED
) {
2656 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
2657 /* subi is unconditional */
2658 tcg_gen_subi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
2659 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, constant
, offset
);
2661 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
2662 /* addi is unconditional */
2663 tcg_gen_addi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
2664 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, constant
, offset
);
2666 tcg_temp_free(temp
);
2669 case OPCM_32_BRN_JTT
:
2670 n
= MASK_OP_BRN_N(ctx
->opcode
);
2672 temp
= tcg_temp_new();
2673 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r1
], (1 << n
));
2675 if (MASK_OP_BRN_OP2(ctx
->opcode
) == OPC2_32_BRN_JNZ_T
) {
2676 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, 0, offset
);
2678 gen_branch_condi(ctx
, TCG_COND_EQ
, temp
, 0, offset
);
2680 tcg_temp_free(temp
);
2683 case OPCM_32_BRR_EQ_NEQ
:
2684 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JEQ
) {
2685 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
2688 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
2692 case OPCM_32_BRR_ADDR_EQ_NEQ
:
2693 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JEQ_A
) {
2694 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
2697 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
2701 case OPCM_32_BRR_GE
:
2702 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JGE
) {
2703 gen_branch_cond(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
2706 gen_branch_cond(ctx
, TCG_COND_GEU
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
2710 case OPCM_32_BRR_JLT
:
2711 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JLT
) {
2712 gen_branch_cond(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
2715 gen_branch_cond(ctx
, TCG_COND_LTU
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
2719 case OPCM_32_BRR_LOOP
:
2720 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_LOOP
) {
2721 gen_loop(ctx
, r1
, offset
* 2);
2723 /* OPC2_32_BRR_LOOPU */
2724 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
2727 case OPCM_32_BRR_JNE
:
2728 temp
= tcg_temp_new();
2729 temp2
= tcg_temp_new();
2730 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRR_JNED
) {
2731 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
2732 /* also save r2, in case of r1 == r2, so r2 is not decremented */
2733 tcg_gen_mov_tl(temp2
, cpu_gpr_d
[r2
]);
2734 /* subi is unconditional */
2735 tcg_gen_subi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
2736 gen_branch_cond(ctx
, TCG_COND_NE
, temp
, temp2
, offset
);
2738 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
2739 /* also save r2, in case of r1 == r2, so r2 is not decremented */
2740 tcg_gen_mov_tl(temp2
, cpu_gpr_d
[r2
]);
2741 /* addi is unconditional */
2742 tcg_gen_addi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
2743 gen_branch_cond(ctx
, TCG_COND_NE
, temp
, temp2
, offset
);
2745 tcg_temp_free(temp
);
2746 tcg_temp_free(temp2
);
2748 case OPCM_32_BRR_JNZ
:
2749 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JNZ_A
) {
2750 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], 0, offset
);
2752 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], 0, offset
);
2756 printf("Branch Error at %x\n", ctx
->pc
);
2758 ctx
->bstate
= BS_BRANCH
;
2763 * Functions for decoding instructions
2766 static void decode_src_opc(DisasContext
*ctx
, int op1
)
2772 r1
= MASK_OP_SRC_S1D(ctx
->opcode
);
2773 const4
= MASK_OP_SRC_CONST4_SEXT(ctx
->opcode
);
2776 case OPC1_16_SRC_ADD
:
2777 gen_addi_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
2779 case OPC1_16_SRC_ADD_A15
:
2780 gen_addi_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], const4
);
2782 case OPC1_16_SRC_ADD_15A
:
2783 gen_addi_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], const4
);
2785 case OPC1_16_SRC_ADD_A
:
2786 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], const4
);
2788 case OPC1_16_SRC_CADD
:
2789 gen_condi_add(TCG_COND_NE
, cpu_gpr_d
[r1
], const4
, cpu_gpr_d
[r1
],
2792 case OPC1_16_SRC_CADDN
:
2793 gen_condi_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], const4
, cpu_gpr_d
[r1
],
2796 case OPC1_16_SRC_CMOV
:
2797 temp
= tcg_const_tl(0);
2798 temp2
= tcg_const_tl(const4
);
2799 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
2800 temp2
, cpu_gpr_d
[r1
]);
2801 tcg_temp_free(temp
);
2802 tcg_temp_free(temp2
);
2804 case OPC1_16_SRC_CMOVN
:
2805 temp
= tcg_const_tl(0);
2806 temp2
= tcg_const_tl(const4
);
2807 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
2808 temp2
, cpu_gpr_d
[r1
]);
2809 tcg_temp_free(temp
);
2810 tcg_temp_free(temp2
);
2812 case OPC1_16_SRC_EQ
:
2813 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
2816 case OPC1_16_SRC_LT
:
2817 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
2820 case OPC1_16_SRC_MOV
:
2821 tcg_gen_movi_tl(cpu_gpr_d
[r1
], const4
);
2823 case OPC1_16_SRC_MOV_A
:
2824 const4
= MASK_OP_SRC_CONST4(ctx
->opcode
);
2825 tcg_gen_movi_tl(cpu_gpr_a
[r1
], const4
);
2827 case OPC1_16_SRC_SH
:
2828 gen_shi(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
2830 case OPC1_16_SRC_SHA
:
2831 gen_shaci(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
2836 static void decode_srr_opc(DisasContext
*ctx
, int op1
)
2841 r1
= MASK_OP_SRR_S1D(ctx
->opcode
);
2842 r2
= MASK_OP_SRR_S2(ctx
->opcode
);
2845 case OPC1_16_SRR_ADD
:
2846 gen_add_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2848 case OPC1_16_SRR_ADD_A15
:
2849 gen_add_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], cpu_gpr_d
[r2
]);
2851 case OPC1_16_SRR_ADD_15A
:
2852 gen_add_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2854 case OPC1_16_SRR_ADD_A
:
2855 tcg_gen_add_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
2857 case OPC1_16_SRR_ADDS
:
2858 gen_adds(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2860 case OPC1_16_SRR_AND
:
2861 tcg_gen_and_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2863 case OPC1_16_SRR_CMOV
:
2864 temp
= tcg_const_tl(0);
2865 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
2866 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
]);
2867 tcg_temp_free(temp
);
2869 case OPC1_16_SRR_CMOVN
:
2870 temp
= tcg_const_tl(0);
2871 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
2872 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
]);
2873 tcg_temp_free(temp
);
2875 case OPC1_16_SRR_EQ
:
2876 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
2879 case OPC1_16_SRR_LT
:
2880 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
2883 case OPC1_16_SRR_MOV
:
2884 tcg_gen_mov_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2886 case OPC1_16_SRR_MOV_A
:
2887 tcg_gen_mov_tl(cpu_gpr_a
[r1
], cpu_gpr_d
[r2
]);
2889 case OPC1_16_SRR_MOV_AA
:
2890 tcg_gen_mov_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
2892 case OPC1_16_SRR_MOV_D
:
2893 tcg_gen_mov_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
]);
2895 case OPC1_16_SRR_MUL
:
2896 gen_mul_i32s(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2898 case OPC1_16_SRR_OR
:
2899 tcg_gen_or_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2901 case OPC1_16_SRR_SUB
:
2902 gen_sub_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2904 case OPC1_16_SRR_SUB_A15B
:
2905 gen_sub_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], cpu_gpr_d
[r2
]);
2907 case OPC1_16_SRR_SUB_15AB
:
2908 gen_sub_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2910 case OPC1_16_SRR_SUBS
:
2911 gen_subs(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2913 case OPC1_16_SRR_XOR
:
2914 tcg_gen_xor_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
2919 static void decode_ssr_opc(DisasContext
*ctx
, int op1
)
2923 r1
= MASK_OP_SSR_S1(ctx
->opcode
);
2924 r2
= MASK_OP_SSR_S2(ctx
->opcode
);
2927 case OPC1_16_SSR_ST_A
:
2928 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
2930 case OPC1_16_SSR_ST_A_POSTINC
:
2931 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
2932 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
2934 case OPC1_16_SSR_ST_B
:
2935 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
2937 case OPC1_16_SSR_ST_B_POSTINC
:
2938 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
2939 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 1);
2941 case OPC1_16_SSR_ST_H
:
2942 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUW
);
2944 case OPC1_16_SSR_ST_H_POSTINC
:
2945 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUW
);
2946 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 2);
2948 case OPC1_16_SSR_ST_W
:
2949 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
2951 case OPC1_16_SSR_ST_W_POSTINC
:
2952 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
2953 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
2958 static void decode_sc_opc(DisasContext
*ctx
, int op1
)
2962 const16
= MASK_OP_SC_CONST8(ctx
->opcode
);
2965 case OPC1_16_SC_AND
:
2966 tcg_gen_andi_tl(cpu_gpr_d
[15], cpu_gpr_d
[15], const16
);
2968 case OPC1_16_SC_BISR
:
2969 gen_helper_1arg(bisr
, const16
& 0xff);
2971 case OPC1_16_SC_LD_A
:
2972 gen_offset_ld(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
2974 case OPC1_16_SC_LD_W
:
2975 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
2977 case OPC1_16_SC_MOV
:
2978 tcg_gen_movi_tl(cpu_gpr_d
[15], const16
);
2981 tcg_gen_ori_tl(cpu_gpr_d
[15], cpu_gpr_d
[15], const16
);
2983 case OPC1_16_SC_ST_A
:
2984 gen_offset_st(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
2986 case OPC1_16_SC_ST_W
:
2987 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
2989 case OPC1_16_SC_SUB_A
:
2990 tcg_gen_subi_tl(cpu_gpr_a
[10], cpu_gpr_a
[10], const16
);
2995 static void decode_slr_opc(DisasContext
*ctx
, int op1
)
2999 r1
= MASK_OP_SLR_D(ctx
->opcode
);
3000 r2
= MASK_OP_SLR_S2(ctx
->opcode
);
3004 case OPC1_16_SLR_LD_A
:
3005 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3007 case OPC1_16_SLR_LD_A_POSTINC
:
3008 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3009 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3011 case OPC1_16_SLR_LD_BU
:
3012 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3014 case OPC1_16_SLR_LD_BU_POSTINC
:
3015 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3016 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 1);
3018 case OPC1_16_SLR_LD_H
:
3019 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3021 case OPC1_16_SLR_LD_H_POSTINC
:
3022 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3023 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 2);
3025 case OPC1_16_SLR_LD_W
:
3026 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3028 case OPC1_16_SLR_LD_W_POSTINC
:
3029 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3030 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3035 static void decode_sro_opc(DisasContext
*ctx
, int op1
)
3040 r2
= MASK_OP_SRO_S2(ctx
->opcode
);
3041 address
= MASK_OP_SRO_OFF4(ctx
->opcode
);
3045 case OPC1_16_SRO_LD_A
:
3046 gen_offset_ld(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3048 case OPC1_16_SRO_LD_BU
:
3049 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_UB
);
3051 case OPC1_16_SRO_LD_H
:
3052 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_LESW
);
3054 case OPC1_16_SRO_LD_W
:
3055 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3057 case OPC1_16_SRO_ST_A
:
3058 gen_offset_st(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3060 case OPC1_16_SRO_ST_B
:
3061 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_UB
);
3063 case OPC1_16_SRO_ST_H
:
3064 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 2, MO_LESW
);
3066 case OPC1_16_SRO_ST_W
:
3067 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3072 static void decode_sr_system(CPUTriCoreState
*env
, DisasContext
*ctx
)
3075 op2
= MASK_OP_SR_OP2(ctx
->opcode
);
3078 case OPC2_16_SR_NOP
:
3080 case OPC2_16_SR_RET
:
3081 gen_compute_branch(ctx
, op2
, 0, 0, 0, 0);
3083 case OPC2_16_SR_RFE
:
3084 gen_helper_rfe(cpu_env
);
3086 ctx
->bstate
= BS_BRANCH
;
3088 case OPC2_16_SR_DEBUG
:
3089 /* raise EXCP_DEBUG */
3094 static void decode_sr_accu(CPUTriCoreState
*env
, DisasContext
*ctx
)
3100 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
3101 op2
= MASK_OP_SR_OP2(ctx
->opcode
);
3104 case OPC2_16_SR_RSUB
:
3105 /* overflow only if r1 = -0x80000000 */
3106 temp
= tcg_const_i32(-0x80000000);
3108 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r1
], temp
);
3109 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
3111 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
3113 tcg_gen_neg_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3115 tcg_gen_add_tl(cpu_PSW_AV
, cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3116 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_gpr_d
[r1
], cpu_PSW_AV
);
3118 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3119 tcg_temp_free(temp
);
3121 case OPC2_16_SR_SAT_B
:
3122 gen_saturate(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0x7f, -0x80);
3124 case OPC2_16_SR_SAT_BU
:
3125 gen_saturate_u(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0xff);
3127 case OPC2_16_SR_SAT_H
:
3128 gen_saturate(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0x7fff, -0x8000);
3130 case OPC2_16_SR_SAT_HU
:
3131 gen_saturate_u(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0xffff);
3136 static void decode_16Bit_opc(CPUTriCoreState
*env
, DisasContext
*ctx
)
3144 op1
= MASK_OP_MAJOR(ctx
->opcode
);
3146 /* handle ADDSC.A opcode only being 6 bit long */
3147 if (unlikely((op1
& 0x3f) == OPC1_16_SRRS_ADDSC_A
)) {
3148 op1
= OPC1_16_SRRS_ADDSC_A
;
3152 case OPC1_16_SRC_ADD
:
3153 case OPC1_16_SRC_ADD_A15
:
3154 case OPC1_16_SRC_ADD_15A
:
3155 case OPC1_16_SRC_ADD_A
:
3156 case OPC1_16_SRC_CADD
:
3157 case OPC1_16_SRC_CADDN
:
3158 case OPC1_16_SRC_CMOV
:
3159 case OPC1_16_SRC_CMOVN
:
3160 case OPC1_16_SRC_EQ
:
3161 case OPC1_16_SRC_LT
:
3162 case OPC1_16_SRC_MOV
:
3163 case OPC1_16_SRC_MOV_A
:
3164 case OPC1_16_SRC_SH
:
3165 case OPC1_16_SRC_SHA
:
3166 decode_src_opc(ctx
, op1
);
3169 case OPC1_16_SRR_ADD
:
3170 case OPC1_16_SRR_ADD_A15
:
3171 case OPC1_16_SRR_ADD_15A
:
3172 case OPC1_16_SRR_ADD_A
:
3173 case OPC1_16_SRR_ADDS
:
3174 case OPC1_16_SRR_AND
:
3175 case OPC1_16_SRR_CMOV
:
3176 case OPC1_16_SRR_CMOVN
:
3177 case OPC1_16_SRR_EQ
:
3178 case OPC1_16_SRR_LT
:
3179 case OPC1_16_SRR_MOV
:
3180 case OPC1_16_SRR_MOV_A
:
3181 case OPC1_16_SRR_MOV_AA
:
3182 case OPC1_16_SRR_MOV_D
:
3183 case OPC1_16_SRR_MUL
:
3184 case OPC1_16_SRR_OR
:
3185 case OPC1_16_SRR_SUB
:
3186 case OPC1_16_SRR_SUB_A15B
:
3187 case OPC1_16_SRR_SUB_15AB
:
3188 case OPC1_16_SRR_SUBS
:
3189 case OPC1_16_SRR_XOR
:
3190 decode_srr_opc(ctx
, op1
);
3193 case OPC1_16_SSR_ST_A
:
3194 case OPC1_16_SSR_ST_A_POSTINC
:
3195 case OPC1_16_SSR_ST_B
:
3196 case OPC1_16_SSR_ST_B_POSTINC
:
3197 case OPC1_16_SSR_ST_H
:
3198 case OPC1_16_SSR_ST_H_POSTINC
:
3199 case OPC1_16_SSR_ST_W
:
3200 case OPC1_16_SSR_ST_W_POSTINC
:
3201 decode_ssr_opc(ctx
, op1
);
3204 case OPC1_16_SRRS_ADDSC_A
:
3205 r2
= MASK_OP_SRRS_S2(ctx
->opcode
);
3206 r1
= MASK_OP_SRRS_S1D(ctx
->opcode
);
3207 const16
= MASK_OP_SRRS_N(ctx
->opcode
);
3208 temp
= tcg_temp_new();
3209 tcg_gen_shli_tl(temp
, cpu_gpr_d
[15], const16
);
3210 tcg_gen_add_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], temp
);
3211 tcg_temp_free(temp
);
3214 case OPC1_16_SLRO_LD_A
:
3215 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
3216 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
3217 gen_offset_ld(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
3219 case OPC1_16_SLRO_LD_BU
:
3220 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
3221 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
3222 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
, MO_UB
);
3224 case OPC1_16_SLRO_LD_H
:
3225 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
3226 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
3227 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 2, MO_LESW
);
3229 case OPC1_16_SLRO_LD_W
:
3230 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
3231 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
3232 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
3235 case OPC1_16_SB_CALL
:
3237 case OPC1_16_SB_JNZ
:
3239 address
= MASK_OP_SB_DISP8_SEXT(ctx
->opcode
);
3240 gen_compute_branch(ctx
, op1
, 0, 0, 0, address
);
3243 case OPC1_16_SBC_JEQ
:
3244 case OPC1_16_SBC_JNE
:
3245 address
= MASK_OP_SBC_DISP4(ctx
->opcode
);
3246 const16
= MASK_OP_SBC_CONST4_SEXT(ctx
->opcode
);
3247 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
3250 case OPC1_16_SBRN_JNZ_T
:
3251 case OPC1_16_SBRN_JZ_T
:
3252 address
= MASK_OP_SBRN_DISP4(ctx
->opcode
);
3253 const16
= MASK_OP_SBRN_N(ctx
->opcode
);
3254 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
3257 case OPC1_16_SBR_JEQ
:
3258 case OPC1_16_SBR_JGEZ
:
3259 case OPC1_16_SBR_JGTZ
:
3260 case OPC1_16_SBR_JLEZ
:
3261 case OPC1_16_SBR_JLTZ
:
3262 case OPC1_16_SBR_JNE
:
3263 case OPC1_16_SBR_JNZ
:
3264 case OPC1_16_SBR_JNZ_A
:
3265 case OPC1_16_SBR_JZ
:
3266 case OPC1_16_SBR_JZ_A
:
3267 case OPC1_16_SBR_LOOP
:
3268 r1
= MASK_OP_SBR_S2(ctx
->opcode
);
3269 address
= MASK_OP_SBR_DISP4(ctx
->opcode
);
3270 gen_compute_branch(ctx
, op1
, r1
, 0, 0, address
);
3273 case OPC1_16_SC_AND
:
3274 case OPC1_16_SC_BISR
:
3275 case OPC1_16_SC_LD_A
:
3276 case OPC1_16_SC_LD_W
:
3277 case OPC1_16_SC_MOV
:
3279 case OPC1_16_SC_ST_A
:
3280 case OPC1_16_SC_ST_W
:
3281 case OPC1_16_SC_SUB_A
:
3282 decode_sc_opc(ctx
, op1
);
3285 case OPC1_16_SLR_LD_A
:
3286 case OPC1_16_SLR_LD_A_POSTINC
:
3287 case OPC1_16_SLR_LD_BU
:
3288 case OPC1_16_SLR_LD_BU_POSTINC
:
3289 case OPC1_16_SLR_LD_H
:
3290 case OPC1_16_SLR_LD_H_POSTINC
:
3291 case OPC1_16_SLR_LD_W
:
3292 case OPC1_16_SLR_LD_W_POSTINC
:
3293 decode_slr_opc(ctx
, op1
);
3296 case OPC1_16_SRO_LD_A
:
3297 case OPC1_16_SRO_LD_BU
:
3298 case OPC1_16_SRO_LD_H
:
3299 case OPC1_16_SRO_LD_W
:
3300 case OPC1_16_SRO_ST_A
:
3301 case OPC1_16_SRO_ST_B
:
3302 case OPC1_16_SRO_ST_H
:
3303 case OPC1_16_SRO_ST_W
:
3304 decode_sro_opc(ctx
, op1
);
3307 case OPC1_16_SSRO_ST_A
:
3308 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
3309 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
3310 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
3312 case OPC1_16_SSRO_ST_B
:
3313 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
3314 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
3315 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
, MO_UB
);
3317 case OPC1_16_SSRO_ST_H
:
3318 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
3319 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
3320 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 2, MO_LESW
);
3322 case OPC1_16_SSRO_ST_W
:
3323 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
3324 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
3325 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
3328 case OPCM_16_SR_SYSTEM
:
3329 decode_sr_system(env
, ctx
);
3331 case OPCM_16_SR_ACCU
:
3332 decode_sr_accu(env
, ctx
);
3335 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
3336 gen_compute_branch(ctx
, op1
, r1
, 0, 0, 0);
3338 case OPC1_16_SR_NOT
:
3339 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
3340 tcg_gen_not_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3346 * 32 bit instructions
3350 static void decode_abs_ldw(CPUTriCoreState
*env
, DisasContext
*ctx
)
3357 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
3358 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
3359 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
3361 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
3364 case OPC2_32_ABS_LD_A
:
3365 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
3367 case OPC2_32_ABS_LD_D
:
3368 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
3370 case OPC2_32_ABS_LD_DA
:
3371 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
3373 case OPC2_32_ABS_LD_W
:
3374 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
3378 tcg_temp_free(temp
);
3381 static void decode_abs_ldb(CPUTriCoreState
*env
, DisasContext
*ctx
)
3388 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
3389 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
3390 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
3392 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
3395 case OPC2_32_ABS_LD_B
:
3396 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_SB
);
3398 case OPC2_32_ABS_LD_BU
:
3399 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_UB
);
3401 case OPC2_32_ABS_LD_H
:
3402 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESW
);
3404 case OPC2_32_ABS_LD_HU
:
3405 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
3409 tcg_temp_free(temp
);
3412 static void decode_abs_ldst_swap(CPUTriCoreState
*env
, DisasContext
*ctx
)
3419 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
3420 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
3421 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
3423 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
3426 case OPC2_32_ABS_LDMST
:
3427 gen_ldmst(ctx
, r1
, temp
);
3429 case OPC2_32_ABS_SWAP_W
:
3430 gen_swap(ctx
, r1
, temp
);
3434 tcg_temp_free(temp
);
3437 static void decode_abs_ldst_context(CPUTriCoreState
*env
, DisasContext
*ctx
)
3442 off18
= MASK_OP_ABS_OFF18(ctx
->opcode
);
3443 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
3446 case OPC2_32_ABS_LDLCX
:
3447 gen_helper_1arg(ldlcx
, EA_ABS_FORMAT(off18
));
3449 case OPC2_32_ABS_LDUCX
:
3450 gen_helper_1arg(lducx
, EA_ABS_FORMAT(off18
));
3452 case OPC2_32_ABS_STLCX
:
3453 gen_helper_1arg(stlcx
, EA_ABS_FORMAT(off18
));
3455 case OPC2_32_ABS_STUCX
:
3456 gen_helper_1arg(stucx
, EA_ABS_FORMAT(off18
));
3461 static void decode_abs_store(CPUTriCoreState
*env
, DisasContext
*ctx
)
3468 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
3469 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
3470 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
3472 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
3475 case OPC2_32_ABS_ST_A
:
3476 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
3478 case OPC2_32_ABS_ST_D
:
3479 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
3481 case OPC2_32_ABS_ST_DA
:
3482 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
3484 case OPC2_32_ABS_ST_W
:
3485 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
3489 tcg_temp_free(temp
);
3492 static void decode_abs_storeb_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
3499 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
3500 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
3501 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
3503 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
3506 case OPC2_32_ABS_ST_B
:
3507 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_UB
);
3509 case OPC2_32_ABS_ST_H
:
3510 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
3513 tcg_temp_free(temp
);
3518 static void decode_bit_andacc(CPUTriCoreState
*env
, DisasContext
*ctx
)
3524 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3525 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3526 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3527 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3528 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3529 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3533 case OPC2_32_BIT_AND_AND_T
:
3534 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3535 pos1
, pos2
, &tcg_gen_and_tl
, &tcg_gen_and_tl
);
3537 case OPC2_32_BIT_AND_ANDN_T
:
3538 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3539 pos1
, pos2
, &tcg_gen_andc_tl
, &tcg_gen_and_tl
);
3541 case OPC2_32_BIT_AND_NOR_T
:
3542 if (TCG_TARGET_HAS_andc_i32
) {
3543 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3544 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_andc_tl
);
3546 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3547 pos1
, pos2
, &tcg_gen_nor_tl
, &tcg_gen_and_tl
);
3550 case OPC2_32_BIT_AND_OR_T
:
3551 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3552 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_and_tl
);
3557 static void decode_bit_logical_t(CPUTriCoreState
*env
, DisasContext
*ctx
)
3562 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3563 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3564 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3565 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3566 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3567 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3570 case OPC2_32_BIT_AND_T
:
3571 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3572 pos1
, pos2
, &tcg_gen_and_tl
);
3574 case OPC2_32_BIT_ANDN_T
:
3575 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3576 pos1
, pos2
, &tcg_gen_andc_tl
);
3578 case OPC2_32_BIT_NOR_T
:
3579 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3580 pos1
, pos2
, &tcg_gen_nor_tl
);
3582 case OPC2_32_BIT_OR_T
:
3583 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3584 pos1
, pos2
, &tcg_gen_or_tl
);
3589 static void decode_bit_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
3595 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3596 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3597 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3598 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3599 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3600 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3602 temp
= tcg_temp_new();
3604 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r2
], pos2
);
3605 if (op2
== OPC2_32_BIT_INSN_T
) {
3606 tcg_gen_not_tl(temp
, temp
);
3608 tcg_gen_deposit_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], temp
, pos1
, 1);
3609 tcg_temp_free(temp
);
3612 static void decode_bit_logical_t2(CPUTriCoreState
*env
, DisasContext
*ctx
)
3619 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3620 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3621 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3622 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3623 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3624 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3627 case OPC2_32_BIT_NAND_T
:
3628 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3629 pos1
, pos2
, &tcg_gen_nand_tl
);
3631 case OPC2_32_BIT_ORN_T
:
3632 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3633 pos1
, pos2
, &tcg_gen_orc_tl
);
3635 case OPC2_32_BIT_XNOR_T
:
3636 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3637 pos1
, pos2
, &tcg_gen_eqv_tl
);
3639 case OPC2_32_BIT_XOR_T
:
3640 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3641 pos1
, pos2
, &tcg_gen_xor_tl
);
3646 static void decode_bit_orand(CPUTriCoreState
*env
, DisasContext
*ctx
)
3653 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3654 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3655 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3656 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3657 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3658 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3661 case OPC2_32_BIT_OR_AND_T
:
3662 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3663 pos1
, pos2
, &tcg_gen_and_tl
, &tcg_gen_or_tl
);
3665 case OPC2_32_BIT_OR_ANDN_T
:
3666 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3667 pos1
, pos2
, &tcg_gen_andc_tl
, &tcg_gen_or_tl
);
3669 case OPC2_32_BIT_OR_NOR_T
:
3670 if (TCG_TARGET_HAS_orc_i32
) {
3671 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3672 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_orc_tl
);
3674 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3675 pos1
, pos2
, &tcg_gen_nor_tl
, &tcg_gen_or_tl
);
3678 case OPC2_32_BIT_OR_OR_T
:
3679 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3680 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_or_tl
);
3685 static void decode_bit_sh_logic1(CPUTriCoreState
*env
, DisasContext
*ctx
)
3692 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3693 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3694 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3695 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3696 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3697 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3699 temp
= tcg_temp_new();
3702 case OPC2_32_BIT_SH_AND_T
:
3703 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3704 pos1
, pos2
, &tcg_gen_and_tl
);
3706 case OPC2_32_BIT_SH_ANDN_T
:
3707 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3708 pos1
, pos2
, &tcg_gen_andc_tl
);
3710 case OPC2_32_BIT_SH_NOR_T
:
3711 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3712 pos1
, pos2
, &tcg_gen_nor_tl
);
3714 case OPC2_32_BIT_SH_OR_T
:
3715 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3716 pos1
, pos2
, &tcg_gen_or_tl
);
3719 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 1);
3720 tcg_gen_add_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
3721 tcg_temp_free(temp
);
3724 static void decode_bit_sh_logic2(CPUTriCoreState
*env
, DisasContext
*ctx
)
3731 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
3732 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
3733 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
3734 r3
= MASK_OP_BIT_D(ctx
->opcode
);
3735 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
3736 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
3738 temp
= tcg_temp_new();
3741 case OPC2_32_BIT_SH_NAND_T
:
3742 gen_bit_1op(temp
, cpu_gpr_d
[r1
] , cpu_gpr_d
[r2
] ,
3743 pos1
, pos2
, &tcg_gen_nand_tl
);
3745 case OPC2_32_BIT_SH_ORN_T
:
3746 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3747 pos1
, pos2
, &tcg_gen_orc_tl
);
3749 case OPC2_32_BIT_SH_XNOR_T
:
3750 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3751 pos1
, pos2
, &tcg_gen_eqv_tl
);
3753 case OPC2_32_BIT_SH_XOR_T
:
3754 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3755 pos1
, pos2
, &tcg_gen_xor_tl
);
3758 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 1);
3759 tcg_gen_add_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
3760 tcg_temp_free(temp
);
3766 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState
*env
,
3774 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
3775 r2
= MASK_OP_BO_S2(ctx
->opcode
);
3776 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
3777 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
3780 case OPC2_32_BO_CACHEA_WI_SHORTOFF
:
3781 case OPC2_32_BO_CACHEA_W_SHORTOFF
:
3782 case OPC2_32_BO_CACHEA_I_SHORTOFF
:
3783 /* instruction to access the cache */
3785 case OPC2_32_BO_CACHEA_WI_POSTINC
:
3786 case OPC2_32_BO_CACHEA_W_POSTINC
:
3787 case OPC2_32_BO_CACHEA_I_POSTINC
:
3788 /* instruction to access the cache, but we still need to handle
3789 the addressing mode */
3790 tcg_gen_addi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
], off10
);
3792 case OPC2_32_BO_CACHEA_WI_PREINC
:
3793 case OPC2_32_BO_CACHEA_W_PREINC
:
3794 case OPC2_32_BO_CACHEA_I_PREINC
:
3795 /* instruction to access the cache, but we still need to handle
3796 the addressing mode */
3797 tcg_gen_addi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
], off10
);
3799 case OPC2_32_BO_CACHEI_WI_SHORTOFF
:
3800 case OPC2_32_BO_CACHEI_W_SHORTOFF
:
3801 /* TODO: Raise illegal opcode trap,
3802 if !tricore_feature(TRICORE_FEATURE_131) */
3804 case OPC2_32_BO_CACHEI_W_POSTINC
:
3805 case OPC2_32_BO_CACHEI_WI_POSTINC
:
3806 if (tricore_feature(env
, TRICORE_FEATURE_131
)) {
3807 tcg_gen_addi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
], off10
);
3808 } /* TODO: else raise illegal opcode trap */
3810 case OPC2_32_BO_CACHEI_W_PREINC
:
3811 case OPC2_32_BO_CACHEI_WI_PREINC
:
3812 if (tricore_feature(env
, TRICORE_FEATURE_131
)) {
3813 tcg_gen_addi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
], off10
);
3814 } /* TODO: else raise illegal opcode trap */
3816 case OPC2_32_BO_ST_A_SHORTOFF
:
3817 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESL
);
3819 case OPC2_32_BO_ST_A_POSTINC
:
3820 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
3822 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3824 case OPC2_32_BO_ST_A_PREINC
:
3825 gen_st_preincr(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESL
);
3827 case OPC2_32_BO_ST_B_SHORTOFF
:
3828 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
3830 case OPC2_32_BO_ST_B_POSTINC
:
3831 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
3833 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3835 case OPC2_32_BO_ST_B_PREINC
:
3836 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
3838 case OPC2_32_BO_ST_D_SHORTOFF
:
3839 gen_offset_st_2regs(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
],
3842 case OPC2_32_BO_ST_D_POSTINC
:
3843 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
);
3844 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3846 case OPC2_32_BO_ST_D_PREINC
:
3847 temp
= tcg_temp_new();
3848 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
3849 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
3850 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
3851 tcg_temp_free(temp
);
3853 case OPC2_32_BO_ST_DA_SHORTOFF
:
3854 gen_offset_st_2regs(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
3857 case OPC2_32_BO_ST_DA_POSTINC
:
3858 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
);
3859 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3861 case OPC2_32_BO_ST_DA_PREINC
:
3862 temp
= tcg_temp_new();
3863 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
3864 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
3865 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
3866 tcg_temp_free(temp
);
3868 case OPC2_32_BO_ST_H_SHORTOFF
:
3869 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
3871 case OPC2_32_BO_ST_H_POSTINC
:
3872 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
3874 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3876 case OPC2_32_BO_ST_H_PREINC
:
3877 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
3879 case OPC2_32_BO_ST_Q_SHORTOFF
:
3880 temp
= tcg_temp_new();
3881 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
3882 gen_offset_st(ctx
, temp
, cpu_gpr_a
[r2
], off10
, MO_LEUW
);
3883 tcg_temp_free(temp
);
3885 case OPC2_32_BO_ST_Q_POSTINC
:
3886 temp
= tcg_temp_new();
3887 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
3888 tcg_gen_qemu_st_tl(temp
, cpu_gpr_a
[r2
], ctx
->mem_idx
,
3890 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3891 tcg_temp_free(temp
);
3893 case OPC2_32_BO_ST_Q_PREINC
:
3894 temp
= tcg_temp_new();
3895 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
3896 gen_st_preincr(ctx
, temp
, cpu_gpr_a
[r2
], off10
, MO_LEUW
);
3897 tcg_temp_free(temp
);
3899 case OPC2_32_BO_ST_W_SHORTOFF
:
3900 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
3902 case OPC2_32_BO_ST_W_POSTINC
:
3903 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
3905 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
3907 case OPC2_32_BO_ST_W_PREINC
:
3908 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
3913 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState
*env
,
3919 TCGv temp
, temp2
, temp3
;
3921 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
3922 r2
= MASK_OP_BO_S2(ctx
->opcode
);
3923 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
3924 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
3926 temp
= tcg_temp_new();
3927 temp2
= tcg_temp_new();
3928 temp3
= tcg_const_i32(off10
);
3930 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
3931 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
3934 case OPC2_32_BO_CACHEA_WI_BR
:
3935 case OPC2_32_BO_CACHEA_W_BR
:
3936 case OPC2_32_BO_CACHEA_I_BR
:
3937 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3939 case OPC2_32_BO_CACHEA_WI_CIRC
:
3940 case OPC2_32_BO_CACHEA_W_CIRC
:
3941 case OPC2_32_BO_CACHEA_I_CIRC
:
3942 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
3944 case OPC2_32_BO_ST_A_BR
:
3945 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
3946 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3948 case OPC2_32_BO_ST_A_CIRC
:
3949 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
3950 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
3952 case OPC2_32_BO_ST_B_BR
:
3953 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
3954 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3956 case OPC2_32_BO_ST_B_CIRC
:
3957 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
3958 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
3960 case OPC2_32_BO_ST_D_BR
:
3961 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp2
, ctx
);
3962 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3964 case OPC2_32_BO_ST_D_CIRC
:
3965 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
3966 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
3967 tcg_gen_addi_tl(temp
, temp
, 4);
3968 tcg_gen_rem_tl(temp
, temp
, temp2
);
3969 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
3970 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
3971 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
3973 case OPC2_32_BO_ST_DA_BR
:
3974 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp2
, ctx
);
3975 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3977 case OPC2_32_BO_ST_DA_CIRC
:
3978 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
3979 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
3980 tcg_gen_addi_tl(temp
, temp
, 4);
3981 tcg_gen_rem_tl(temp
, temp
, temp2
);
3982 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
3983 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
3984 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
3986 case OPC2_32_BO_ST_H_BR
:
3987 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
3988 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3990 case OPC2_32_BO_ST_H_CIRC
:
3991 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
3992 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
3994 case OPC2_32_BO_ST_Q_BR
:
3995 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
3996 tcg_gen_qemu_st_tl(temp
, temp2
, ctx
->mem_idx
, MO_LEUW
);
3997 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
3999 case OPC2_32_BO_ST_Q_CIRC
:
4000 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4001 tcg_gen_qemu_st_tl(temp
, temp2
, ctx
->mem_idx
, MO_LEUW
);
4002 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4004 case OPC2_32_BO_ST_W_BR
:
4005 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4006 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4008 case OPC2_32_BO_ST_W_CIRC
:
4009 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4010 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4013 tcg_temp_free(temp
);
4014 tcg_temp_free(temp2
);
4015 tcg_temp_free(temp3
);
4018 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState
*env
,
4026 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4027 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4028 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4029 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4032 case OPC2_32_BO_LD_A_SHORTOFF
:
4033 gen_offset_ld(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4035 case OPC2_32_BO_LD_A_POSTINC
:
4036 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4038 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4040 case OPC2_32_BO_LD_A_PREINC
:
4041 gen_ld_preincr(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4043 case OPC2_32_BO_LD_B_SHORTOFF
:
4044 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4046 case OPC2_32_BO_LD_B_POSTINC
:
4047 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4049 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4051 case OPC2_32_BO_LD_B_PREINC
:
4052 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4054 case OPC2_32_BO_LD_BU_SHORTOFF
:
4055 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4057 case OPC2_32_BO_LD_BU_POSTINC
:
4058 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4060 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4062 case OPC2_32_BO_LD_BU_PREINC
:
4063 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4065 case OPC2_32_BO_LD_D_SHORTOFF
:
4066 gen_offset_ld_2regs(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
],
4069 case OPC2_32_BO_LD_D_POSTINC
:
4070 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
);
4071 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4073 case OPC2_32_BO_LD_D_PREINC
:
4074 temp
= tcg_temp_new();
4075 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4076 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4077 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4078 tcg_temp_free(temp
);
4080 case OPC2_32_BO_LD_DA_SHORTOFF
:
4081 gen_offset_ld_2regs(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
4084 case OPC2_32_BO_LD_DA_POSTINC
:
4085 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
);
4086 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4088 case OPC2_32_BO_LD_DA_PREINC
:
4089 temp
= tcg_temp_new();
4090 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4091 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4092 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4093 tcg_temp_free(temp
);
4095 case OPC2_32_BO_LD_H_SHORTOFF
:
4096 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESW
);
4098 case OPC2_32_BO_LD_H_POSTINC
:
4099 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4101 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4103 case OPC2_32_BO_LD_H_PREINC
:
4104 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESW
);
4106 case OPC2_32_BO_LD_HU_SHORTOFF
:
4107 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4109 case OPC2_32_BO_LD_HU_POSTINC
:
4110 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4112 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4114 case OPC2_32_BO_LD_HU_PREINC
:
4115 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4117 case OPC2_32_BO_LD_Q_SHORTOFF
:
4118 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4119 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
4121 case OPC2_32_BO_LD_Q_POSTINC
:
4122 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4124 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
4125 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4127 case OPC2_32_BO_LD_Q_PREINC
:
4128 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4129 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
4131 case OPC2_32_BO_LD_W_SHORTOFF
:
4132 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4134 case OPC2_32_BO_LD_W_POSTINC
:
4135 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4137 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4139 case OPC2_32_BO_LD_W_PREINC
:
4140 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4145 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState
*env
,
4152 TCGv temp
, temp2
, temp3
;
4154 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4155 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4156 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4157 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4159 temp
= tcg_temp_new();
4160 temp2
= tcg_temp_new();
4161 temp3
= tcg_const_i32(off10
);
4163 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
4164 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4168 case OPC2_32_BO_LD_A_BR
:
4169 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4170 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4172 case OPC2_32_BO_LD_A_CIRC
:
4173 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4174 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4176 case OPC2_32_BO_LD_B_BR
:
4177 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_SB
);
4178 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4180 case OPC2_32_BO_LD_B_CIRC
:
4181 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_SB
);
4182 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4184 case OPC2_32_BO_LD_BU_BR
:
4185 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
4186 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4188 case OPC2_32_BO_LD_BU_CIRC
:
4189 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
4190 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4192 case OPC2_32_BO_LD_D_BR
:
4193 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp2
, ctx
);
4194 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4196 case OPC2_32_BO_LD_D_CIRC
:
4197 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4198 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
4199 tcg_gen_addi_tl(temp
, temp
, 4);
4200 tcg_gen_rem_tl(temp
, temp
, temp2
);
4201 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4202 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
4203 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4205 case OPC2_32_BO_LD_DA_BR
:
4206 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp2
, ctx
);
4207 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4209 case OPC2_32_BO_LD_DA_CIRC
:
4210 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4211 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
4212 tcg_gen_addi_tl(temp
, temp
, 4);
4213 tcg_gen_rem_tl(temp
, temp
, temp2
);
4214 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4215 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
4216 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4218 case OPC2_32_BO_LD_H_BR
:
4219 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LESW
);
4220 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4222 case OPC2_32_BO_LD_H_CIRC
:
4223 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LESW
);
4224 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4226 case OPC2_32_BO_LD_HU_BR
:
4227 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4228 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4230 case OPC2_32_BO_LD_HU_CIRC
:
4231 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4232 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4234 case OPC2_32_BO_LD_Q_BR
:
4235 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4236 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
4237 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4239 case OPC2_32_BO_LD_Q_CIRC
:
4240 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4241 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
4242 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4244 case OPC2_32_BO_LD_W_BR
:
4245 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4246 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4248 case OPC2_32_BO_LD_W_CIRC
:
4249 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4250 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4253 tcg_temp_free(temp
);
4254 tcg_temp_free(temp2
);
4255 tcg_temp_free(temp3
);
4258 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState
*env
,
4267 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4268 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4269 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4270 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4273 temp
= tcg_temp_new();
4274 temp2
= tcg_temp_new();
4277 case OPC2_32_BO_LDLCX_SHORTOFF
:
4278 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4279 gen_helper_ldlcx(cpu_env
, temp
);
4281 case OPC2_32_BO_LDMST_SHORTOFF
:
4282 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4283 gen_ldmst(ctx
, r1
, temp
);
4285 case OPC2_32_BO_LDMST_POSTINC
:
4286 gen_ldmst(ctx
, r1
, cpu_gpr_a
[r2
]);
4287 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4289 case OPC2_32_BO_LDMST_PREINC
:
4290 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4291 gen_ldmst(ctx
, r1
, cpu_gpr_a
[r2
]);
4293 case OPC2_32_BO_LDUCX_SHORTOFF
:
4294 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4295 gen_helper_lducx(cpu_env
, temp
);
4297 case OPC2_32_BO_LEA_SHORTOFF
:
4298 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
);
4300 case OPC2_32_BO_STLCX_SHORTOFF
:
4301 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4302 gen_helper_stlcx(cpu_env
, temp
);
4304 case OPC2_32_BO_STUCX_SHORTOFF
:
4305 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4306 gen_helper_stucx(cpu_env
, temp
);
4308 case OPC2_32_BO_SWAP_W_SHORTOFF
:
4309 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4310 gen_swap(ctx
, r1
, temp
);
4312 case OPC2_32_BO_SWAP_W_POSTINC
:
4313 gen_swap(ctx
, r1
, cpu_gpr_a
[r2
]);
4314 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4316 case OPC2_32_BO_SWAP_W_PREINC
:
4317 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4318 gen_swap(ctx
, r1
, cpu_gpr_a
[r2
]);
4321 tcg_temp_free(temp
);
4322 tcg_temp_free(temp2
);
4325 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState
*env
,
4332 TCGv temp
, temp2
, temp3
;
4334 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4335 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4336 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4337 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4339 temp
= tcg_temp_new();
4340 temp2
= tcg_temp_new();
4341 temp3
= tcg_const_i32(off10
);
4343 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
4344 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4347 case OPC2_32_BO_LDMST_BR
:
4348 gen_ldmst(ctx
, r1
, temp2
);
4349 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4351 case OPC2_32_BO_LDMST_CIRC
:
4352 gen_ldmst(ctx
, r1
, temp2
);
4353 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4355 case OPC2_32_BO_SWAP_W_BR
:
4356 gen_swap(ctx
, r1
, temp2
);
4357 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4359 case OPC2_32_BO_SWAP_W_CIRC
:
4360 gen_swap(ctx
, r1
, temp2
);
4361 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4364 tcg_temp_free(temp
);
4365 tcg_temp_free(temp2
);
4366 tcg_temp_free(temp3
);
4369 static void decode_bol_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int32_t op1
)
4375 r1
= MASK_OP_BOL_S1D(ctx
->opcode
);
4376 r2
= MASK_OP_BOL_S2(ctx
->opcode
);
4377 address
= MASK_OP_BOL_OFF16_SEXT(ctx
->opcode
);
4380 case OPC1_32_BOL_LD_A_LONGOFF
:
4381 temp
= tcg_temp_new();
4382 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], address
);
4383 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LEUL
);
4384 tcg_temp_free(temp
);
4386 case OPC1_32_BOL_LD_W_LONGOFF
:
4387 temp
= tcg_temp_new();
4388 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], address
);
4389 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUL
);
4390 tcg_temp_free(temp
);
4392 case OPC1_32_BOL_LEA_LONGOFF
:
4393 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], address
);
4395 case OPC1_32_BOL_ST_A_LONGOFF
:
4396 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4397 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUL
);
4399 /* raise illegal opcode trap */
4402 case OPC1_32_BOL_ST_W_LONGOFF
:
4403 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUL
);
4405 case OPC1_32_BOL_LD_B_LONGOFF
:
4406 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4407 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_SB
);
4409 /* raise illegal opcode trap */
4412 case OPC1_32_BOL_LD_BU_LONGOFF
:
4413 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4414 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_UB
);
4416 /* raise illegal opcode trap */
4419 case OPC1_32_BOL_LD_H_LONGOFF
:
4420 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4421 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LESW
);
4423 /* raise illegal opcode trap */
4426 case OPC1_32_BOL_LD_HU_LONGOFF
:
4427 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4428 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUW
);
4430 /* raise illegal opcode trap */
4433 case OPC1_32_BOL_ST_B_LONGOFF
:
4434 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4435 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_SB
);
4437 /* raise illegal opcode trap */
4440 case OPC1_32_BOL_ST_H_LONGOFF
:
4441 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4442 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LESW
);
4444 /* raise illegal opcode trap */
4451 static void decode_rc_logical_shift(CPUTriCoreState
*env
, DisasContext
*ctx
)
4458 r2
= MASK_OP_RC_D(ctx
->opcode
);
4459 r1
= MASK_OP_RC_S1(ctx
->opcode
);
4460 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4461 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
4463 temp
= tcg_temp_new();
4466 case OPC2_32_RC_AND
:
4467 tcg_gen_andi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4469 case OPC2_32_RC_ANDN
:
4470 tcg_gen_andi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], ~const9
);
4472 case OPC2_32_RC_NAND
:
4473 tcg_gen_movi_tl(temp
, const9
);
4474 tcg_gen_nand_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
);
4476 case OPC2_32_RC_NOR
:
4477 tcg_gen_movi_tl(temp
, const9
);
4478 tcg_gen_nor_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
);
4481 tcg_gen_ori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4483 case OPC2_32_RC_ORN
:
4484 tcg_gen_ori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], ~const9
);
4487 const9
= sextract32(const9
, 0, 6);
4488 gen_shi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4490 case OPC2_32_RC_SH_H
:
4491 const9
= sextract32(const9
, 0, 5);
4492 gen_sh_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4494 case OPC2_32_RC_SHA
:
4495 const9
= sextract32(const9
, 0, 6);
4496 gen_shaci(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4498 case OPC2_32_RC_SHA_H
:
4499 const9
= sextract32(const9
, 0, 5);
4500 gen_sha_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4502 case OPC2_32_RC_SHAS
:
4503 gen_shasi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4505 case OPC2_32_RC_XNOR
:
4506 tcg_gen_xori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4507 tcg_gen_not_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
]);
4509 case OPC2_32_RC_XOR
:
4510 tcg_gen_xori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4513 tcg_temp_free(temp
);
4516 static void decode_rc_accumulator(CPUTriCoreState
*env
, DisasContext
*ctx
)
4524 r2
= MASK_OP_RC_D(ctx
->opcode
);
4525 r1
= MASK_OP_RC_S1(ctx
->opcode
);
4526 const9
= MASK_OP_RC_CONST9_SEXT(ctx
->opcode
);
4528 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
4530 temp
= tcg_temp_new();
4533 case OPC2_32_RC_ABSDIF
:
4534 gen_absdifi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4536 case OPC2_32_RC_ABSDIFS
:
4537 gen_absdifsi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4539 case OPC2_32_RC_ADD
:
4540 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4542 case OPC2_32_RC_ADDC
:
4543 gen_addci_CC(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4545 case OPC2_32_RC_ADDS
:
4546 gen_addsi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4548 case OPC2_32_RC_ADDS_U
:
4549 gen_addsui(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4551 case OPC2_32_RC_ADDX
:
4552 gen_addi_CC(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4554 case OPC2_32_RC_AND_EQ
:
4555 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4556 const9
, &tcg_gen_and_tl
);
4558 case OPC2_32_RC_AND_GE
:
4559 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4560 const9
, &tcg_gen_and_tl
);
4562 case OPC2_32_RC_AND_GE_U
:
4563 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4564 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4565 const9
, &tcg_gen_and_tl
);
4567 case OPC2_32_RC_AND_LT
:
4568 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4569 const9
, &tcg_gen_and_tl
);
4571 case OPC2_32_RC_AND_LT_U
:
4572 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4573 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4574 const9
, &tcg_gen_and_tl
);
4576 case OPC2_32_RC_AND_NE
:
4577 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4578 const9
, &tcg_gen_and_tl
);
4581 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4583 case OPC2_32_RC_EQANY_B
:
4584 gen_eqany_bi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4586 case OPC2_32_RC_EQANY_H
:
4587 gen_eqany_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4590 tcg_gen_setcondi_tl(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4592 case OPC2_32_RC_GE_U
:
4593 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4594 tcg_gen_setcondi_tl(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4597 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4599 case OPC2_32_RC_LT_U
:
4600 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4601 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4603 case OPC2_32_RC_MAX
:
4604 tcg_gen_movi_tl(temp
, const9
);
4605 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
4606 cpu_gpr_d
[r1
], temp
);
4608 case OPC2_32_RC_MAX_U
:
4609 tcg_gen_movi_tl(temp
, MASK_OP_RC_CONST9(ctx
->opcode
));
4610 tcg_gen_movcond_tl(TCG_COND_GTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
4611 cpu_gpr_d
[r1
], temp
);
4613 case OPC2_32_RC_MIN
:
4614 tcg_gen_movi_tl(temp
, const9
);
4615 tcg_gen_movcond_tl(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
4616 cpu_gpr_d
[r1
], temp
);
4618 case OPC2_32_RC_MIN_U
:
4619 tcg_gen_movi_tl(temp
, MASK_OP_RC_CONST9(ctx
->opcode
));
4620 tcg_gen_movcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
4621 cpu_gpr_d
[r1
], temp
);
4624 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4626 case OPC2_32_RC_OR_EQ
:
4627 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4628 const9
, &tcg_gen_or_tl
);
4630 case OPC2_32_RC_OR_GE
:
4631 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4632 const9
, &tcg_gen_or_tl
);
4634 case OPC2_32_RC_OR_GE_U
:
4635 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4636 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4637 const9
, &tcg_gen_or_tl
);
4639 case OPC2_32_RC_OR_LT
:
4640 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4641 const9
, &tcg_gen_or_tl
);
4643 case OPC2_32_RC_OR_LT_U
:
4644 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4645 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4646 const9
, &tcg_gen_or_tl
);
4648 case OPC2_32_RC_OR_NE
:
4649 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4650 const9
, &tcg_gen_or_tl
);
4652 case OPC2_32_RC_RSUB
:
4653 tcg_gen_movi_tl(temp
, const9
);
4654 gen_sub_d(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
4656 case OPC2_32_RC_RSUBS
:
4657 tcg_gen_movi_tl(temp
, const9
);
4658 gen_subs(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
4660 case OPC2_32_RC_RSUBS_U
:
4661 tcg_gen_movi_tl(temp
, const9
);
4662 gen_subsu(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
4664 case OPC2_32_RC_SH_EQ
:
4665 gen_sh_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4667 case OPC2_32_RC_SH_GE
:
4668 gen_sh_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4670 case OPC2_32_RC_SH_GE_U
:
4671 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4672 gen_sh_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4674 case OPC2_32_RC_SH_LT
:
4675 gen_sh_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4677 case OPC2_32_RC_SH_LT_U
:
4678 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4679 gen_sh_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4681 case OPC2_32_RC_SH_NE
:
4682 gen_sh_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4684 case OPC2_32_RC_XOR_EQ
:
4685 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4686 const9
, &tcg_gen_xor_tl
);
4688 case OPC2_32_RC_XOR_GE
:
4689 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4690 const9
, &tcg_gen_xor_tl
);
4692 case OPC2_32_RC_XOR_GE_U
:
4693 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4694 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4695 const9
, &tcg_gen_xor_tl
);
4697 case OPC2_32_RC_XOR_LT
:
4698 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4699 const9
, &tcg_gen_xor_tl
);
4701 case OPC2_32_RC_XOR_LT_U
:
4702 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4703 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4704 const9
, &tcg_gen_xor_tl
);
4706 case OPC2_32_RC_XOR_NE
:
4707 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
4708 const9
, &tcg_gen_xor_tl
);
4711 tcg_temp_free(temp
);
4714 static void decode_rc_serviceroutine(CPUTriCoreState
*env
, DisasContext
*ctx
)
4719 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
4720 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4723 case OPC2_32_RC_BISR
:
4724 gen_helper_1arg(bisr
, const9
);
4726 case OPC2_32_RC_SYSCALL
:
4727 /* TODO: Add exception generation */
4732 static void decode_rc_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
4738 r2
= MASK_OP_RC_D(ctx
->opcode
);
4739 r1
= MASK_OP_RC_S1(ctx
->opcode
);
4740 const9
= MASK_OP_RC_CONST9_SEXT(ctx
->opcode
);
4742 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
4745 case OPC2_32_RC_MUL_32
:
4746 gen_muli_i32s(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4748 case OPC2_32_RC_MUL_64
:
4749 gen_muli_i64s(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
+1], cpu_gpr_d
[r1
], const9
);
4751 case OPC2_32_RC_MULS_32
:
4752 gen_mulsi_i32(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4754 case OPC2_32_RC_MUL_U_64
:
4755 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4756 gen_muli_i64u(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
+1], cpu_gpr_d
[r1
], const9
);
4758 case OPC2_32_RC_MULS_U_32
:
4759 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
4760 gen_mulsui_i32(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
4766 static void decode_rcpw_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
4770 int32_t pos
, width
, const4
;
4774 op2
= MASK_OP_RCPW_OP2(ctx
->opcode
);
4775 r1
= MASK_OP_RCPW_S1(ctx
->opcode
);
4776 r2
= MASK_OP_RCPW_D(ctx
->opcode
);
4777 const4
= MASK_OP_RCPW_CONST4(ctx
->opcode
);
4778 width
= MASK_OP_RCPW_WIDTH(ctx
->opcode
);
4779 pos
= MASK_OP_RCPW_POS(ctx
->opcode
);
4782 case OPC2_32_RCPW_IMASK
:
4783 /* if pos + width > 31 undefined result */
4784 if (pos
+ width
<= 31) {
4785 tcg_gen_movi_tl(cpu_gpr_d
[r2
+1], ((1u << width
) - 1) << pos
);
4786 tcg_gen_movi_tl(cpu_gpr_d
[r2
], (const4
<< pos
));
4789 case OPC2_32_RCPW_INSERT
:
4790 /* if pos + width > 32 undefined result */
4791 if (pos
+ width
<= 32) {
4792 temp
= tcg_const_i32(const4
);
4793 tcg_gen_deposit_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
, pos
, width
);
4794 tcg_temp_free(temp
);
4802 static void decode_rcrw_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
4806 int32_t width
, const4
;
4808 TCGv temp
, temp2
, temp3
;
4810 op2
= MASK_OP_RCRW_OP2(ctx
->opcode
);
4811 r1
= MASK_OP_RCRW_S1(ctx
->opcode
);
4812 r3
= MASK_OP_RCRW_S3(ctx
->opcode
);
4813 r4
= MASK_OP_RCRW_D(ctx
->opcode
);
4814 width
= MASK_OP_RCRW_WIDTH(ctx
->opcode
);
4815 const4
= MASK_OP_RCRW_CONST4(ctx
->opcode
);
4817 temp
= tcg_temp_new();
4818 temp2
= tcg_temp_new();
4821 case OPC2_32_RCRW_IMASK
:
4822 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r4
], 0x1f);
4823 tcg_gen_movi_tl(temp2
, (1 << width
) - 1);
4824 tcg_gen_shl_tl(cpu_gpr_d
[r3
+ 1], temp2
, temp
);
4825 tcg_gen_movi_tl(temp2
, const4
);
4826 tcg_gen_shl_tl(cpu_gpr_d
[r3
], temp2
, temp
);
4828 case OPC2_32_RCRW_INSERT
:
4829 temp3
= tcg_temp_new();
4831 tcg_gen_movi_tl(temp
, width
);
4832 tcg_gen_movi_tl(temp2
, const4
);
4833 tcg_gen_andi_tl(temp3
, cpu_gpr_d
[r4
], 0x1f);
4834 gen_insert(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], temp2
, temp
, temp3
);
4836 tcg_temp_free(temp3
);
4839 tcg_temp_free(temp
);
4840 tcg_temp_free(temp2
);
4845 static void decode_rcr_cond_select(CPUTriCoreState
*env
, DisasContext
*ctx
)
4853 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
4854 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
4855 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
4856 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
4857 r4
= MASK_OP_RCR_D(ctx
->opcode
);
4860 case OPC2_32_RCR_CADD
:
4861 gen_condi_add(TCG_COND_NE
, cpu_gpr_d
[r1
], const9
, cpu_gpr_d
[r3
],
4864 case OPC2_32_RCR_CADDN
:
4865 gen_condi_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], const9
, cpu_gpr_d
[r3
],
4868 case OPC2_32_RCR_SEL
:
4869 temp
= tcg_const_i32(0);
4870 temp2
= tcg_const_i32(const9
);
4871 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
4872 cpu_gpr_d
[r1
], temp2
);
4873 tcg_temp_free(temp
);
4874 tcg_temp_free(temp2
);
4876 case OPC2_32_RCR_SELN
:
4877 temp
= tcg_const_i32(0);
4878 temp2
= tcg_const_i32(const9
);
4879 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
4880 cpu_gpr_d
[r1
], temp2
);
4881 tcg_temp_free(temp
);
4882 tcg_temp_free(temp2
);
4887 static void decode_rcr_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
4894 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
4895 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
4896 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
4897 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
4898 r4
= MASK_OP_RCR_D(ctx
->opcode
);
4901 case OPC2_32_RCR_MADD_32
:
4902 gen_maddi32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
4904 case OPC2_32_RCR_MADD_64
:
4905 gen_maddi64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4906 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4908 case OPC2_32_RCR_MADDS_32
:
4909 gen_maddsi_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
4911 case OPC2_32_RCR_MADDS_64
:
4912 gen_maddsi_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4913 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4915 case OPC2_32_RCR_MADD_U_64
:
4916 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
4917 gen_maddui64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4918 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4920 case OPC2_32_RCR_MADDS_U_32
:
4921 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
4922 gen_maddsui_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
4924 case OPC2_32_RCR_MADDS_U_64
:
4925 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
4926 gen_maddsui_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4927 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4932 static void decode_rcr_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
4939 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
4940 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
4941 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
4942 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
4943 r4
= MASK_OP_RCR_D(ctx
->opcode
);
4946 case OPC2_32_RCR_MSUB_32
:
4947 gen_msubi32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
4949 case OPC2_32_RCR_MSUB_64
:
4950 gen_msubi64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4951 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4953 case OPC2_32_RCR_MSUBS_32
:
4954 gen_msubsi_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
4956 case OPC2_32_RCR_MSUBS_64
:
4957 gen_msubsi_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4958 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4960 case OPC2_32_RCR_MSUB_U_64
:
4961 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
4962 gen_msubui64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4963 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4965 case OPC2_32_RCR_MSUBS_U_32
:
4966 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
4967 gen_msubsui_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
4969 case OPC2_32_RCR_MSUBS_U_64
:
4970 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
4971 gen_msubsui_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
4972 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
4979 static void decode_rlc_opc(CPUTriCoreState
*env
, DisasContext
*ctx
,
4985 const16
= MASK_OP_RLC_CONST16_SEXT(ctx
->opcode
);
4986 r1
= MASK_OP_RLC_S1(ctx
->opcode
);
4987 r2
= MASK_OP_RLC_D(ctx
->opcode
);
4990 case OPC1_32_RLC_ADDI
:
4991 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const16
);
4993 case OPC1_32_RLC_ADDIH
:
4994 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const16
<< 16);
4996 case OPC1_32_RLC_ADDIH_A
:
4997 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r1
], const16
<< 16);
4999 case OPC1_32_RLC_MFCR
:
5000 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
5001 gen_mfcr(env
, cpu_gpr_d
[r2
], const16
);
5003 case OPC1_32_RLC_MOV
:
5004 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
5006 case OPC1_32_RLC_MOV_64
:
5007 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5008 if ((r2
& 0x1) != 0) {
5009 /* TODO: raise OPD trap */
5011 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
5012 tcg_gen_movi_tl(cpu_gpr_d
[r2
+1], const16
>> 15);
5014 /* TODO: raise illegal opcode trap */
5017 case OPC1_32_RLC_MOV_U
:
5018 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
5019 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
5021 case OPC1_32_RLC_MOV_H
:
5022 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
<< 16);
5024 case OPC1_32_RLC_MOVH_A
:
5025 tcg_gen_movi_tl(cpu_gpr_a
[r2
], const16
<< 16);
5027 case OPC1_32_RLC_MTCR
:
5028 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
5029 gen_mtcr(env
, ctx
, cpu_gpr_d
[r1
], const16
);
5035 static void decode_rr_accumulator(CPUTriCoreState
*env
, DisasContext
*ctx
)
5040 r3
= MASK_OP_RR_D(ctx
->opcode
);
5041 r2
= MASK_OP_RR_S2(ctx
->opcode
);
5042 r1
= MASK_OP_RR_S1(ctx
->opcode
);
5043 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
5046 case OPC2_32_RR_ABS
:
5047 gen_abs(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
5049 case OPC2_32_RR_ABS_B
:
5050 gen_helper_abs_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
5052 case OPC2_32_RR_ABS_H
:
5053 gen_helper_abs_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
5055 case OPC2_32_RR_ABSDIF
:
5056 gen_absdif(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5058 case OPC2_32_RR_ABSDIF_B
:
5059 gen_helper_absdif_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5062 case OPC2_32_RR_ABSDIF_H
:
5063 gen_helper_absdif_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5066 case OPC2_32_RR_ABSDIFS
:
5067 gen_helper_absdif_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5070 case OPC2_32_RR_ABSDIFS_H
:
5071 gen_helper_absdif_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5074 case OPC2_32_RR_ABSS
:
5075 gen_helper_abs_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
5077 case OPC2_32_RR_ABSS_H
:
5078 gen_helper_abs_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
5080 case OPC2_32_RR_ADD
:
5081 gen_add_d(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5083 case OPC2_32_RR_ADD_B
:
5084 gen_helper_add_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5086 case OPC2_32_RR_ADD_H
:
5087 gen_helper_add_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5089 case OPC2_32_RR_ADDC
:
5090 gen_addc_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5092 case OPC2_32_RR_ADDS
:
5093 gen_adds(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5095 case OPC2_32_RR_ADDS_H
:
5096 gen_helper_add_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5099 case OPC2_32_RR_ADDS_HU
:
5100 gen_helper_add_h_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5103 case OPC2_32_RR_ADDS_U
:
5104 gen_helper_add_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5107 case OPC2_32_RR_ADDX
:
5108 gen_add_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5110 case OPC2_32_RR_AND_EQ
:
5111 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5112 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
5114 case OPC2_32_RR_AND_GE
:
5115 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5116 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
5118 case OPC2_32_RR_AND_GE_U
:
5119 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5120 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
5122 case OPC2_32_RR_AND_LT
:
5123 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5124 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
5126 case OPC2_32_RR_AND_LT_U
:
5127 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5128 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
5130 case OPC2_32_RR_AND_NE
:
5131 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5132 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
5135 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5138 case OPC2_32_RR_EQ_B
:
5139 gen_helper_eq_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5141 case OPC2_32_RR_EQ_H
:
5142 gen_helper_eq_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5144 case OPC2_32_RR_EQ_W
:
5145 gen_cond_w(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5147 case OPC2_32_RR_EQANY_B
:
5148 gen_helper_eqany_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5150 case OPC2_32_RR_EQANY_H
:
5151 gen_helper_eqany_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5154 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5157 case OPC2_32_RR_GE_U
:
5158 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5162 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5165 case OPC2_32_RR_LT_U
:
5166 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5169 case OPC2_32_RR_LT_B
:
5170 gen_helper_lt_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5172 case OPC2_32_RR_LT_BU
:
5173 gen_helper_lt_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5175 case OPC2_32_RR_LT_H
:
5176 gen_helper_lt_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5178 case OPC2_32_RR_LT_HU
:
5179 gen_helper_lt_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5181 case OPC2_32_RR_LT_W
:
5182 gen_cond_w(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5184 case OPC2_32_RR_LT_WU
:
5185 gen_cond_w(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5187 case OPC2_32_RR_MAX
:
5188 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5189 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5191 case OPC2_32_RR_MAX_U
:
5192 tcg_gen_movcond_tl(TCG_COND_GTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5193 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5195 case OPC2_32_RR_MAX_B
:
5196 gen_helper_max_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5198 case OPC2_32_RR_MAX_BU
:
5199 gen_helper_max_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5201 case OPC2_32_RR_MAX_H
:
5202 gen_helper_max_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5204 case OPC2_32_RR_MAX_HU
:
5205 gen_helper_max_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5207 case OPC2_32_RR_MIN
:
5208 tcg_gen_movcond_tl(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5209 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5211 case OPC2_32_RR_MIN_U
:
5212 tcg_gen_movcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5213 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5215 case OPC2_32_RR_MIN_B
:
5216 gen_helper_min_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5218 case OPC2_32_RR_MIN_BU
:
5219 gen_helper_min_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5221 case OPC2_32_RR_MIN_H
:
5222 gen_helper_min_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5224 case OPC2_32_RR_MIN_HU
:
5225 gen_helper_min_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5227 case OPC2_32_RR_MOV
:
5228 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
5231 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5234 case OPC2_32_RR_OR_EQ
:
5235 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5236 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
5238 case OPC2_32_RR_OR_GE
:
5239 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5240 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
5242 case OPC2_32_RR_OR_GE_U
:
5243 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5244 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
5246 case OPC2_32_RR_OR_LT
:
5247 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5248 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
5250 case OPC2_32_RR_OR_LT_U
:
5251 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5252 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
5254 case OPC2_32_RR_OR_NE
:
5255 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5256 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
5258 case OPC2_32_RR_SAT_B
:
5259 gen_saturate(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0x7f, -0x80);
5261 case OPC2_32_RR_SAT_BU
:
5262 gen_saturate_u(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0xff);
5264 case OPC2_32_RR_SAT_H
:
5265 gen_saturate(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0x7fff, -0x8000);
5267 case OPC2_32_RR_SAT_HU
:
5268 gen_saturate_u(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0xffff);
5270 case OPC2_32_RR_SH_EQ
:
5271 gen_sh_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5274 case OPC2_32_RR_SH_GE
:
5275 gen_sh_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5278 case OPC2_32_RR_SH_GE_U
:
5279 gen_sh_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5282 case OPC2_32_RR_SH_LT
:
5283 gen_sh_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5286 case OPC2_32_RR_SH_LT_U
:
5287 gen_sh_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5290 case OPC2_32_RR_SH_NE
:
5291 gen_sh_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5294 case OPC2_32_RR_SUB
:
5295 gen_sub_d(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5297 case OPC2_32_RR_SUB_B
:
5298 gen_helper_sub_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5300 case OPC2_32_RR_SUB_H
:
5301 gen_helper_sub_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5303 case OPC2_32_RR_SUBC
:
5304 gen_subc_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5306 case OPC2_32_RR_SUBS
:
5307 gen_subs(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5309 case OPC2_32_RR_SUBS_U
:
5310 gen_subsu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5312 case OPC2_32_RR_SUBS_H
:
5313 gen_helper_sub_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5316 case OPC2_32_RR_SUBS_HU
:
5317 gen_helper_sub_h_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5320 case OPC2_32_RR_SUBX
:
5321 gen_sub_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5323 case OPC2_32_RR_XOR_EQ
:
5324 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5325 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
5327 case OPC2_32_RR_XOR_GE
:
5328 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5329 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
5331 case OPC2_32_RR_XOR_GE_U
:
5332 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5333 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
5335 case OPC2_32_RR_XOR_LT
:
5336 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5337 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
5339 case OPC2_32_RR_XOR_LT_U
:
5340 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5341 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
5343 case OPC2_32_RR_XOR_NE
:
5344 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
5345 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
5350 static void decode_rr_logical_shift(CPUTriCoreState
*env
, DisasContext
*ctx
)
5356 r3
= MASK_OP_RR_D(ctx
->opcode
);
5357 r2
= MASK_OP_RR_S2(ctx
->opcode
);
5358 r1
= MASK_OP_RR_S1(ctx
->opcode
);
5360 temp
= tcg_temp_new();
5361 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
5364 case OPC2_32_RR_AND
:
5365 tcg_gen_and_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5367 case OPC2_32_RR_ANDN
:
5368 tcg_gen_andc_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5370 case OPC2_32_RR_CLO
:
5371 gen_helper_clo(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5373 case OPC2_32_RR_CLO_H
:
5374 gen_helper_clo_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5376 case OPC2_32_RR_CLS
:
5377 gen_helper_cls(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5379 case OPC2_32_RR_CLS_H
:
5380 gen_helper_cls_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5382 case OPC2_32_RR_CLZ
:
5383 gen_helper_clz(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5385 case OPC2_32_RR_CLZ_H
:
5386 gen_helper_clz_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5388 case OPC2_32_RR_NAND
:
5389 tcg_gen_nand_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5391 case OPC2_32_RR_NOR
:
5392 tcg_gen_nor_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5395 tcg_gen_or_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5397 case OPC2_32_RR_ORN
:
5398 tcg_gen_orc_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5401 gen_helper_sh(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5403 case OPC2_32_RR_SH_H
:
5404 gen_helper_sh_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5406 case OPC2_32_RR_SHA
:
5407 gen_helper_sha(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5409 case OPC2_32_RR_SHA_H
:
5410 gen_helper_sha_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5412 case OPC2_32_RR_SHAS
:
5413 gen_shas(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5415 case OPC2_32_RR_XNOR
:
5416 tcg_gen_eqv_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5418 case OPC2_32_RR_XOR
:
5419 tcg_gen_xor_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5422 tcg_temp_free(temp
);
5425 static void decode_rr_address(CPUTriCoreState
*env
, DisasContext
*ctx
)
5431 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
5432 r3
= MASK_OP_RR_D(ctx
->opcode
);
5433 r2
= MASK_OP_RR_S2(ctx
->opcode
);
5434 r1
= MASK_OP_RR_S1(ctx
->opcode
);
5435 n
= MASK_OP_RR_N(ctx
->opcode
);
5438 case OPC2_32_RR_ADD_A
:
5439 tcg_gen_add_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
5441 case OPC2_32_RR_ADDSC_A
:
5442 temp
= tcg_temp_new();
5443 tcg_gen_shli_tl(temp
, cpu_gpr_d
[r1
], n
);
5444 tcg_gen_add_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r2
], temp
);
5445 tcg_temp_free(temp
);
5447 case OPC2_32_RR_ADDSC_AT
:
5448 temp
= tcg_temp_new();
5449 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 3);
5450 tcg_gen_add_tl(temp
, cpu_gpr_a
[r2
], temp
);
5451 tcg_gen_andi_tl(cpu_gpr_a
[r3
], temp
, 0xFFFFFFFC);
5452 tcg_temp_free(temp
);
5454 case OPC2_32_RR_EQ_A
:
5455 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
5458 case OPC2_32_RR_EQZ
:
5459 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
], 0);
5461 case OPC2_32_RR_GE_A
:
5462 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
5465 case OPC2_32_RR_LT_A
:
5466 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
5469 case OPC2_32_RR_MOV_A
:
5470 tcg_gen_mov_tl(cpu_gpr_a
[r3
], cpu_gpr_d
[r2
]);
5472 case OPC2_32_RR_MOV_AA
:
5473 tcg_gen_mov_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r2
]);
5475 case OPC2_32_RR_MOV_D
:
5476 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_a
[r2
]);
5478 case OPC2_32_RR_NE_A
:
5479 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
5482 case OPC2_32_RR_NEZ_A
:
5483 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
], 0);
5485 case OPC2_32_RR_SUB_A
:
5486 tcg_gen_sub_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
5491 static void decode_rr_idirect(CPUTriCoreState
*env
, DisasContext
*ctx
)
5496 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
5497 r1
= MASK_OP_RR_S1(ctx
->opcode
);
5501 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
5503 case OPC2_32_RR_JLI
:
5504 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
5505 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
5507 case OPC2_32_RR_CALLI
:
5508 gen_helper_1arg(call
, ctx
->next_pc
);
5509 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
5513 ctx
->bstate
= BS_BRANCH
;
5516 static void decode_rr_divide(CPUTriCoreState
*env
, DisasContext
*ctx
)
5523 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
5524 r3
= MASK_OP_RR_D(ctx
->opcode
);
5525 r2
= MASK_OP_RR_S2(ctx
->opcode
);
5526 r1
= MASK_OP_RR_S1(ctx
->opcode
);
5529 case OPC2_32_RR_BMERGE
:
5530 gen_helper_bmerge(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5532 case OPC2_32_RR_BSPLIT
:
5533 gen_bsplit(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
5535 case OPC2_32_RR_DVINIT_B
:
5536 gen_dvinit_b(env
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
5539 case OPC2_32_RR_DVINIT_BU
:
5540 temp
= tcg_temp_new();
5541 temp2
= tcg_temp_new();
5543 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
5544 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
5545 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
5546 tcg_gen_neg_tl(temp
, cpu_gpr_d
[r3
+1]);
5547 /* use cpu_PSW_AV to compare against 0 */
5548 tcg_gen_movcond_tl(TCG_COND_LT
, temp
, cpu_gpr_d
[r3
+1], cpu_PSW_AV
,
5549 temp
, cpu_gpr_d
[r3
+1]);
5550 tcg_gen_neg_tl(temp2
, cpu_gpr_d
[r2
]);
5551 tcg_gen_movcond_tl(TCG_COND_LT
, temp2
, cpu_gpr_d
[r2
], cpu_PSW_AV
,
5552 temp2
, cpu_gpr_d
[r2
]);
5553 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_PSW_V
, temp
, temp2
);
5555 /* overflow = (D[b] == 0) */
5556 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
5558 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
5560 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
5562 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 8);
5563 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 24);
5564 tcg_gen_mov_tl(cpu_gpr_d
[r3
+1], temp
);
5566 tcg_temp_free(temp
);
5567 tcg_temp_free(temp2
);
5569 case OPC2_32_RR_DVINIT_H
:
5570 gen_dvinit_h(env
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
5573 case OPC2_32_RR_DVINIT_HU
:
5574 temp
= tcg_temp_new();
5575 temp2
= tcg_temp_new();
5577 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
5578 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
5579 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
5580 tcg_gen_neg_tl(temp
, cpu_gpr_d
[r3
+1]);
5581 /* use cpu_PSW_AV to compare against 0 */
5582 tcg_gen_movcond_tl(TCG_COND_LT
, temp
, cpu_gpr_d
[r3
+1], cpu_PSW_AV
,
5583 temp
, cpu_gpr_d
[r3
+1]);
5584 tcg_gen_neg_tl(temp2
, cpu_gpr_d
[r2
]);
5585 tcg_gen_movcond_tl(TCG_COND_LT
, temp2
, cpu_gpr_d
[r2
], cpu_PSW_AV
,
5586 temp2
, cpu_gpr_d
[r2
]);
5587 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_PSW_V
, temp
, temp2
);
5589 /* overflow = (D[b] == 0) */
5590 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
5592 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
5594 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
5596 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
5597 tcg_gen_shri_tl(cpu_gpr_d
[r3
+1], temp
, 16);
5598 tcg_gen_shli_tl(cpu_gpr_d
[r3
], temp
, 16);
5599 tcg_temp_free(temp
);
5600 tcg_temp_free(temp2
);
5602 case OPC2_32_RR_DVINIT
:
5603 temp
= tcg_temp_new();
5604 temp2
= tcg_temp_new();
5605 /* overflow = ((D[b] == 0) ||
5606 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
5607 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, cpu_gpr_d
[r2
], 0xffffffff);
5608 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[r1
], 0x80000000);
5609 tcg_gen_and_tl(temp
, temp
, temp2
);
5610 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[r2
], 0);
5611 tcg_gen_or_tl(cpu_PSW_V
, temp
, temp2
);
5612 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
5614 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
5616 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
5618 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5619 /* sign extend to high reg */
5620 tcg_gen_sari_tl(cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], 31);
5621 tcg_temp_free(temp
);
5622 tcg_temp_free(temp2
);
5624 case OPC2_32_RR_DVINIT_U
:
5625 /* overflow = (D[b] == 0) */
5626 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
5627 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
5629 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
5631 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
5633 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5634 /* zero extend to high reg*/
5635 tcg_gen_movi_tl(cpu_gpr_d
[r3
+1], 0);
5637 case OPC2_32_RR_PARITY
:
5638 gen_helper_parity(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5640 case OPC2_32_RR_UNPACK
:
5641 gen_unpack(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
5647 static void decode_rr1_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
5655 r1
= MASK_OP_RR1_S1(ctx
->opcode
);
5656 r2
= MASK_OP_RR1_S2(ctx
->opcode
);
5657 r3
= MASK_OP_RR1_D(ctx
->opcode
);
5658 n
= tcg_const_i32(MASK_OP_RR1_N(ctx
->opcode
));
5659 op2
= MASK_OP_RR1_OP2(ctx
->opcode
);
5662 case OPC2_32_RR1_MUL_H_32_LL
:
5663 temp64
= tcg_temp_new_i64();
5664 GEN_HELPER_LL(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5665 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5666 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
5667 tcg_temp_free_i64(temp64
);
5669 case OPC2_32_RR1_MUL_H_32_LU
:
5670 temp64
= tcg_temp_new_i64();
5671 GEN_HELPER_LU(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5672 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5673 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
5674 tcg_temp_free_i64(temp64
);
5676 case OPC2_32_RR1_MUL_H_32_UL
:
5677 temp64
= tcg_temp_new_i64();
5678 GEN_HELPER_UL(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5679 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5680 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
5681 tcg_temp_free_i64(temp64
);
5683 case OPC2_32_RR1_MUL_H_32_UU
:
5684 temp64
= tcg_temp_new_i64();
5685 GEN_HELPER_UU(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5686 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5687 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
5688 tcg_temp_free_i64(temp64
);
5690 case OPC2_32_RR1_MULM_H_64_LL
:
5691 temp64
= tcg_temp_new_i64();
5692 GEN_HELPER_LL(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5693 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5695 tcg_gen_movi_tl(cpu_PSW_V
, 0);
5697 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
5698 tcg_temp_free_i64(temp64
);
5700 case OPC2_32_RR1_MULM_H_64_LU
:
5701 temp64
= tcg_temp_new_i64();
5702 GEN_HELPER_LU(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5703 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5705 tcg_gen_movi_tl(cpu_PSW_V
, 0);
5707 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
5708 tcg_temp_free_i64(temp64
);
5710 case OPC2_32_RR1_MULM_H_64_UL
:
5711 temp64
= tcg_temp_new_i64();
5712 GEN_HELPER_UL(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5713 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5715 tcg_gen_movi_tl(cpu_PSW_V
, 0);
5717 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
5718 tcg_temp_free_i64(temp64
);
5720 case OPC2_32_RR1_MULM_H_64_UU
:
5721 temp64
= tcg_temp_new_i64();
5722 GEN_HELPER_UU(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5723 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
5725 tcg_gen_movi_tl(cpu_PSW_V
, 0);
5727 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
5728 tcg_temp_free_i64(temp64
);
5731 case OPC2_32_RR1_MULR_H_16_LL
:
5732 GEN_HELPER_LL(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5733 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
5735 case OPC2_32_RR1_MULR_H_16_LU
:
5736 GEN_HELPER_LU(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5737 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
5739 case OPC2_32_RR1_MULR_H_16_UL
:
5740 GEN_HELPER_UL(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5741 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
5743 case OPC2_32_RR1_MULR_H_16_UU
:
5744 GEN_HELPER_UU(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
5745 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
5751 static void decode_rr1_mulq(CPUTriCoreState
*env
, DisasContext
*ctx
)
5759 r1
= MASK_OP_RR1_S1(ctx
->opcode
);
5760 r2
= MASK_OP_RR1_S2(ctx
->opcode
);
5761 r3
= MASK_OP_RR1_D(ctx
->opcode
);
5762 n
= MASK_OP_RR1_N(ctx
->opcode
);
5763 op2
= MASK_OP_RR1_OP2(ctx
->opcode
);
5765 temp
= tcg_temp_new();
5766 temp2
= tcg_temp_new();
5769 case OPC2_32_RR1_MUL_Q_32
:
5770 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 32);
5772 case OPC2_32_RR1_MUL_Q_64
:
5773 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
5776 case OPC2_32_RR1_MUL_Q_32_L
:
5777 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
5778 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], temp
, n
, 16);
5780 case OPC2_32_RR1_MUL_Q_64_L
:
5781 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
5782 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
, n
, 0);
5784 case OPC2_32_RR1_MUL_Q_32_U
:
5785 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
5786 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], temp
, n
, 16);
5788 case OPC2_32_RR1_MUL_Q_64_U
:
5789 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
5790 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
, n
, 0);
5792 case OPC2_32_RR1_MUL_Q_32_LL
:
5793 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
5794 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
5795 gen_mul_q_16(cpu_gpr_d
[r3
], temp
, temp2
, n
);
5797 case OPC2_32_RR1_MUL_Q_32_UU
:
5798 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
5799 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
5800 gen_mul_q_16(cpu_gpr_d
[r3
], temp
, temp2
, n
);
5802 case OPC2_32_RR1_MULR_Q_32_L
:
5803 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
5804 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
5805 gen_mulr_q(cpu_gpr_d
[r3
], temp
, temp2
, n
);
5807 case OPC2_32_RR1_MULR_Q_32_U
:
5808 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
5809 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
5810 gen_mulr_q(cpu_gpr_d
[r3
], temp
, temp2
, n
);
5813 tcg_temp_free(temp
);
5814 tcg_temp_free(temp2
);
5818 static void decode_rr2_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
5823 op2
= MASK_OP_RR2_OP2(ctx
->opcode
);
5824 r1
= MASK_OP_RR2_S1(ctx
->opcode
);
5825 r2
= MASK_OP_RR2_S2(ctx
->opcode
);
5826 r3
= MASK_OP_RR2_D(ctx
->opcode
);
5828 case OPC2_32_RR2_MUL_32
:
5829 gen_mul_i32s(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5831 case OPC2_32_RR2_MUL_64
:
5832 gen_mul_i64s(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
5835 case OPC2_32_RR2_MULS_32
:
5836 gen_helper_mul_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5839 case OPC2_32_RR2_MUL_U_64
:
5840 gen_mul_i64u(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
5843 case OPC2_32_RR2_MULS_U_32
:
5844 gen_helper_mul_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
5851 static void decode_rrpw_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
5857 op2
= MASK_OP_RRPW_OP2(ctx
->opcode
);
5858 r1
= MASK_OP_RRPW_S1(ctx
->opcode
);
5859 r2
= MASK_OP_RRPW_S2(ctx
->opcode
);
5860 r3
= MASK_OP_RRPW_D(ctx
->opcode
);
5861 pos
= MASK_OP_RRPW_POS(ctx
->opcode
);
5862 width
= MASK_OP_RRPW_WIDTH(ctx
->opcode
);
5865 case OPC2_32_RRPW_EXTR
:
5866 if (pos
+ width
<= 31) {
5867 /* optimize special cases */
5868 if ((pos
== 0) && (width
== 8)) {
5869 tcg_gen_ext8s_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5870 } else if ((pos
== 0) && (width
== 16)) {
5871 tcg_gen_ext16s_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
5873 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 32 - pos
- width
);
5874 tcg_gen_sari_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 32 - width
);
5878 case OPC2_32_RRPW_EXTR_U
:
5880 tcg_gen_movi_tl(cpu_gpr_d
[r3
], 0);
5882 tcg_gen_shri_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], pos
);
5883 tcg_gen_andi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], ~0u >> (32-width
));
5886 case OPC2_32_RRPW_IMASK
:
5887 if (pos
+ width
<= 31) {
5888 tcg_gen_movi_tl(cpu_gpr_d
[r3
+1], ((1u << width
) - 1) << pos
);
5889 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
], pos
);
5892 case OPC2_32_RRPW_INSERT
:
5893 if (pos
+ width
<= 31) {
5894 tcg_gen_deposit_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
5902 static void decode_rrr_cond_select(CPUTriCoreState
*env
, DisasContext
*ctx
)
5908 op2
= MASK_OP_RRR_OP2(ctx
->opcode
);
5909 r1
= MASK_OP_RRR_S1(ctx
->opcode
);
5910 r2
= MASK_OP_RRR_S2(ctx
->opcode
);
5911 r3
= MASK_OP_RRR_S3(ctx
->opcode
);
5912 r4
= MASK_OP_RRR_D(ctx
->opcode
);
5915 case OPC2_32_RRR_CADD
:
5916 gen_cond_add(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
5917 cpu_gpr_d
[r4
], cpu_gpr_d
[r3
]);
5919 case OPC2_32_RRR_CADDN
:
5920 gen_cond_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
5923 case OPC2_32_RRR_CSUB
:
5924 gen_cond_sub(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
5927 case OPC2_32_RRR_CSUBN
:
5928 gen_cond_sub(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
5931 case OPC2_32_RRR_SEL
:
5932 temp
= tcg_const_i32(0);
5933 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
5934 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5935 tcg_temp_free(temp
);
5937 case OPC2_32_RRR_SELN
:
5938 temp
= tcg_const_i32(0);
5939 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
5940 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
5941 tcg_temp_free(temp
);
5946 static void decode_rrr_divide(CPUTriCoreState
*env
, DisasContext
*ctx
)
5952 op2
= MASK_OP_RRR_OP2(ctx
->opcode
);
5953 r1
= MASK_OP_RRR_S1(ctx
->opcode
);
5954 r2
= MASK_OP_RRR_S2(ctx
->opcode
);
5955 r3
= MASK_OP_RRR_S3(ctx
->opcode
);
5956 r4
= MASK_OP_RRR_D(ctx
->opcode
);
5959 case OPC2_32_RRR_DVADJ
:
5960 GEN_HELPER_RRR(dvadj
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5961 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5963 case OPC2_32_RRR_DVSTEP
:
5964 GEN_HELPER_RRR(dvstep
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5965 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5967 case OPC2_32_RRR_DVSTEP_U
:
5968 GEN_HELPER_RRR(dvstep_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5969 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5971 case OPC2_32_RRR_IXMAX
:
5972 GEN_HELPER_RRR(ixmax
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5973 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5975 case OPC2_32_RRR_IXMAX_U
:
5976 GEN_HELPER_RRR(ixmax_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5977 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5979 case OPC2_32_RRR_IXMIN
:
5980 GEN_HELPER_RRR(ixmin
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5981 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5983 case OPC2_32_RRR_IXMIN_U
:
5984 GEN_HELPER_RRR(ixmin_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
5985 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
5987 case OPC2_32_RRR_PACK
:
5988 gen_helper_pack(cpu_gpr_d
[r4
], cpu_PSW_C
, cpu_gpr_d
[r3
],
5989 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
5995 static void decode_rrr2_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
5998 uint32_t r1
, r2
, r3
, r4
;
6000 op2
= MASK_OP_RRR2_OP2(ctx
->opcode
);
6001 r1
= MASK_OP_RRR2_S1(ctx
->opcode
);
6002 r2
= MASK_OP_RRR2_S2(ctx
->opcode
);
6003 r3
= MASK_OP_RRR2_S3(ctx
->opcode
);
6004 r4
= MASK_OP_RRR2_D(ctx
->opcode
);
6006 case OPC2_32_RRR2_MADD_32
:
6007 gen_madd32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
],
6010 case OPC2_32_RRR2_MADD_64
:
6011 gen_madd64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6012 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6014 case OPC2_32_RRR2_MADDS_32
:
6015 gen_helper_madd32_ssov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
6016 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6018 case OPC2_32_RRR2_MADDS_64
:
6019 gen_madds_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6020 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6022 case OPC2_32_RRR2_MADD_U_64
:
6023 gen_maddu64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6024 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6026 case OPC2_32_RRR2_MADDS_U_32
:
6027 gen_helper_madd32_suov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
6028 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6030 case OPC2_32_RRR2_MADDS_U_64
:
6031 gen_maddsu_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6032 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6037 static void decode_rrr2_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
6040 uint32_t r1
, r2
, r3
, r4
;
6042 op2
= MASK_OP_RRR2_OP2(ctx
->opcode
);
6043 r1
= MASK_OP_RRR2_S1(ctx
->opcode
);
6044 r2
= MASK_OP_RRR2_S2(ctx
->opcode
);
6045 r3
= MASK_OP_RRR2_S3(ctx
->opcode
);
6046 r4
= MASK_OP_RRR2_D(ctx
->opcode
);
6049 case OPC2_32_RRR2_MSUB_32
:
6050 gen_msub32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
],
6053 case OPC2_32_RRR2_MSUB_64
:
6054 gen_msub64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6055 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6057 case OPC2_32_RRR2_MSUBS_32
:
6058 gen_helper_msub32_ssov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
6059 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6061 case OPC2_32_RRR2_MSUBS_64
:
6062 gen_msubs_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6063 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6065 case OPC2_32_RRR2_MSUB_U_64
:
6066 gen_msubu64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6067 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6069 case OPC2_32_RRR2_MSUBS_U_32
:
6070 gen_helper_msub32_suov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
6071 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6073 case OPC2_32_RRR2_MSUBS_U_64
:
6074 gen_msubsu_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
6075 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
6081 static void decode_rrr1_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
6084 uint32_t r1
, r2
, r3
, r4
, n
;
6086 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
6087 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
6088 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
6089 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
6090 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
6091 n
= MASK_OP_RRR1_N(ctx
->opcode
);
6094 case OPC2_32_RRR1_MADD_H_LL
:
6095 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6096 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
6098 case OPC2_32_RRR1_MADD_H_LU
:
6099 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6100 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
6102 case OPC2_32_RRR1_MADD_H_UL
:
6103 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6104 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
6106 case OPC2_32_RRR1_MADD_H_UU
:
6107 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6108 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
6110 case OPC2_32_RRR1_MADDS_H_LL
:
6111 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6112 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
6114 case OPC2_32_RRR1_MADDS_H_LU
:
6115 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6116 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
6118 case OPC2_32_RRR1_MADDS_H_UL
:
6119 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6120 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
6122 case OPC2_32_RRR1_MADDS_H_UU
:
6123 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6124 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
6126 case OPC2_32_RRR1_MADDM_H_LL
:
6127 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6128 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
6130 case OPC2_32_RRR1_MADDM_H_LU
:
6131 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6132 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
6134 case OPC2_32_RRR1_MADDM_H_UL
:
6135 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6136 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
6138 case OPC2_32_RRR1_MADDM_H_UU
:
6139 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6140 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
6142 case OPC2_32_RRR1_MADDMS_H_LL
:
6143 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6144 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
6146 case OPC2_32_RRR1_MADDMS_H_LU
:
6147 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6148 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
6150 case OPC2_32_RRR1_MADDMS_H_UL
:
6151 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6152 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
6154 case OPC2_32_RRR1_MADDMS_H_UU
:
6155 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6156 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
6158 case OPC2_32_RRR1_MADDR_H_LL
:
6159 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6160 cpu_gpr_d
[r2
], n
, MODE_LL
);
6162 case OPC2_32_RRR1_MADDR_H_LU
:
6163 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6164 cpu_gpr_d
[r2
], n
, MODE_LU
);
6166 case OPC2_32_RRR1_MADDR_H_UL
:
6167 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6168 cpu_gpr_d
[r2
], n
, MODE_UL
);
6170 case OPC2_32_RRR1_MADDR_H_UU
:
6171 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6172 cpu_gpr_d
[r2
], n
, MODE_UU
);
6174 case OPC2_32_RRR1_MADDRS_H_LL
:
6175 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6176 cpu_gpr_d
[r2
], n
, MODE_LL
);
6178 case OPC2_32_RRR1_MADDRS_H_LU
:
6179 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6180 cpu_gpr_d
[r2
], n
, MODE_LU
);
6182 case OPC2_32_RRR1_MADDRS_H_UL
:
6183 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6184 cpu_gpr_d
[r2
], n
, MODE_UL
);
6186 case OPC2_32_RRR1_MADDRS_H_UU
:
6187 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6188 cpu_gpr_d
[r2
], n
, MODE_UU
);
6193 static void decode_rrr1_maddq_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
6196 uint32_t r1
, r2
, r3
, r4
, n
;
6199 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
6200 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
6201 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
6202 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
6203 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
6204 n
= MASK_OP_RRR1_N(ctx
->opcode
);
6206 temp
= tcg_const_i32(n
);
6207 temp2
= tcg_temp_new();
6210 case OPC2_32_RRR1_MADD_Q_32
:
6211 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6212 cpu_gpr_d
[r2
], n
, 32, env
);
6214 case OPC2_32_RRR1_MADD_Q_64
:
6215 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6216 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6219 case OPC2_32_RRR1_MADD_Q_32_L
:
6220 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6221 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6224 case OPC2_32_RRR1_MADD_Q_64_L
:
6225 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6226 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6227 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
6230 case OPC2_32_RRR1_MADD_Q_32_U
:
6231 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6232 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6235 case OPC2_32_RRR1_MADD_Q_64_U
:
6236 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6237 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6238 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
6241 case OPC2_32_RRR1_MADD_Q_32_LL
:
6242 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6243 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6244 gen_m16add32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6246 case OPC2_32_RRR1_MADD_Q_64_LL
:
6247 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6248 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6249 gen_m16add64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6250 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
6252 case OPC2_32_RRR1_MADD_Q_32_UU
:
6253 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6254 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6255 gen_m16add32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6257 case OPC2_32_RRR1_MADD_Q_64_UU
:
6258 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6259 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6260 gen_m16add64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6261 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
6263 case OPC2_32_RRR1_MADDS_Q_32
:
6264 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6265 cpu_gpr_d
[r2
], n
, 32);
6267 case OPC2_32_RRR1_MADDS_Q_64
:
6268 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6269 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6272 case OPC2_32_RRR1_MADDS_Q_32_L
:
6273 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6274 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6277 case OPC2_32_RRR1_MADDS_Q_64_L
:
6278 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6279 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6280 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
6283 case OPC2_32_RRR1_MADDS_Q_32_U
:
6284 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6285 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6288 case OPC2_32_RRR1_MADDS_Q_64_U
:
6289 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6290 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6291 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
6294 case OPC2_32_RRR1_MADDS_Q_32_LL
:
6295 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6296 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6297 gen_m16adds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6299 case OPC2_32_RRR1_MADDS_Q_64_LL
:
6300 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6301 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6302 gen_m16adds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6303 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
6305 case OPC2_32_RRR1_MADDS_Q_32_UU
:
6306 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6307 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6308 gen_m16adds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6310 case OPC2_32_RRR1_MADDS_Q_64_UU
:
6311 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6312 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6313 gen_m16adds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6314 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
6316 case OPC2_32_RRR1_MADDR_H_64_UL
:
6317 gen_maddr64_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
6318 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
6320 case OPC2_32_RRR1_MADDRS_H_64_UL
:
6321 gen_maddr64s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
6322 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
6324 case OPC2_32_RRR1_MADDR_Q_32_LL
:
6325 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6326 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6327 gen_maddr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6329 case OPC2_32_RRR1_MADDR_Q_32_UU
:
6330 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6331 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6332 gen_maddr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6334 case OPC2_32_RRR1_MADDRS_Q_32_LL
:
6335 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6336 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6337 gen_maddrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6339 case OPC2_32_RRR1_MADDRS_Q_32_UU
:
6340 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6341 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6342 gen_maddrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
6345 tcg_temp_free(temp
);
6346 tcg_temp_free(temp2
);
6349 static void decode_rrr1_maddsu_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
6352 uint32_t r1
, r2
, r3
, r4
, n
;
6354 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
6355 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
6356 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
6357 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
6358 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
6359 n
= MASK_OP_RRR1_N(ctx
->opcode
);
6362 case OPC2_32_RRR1_MADDSU_H_32_LL
:
6363 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6364 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
6366 case OPC2_32_RRR1_MADDSU_H_32_LU
:
6367 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6368 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
6370 case OPC2_32_RRR1_MADDSU_H_32_UL
:
6371 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6372 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
6374 case OPC2_32_RRR1_MADDSU_H_32_UU
:
6375 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6376 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
6378 case OPC2_32_RRR1_MADDSUS_H_32_LL
:
6379 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6380 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6383 case OPC2_32_RRR1_MADDSUS_H_32_LU
:
6384 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6385 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6388 case OPC2_32_RRR1_MADDSUS_H_32_UL
:
6389 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6390 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6393 case OPC2_32_RRR1_MADDSUS_H_32_UU
:
6394 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6395 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6398 case OPC2_32_RRR1_MADDSUM_H_64_LL
:
6399 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6400 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6403 case OPC2_32_RRR1_MADDSUM_H_64_LU
:
6404 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6405 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6408 case OPC2_32_RRR1_MADDSUM_H_64_UL
:
6409 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6410 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6413 case OPC2_32_RRR1_MADDSUM_H_64_UU
:
6414 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6415 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6418 case OPC2_32_RRR1_MADDSUMS_H_64_LL
:
6419 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6420 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6423 case OPC2_32_RRR1_MADDSUMS_H_64_LU
:
6424 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6425 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6428 case OPC2_32_RRR1_MADDSUMS_H_64_UL
:
6429 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6430 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6433 case OPC2_32_RRR1_MADDSUMS_H_64_UU
:
6434 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
6435 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6438 case OPC2_32_RRR1_MADDSUR_H_16_LL
:
6439 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6440 cpu_gpr_d
[r2
], n
, MODE_LL
);
6442 case OPC2_32_RRR1_MADDSUR_H_16_LU
:
6443 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6444 cpu_gpr_d
[r2
], n
, MODE_LU
);
6446 case OPC2_32_RRR1_MADDSUR_H_16_UL
:
6447 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6448 cpu_gpr_d
[r2
], n
, MODE_UL
);
6450 case OPC2_32_RRR1_MADDSUR_H_16_UU
:
6451 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6452 cpu_gpr_d
[r2
], n
, MODE_UU
);
6454 case OPC2_32_RRR1_MADDSURS_H_16_LL
:
6455 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6456 cpu_gpr_d
[r2
], n
, MODE_LL
);
6458 case OPC2_32_RRR1_MADDSURS_H_16_LU
:
6459 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6460 cpu_gpr_d
[r2
], n
, MODE_LU
);
6462 case OPC2_32_RRR1_MADDSURS_H_16_UL
:
6463 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6464 cpu_gpr_d
[r2
], n
, MODE_UL
);
6466 case OPC2_32_RRR1_MADDSURS_H_16_UU
:
6467 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6468 cpu_gpr_d
[r2
], n
, MODE_UU
);
6473 static void decode_32Bit_opc(CPUTriCoreState
*env
, DisasContext
*ctx
)
6477 int32_t address
, const16
;
6480 TCGv temp
, temp2
, temp3
;
6482 op1
= MASK_OP_MAJOR(ctx
->opcode
);
6484 /* handle JNZ.T opcode only being 7 bit long */
6485 if (unlikely((op1
& 0x7f) == OPCM_32_BRN_JTT
)) {
6486 op1
= OPCM_32_BRN_JTT
;
6491 case OPCM_32_ABS_LDW
:
6492 decode_abs_ldw(env
, ctx
);
6494 case OPCM_32_ABS_LDB
:
6495 decode_abs_ldb(env
, ctx
);
6497 case OPCM_32_ABS_LDMST_SWAP
:
6498 decode_abs_ldst_swap(env
, ctx
);
6500 case OPCM_32_ABS_LDST_CONTEXT
:
6501 decode_abs_ldst_context(env
, ctx
);
6503 case OPCM_32_ABS_STORE
:
6504 decode_abs_store(env
, ctx
);
6506 case OPCM_32_ABS_STOREB_H
:
6507 decode_abs_storeb_h(env
, ctx
);
6509 case OPC1_32_ABS_STOREQ
:
6510 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
6511 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
6512 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
6513 temp2
= tcg_temp_new();
6515 tcg_gen_shri_tl(temp2
, cpu_gpr_d
[r1
], 16);
6516 tcg_gen_qemu_st_tl(temp2
, temp
, ctx
->mem_idx
, MO_LEUW
);
6518 tcg_temp_free(temp2
);
6519 tcg_temp_free(temp
);
6521 case OPC1_32_ABS_LD_Q
:
6522 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
6523 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
6524 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
6526 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
6527 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
6529 tcg_temp_free(temp
);
6531 case OPC1_32_ABS_LEA
:
6532 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
6533 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
6534 tcg_gen_movi_tl(cpu_gpr_a
[r1
], EA_ABS_FORMAT(address
));
6537 case OPC1_32_ABSB_ST_T
:
6538 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
6539 b
= MASK_OP_ABSB_B(ctx
->opcode
);
6540 bpos
= MASK_OP_ABSB_BPOS(ctx
->opcode
);
6542 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
6543 temp2
= tcg_temp_new();
6545 tcg_gen_qemu_ld_tl(temp2
, temp
, ctx
->mem_idx
, MO_UB
);
6546 tcg_gen_andi_tl(temp2
, temp2
, ~(0x1u
<< bpos
));
6547 tcg_gen_ori_tl(temp2
, temp2
, (b
<< bpos
));
6548 tcg_gen_qemu_st_tl(temp2
, temp
, ctx
->mem_idx
, MO_UB
);
6550 tcg_temp_free(temp
);
6551 tcg_temp_free(temp2
);
6554 case OPC1_32_B_CALL
:
6555 case OPC1_32_B_CALLA
:
6560 address
= MASK_OP_B_DISP24_SEXT(ctx
->opcode
);
6561 gen_compute_branch(ctx
, op1
, 0, 0, 0, address
);
6564 case OPCM_32_BIT_ANDACC
:
6565 decode_bit_andacc(env
, ctx
);
6567 case OPCM_32_BIT_LOGICAL_T1
:
6568 decode_bit_logical_t(env
, ctx
);
6570 case OPCM_32_BIT_INSERT
:
6571 decode_bit_insert(env
, ctx
);
6573 case OPCM_32_BIT_LOGICAL_T2
:
6574 decode_bit_logical_t2(env
, ctx
);
6576 case OPCM_32_BIT_ORAND
:
6577 decode_bit_orand(env
, ctx
);
6579 case OPCM_32_BIT_SH_LOGIC1
:
6580 decode_bit_sh_logic1(env
, ctx
);
6582 case OPCM_32_BIT_SH_LOGIC2
:
6583 decode_bit_sh_logic2(env
, ctx
);
6586 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE
:
6587 decode_bo_addrmode_post_pre_base(env
, ctx
);
6589 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR
:
6590 decode_bo_addrmode_bitreverse_circular(env
, ctx
);
6592 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE
:
6593 decode_bo_addrmode_ld_post_pre_base(env
, ctx
);
6595 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR
:
6596 decode_bo_addrmode_ld_bitreverse_circular(env
, ctx
);
6598 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE
:
6599 decode_bo_addrmode_stctx_post_pre_base(env
, ctx
);
6601 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR
:
6602 decode_bo_addrmode_ldmst_bitreverse_circular(env
, ctx
);
6605 case OPC1_32_BOL_LD_A_LONGOFF
:
6606 case OPC1_32_BOL_LD_W_LONGOFF
:
6607 case OPC1_32_BOL_LEA_LONGOFF
:
6608 case OPC1_32_BOL_ST_W_LONGOFF
:
6609 case OPC1_32_BOL_ST_A_LONGOFF
:
6610 case OPC1_32_BOL_LD_B_LONGOFF
:
6611 case OPC1_32_BOL_LD_BU_LONGOFF
:
6612 case OPC1_32_BOL_LD_H_LONGOFF
:
6613 case OPC1_32_BOL_LD_HU_LONGOFF
:
6614 case OPC1_32_BOL_ST_B_LONGOFF
:
6615 case OPC1_32_BOL_ST_H_LONGOFF
:
6616 decode_bol_opc(env
, ctx
, op1
);
6619 case OPCM_32_BRC_EQ_NEQ
:
6620 case OPCM_32_BRC_GE
:
6621 case OPCM_32_BRC_JLT
:
6622 case OPCM_32_BRC_JNE
:
6623 const4
= MASK_OP_BRC_CONST4_SEXT(ctx
->opcode
);
6624 address
= MASK_OP_BRC_DISP15_SEXT(ctx
->opcode
);
6625 r1
= MASK_OP_BRC_S1(ctx
->opcode
);
6626 gen_compute_branch(ctx
, op1
, r1
, 0, const4
, address
);
6629 case OPCM_32_BRN_JTT
:
6630 address
= MASK_OP_BRN_DISP15_SEXT(ctx
->opcode
);
6631 r1
= MASK_OP_BRN_S1(ctx
->opcode
);
6632 gen_compute_branch(ctx
, op1
, r1
, 0, 0, address
);
6635 case OPCM_32_BRR_EQ_NEQ
:
6636 case OPCM_32_BRR_ADDR_EQ_NEQ
:
6637 case OPCM_32_BRR_GE
:
6638 case OPCM_32_BRR_JLT
:
6639 case OPCM_32_BRR_JNE
:
6640 case OPCM_32_BRR_JNZ
:
6641 case OPCM_32_BRR_LOOP
:
6642 address
= MASK_OP_BRR_DISP15_SEXT(ctx
->opcode
);
6643 r2
= MASK_OP_BRR_S2(ctx
->opcode
);
6644 r1
= MASK_OP_BRR_S1(ctx
->opcode
);
6645 gen_compute_branch(ctx
, op1
, r1
, r2
, 0, address
);
6648 case OPCM_32_RC_LOGICAL_SHIFT
:
6649 decode_rc_logical_shift(env
, ctx
);
6651 case OPCM_32_RC_ACCUMULATOR
:
6652 decode_rc_accumulator(env
, ctx
);
6654 case OPCM_32_RC_SERVICEROUTINE
:
6655 decode_rc_serviceroutine(env
, ctx
);
6657 case OPCM_32_RC_MUL
:
6658 decode_rc_mul(env
, ctx
);
6661 case OPCM_32_RCPW_MASK_INSERT
:
6662 decode_rcpw_insert(env
, ctx
);
6665 case OPC1_32_RCRR_INSERT
:
6666 r1
= MASK_OP_RCRR_S1(ctx
->opcode
);
6667 r2
= MASK_OP_RCRR_S3(ctx
->opcode
);
6668 r3
= MASK_OP_RCRR_D(ctx
->opcode
);
6669 const16
= MASK_OP_RCRR_CONST4(ctx
->opcode
);
6670 temp
= tcg_const_i32(const16
);
6671 temp2
= tcg_temp_new(); /* width*/
6672 temp3
= tcg_temp_new(); /* pos */
6674 tcg_gen_andi_tl(temp2
, cpu_gpr_d
[r3
+1], 0x1f);
6675 tcg_gen_andi_tl(temp3
, cpu_gpr_d
[r3
], 0x1f);
6677 gen_insert(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
, temp2
, temp3
);
6679 tcg_temp_free(temp
);
6680 tcg_temp_free(temp2
);
6681 tcg_temp_free(temp3
);
6684 case OPCM_32_RCRW_MASK_INSERT
:
6685 decode_rcrw_insert(env
, ctx
);
6688 case OPCM_32_RCR_COND_SELECT
:
6689 decode_rcr_cond_select(env
, ctx
);
6691 case OPCM_32_RCR_MADD
:
6692 decode_rcr_madd(env
, ctx
);
6694 case OPCM_32_RCR_MSUB
:
6695 decode_rcr_msub(env
, ctx
);
6698 case OPC1_32_RLC_ADDI
:
6699 case OPC1_32_RLC_ADDIH
:
6700 case OPC1_32_RLC_ADDIH_A
:
6701 case OPC1_32_RLC_MFCR
:
6702 case OPC1_32_RLC_MOV
:
6703 case OPC1_32_RLC_MOV_64
:
6704 case OPC1_32_RLC_MOV_U
:
6705 case OPC1_32_RLC_MOV_H
:
6706 case OPC1_32_RLC_MOVH_A
:
6707 case OPC1_32_RLC_MTCR
:
6708 decode_rlc_opc(env
, ctx
, op1
);
6711 case OPCM_32_RR_ACCUMULATOR
:
6712 decode_rr_accumulator(env
, ctx
);
6714 case OPCM_32_RR_LOGICAL_SHIFT
:
6715 decode_rr_logical_shift(env
, ctx
);
6717 case OPCM_32_RR_ADDRESS
:
6718 decode_rr_address(env
, ctx
);
6720 case OPCM_32_RR_IDIRECT
:
6721 decode_rr_idirect(env
, ctx
);
6723 case OPCM_32_RR_DIVIDE
:
6724 decode_rr_divide(env
, ctx
);
6727 case OPCM_32_RR1_MUL
:
6728 decode_rr1_mul(env
, ctx
);
6730 case OPCM_32_RR1_MULQ
:
6731 decode_rr1_mulq(env
, ctx
);
6734 case OPCM_32_RR2_MUL
:
6735 decode_rr2_mul(env
, ctx
);
6738 case OPCM_32_RRPW_EXTRACT_INSERT
:
6739 decode_rrpw_extract_insert(env
, ctx
);
6741 case OPC1_32_RRPW_DEXTR
:
6742 r1
= MASK_OP_RRPW_S1(ctx
->opcode
);
6743 r2
= MASK_OP_RRPW_S2(ctx
->opcode
);
6744 r3
= MASK_OP_RRPW_D(ctx
->opcode
);
6745 const16
= MASK_OP_RRPW_POS(ctx
->opcode
);
6747 tcg_gen_rotli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], const16
);
6749 temp
= tcg_temp_new();
6750 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
], const16
);
6751 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 32 - const16
);
6752 tcg_gen_or_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
6753 tcg_temp_free(temp
);
6757 case OPCM_32_RRR_COND_SELECT
:
6758 decode_rrr_cond_select(env
, ctx
);
6760 case OPCM_32_RRR_DIVIDE
:
6761 decode_rrr_divide(env
, ctx
);
6763 case OPCM_32_RRR2_MADD
:
6764 decode_rrr2_madd(env
, ctx
);
6766 case OPCM_32_RRR2_MSUB
:
6767 decode_rrr2_msub(env
, ctx
);
6770 case OPCM_32_RRR1_MADD
:
6771 decode_rrr1_madd(env
, ctx
);
6773 case OPCM_32_RRR1_MADDQ_H
:
6774 decode_rrr1_maddq_h(env
, ctx
);
6776 case OPCM_32_RRR1_MADDSU_H
:
6777 decode_rrr1_maddsu_h(env
, ctx
);
6782 static void decode_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int *is_branch
)
6784 /* 16-Bit Instruction */
6785 if ((ctx
->opcode
& 0x1) == 0) {
6786 ctx
->next_pc
= ctx
->pc
+ 2;
6787 decode_16Bit_opc(env
, ctx
);
6788 /* 32-Bit Instruction */
6790 ctx
->next_pc
= ctx
->pc
+ 4;
6791 decode_32Bit_opc(env
, ctx
);
6796 gen_intermediate_code_internal(TriCoreCPU
*cpu
, struct TranslationBlock
*tb
,
6799 CPUState
*cs
= CPU(cpu
);
6800 CPUTriCoreState
*env
= &cpu
->env
;
6802 target_ulong pc_start
;
6806 qemu_log("search pc %d\n", search_pc
);
6814 ctx
.singlestep_enabled
= cs
->singlestep_enabled
;
6815 ctx
.bstate
= BS_NONE
;
6816 ctx
.mem_idx
= cpu_mmu_index(env
);
6818 tcg_clear_temp_count();
6820 while (ctx
.bstate
== BS_NONE
) {
6821 ctx
.opcode
= cpu_ldl_code(env
, ctx
.pc
);
6822 decode_opc(env
, &ctx
, 0);
6826 if (tcg_op_buf_full()) {
6827 gen_save_pc(ctx
.next_pc
);
6832 gen_save_pc(ctx
.next_pc
);
6836 ctx
.pc
= ctx
.next_pc
;
6839 gen_tb_end(tb
, num_insns
);
6841 printf("done_generating search pc\n");
6843 tb
->size
= ctx
.pc
- pc_start
;
6844 tb
->icount
= num_insns
;
6846 if (tcg_check_temp_count()) {
6847 printf("LEAK at %08x\n", env
->PC
);
6851 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
6852 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
6853 log_target_disas(env
, pc_start
, ctx
.pc
- pc_start
, 0);
6860 gen_intermediate_code(CPUTriCoreState
*env
, struct TranslationBlock
*tb
)
6862 gen_intermediate_code_internal(tricore_env_get_cpu(env
), tb
, false);
6866 gen_intermediate_code_pc(CPUTriCoreState
*env
, struct TranslationBlock
*tb
)
6868 gen_intermediate_code_internal(tricore_env_get_cpu(env
), tb
, true);
6872 restore_state_to_opc(CPUTriCoreState
*env
, TranslationBlock
*tb
, int pc_pos
)
6874 env
->PC
= tcg_ctx
.gen_opc_pc
[pc_pos
];
6882 void cpu_state_reset(CPUTriCoreState
*env
)
6884 /* Reset Regs to Default Value */
6888 static void tricore_tcg_init_csfr(void)
6890 cpu_PCXI
= tcg_global_mem_new(TCG_AREG0
,
6891 offsetof(CPUTriCoreState
, PCXI
), "PCXI");
6892 cpu_PSW
= tcg_global_mem_new(TCG_AREG0
,
6893 offsetof(CPUTriCoreState
, PSW
), "PSW");
6894 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
6895 offsetof(CPUTriCoreState
, PC
), "PC");
6896 cpu_ICR
= tcg_global_mem_new(TCG_AREG0
,
6897 offsetof(CPUTriCoreState
, ICR
), "ICR");
6900 void tricore_tcg_init(void)
6907 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
6909 for (i
= 0 ; i
< 16 ; i
++) {
6910 cpu_gpr_a
[i
] = tcg_global_mem_new(TCG_AREG0
,
6911 offsetof(CPUTriCoreState
, gpr_a
[i
]),
6914 for (i
= 0 ; i
< 16 ; i
++) {
6915 cpu_gpr_d
[i
] = tcg_global_mem_new(TCG_AREG0
,
6916 offsetof(CPUTriCoreState
, gpr_d
[i
]),
6919 tricore_tcg_init_csfr();
6920 /* init PSW flag cache */
6921 cpu_PSW_C
= tcg_global_mem_new(TCG_AREG0
,
6922 offsetof(CPUTriCoreState
, PSW_USB_C
),
6924 cpu_PSW_V
= tcg_global_mem_new(TCG_AREG0
,
6925 offsetof(CPUTriCoreState
, PSW_USB_V
),
6927 cpu_PSW_SV
= tcg_global_mem_new(TCG_AREG0
,
6928 offsetof(CPUTriCoreState
, PSW_USB_SV
),
6930 cpu_PSW_AV
= tcg_global_mem_new(TCG_AREG0
,
6931 offsetof(CPUTriCoreState
, PSW_USB_AV
),
6933 cpu_PSW_SAV
= tcg_global_mem_new(TCG_AREG0
,
6934 offsetof(CPUTriCoreState
, PSW_USB_SAV
),