target/sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "migration/vmstate.h"
  27 #include "exec/exec-all.h"
  28 #include "fpu/softfloat.h"
  29
  30
  31 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     SuperHCPU *cpu = SUPERH_CPU(cs);
  34
  35     cpu->env.pc = value;
  36 }
  37
  38 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  39 {
  40     SuperHCPU *cpu = SUPERH_CPU(cs);
  41
  42     cpu->env.pc = tb->pc;
  43     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
  44 }
  45
  46 static bool superh_cpu_has_work(CPUState *cs)
  47 {
  48     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  49 }
  50
  51 /* CPUClass::reset() */
  52 static void superh_cpu_reset(CPUState *s)
  53 {
  54     SuperHCPU *cpu = SUPERH_CPU(s);
  55     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  56     CPUSH4State *env = &cpu->env;
  57
  58     scc->parent_reset(s);
  59
  60     memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
  61
  62     env->pc = 0xA0000000;
  63 #if defined(CONFIG_USER_ONLY)
  64     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  65     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  66 #else
  67     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  68               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  69     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  70     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  71     set_flush_to_zero(1, &env->fp_status);
  72 #endif
  73     set_default_nan_mode(1, &env->fp_status);
  74 }
  75
  76 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  77 {
  78     info->mach = bfd_mach_sh4;
  79     info->print_insn = print_insn_sh;
  80 }
  81
  82 typedef struct SuperHCPUListState {
  83     fprintf_function cpu_fprintf;
  84     FILE *file;
  85 } SuperHCPUListState;
  86
  87 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
  88 {
  89     SuperHCPUListState *s = user_data;
  90     const char *typename = object_class_get_name(OBJECT_CLASS(data));
  91     int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX);
  92
  93     (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
  94 }
  95
  96 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
  97 {
  98     SuperHCPUListState s = {
  99         .cpu_fprintf = cpu_fprintf,
 100         .file = f,
 101     };
 102     GSList *list;
 103
 104     list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false);
 105     g_slist_foreach(list, superh_cpu_list_entry, &s);
 106     g_slist_free(list);
 107 }
 108
 109 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 110 {
 111     ObjectClass *oc;
 112     char *s, *typename = NULL;
 113
 114     s = g_ascii_strdown(cpu_model, -1);
 115     if (strcmp(s, "any") == 0) {
 116         oc = object_class_by_name(TYPE_SH7750R_CPU);
 117         goto out;
 118     }
 119
 120     typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
 121     oc = object_class_by_name(typename);
 122     if (oc != NULL && object_class_is_abstract(oc)) {
 123         oc = NULL;
 124     }
 125
 126 out:
 127     g_free(s);
 128     g_free(typename);
 129     return oc;
 130 }
 131
 132 static void sh7750r_cpu_initfn(Object *obj)
 133 {
 134     SuperHCPU *cpu = SUPERH_CPU(obj);
 135     CPUSH4State *env = &cpu->env;
 136
 137     env->id = SH_CPU_SH7750R;
 138     env->features = SH_FEATURE_BCR3_AND_BCR4;
 139 }
 140
 141 static void sh7750r_class_init(ObjectClass *oc, void *data)
 142 {
 143     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 144
 145     scc->pvr = 0x00050000;
 146     scc->prr = 0x00000100;
 147     scc->cvr = 0x00110000;
 148 }
 149
 150 static void sh7751r_cpu_initfn(Object *obj)
 151 {
 152     SuperHCPU *cpu = SUPERH_CPU(obj);
 153     CPUSH4State *env = &cpu->env;
 154
 155     env->id = SH_CPU_SH7751R;
 156     env->features = SH_FEATURE_BCR3_AND_BCR4;
 157 }
 158
 159 static void sh7751r_class_init(ObjectClass *oc, void *data)
 160 {
 161     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 162
 163     scc->pvr = 0x04050005;
 164     scc->prr = 0x00000113;
 165     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 166 }
 167
 168 static void sh7785_cpu_initfn(Object *obj)
 169 {
 170     SuperHCPU *cpu = SUPERH_CPU(obj);
 171     CPUSH4State *env = &cpu->env;
 172
 173     env->id = SH_CPU_SH7785;
 174     env->features = SH_FEATURE_SH4A;
 175 }
 176
 177 static void sh7785_class_init(ObjectClass *oc, void *data)
 178 {
 179     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 180
 181     scc->pvr = 0x10300700;
 182     scc->prr = 0x00000200;
 183     scc->cvr = 0x71440211;
 184 }
 185
 186 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 187 {
 188     CPUState *cs = CPU(dev);
 189     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 190     Error *local_err = NULL;
 191
 192     cpu_exec_realizefn(cs, &local_err);
 193     if (local_err != NULL) {
 194         error_propagate(errp, local_err);
 195         return;
 196     }
 197
 198     cpu_reset(cs);
 199     qemu_init_vcpu(cs);
 200
 201     scc->parent_realize(dev, errp);
 202 }
 203
 204 static void superh_cpu_initfn(Object *obj)
 205 {
 206     CPUState *cs = CPU(obj);
 207     SuperHCPU *cpu = SUPERH_CPU(obj);
 208     CPUSH4State *env = &cpu->env;
 209
 210     cs->env_ptr = env;
 211
 212     env->movcal_backup_tail = &(env->movcal_backup);
 213 }
 214
 215 static const VMStateDescription vmstate_sh_cpu = {
 216     .name = "cpu",
 217     .unmigratable = 1,
 218 };
 219
 220 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 221 {
 222     DeviceClass *dc = DEVICE_CLASS(oc);
 223     CPUClass *cc = CPU_CLASS(oc);
 224     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 225
 226     device_class_set_parent_realize(dc, superh_cpu_realizefn,
 227                                     &scc->parent_realize);
 228
 229     scc->parent_reset = cc->reset;
 230     cc->reset = superh_cpu_reset;
 231
 232     cc->class_by_name = superh_cpu_class_by_name;
 233     cc->has_work = superh_cpu_has_work;
 234     cc->do_interrupt = superh_cpu_do_interrupt;
 235     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 236     cc->dump_state = superh_cpu_dump_state;
 237     cc->set_pc = superh_cpu_set_pc;
 238     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 239     cc->gdb_read_register = superh_cpu_gdb_read_register;
 240     cc->gdb_write_register = superh_cpu_gdb_write_register;
 241 #ifdef CONFIG_USER_ONLY
 242     cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
 243 #else
 244     cc->do_unaligned_access = superh_cpu_do_unaligned_access;
 245     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 246 #endif
 247     cc->disas_set_info = superh_cpu_disas_set_info;
 248     cc->tcg_initialize = sh4_translate_init;
 249
 250     cc->gdb_num_core_regs = 59;
 251
 252     dc->vmsd = &vmstate_sh_cpu;
 253 }
 254
 255 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
 256     {                                                    \
 257         .name = type_name,                               \
 258         .parent = TYPE_SUPERH_CPU,                       \
 259         .class_init = cinit,                             \
 260         .instance_init = initfn,                         \
 261     }
 262 static const TypeInfo superh_cpu_type_infos[] = {
 263     {
 264         .name = TYPE_SUPERH_CPU,
 265         .parent = TYPE_CPU,
 266         .instance_size = sizeof(SuperHCPU),
 267         .instance_init = superh_cpu_initfn,
 268         .abstract = true,
 269         .class_size = sizeof(SuperHCPUClass),
 270         .class_init = superh_cpu_class_init,
 271     },
 272     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
 273                            sh7750r_cpu_initfn),
 274     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
 275                            sh7751r_cpu_initfn),
 276     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
 277                            sh7785_cpu_initfn),
 278
 279 };
 280
 281 DEFINE_TYPES(superh_cpu_type_infos)