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cuda: port SET_POWER_MESSAGES command to new framework
[qemu/ar7.git] / hw / arm / omap1.c
blob6f681304198d7b8d6b03023db79aa14f5b246b60
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/boards.h"
22 #include "hw/hw.h"
23 #include "hw/arm/arm.h"
24 #include "hw/arm/omap.h"
25 #include "sysemu/sysemu.h"
26 #include "hw/arm/soc_dma.h"
27 #include "sysemu/block-backend.h"
28 #include "sysemu/blockdev.h"
29 #include "qemu/range.h"
30 #include "hw/sysbus.h"
31
32 /* Should signal the TCMI/GPMC */
33 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
34 {
35 uint8_t ret;
36
37 OMAP_8B_REG(addr);
38 cpu_physical_memory_read(addr, &ret, 1);
39 return ret;
40 }
41
42 void omap_badwidth_write8(void *opaque, hwaddr addr,
43 uint32_t value)
44 {
45 uint8_t val8 = value;
46
47 OMAP_8B_REG(addr);
48 cpu_physical_memory_write(addr, &val8, 1);
49 }
50
51 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
52 {
53 uint16_t ret;
54
55 OMAP_16B_REG(addr);
56 cpu_physical_memory_read(addr, &ret, 2);
57 return ret;
58 }
59
60 void omap_badwidth_write16(void *opaque, hwaddr addr,
61 uint32_t value)
62 {
63 uint16_t val16 = value;
64
65 OMAP_16B_REG(addr);
66 cpu_physical_memory_write(addr, &val16, 2);
67 }
68
69 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
70 {
71 uint32_t ret;
72
73 OMAP_32B_REG(addr);
74 cpu_physical_memory_read(addr, &ret, 4);
75 return ret;
76 }
77
78 void omap_badwidth_write32(void *opaque, hwaddr addr,
79 uint32_t value)
80 {
81 OMAP_32B_REG(addr);
82 cpu_physical_memory_write(addr, &value, 4);
83 }
84
85 /* MPU OS timers */
86 struct omap_mpu_timer_s {
87 MemoryRegion iomem;
88 qemu_irq irq;
89 omap_clk clk;
90 uint32_t val;
91 int64_t time;
92 QEMUTimer *timer;
93 QEMUBH *tick;
94 int64_t rate;
95 int it_ena;
96
97 int enable;
98 int ptv;
99 int ar;
100 int st;
101 uint32_t reset_val;
102 };
103
104 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
105 {
106 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
107
108 if (timer->st && timer->enable && timer->rate)
109 return timer->val - muldiv64(distance >> (timer->ptv + 1),
110 timer->rate, get_ticks_per_sec());
111 else
112 return timer->val;
113 }
114
115 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
116 {
117 timer->val = omap_timer_read(timer);
118 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
119 }
120
121 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
122 {
123 int64_t expires;
124
125 if (timer->enable && timer->st && timer->rate) {
126 timer->val = timer->reset_val; /* Should skip this on clk enable */
127 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
128 get_ticks_per_sec(), timer->rate);
129
130 /* If timer expiry would be sooner than in about 1 ms and
131 * auto-reload isn't set, then fire immediately. This is a hack
132 * to make systems like PalmOS run in acceptable time. PalmOS
133 * sets the interval to a very low value and polls the status bit
134 * in a busy loop when it wants to sleep just a couple of CPU
135 * ticks. */
136 if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
137 timer_mod(timer->timer, timer->time + expires);
138 else
139 qemu_bh_schedule(timer->tick);
140 } else
141 timer_del(timer->timer);
142 }
143
144 static void omap_timer_fire(void *opaque)
145 {
146 struct omap_mpu_timer_s *timer = opaque;
147
148 if (!timer->ar) {
149 timer->val = 0;
150 timer->st = 0;
151 }
152
153 if (timer->it_ena)
154 /* Edge-triggered irq */
155 qemu_irq_pulse(timer->irq);
156 }
157
158 static void omap_timer_tick(void *opaque)
159 {
160 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
161
162 omap_timer_sync(timer);
163 omap_timer_fire(timer);
164 omap_timer_update(timer);
165 }
166
167 static void omap_timer_clk_update(void *opaque, int line, int on)
168 {
169 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
170
171 omap_timer_sync(timer);
172 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
173 omap_timer_update(timer);
174 }
175
176 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
177 {
178 omap_clk_adduser(timer->clk,
179 qemu_allocate_irq(omap_timer_clk_update, timer, 0));
180 timer->rate = omap_clk_getrate(timer->clk);
181 }
182
183 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
184 unsigned size)
185 {
186 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
187
188 if (size != 4) {
189 return omap_badwidth_read32(opaque, addr);
190 }
191
192 switch (addr) {
193 case 0x00: /* CNTL_TIMER */
194 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
195
196 case 0x04: /* LOAD_TIM */
197 break;
198
199 case 0x08: /* READ_TIM */
200 return omap_timer_read(s);
201 }
202
203 OMAP_BAD_REG(addr);
204 return 0;
205 }
206
207 static void omap_mpu_timer_write(void *opaque, hwaddr addr,
208 uint64_t value, unsigned size)
209 {
210 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
211
212 if (size != 4) {
213 omap_badwidth_write32(opaque, addr, value);
214 return;
215 }
216
217 switch (addr) {
218 case 0x00: /* CNTL_TIMER */
219 omap_timer_sync(s);
220 s->enable = (value >> 5) & 1;
221 s->ptv = (value >> 2) & 7;
222 s->ar = (value >> 1) & 1;
223 s->st = value & 1;
224 omap_timer_update(s);
225 return;
226
227 case 0x04: /* LOAD_TIM */
228 s->reset_val = value;
229 return;
230
231 case 0x08: /* READ_TIM */
232 OMAP_RO_REG(addr);
233 break;
234
235 default:
236 OMAP_BAD_REG(addr);
237 }
238 }
239
240 static const MemoryRegionOps omap_mpu_timer_ops = {
241 .read = omap_mpu_timer_read,
242 .write = omap_mpu_timer_write,
243 .endianness = DEVICE_LITTLE_ENDIAN,
244 };
245
246 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
247 {
248 timer_del(s->timer);
249 s->enable = 0;
250 s->reset_val = 31337;
251 s->val = 0;
252 s->ptv = 0;
253 s->ar = 0;
254 s->st = 0;
255 s->it_ena = 1;
256 }
257
258 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
259 hwaddr base,
260 qemu_irq irq, omap_clk clk)
261 {
262 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
263
264 s->irq = irq;
265 s->clk = clk;
266 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
267 s->tick = qemu_bh_new(omap_timer_fire, s);
268 omap_mpu_timer_reset(s);
269 omap_timer_clk_setup(s);
270
271 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
272 "omap-mpu-timer", 0x100);
273
274 memory_region_add_subregion(system_memory, base, &s->iomem);
275
276 return s;
277 }
278
279 /* Watchdog timer */
280 struct omap_watchdog_timer_s {
281 struct omap_mpu_timer_s timer;
282 MemoryRegion iomem;
283 uint8_t last_wr;
284 int mode;
285 int free;
286 int reset;
287 };
288
289 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
290 unsigned size)
291 {
292 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
293
294 if (size != 2) {
295 return omap_badwidth_read16(opaque, addr);
296 }
297
298 switch (addr) {
299 case 0x00: /* CNTL_TIMER */
300 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
301 (s->timer.st << 7) | (s->free << 1);
302
303 case 0x04: /* READ_TIMER */
304 return omap_timer_read(&s->timer);
305
306 case 0x08: /* TIMER_MODE */
307 return s->mode << 15;
308 }
309
310 OMAP_BAD_REG(addr);
311 return 0;
312 }
313
314 static void omap_wd_timer_write(void *opaque, hwaddr addr,
315 uint64_t value, unsigned size)
316 {
317 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
318
319 if (size != 2) {
320 omap_badwidth_write16(opaque, addr, value);
321 return;
322 }
323
324 switch (addr) {
325 case 0x00: /* CNTL_TIMER */
326 omap_timer_sync(&s->timer);
327 s->timer.ptv = (value >> 9) & 7;
328 s->timer.ar = (value >> 8) & 1;
329 s->timer.st = (value >> 7) & 1;
330 s->free = (value >> 1) & 1;
331 omap_timer_update(&s->timer);
332 break;
333
334 case 0x04: /* LOAD_TIMER */
335 s->timer.reset_val = value & 0xffff;
336 break;
337
338 case 0x08: /* TIMER_MODE */
339 if (!s->mode && ((value >> 15) & 1))
340 omap_clk_get(s->timer.clk);
341 s->mode |= (value >> 15) & 1;
342 if (s->last_wr == 0xf5) {
343 if ((value & 0xff) == 0xa0) {
344 if (s->mode) {
345 s->mode = 0;
346 omap_clk_put(s->timer.clk);
347 }
348 } else {
349 /* XXX: on T|E hardware somehow this has no effect,
350 * on Zire 71 it works as specified. */
351 s->reset = 1;
352 qemu_system_reset_request();
353 }
354 }
355 s->last_wr = value & 0xff;
356 break;
357
358 default:
359 OMAP_BAD_REG(addr);
360 }
361 }
362
363 static const MemoryRegionOps omap_wd_timer_ops = {
364 .read = omap_wd_timer_read,
365 .write = omap_wd_timer_write,
366 .endianness = DEVICE_NATIVE_ENDIAN,
367 };
368
369 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
370 {
371 timer_del(s->timer.timer);
372 if (!s->mode)
373 omap_clk_get(s->timer.clk);
374 s->mode = 1;
375 s->free = 1;
376 s->reset = 0;
377 s->timer.enable = 1;
378 s->timer.it_ena = 1;
379 s->timer.reset_val = 0xffff;
380 s->timer.val = 0;
381 s->timer.st = 0;
382 s->timer.ptv = 0;
383 s->timer.ar = 0;
384 omap_timer_update(&s->timer);
385 }
386
387 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
388 hwaddr base,
389 qemu_irq irq, omap_clk clk)
390 {
391 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
392
393 s->timer.irq = irq;
394 s->timer.clk = clk;
395 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
396 omap_wd_timer_reset(s);
397 omap_timer_clk_setup(&s->timer);
398
399 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
400 "omap-wd-timer", 0x100);
401 memory_region_add_subregion(memory, base, &s->iomem);
402
403 return s;
404 }
405
406 /* 32-kHz timer */
407 struct omap_32khz_timer_s {
408 struct omap_mpu_timer_s timer;
409 MemoryRegion iomem;
410 };
411
412 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
413 unsigned size)
414 {
415 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
416 int offset = addr & OMAP_MPUI_REG_MASK;
417
418 if (size != 4) {
419 return omap_badwidth_read32(opaque, addr);
420 }
421
422 switch (offset) {
423 case 0x00: /* TVR */
424 return s->timer.reset_val;
425
426 case 0x04: /* TCR */
427 return omap_timer_read(&s->timer);
428
429 case 0x08: /* CR */
430 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
431
432 default:
433 break;
434 }
435 OMAP_BAD_REG(addr);
436 return 0;
437 }
438
439 static void omap_os_timer_write(void *opaque, hwaddr addr,
440 uint64_t value, unsigned size)
441 {
442 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
443 int offset = addr & OMAP_MPUI_REG_MASK;
444
445 if (size != 4) {
446 omap_badwidth_write32(opaque, addr, value);
447 return;
448 }
449
450 switch (offset) {
451 case 0x00: /* TVR */
452 s->timer.reset_val = value & 0x00ffffff;
453 break;
454
455 case 0x04: /* TCR */
456 OMAP_RO_REG(addr);
457 break;
458
459 case 0x08: /* CR */
460 s->timer.ar = (value >> 3) & 1;
461 s->timer.it_ena = (value >> 2) & 1;
462 if (s->timer.st != (value & 1) || (value & 2)) {
463 omap_timer_sync(&s->timer);
464 s->timer.enable = value & 1;
465 s->timer.st = value & 1;
466 omap_timer_update(&s->timer);
467 }
468 break;
469
470 default:
471 OMAP_BAD_REG(addr);
472 }
473 }
474
475 static const MemoryRegionOps omap_os_timer_ops = {
476 .read = omap_os_timer_read,
477 .write = omap_os_timer_write,
478 .endianness = DEVICE_NATIVE_ENDIAN,
479 };
480
481 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
482 {
483 timer_del(s->timer.timer);
484 s->timer.enable = 0;
485 s->timer.it_ena = 0;
486 s->timer.reset_val = 0x00ffffff;
487 s->timer.val = 0;
488 s->timer.st = 0;
489 s->timer.ptv = 0;
490 s->timer.ar = 1;
491 }
492
493 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
494 hwaddr base,
495 qemu_irq irq, omap_clk clk)
496 {
497 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
498
499 s->timer.irq = irq;
500 s->timer.clk = clk;
501 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
502 omap_os_timer_reset(s);
503 omap_timer_clk_setup(&s->timer);
504
505 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
506 "omap-os-timer", 0x800);
507 memory_region_add_subregion(memory, base, &s->iomem);
508
509 return s;
510 }
511
512 /* Ultra Low-Power Device Module */
513 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
514 unsigned size)
515 {
516 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
517 uint16_t ret;
518
519 if (size != 2) {
520 return omap_badwidth_read16(opaque, addr);
521 }
522
523 switch (addr) {
524 case 0x14: /* IT_STATUS */
525 ret = s->ulpd_pm_regs[addr >> 2];
526 s->ulpd_pm_regs[addr >> 2] = 0;
527 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
528 return ret;
529
530 case 0x18: /* Reserved */
531 case 0x1c: /* Reserved */
532 case 0x20: /* Reserved */
533 case 0x28: /* Reserved */
534 case 0x2c: /* Reserved */
535 OMAP_BAD_REG(addr);
536 /* fall through */
537 case 0x00: /* COUNTER_32_LSB */
538 case 0x04: /* COUNTER_32_MSB */
539 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
540 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
541 case 0x10: /* GAUGING_CTRL */
542 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
543 case 0x30: /* CLOCK_CTRL */
544 case 0x34: /* SOFT_REQ */
545 case 0x38: /* COUNTER_32_FIQ */
546 case 0x3c: /* DPLL_CTRL */
547 case 0x40: /* STATUS_REQ */
548 /* XXX: check clk::usecount state for every clock */
549 case 0x48: /* LOCL_TIME */
550 case 0x4c: /* APLL_CTRL */
551 case 0x50: /* POWER_CTRL */
552 return s->ulpd_pm_regs[addr >> 2];
553 }
554
555 OMAP_BAD_REG(addr);
556 return 0;
557 }
558
559 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
560 uint16_t diff, uint16_t value)
561 {
562 if (diff & (1 << 4)) /* USB_MCLK_EN */
563 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
564 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
565 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
566 }
567
568 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
569 uint16_t diff, uint16_t value)
570 {
571 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
572 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
573 if (diff & (1 << 1)) /* SOFT_COM_REQ */
574 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
575 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
576 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
577 if (diff & (1 << 3)) /* SOFT_USB_REQ */
578 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
579 }
580
581 static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
582 uint64_t value, unsigned size)
583 {
584 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
585 int64_t now, ticks;
586 int div, mult;
587 static const int bypass_div[4] = { 1, 2, 4, 4 };
588 uint16_t diff;
589
590 if (size != 2) {
591 omap_badwidth_write16(opaque, addr, value);
592 return;
593 }
594
595 switch (addr) {
596 case 0x00: /* COUNTER_32_LSB */
597 case 0x04: /* COUNTER_32_MSB */
598 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
599 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
600 case 0x14: /* IT_STATUS */
601 case 0x40: /* STATUS_REQ */
602 OMAP_RO_REG(addr);
603 break;
604
605 case 0x10: /* GAUGING_CTRL */
606 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
607 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
608 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
609
610 if (value & 1)
611 s->ulpd_gauge_start = now;
612 else {
613 now -= s->ulpd_gauge_start;
614
615 /* 32-kHz ticks */
616 ticks = muldiv64(now, 32768, get_ticks_per_sec());
617 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
618 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
619 if (ticks >> 32) /* OVERFLOW_32K */
620 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
621
622 /* High frequency ticks */
623 ticks = muldiv64(now, 12000000, get_ticks_per_sec());
624 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
625 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
626 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
627 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
628
629 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
630 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
631 }
632 }
633 s->ulpd_pm_regs[addr >> 2] = value;
634 break;
635
636 case 0x18: /* Reserved */
637 case 0x1c: /* Reserved */
638 case 0x20: /* Reserved */
639 case 0x28: /* Reserved */
640 case 0x2c: /* Reserved */
641 OMAP_BAD_REG(addr);
642 /* fall through */
643 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
644 case 0x38: /* COUNTER_32_FIQ */
645 case 0x48: /* LOCL_TIME */
646 case 0x50: /* POWER_CTRL */
647 s->ulpd_pm_regs[addr >> 2] = value;
648 break;
649
650 case 0x30: /* CLOCK_CTRL */
651 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
652 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
653 omap_ulpd_clk_update(s, diff, value);
654 break;
655
656 case 0x34: /* SOFT_REQ */
657 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
658 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
659 omap_ulpd_req_update(s, diff, value);
660 break;
661
662 case 0x3c: /* DPLL_CTRL */
663 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
664 * omitted altogether, probably a typo. */
665 /* This register has identical semantics with DPLL(1:3) control
666 * registers, see omap_dpll_write() */
667 diff = s->ulpd_pm_regs[addr >> 2] & value;
668 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
669 if (diff & (0x3ff << 2)) {
670 if (value & (1 << 4)) { /* PLL_ENABLE */
671 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
672 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
673 } else {
674 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
675 mult = 1;
676 }
677 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
678 }
679
680 /* Enter the desired mode. */
681 s->ulpd_pm_regs[addr >> 2] =
682 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
683 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
684
685 /* Act as if the lock is restored. */
686 s->ulpd_pm_regs[addr >> 2] |= 2;
687 break;
688
689 case 0x4c: /* APLL_CTRL */
690 diff = s->ulpd_pm_regs[addr >> 2] & value;
691 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
692 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
693 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
694 (value & (1 << 0)) ? "apll" : "dpll4"));
695 break;
696
697 default:
698 OMAP_BAD_REG(addr);
699 }
700 }
701
702 static const MemoryRegionOps omap_ulpd_pm_ops = {
703 .read = omap_ulpd_pm_read,
704 .write = omap_ulpd_pm_write,
705 .endianness = DEVICE_NATIVE_ENDIAN,
706 };
707
708 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
709 {
710 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
711 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
712 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
713 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
714 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
715 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
716 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
717 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
718 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
719 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
720 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
721 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
722 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
723 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
724 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
725 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
726 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
727 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
728 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
729 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
730 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
731 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
732 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
733 }
734
735 static void omap_ulpd_pm_init(MemoryRegion *system_memory,
736 hwaddr base,
737 struct omap_mpu_state_s *mpu)
738 {
739 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
740 "omap-ulpd-pm", 0x800);
741 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
742 omap_ulpd_pm_reset(mpu);
743 }
744
745 /* OMAP Pin Configuration */
746 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
747 unsigned size)
748 {
749 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
750
751 if (size != 4) {
752 return omap_badwidth_read32(opaque, addr);
753 }
754
755 switch (addr) {
756 case 0x00: /* FUNC_MUX_CTRL_0 */
757 case 0x04: /* FUNC_MUX_CTRL_1 */
758 case 0x08: /* FUNC_MUX_CTRL_2 */
759 return s->func_mux_ctrl[addr >> 2];
760
761 case 0x0c: /* COMP_MODE_CTRL_0 */
762 return s->comp_mode_ctrl[0];
763
764 case 0x10: /* FUNC_MUX_CTRL_3 */
765 case 0x14: /* FUNC_MUX_CTRL_4 */
766 case 0x18: /* FUNC_MUX_CTRL_5 */
767 case 0x1c: /* FUNC_MUX_CTRL_6 */
768 case 0x20: /* FUNC_MUX_CTRL_7 */
769 case 0x24: /* FUNC_MUX_CTRL_8 */
770 case 0x28: /* FUNC_MUX_CTRL_9 */
771 case 0x2c: /* FUNC_MUX_CTRL_A */
772 case 0x30: /* FUNC_MUX_CTRL_B */
773 case 0x34: /* FUNC_MUX_CTRL_C */
774 case 0x38: /* FUNC_MUX_CTRL_D */
775 return s->func_mux_ctrl[(addr >> 2) - 1];
776
777 case 0x40: /* PULL_DWN_CTRL_0 */
778 case 0x44: /* PULL_DWN_CTRL_1 */
779 case 0x48: /* PULL_DWN_CTRL_2 */
780 case 0x4c: /* PULL_DWN_CTRL_3 */
781 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
782
783 case 0x50: /* GATE_INH_CTRL_0 */
784 return s->gate_inh_ctrl[0];
785
786 case 0x60: /* VOLTAGE_CTRL_0 */
787 return s->voltage_ctrl[0];
788
789 case 0x70: /* TEST_DBG_CTRL_0 */
790 return s->test_dbg_ctrl[0];
791
792 case 0x80: /* MOD_CONF_CTRL_0 */
793 return s->mod_conf_ctrl[0];
794 }
795
796 OMAP_BAD_REG(addr);
797 return 0;
798 }
799
800 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
801 uint32_t diff, uint32_t value)
802 {
803 if (s->compat1509) {
804 if (diff & (1 << 9)) /* BLUETOOTH */
805 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
806 (~value >> 9) & 1);
807 if (diff & (1 << 7)) /* USB.CLKO */
808 omap_clk_onoff(omap_findclk(s, "usb.clko"),
809 (value >> 7) & 1);
810 }
811 }
812
813 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
814 uint32_t diff, uint32_t value)
815 {
816 if (s->compat1509) {
817 if (diff & (1U << 31)) {
818 /* MCBSP3_CLK_HIZ_DI */
819 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
820 }
821 if (diff & (1 << 1)) {
822 /* CLK32K */
823 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
824 }
825 }
826 }
827
828 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
829 uint32_t diff, uint32_t value)
830 {
831 if (diff & (1U << 31)) {
832 /* CONF_MOD_UART3_CLK_MODE_R */
833 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
834 omap_findclk(s, ((value >> 31) & 1) ?
835 "ck_48m" : "armper_ck"));
836 }
837 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
838 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
839 omap_findclk(s, ((value >> 30) & 1) ?
840 "ck_48m" : "armper_ck"));
841 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
842 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
843 omap_findclk(s, ((value >> 29) & 1) ?
844 "ck_48m" : "armper_ck"));
845 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
846 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
847 omap_findclk(s, ((value >> 23) & 1) ?
848 "ck_48m" : "armper_ck"));
849 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
850 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
851 omap_findclk(s, ((value >> 12) & 1) ?
852 "ck_48m" : "armper_ck"));
853 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
854 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
855 }
856
857 static void omap_pin_cfg_write(void *opaque, hwaddr addr,
858 uint64_t value, unsigned size)
859 {
860 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
861 uint32_t diff;
862
863 if (size != 4) {
864 omap_badwidth_write32(opaque, addr, value);
865 return;
866 }
867
868 switch (addr) {
869 case 0x00: /* FUNC_MUX_CTRL_0 */
870 diff = s->func_mux_ctrl[addr >> 2] ^ value;
871 s->func_mux_ctrl[addr >> 2] = value;
872 omap_pin_funcmux0_update(s, diff, value);
873 return;
874
875 case 0x04: /* FUNC_MUX_CTRL_1 */
876 diff = s->func_mux_ctrl[addr >> 2] ^ value;
877 s->func_mux_ctrl[addr >> 2] = value;
878 omap_pin_funcmux1_update(s, diff, value);
879 return;
880
881 case 0x08: /* FUNC_MUX_CTRL_2 */
882 s->func_mux_ctrl[addr >> 2] = value;
883 return;
884
885 case 0x0c: /* COMP_MODE_CTRL_0 */
886 s->comp_mode_ctrl[0] = value;
887 s->compat1509 = (value != 0x0000eaef);
888 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
889 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
890 return;
891
892 case 0x10: /* FUNC_MUX_CTRL_3 */
893 case 0x14: /* FUNC_MUX_CTRL_4 */
894 case 0x18: /* FUNC_MUX_CTRL_5 */
895 case 0x1c: /* FUNC_MUX_CTRL_6 */
896 case 0x20: /* FUNC_MUX_CTRL_7 */
897 case 0x24: /* FUNC_MUX_CTRL_8 */
898 case 0x28: /* FUNC_MUX_CTRL_9 */
899 case 0x2c: /* FUNC_MUX_CTRL_A */
900 case 0x30: /* FUNC_MUX_CTRL_B */
901 case 0x34: /* FUNC_MUX_CTRL_C */
902 case 0x38: /* FUNC_MUX_CTRL_D */
903 s->func_mux_ctrl[(addr >> 2) - 1] = value;
904 return;
905
906 case 0x40: /* PULL_DWN_CTRL_0 */
907 case 0x44: /* PULL_DWN_CTRL_1 */
908 case 0x48: /* PULL_DWN_CTRL_2 */
909 case 0x4c: /* PULL_DWN_CTRL_3 */
910 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
911 return;
912
913 case 0x50: /* GATE_INH_CTRL_0 */
914 s->gate_inh_ctrl[0] = value;
915 return;
916
917 case 0x60: /* VOLTAGE_CTRL_0 */
918 s->voltage_ctrl[0] = value;
919 return;
920
921 case 0x70: /* TEST_DBG_CTRL_0 */
922 s->test_dbg_ctrl[0] = value;
923 return;
924
925 case 0x80: /* MOD_CONF_CTRL_0 */
926 diff = s->mod_conf_ctrl[0] ^ value;
927 s->mod_conf_ctrl[0] = value;
928 omap_pin_modconf1_update(s, diff, value);
929 return;
930
931 default:
932 OMAP_BAD_REG(addr);
933 }
934 }
935
936 static const MemoryRegionOps omap_pin_cfg_ops = {
937 .read = omap_pin_cfg_read,
938 .write = omap_pin_cfg_write,
939 .endianness = DEVICE_NATIVE_ENDIAN,
940 };
941
942 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
943 {
944 /* Start in Compatibility Mode. */
945 mpu->compat1509 = 1;
946 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
947 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
948 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
949 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
950 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
951 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
952 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
953 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
954 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
955 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
956 }
957
958 static void omap_pin_cfg_init(MemoryRegion *system_memory,
959 hwaddr base,
960 struct omap_mpu_state_s *mpu)
961 {
962 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
963 "omap-pin-cfg", 0x800);
964 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
965 omap_pin_cfg_reset(mpu);
966 }
967
968 /* Device Identification, Die Identification */
969 static uint64_t omap_id_read(void *opaque, hwaddr addr,
970 unsigned size)
971 {
972 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
973
974 if (size != 4) {
975 return omap_badwidth_read32(opaque, addr);
976 }
977
978 switch (addr) {
979 case 0xfffe1800: /* DIE_ID_LSB */
980 return 0xc9581f0e;
981 case 0xfffe1804: /* DIE_ID_MSB */
982 return 0xa8858bfa;
983
984 case 0xfffe2000: /* PRODUCT_ID_LSB */
985 return 0x00aaaafc;
986 case 0xfffe2004: /* PRODUCT_ID_MSB */
987 return 0xcafeb574;
988
989 case 0xfffed400: /* JTAG_ID_LSB */
990 switch (s->mpu_model) {
991 case omap310:
992 return 0x03310315;
993 case omap1510:
994 return 0x03310115;
995 default:
996 hw_error("%s: bad mpu model\n", __FUNCTION__);
997 }
998 break;
999
1000 case 0xfffed404: /* JTAG_ID_MSB */
1001 switch (s->mpu_model) {
1002 case omap310:
1003 return 0xfb57402f;
1004 case omap1510:
1005 return 0xfb47002f;
1006 default:
1007 hw_error("%s: bad mpu model\n", __FUNCTION__);
1008 }
1009 break;
1010 }
1011
1012 OMAP_BAD_REG(addr);
1013 return 0;
1014 }
1015
1016 static void omap_id_write(void *opaque, hwaddr addr,
1017 uint64_t value, unsigned size)
1018 {
1019 if (size != 4) {
1020 omap_badwidth_write32(opaque, addr, value);
1021 return;
1022 }
1023
1024 OMAP_BAD_REG(addr);
1025 }
1026
1027 static const MemoryRegionOps omap_id_ops = {
1028 .read = omap_id_read,
1029 .write = omap_id_write,
1030 .endianness = DEVICE_NATIVE_ENDIAN,
1031 };
1032
1033 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
1034 {
1035 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
1036 "omap-id", 0x100000000ULL);
1037 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
1038 0xfffe1800, 0x800);
1039 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
1040 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
1041 0xfffed400, 0x100);
1042 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
1043 if (!cpu_is_omap15xx(mpu)) {
1044 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
1045 &mpu->id_iomem, 0xfffe2000, 0x800);
1046 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
1047 }
1048 }
1049
1050 /* MPUI Control (Dummy) */
1051 static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
1052 unsigned size)
1053 {
1054 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1055
1056 if (size != 4) {
1057 return omap_badwidth_read32(opaque, addr);
1058 }
1059
1060 switch (addr) {
1061 case 0x00: /* CTRL */
1062 return s->mpui_ctrl;
1063 case 0x04: /* DEBUG_ADDR */
1064 return 0x01ffffff;
1065 case 0x08: /* DEBUG_DATA */
1066 return 0xffffffff;
1067 case 0x0c: /* DEBUG_FLAG */
1068 return 0x00000800;
1069 case 0x10: /* STATUS */
1070 return 0x00000000;
1071
1072 /* Not in OMAP310 */
1073 case 0x14: /* DSP_STATUS */
1074 case 0x18: /* DSP_BOOT_CONFIG */
1075 return 0x00000000;
1076 case 0x1c: /* DSP_MPUI_CONFIG */
1077 return 0x0000ffff;
1078 }
1079
1080 OMAP_BAD_REG(addr);
1081 return 0;
1082 }
1083
1084 static void omap_mpui_write(void *opaque, hwaddr addr,
1085 uint64_t value, unsigned size)
1086 {
1087 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1088
1089 if (size != 4) {
1090 omap_badwidth_write32(opaque, addr, value);
1091 return;
1092 }
1093
1094 switch (addr) {
1095 case 0x00: /* CTRL */
1096 s->mpui_ctrl = value & 0x007fffff;
1097 break;
1098
1099 case 0x04: /* DEBUG_ADDR */
1100 case 0x08: /* DEBUG_DATA */
1101 case 0x0c: /* DEBUG_FLAG */
1102 case 0x10: /* STATUS */
1103 /* Not in OMAP310 */
1104 case 0x14: /* DSP_STATUS */
1105 OMAP_RO_REG(addr);
1106 break;
1107 case 0x18: /* DSP_BOOT_CONFIG */
1108 case 0x1c: /* DSP_MPUI_CONFIG */
1109 break;
1110
1111 default:
1112 OMAP_BAD_REG(addr);
1113 }
1114 }
1115
1116 static const MemoryRegionOps omap_mpui_ops = {
1117 .read = omap_mpui_read,
1118 .write = omap_mpui_write,
1119 .endianness = DEVICE_NATIVE_ENDIAN,
1120 };
1121
1122 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1123 {
1124 s->mpui_ctrl = 0x0003ff1b;
1125 }
1126
1127 static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
1128 struct omap_mpu_state_s *mpu)
1129 {
1130 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
1131 "omap-mpui", 0x100);
1132 memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
1133
1134 omap_mpui_reset(mpu);
1135 }
1136
1137 /* TIPB Bridges */
1138 struct omap_tipb_bridge_s {
1139 qemu_irq abort;
1140 MemoryRegion iomem;
1141
1142 int width_intr;
1143 uint16_t control;
1144 uint16_t alloc;
1145 uint16_t buffer;
1146 uint16_t enh_control;
1147 };
1148
1149 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
1150 unsigned size)
1151 {
1152 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1153
1154 if (size < 2) {
1155 return omap_badwidth_read16(opaque, addr);
1156 }
1157
1158 switch (addr) {
1159 case 0x00: /* TIPB_CNTL */
1160 return s->control;
1161 case 0x04: /* TIPB_BUS_ALLOC */
1162 return s->alloc;
1163 case 0x08: /* MPU_TIPB_CNTL */
1164 return s->buffer;
1165 case 0x0c: /* ENHANCED_TIPB_CNTL */
1166 return s->enh_control;
1167 case 0x10: /* ADDRESS_DBG */
1168 case 0x14: /* DATA_DEBUG_LOW */
1169 case 0x18: /* DATA_DEBUG_HIGH */
1170 return 0xffff;
1171 case 0x1c: /* DEBUG_CNTR_SIG */
1172 return 0x00f8;
1173 }
1174
1175 OMAP_BAD_REG(addr);
1176 return 0;
1177 }
1178
1179 static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
1180 uint64_t value, unsigned size)
1181 {
1182 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1183
1184 if (size < 2) {
1185 omap_badwidth_write16(opaque, addr, value);
1186 return;
1187 }
1188
1189 switch (addr) {
1190 case 0x00: /* TIPB_CNTL */
1191 s->control = value & 0xffff;
1192 break;
1193
1194 case 0x04: /* TIPB_BUS_ALLOC */
1195 s->alloc = value & 0x003f;
1196 break;
1197
1198 case 0x08: /* MPU_TIPB_CNTL */
1199 s->buffer = value & 0x0003;
1200 break;
1201
1202 case 0x0c: /* ENHANCED_TIPB_CNTL */
1203 s->width_intr = !(value & 2);
1204 s->enh_control = value & 0x000f;
1205 break;
1206
1207 case 0x10: /* ADDRESS_DBG */
1208 case 0x14: /* DATA_DEBUG_LOW */
1209 case 0x18: /* DATA_DEBUG_HIGH */
1210 case 0x1c: /* DEBUG_CNTR_SIG */
1211 OMAP_RO_REG(addr);
1212 break;
1213
1214 default:
1215 OMAP_BAD_REG(addr);
1216 }
1217 }
1218
1219 static const MemoryRegionOps omap_tipb_bridge_ops = {
1220 .read = omap_tipb_bridge_read,
1221 .write = omap_tipb_bridge_write,
1222 .endianness = DEVICE_NATIVE_ENDIAN,
1223 };
1224
1225 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1226 {
1227 s->control = 0xffff;
1228 s->alloc = 0x0009;
1229 s->buffer = 0x0000;
1230 s->enh_control = 0x000f;
1231 }
1232
1233 static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
1234 MemoryRegion *memory, hwaddr base,
1235 qemu_irq abort_irq, omap_clk clk)
1236 {
1237 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
1238
1239 s->abort = abort_irq;
1240 omap_tipb_bridge_reset(s);
1241
1242 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
1243 "omap-tipb-bridge", 0x100);
1244 memory_region_add_subregion(memory, base, &s->iomem);
1245
1246 return s;
1247 }
1248
1249 /* Dummy Traffic Controller's Memory Interface */
1250 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
1251 unsigned size)
1252 {
1253 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1254 uint32_t ret;
1255
1256 if (size != 4) {
1257 return omap_badwidth_read32(opaque, addr);
1258 }
1259
1260 switch (addr) {
1261 case 0x00: /* IMIF_PRIO */
1262 case 0x04: /* EMIFS_PRIO */
1263 case 0x08: /* EMIFF_PRIO */
1264 case 0x0c: /* EMIFS_CONFIG */
1265 case 0x10: /* EMIFS_CS0_CONFIG */
1266 case 0x14: /* EMIFS_CS1_CONFIG */
1267 case 0x18: /* EMIFS_CS2_CONFIG */
1268 case 0x1c: /* EMIFS_CS3_CONFIG */
1269 case 0x24: /* EMIFF_MRS */
1270 case 0x28: /* TIMEOUT1 */
1271 case 0x2c: /* TIMEOUT2 */
1272 case 0x30: /* TIMEOUT3 */
1273 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1274 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1275 return s->tcmi_regs[addr >> 2];
1276
1277 case 0x20: /* EMIFF_SDRAM_CONFIG */
1278 ret = s->tcmi_regs[addr >> 2];
1279 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1280 /* XXX: We can try using the VGA_DIRTY flag for this */
1281 return ret;
1282 }
1283
1284 OMAP_BAD_REG(addr);
1285 return 0;
1286 }
1287
1288 static void omap_tcmi_write(void *opaque, hwaddr addr,
1289 uint64_t value, unsigned size)
1290 {
1291 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1292
1293 if (size != 4) {
1294 omap_badwidth_write32(opaque, addr, value);
1295 return;
1296 }
1297
1298 switch (addr) {
1299 case 0x00: /* IMIF_PRIO */
1300 case 0x04: /* EMIFS_PRIO */
1301 case 0x08: /* EMIFF_PRIO */
1302 case 0x10: /* EMIFS_CS0_CONFIG */
1303 case 0x14: /* EMIFS_CS1_CONFIG */
1304 case 0x18: /* EMIFS_CS2_CONFIG */
1305 case 0x1c: /* EMIFS_CS3_CONFIG */
1306 case 0x20: /* EMIFF_SDRAM_CONFIG */
1307 case 0x24: /* EMIFF_MRS */
1308 case 0x28: /* TIMEOUT1 */
1309 case 0x2c: /* TIMEOUT2 */
1310 case 0x30: /* TIMEOUT3 */
1311 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1312 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1313 s->tcmi_regs[addr >> 2] = value;
1314 break;
1315 case 0x0c: /* EMIFS_CONFIG */
1316 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
1317 break;
1318
1319 default:
1320 OMAP_BAD_REG(addr);
1321 }
1322 }
1323
1324 static const MemoryRegionOps omap_tcmi_ops = {
1325 .read = omap_tcmi_read,
1326 .write = omap_tcmi_write,
1327 .endianness = DEVICE_NATIVE_ENDIAN,
1328 };
1329
1330 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1331 {
1332 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1333 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1334 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1335 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1336 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1337 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1338 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1339 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1340 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1341 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1342 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1343 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1344 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1345 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1346 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1347 }
1348
1349 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
1350 struct omap_mpu_state_s *mpu)
1351 {
1352 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
1353 "omap-tcmi", 0x100);
1354 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
1355 omap_tcmi_reset(mpu);
1356 }
1357
1358 /* Digital phase-locked loops control */
1359 struct dpll_ctl_s {
1360 MemoryRegion iomem;
1361 uint16_t mode;
1362 omap_clk dpll;
1363 };
1364
1365 static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
1366 unsigned size)
1367 {
1368 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1369
1370 if (size != 2) {
1371 return omap_badwidth_read16(opaque, addr);
1372 }
1373
1374 if (addr == 0x00) /* CTL_REG */
1375 return s->mode;
1376
1377 OMAP_BAD_REG(addr);
1378 return 0;
1379 }
1380
1381 static void omap_dpll_write(void *opaque, hwaddr addr,
1382 uint64_t value, unsigned size)
1383 {
1384 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1385 uint16_t diff;
1386 static const int bypass_div[4] = { 1, 2, 4, 4 };
1387 int div, mult;
1388
1389 if (size != 2) {
1390 omap_badwidth_write16(opaque, addr, value);
1391 return;
1392 }
1393
1394 if (addr == 0x00) { /* CTL_REG */
1395 /* See omap_ulpd_pm_write() too */
1396 diff = s->mode & value;
1397 s->mode = value & 0x2fff;
1398 if (diff & (0x3ff << 2)) {
1399 if (value & (1 << 4)) { /* PLL_ENABLE */
1400 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1401 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1402 } else {
1403 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1404 mult = 1;
1405 }
1406 omap_clk_setrate(s->dpll, div, mult);
1407 }
1408
1409 /* Enter the desired mode. */
1410 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1411
1412 /* Act as if the lock is restored. */
1413 s->mode |= 2;
1414 } else {
1415 OMAP_BAD_REG(addr);
1416 }
1417 }
1418
1419 static const MemoryRegionOps omap_dpll_ops = {
1420 .read = omap_dpll_read,
1421 .write = omap_dpll_write,
1422 .endianness = DEVICE_NATIVE_ENDIAN,
1423 };
1424
1425 static void omap_dpll_reset(struct dpll_ctl_s *s)
1426 {
1427 s->mode = 0x2002;
1428 omap_clk_setrate(s->dpll, 1, 1);
1429 }
1430
1431 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
1432 hwaddr base, omap_clk clk)
1433 {
1434 struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
1435 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
1436
1437 s->dpll = clk;
1438 omap_dpll_reset(s);
1439
1440 memory_region_add_subregion(memory, base, &s->iomem);
1441 return s;
1442 }
1443
1444 /* MPU Clock/Reset/Power Mode Control */
1445 static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
1446 unsigned size)
1447 {
1448 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1449
1450 if (size != 2) {
1451 return omap_badwidth_read16(opaque, addr);
1452 }
1453
1454 switch (addr) {
1455 case 0x00: /* ARM_CKCTL */
1456 return s->clkm.arm_ckctl;
1457
1458 case 0x04: /* ARM_IDLECT1 */
1459 return s->clkm.arm_idlect1;
1460
1461 case 0x08: /* ARM_IDLECT2 */
1462 return s->clkm.arm_idlect2;
1463
1464 case 0x0c: /* ARM_EWUPCT */
1465 return s->clkm.arm_ewupct;
1466
1467 case 0x10: /* ARM_RSTCT1 */
1468 return s->clkm.arm_rstct1;
1469
1470 case 0x14: /* ARM_RSTCT2 */
1471 return s->clkm.arm_rstct2;
1472
1473 case 0x18: /* ARM_SYSST */
1474 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
1475
1476 case 0x1c: /* ARM_CKOUT1 */
1477 return s->clkm.arm_ckout1;
1478
1479 case 0x20: /* ARM_CKOUT2 */
1480 break;
1481 }
1482
1483 OMAP_BAD_REG(addr);
1484 return 0;
1485 }
1486
1487 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1488 uint16_t diff, uint16_t value)
1489 {
1490 omap_clk clk;
1491
1492 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1493 if (value & (1 << 14))
1494 /* Reserved */;
1495 else {
1496 clk = omap_findclk(s, "arminth_ck");
1497 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1498 }
1499 }
1500 if (diff & (1 << 12)) { /* ARM_TIMXO */
1501 clk = omap_findclk(s, "armtim_ck");
1502 if (value & (1 << 12))
1503 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1504 else
1505 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1506 }
1507 /* XXX: en_dspck */
1508 if (diff & (3 << 10)) { /* DSPMMUDIV */
1509 clk = omap_findclk(s, "dspmmu_ck");
1510 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1511 }
1512 if (diff & (3 << 8)) { /* TCDIV */
1513 clk = omap_findclk(s, "tc_ck");
1514 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1515 }
1516 if (diff & (3 << 6)) { /* DSPDIV */
1517 clk = omap_findclk(s, "dsp_ck");
1518 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1519 }
1520 if (diff & (3 << 4)) { /* ARMDIV */
1521 clk = omap_findclk(s, "arm_ck");
1522 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1523 }
1524 if (diff & (3 << 2)) { /* LCDDIV */
1525 clk = omap_findclk(s, "lcd_ck");
1526 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1527 }
1528 if (diff & (3 << 0)) { /* PERDIV */
1529 clk = omap_findclk(s, "armper_ck");
1530 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1531 }
1532 }
1533
1534 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1535 uint16_t diff, uint16_t value)
1536 {
1537 omap_clk clk;
1538
1539 if (value & (1 << 11)) { /* SETARM_IDLE */
1540 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
1541 }
1542 if (!(value & (1 << 10))) /* WKUP_MODE */
1543 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
1544
1545 #define SET_CANIDLE(clock, bit) \
1546 if (diff & (1 << bit)) { \
1547 clk = omap_findclk(s, clock); \
1548 omap_clk_canidle(clk, (value >> bit) & 1); \
1549 }
1550 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1551 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1552 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1553 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1554 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1555 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1556 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1557 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1558 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1559 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1560 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1561 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1562 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1563 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1564 }
1565
1566 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1567 uint16_t diff, uint16_t value)
1568 {
1569 omap_clk clk;
1570
1571 #define SET_ONOFF(clock, bit) \
1572 if (diff & (1 << bit)) { \
1573 clk = omap_findclk(s, clock); \
1574 omap_clk_onoff(clk, (value >> bit) & 1); \
1575 }
1576 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1577 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1578 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1579 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1580 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1581 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1582 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1583 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1584 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1585 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1586 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1587 }
1588
1589 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1590 uint16_t diff, uint16_t value)
1591 {
1592 omap_clk clk;
1593
1594 if (diff & (3 << 4)) { /* TCLKOUT */
1595 clk = omap_findclk(s, "tclk_out");
1596 switch ((value >> 4) & 3) {
1597 case 1:
1598 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1599 omap_clk_onoff(clk, 1);
1600 break;
1601 case 2:
1602 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1603 omap_clk_onoff(clk, 1);
1604 break;
1605 default:
1606 omap_clk_onoff(clk, 0);
1607 }
1608 }
1609 if (diff & (3 << 2)) { /* DCLKOUT */
1610 clk = omap_findclk(s, "dclk_out");
1611 switch ((value >> 2) & 3) {
1612 case 0:
1613 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1614 break;
1615 case 1:
1616 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1617 break;
1618 case 2:
1619 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1620 break;
1621 case 3:
1622 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1623 break;
1624 }
1625 }
1626 if (diff & (3 << 0)) { /* ACLKOUT */
1627 clk = omap_findclk(s, "aclk_out");
1628 switch ((value >> 0) & 3) {
1629 case 1:
1630 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1631 omap_clk_onoff(clk, 1);
1632 break;
1633 case 2:
1634 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1635 omap_clk_onoff(clk, 1);
1636 break;
1637 case 3:
1638 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1639 omap_clk_onoff(clk, 1);
1640 break;
1641 default:
1642 omap_clk_onoff(clk, 0);
1643 }
1644 }
1645 }
1646
1647 static void omap_clkm_write(void *opaque, hwaddr addr,
1648 uint64_t value, unsigned size)
1649 {
1650 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1651 uint16_t diff;
1652 omap_clk clk;
1653 static const char *clkschemename[8] = {
1654 "fully synchronous", "fully asynchronous", "synchronous scalable",
1655 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1656 };
1657
1658 if (size != 2) {
1659 omap_badwidth_write16(opaque, addr, value);
1660 return;
1661 }
1662
1663 switch (addr) {
1664 case 0x00: /* ARM_CKCTL */
1665 diff = s->clkm.arm_ckctl ^ value;
1666 s->clkm.arm_ckctl = value & 0x7fff;
1667 omap_clkm_ckctl_update(s, diff, value);
1668 return;
1669
1670 case 0x04: /* ARM_IDLECT1 */
1671 diff = s->clkm.arm_idlect1 ^ value;
1672 s->clkm.arm_idlect1 = value & 0x0fff;
1673 omap_clkm_idlect1_update(s, diff, value);
1674 return;
1675
1676 case 0x08: /* ARM_IDLECT2 */
1677 diff = s->clkm.arm_idlect2 ^ value;
1678 s->clkm.arm_idlect2 = value & 0x07ff;
1679 omap_clkm_idlect2_update(s, diff, value);
1680 return;
1681
1682 case 0x0c: /* ARM_EWUPCT */
1683 s->clkm.arm_ewupct = value & 0x003f;
1684 return;
1685
1686 case 0x10: /* ARM_RSTCT1 */
1687 diff = s->clkm.arm_rstct1 ^ value;
1688 s->clkm.arm_rstct1 = value & 0x0007;
1689 if (value & 9) {
1690 qemu_system_reset_request();
1691 s->clkm.cold_start = 0xa;
1692 }
1693 if (diff & ~value & 4) { /* DSP_RST */
1694 omap_mpui_reset(s);
1695 omap_tipb_bridge_reset(s->private_tipb);
1696 omap_tipb_bridge_reset(s->public_tipb);
1697 }
1698 if (diff & 2) { /* DSP_EN */
1699 clk = omap_findclk(s, "dsp_ck");
1700 omap_clk_canidle(clk, (~value >> 1) & 1);
1701 }
1702 return;
1703
1704 case 0x14: /* ARM_RSTCT2 */
1705 s->clkm.arm_rstct2 = value & 0x0001;
1706 return;
1707
1708 case 0x18: /* ARM_SYSST */
1709 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1710 s->clkm.clocking_scheme = (value >> 11) & 7;
1711 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
1712 clkschemename[s->clkm.clocking_scheme]);
1713 }
1714 s->clkm.cold_start &= value & 0x3f;
1715 return;
1716
1717 case 0x1c: /* ARM_CKOUT1 */
1718 diff = s->clkm.arm_ckout1 ^ value;
1719 s->clkm.arm_ckout1 = value & 0x003f;
1720 omap_clkm_ckout1_update(s, diff, value);
1721 return;
1722
1723 case 0x20: /* ARM_CKOUT2 */
1724 default:
1725 OMAP_BAD_REG(addr);
1726 }
1727 }
1728
1729 static const MemoryRegionOps omap_clkm_ops = {
1730 .read = omap_clkm_read,
1731 .write = omap_clkm_write,
1732 .endianness = DEVICE_NATIVE_ENDIAN,
1733 };
1734
1735 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
1736 unsigned size)
1737 {
1738 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1739 CPUState *cpu = CPU(s->cpu);
1740
1741 if (size != 2) {
1742 return omap_badwidth_read16(opaque, addr);
1743 }
1744
1745 switch (addr) {
1746 case 0x04: /* DSP_IDLECT1 */
1747 return s->clkm.dsp_idlect1;
1748
1749 case 0x08: /* DSP_IDLECT2 */
1750 return s->clkm.dsp_idlect2;
1751
1752 case 0x14: /* DSP_RSTCT2 */
1753 return s->clkm.dsp_rstct2;
1754
1755 case 0x18: /* DSP_SYSST */
1756 cpu = CPU(s->cpu);
1757 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
1758 (cpu->halted << 6); /* Quite useless... */
1759 }
1760
1761 OMAP_BAD_REG(addr);
1762 return 0;
1763 }
1764
1765 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1766 uint16_t diff, uint16_t value)
1767 {
1768 omap_clk clk;
1769
1770 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1771 }
1772
1773 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1774 uint16_t diff, uint16_t value)
1775 {
1776 omap_clk clk;
1777
1778 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1779 }
1780
1781 static void omap_clkdsp_write(void *opaque, hwaddr addr,
1782 uint64_t value, unsigned size)
1783 {
1784 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1785 uint16_t diff;
1786
1787 if (size != 2) {
1788 omap_badwidth_write16(opaque, addr, value);
1789 return;
1790 }
1791
1792 switch (addr) {
1793 case 0x04: /* DSP_IDLECT1 */
1794 diff = s->clkm.dsp_idlect1 ^ value;
1795 s->clkm.dsp_idlect1 = value & 0x01f7;
1796 omap_clkdsp_idlect1_update(s, diff, value);
1797 break;
1798
1799 case 0x08: /* DSP_IDLECT2 */
1800 s->clkm.dsp_idlect2 = value & 0x0037;
1801 diff = s->clkm.dsp_idlect1 ^ value;
1802 omap_clkdsp_idlect2_update(s, diff, value);
1803 break;
1804
1805 case 0x14: /* DSP_RSTCT2 */
1806 s->clkm.dsp_rstct2 = value & 0x0001;
1807 break;
1808
1809 case 0x18: /* DSP_SYSST */
1810 s->clkm.cold_start &= value & 0x3f;
1811 break;
1812
1813 default:
1814 OMAP_BAD_REG(addr);
1815 }
1816 }
1817
1818 static const MemoryRegionOps omap_clkdsp_ops = {
1819 .read = omap_clkdsp_read,
1820 .write = omap_clkdsp_write,
1821 .endianness = DEVICE_NATIVE_ENDIAN,
1822 };
1823
1824 static void omap_clkm_reset(struct omap_mpu_state_s *s)
1825 {
1826 if (s->wdt && s->wdt->reset)
1827 s->clkm.cold_start = 0x6;
1828 s->clkm.clocking_scheme = 0;
1829 omap_clkm_ckctl_update(s, ~0, 0x3000);
1830 s->clkm.arm_ckctl = 0x3000;
1831 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
1832 s->clkm.arm_idlect1 = 0x0400;
1833 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
1834 s->clkm.arm_idlect2 = 0x0100;
1835 s->clkm.arm_ewupct = 0x003f;
1836 s->clkm.arm_rstct1 = 0x0000;
1837 s->clkm.arm_rstct2 = 0x0000;
1838 s->clkm.arm_ckout1 = 0x0015;
1839 s->clkm.dpll1_mode = 0x2002;
1840 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1841 s->clkm.dsp_idlect1 = 0x0040;
1842 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1843 s->clkm.dsp_idlect2 = 0x0000;
1844 s->clkm.dsp_rstct2 = 0x0000;
1845 }
1846
1847 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
1848 hwaddr dsp_base, struct omap_mpu_state_s *s)
1849 {
1850 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
1851 "omap-clkm", 0x100);
1852 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
1853 "omap-clkdsp", 0x1000);
1854
1855 s->clkm.arm_idlect1 = 0x03ff;
1856 s->clkm.arm_idlect2 = 0x0100;
1857 s->clkm.dsp_idlect1 = 0x0002;
1858 omap_clkm_reset(s);
1859 s->clkm.cold_start = 0x3a;
1860
1861 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
1862 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
1863 }
1864
1865 /* MPU I/O */
1866 struct omap_mpuio_s {
1867 qemu_irq irq;
1868 qemu_irq kbd_irq;
1869 qemu_irq *in;
1870 qemu_irq handler[16];
1871 qemu_irq wakeup;
1872 MemoryRegion iomem;
1873
1874 uint16_t inputs;
1875 uint16_t outputs;
1876 uint16_t dir;
1877 uint16_t edge;
1878 uint16_t mask;
1879 uint16_t ints;
1880
1881 uint16_t debounce;
1882 uint16_t latch;
1883 uint8_t event;
1884
1885 uint8_t buttons[5];
1886 uint8_t row_latch;
1887 uint8_t cols;
1888 int kbd_mask;
1889 int clk;
1890 };
1891
1892 static void omap_mpuio_set(void *opaque, int line, int level)
1893 {
1894 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1895 uint16_t prev = s->inputs;
1896
1897 if (level)
1898 s->inputs |= 1 << line;
1899 else
1900 s->inputs &= ~(1 << line);
1901
1902 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1903 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1904 s->ints |= 1 << line;
1905 qemu_irq_raise(s->irq);
1906 /* TODO: wakeup */
1907 }
1908 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1909 (s->event >> 1) == line) /* PIN_SELECT */
1910 s->latch = s->inputs;
1911 }
1912 }
1913
1914 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1915 {
1916 int i;
1917 uint8_t *row, rows = 0, cols = ~s->cols;
1918
1919 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
1920 if (*row & cols)
1921 rows |= i;
1922
1923 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1924 s->row_latch = ~rows;
1925 }
1926
1927 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
1928 unsigned size)
1929 {
1930 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1931 int offset = addr & OMAP_MPUI_REG_MASK;
1932 uint16_t ret;
1933
1934 if (size != 2) {
1935 return omap_badwidth_read16(opaque, addr);
1936 }
1937
1938 switch (offset) {
1939 case 0x00: /* INPUT_LATCH */
1940 return s->inputs;
1941
1942 case 0x04: /* OUTPUT_REG */
1943 return s->outputs;
1944
1945 case 0x08: /* IO_CNTL */
1946 return s->dir;
1947
1948 case 0x10: /* KBR_LATCH */
1949 return s->row_latch;
1950
1951 case 0x14: /* KBC_REG */
1952 return s->cols;
1953
1954 case 0x18: /* GPIO_EVENT_MODE_REG */
1955 return s->event;
1956
1957 case 0x1c: /* GPIO_INT_EDGE_REG */
1958 return s->edge;
1959
1960 case 0x20: /* KBD_INT */
1961 return (~s->row_latch & 0x1f) && !s->kbd_mask;
1962
1963 case 0x24: /* GPIO_INT */
1964 ret = s->ints;
1965 s->ints &= s->mask;
1966 if (ret)
1967 qemu_irq_lower(s->irq);
1968 return ret;
1969
1970 case 0x28: /* KBD_MASKIT */
1971 return s->kbd_mask;
1972
1973 case 0x2c: /* GPIO_MASKIT */
1974 return s->mask;
1975
1976 case 0x30: /* GPIO_DEBOUNCING_REG */
1977 return s->debounce;
1978
1979 case 0x34: /* GPIO_LATCH_REG */
1980 return s->latch;
1981 }
1982
1983 OMAP_BAD_REG(addr);
1984 return 0;
1985 }
1986
1987 static void omap_mpuio_write(void *opaque, hwaddr addr,
1988 uint64_t value, unsigned size)
1989 {
1990 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1991 int offset = addr & OMAP_MPUI_REG_MASK;
1992 uint16_t diff;
1993 int ln;
1994
1995 if (size != 2) {
1996 omap_badwidth_write16(opaque, addr, value);
1997 return;
1998 }
1999
2000 switch (offset) {
2001 case 0x04: /* OUTPUT_REG */
2002 diff = (s->outputs ^ value) & ~s->dir;
2003 s->outputs = value;
2004 while ((ln = ctz32(diff)) != 32) {
2005 if (s->handler[ln])
2006 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2007 diff &= ~(1 << ln);
2008 }
2009 break;
2010
2011 case 0x08: /* IO_CNTL */
2012 diff = s->outputs & (s->dir ^ value);
2013 s->dir = value;
2014
2015 value = s->outputs & ~s->dir;
2016 while ((ln = ctz32(diff)) != 32) {
2017 if (s->handler[ln])
2018 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2019 diff &= ~(1 << ln);
2020 }
2021 break;
2022
2023 case 0x14: /* KBC_REG */
2024 s->cols = value;
2025 omap_mpuio_kbd_update(s);
2026 break;
2027
2028 case 0x18: /* GPIO_EVENT_MODE_REG */
2029 s->event = value & 0x1f;
2030 break;
2031
2032 case 0x1c: /* GPIO_INT_EDGE_REG */
2033 s->edge = value;
2034 break;
2035
2036 case 0x28: /* KBD_MASKIT */
2037 s->kbd_mask = value & 1;
2038 omap_mpuio_kbd_update(s);
2039 break;
2040
2041 case 0x2c: /* GPIO_MASKIT */
2042 s->mask = value;
2043 break;
2044
2045 case 0x30: /* GPIO_DEBOUNCING_REG */
2046 s->debounce = value & 0x1ff;
2047 break;
2048
2049 case 0x00: /* INPUT_LATCH */
2050 case 0x10: /* KBR_LATCH */
2051 case 0x20: /* KBD_INT */
2052 case 0x24: /* GPIO_INT */
2053 case 0x34: /* GPIO_LATCH_REG */
2054 OMAP_RO_REG(addr);
2055 return;
2056
2057 default:
2058 OMAP_BAD_REG(addr);
2059 return;
2060 }
2061 }
2062
2063 static const MemoryRegionOps omap_mpuio_ops = {
2064 .read = omap_mpuio_read,
2065 .write = omap_mpuio_write,
2066 .endianness = DEVICE_NATIVE_ENDIAN,
2067 };
2068
2069 static void omap_mpuio_reset(struct omap_mpuio_s *s)
2070 {
2071 s->inputs = 0;
2072 s->outputs = 0;
2073 s->dir = ~0;
2074 s->event = 0;
2075 s->edge = 0;
2076 s->kbd_mask = 0;
2077 s->mask = 0;
2078 s->debounce = 0;
2079 s->latch = 0;
2080 s->ints = 0;
2081 s->row_latch = 0x1f;
2082 s->clk = 1;
2083 }
2084
2085 static void omap_mpuio_onoff(void *opaque, int line, int on)
2086 {
2087 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2088
2089 s->clk = on;
2090 if (on)
2091 omap_mpuio_kbd_update(s);
2092 }
2093
2094 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
2095 hwaddr base,
2096 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2097 omap_clk clk)
2098 {
2099 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
2100
2101 s->irq = gpio_int;
2102 s->kbd_irq = kbd_int;
2103 s->wakeup = wakeup;
2104 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2105 omap_mpuio_reset(s);
2106
2107 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
2108 "omap-mpuio", 0x800);
2109 memory_region_add_subregion(memory, base, &s->iomem);
2110
2111 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0));
2112
2113 return s;
2114 }
2115
2116 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2117 {
2118 return s->in;
2119 }
2120
2121 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2122 {
2123 if (line >= 16 || line < 0)
2124 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
2125 s->handler[line] = handler;
2126 }
2127
2128 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2129 {
2130 if (row >= 5 || row < 0)
2131 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
2132
2133 if (down)
2134 s->buttons[row] |= 1 << col;
2135 else
2136 s->buttons[row] &= ~(1 << col);
2137
2138 omap_mpuio_kbd_update(s);
2139 }
2140
2141 /* MicroWire Interface */
2142 struct omap_uwire_s {
2143 MemoryRegion iomem;
2144 qemu_irq txirq;
2145 qemu_irq rxirq;
2146 qemu_irq txdrq;
2147
2148 uint16_t txbuf;
2149 uint16_t rxbuf;
2150 uint16_t control;
2151 uint16_t setup[5];
2152
2153 uWireSlave *chip[4];
2154 };
2155
2156 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2157 {
2158 int chipselect = (s->control >> 10) & 3; /* INDEX */
2159 uWireSlave *slave = s->chip[chipselect];
2160
2161 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2162 if (s->control & (1 << 12)) /* CS_CMD */
2163 if (slave && slave->send)
2164 slave->send(slave->opaque,
2165 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2166 s->control &= ~(1 << 14); /* CSRB */
2167 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2168 * a DRQ. When is the level IRQ supposed to be reset? */
2169 }
2170
2171 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2172 if (s->control & (1 << 12)) /* CS_CMD */
2173 if (slave && slave->receive)
2174 s->rxbuf = slave->receive(slave->opaque);
2175 s->control |= 1 << 15; /* RDRB */
2176 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2177 * a DRQ. When is the level IRQ supposed to be reset? */
2178 }
2179 }
2180
2181 static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
2182 unsigned size)
2183 {
2184 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
2185 int offset = addr & OMAP_MPUI_REG_MASK;
2186
2187 if (size != 2) {
2188 return omap_badwidth_read16(opaque, addr);
2189 }
2190
2191 switch (offset) {
2192 case 0x00: /* RDR */
2193 s->control &= ~(1 << 15); /* RDRB */
2194 return s->rxbuf;
2195
2196 case 0x04: /* CSR */
2197 return s->control;
2198
2199 case 0x08: /* SR1 */
2200 return s->setup[0];
2201 case 0x0c: /* SR2 */
2202 return s->setup[1];
2203 case 0x10: /* SR3 */
2204 return s->setup[2];
2205 case 0x14: /* SR4 */
2206 return s->setup[3];
2207 case 0x18: /* SR5 */
2208 return s->setup[4];
2209 }
2210
2211 OMAP_BAD_REG(addr);
2212 return 0;
2213 }
2214
2215 static void omap_uwire_write(void *opaque, hwaddr addr,
2216 uint64_t value, unsigned size)
2217 {
2218 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
2219 int offset = addr & OMAP_MPUI_REG_MASK;
2220
2221 if (size != 2) {
2222 omap_badwidth_write16(opaque, addr, value);
2223 return;
2224 }
2225
2226 switch (offset) {
2227 case 0x00: /* TDR */
2228 s->txbuf = value; /* TD */
2229 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2230 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2231 (s->control & (1 << 12)))) { /* CS_CMD */
2232 s->control |= 1 << 14; /* CSRB */
2233 omap_uwire_transfer_start(s);
2234 }
2235 break;
2236
2237 case 0x04: /* CSR */
2238 s->control = value & 0x1fff;
2239 if (value & (1 << 13)) /* START */
2240 omap_uwire_transfer_start(s);
2241 break;
2242
2243 case 0x08: /* SR1 */
2244 s->setup[0] = value & 0x003f;
2245 break;
2246
2247 case 0x0c: /* SR2 */
2248 s->setup[1] = value & 0x0fc0;
2249 break;
2250
2251 case 0x10: /* SR3 */
2252 s->setup[2] = value & 0x0003;
2253 break;
2254
2255 case 0x14: /* SR4 */
2256 s->setup[3] = value & 0x0001;
2257 break;
2258
2259 case 0x18: /* SR5 */
2260 s->setup[4] = value & 0x000f;
2261 break;
2262
2263 default:
2264 OMAP_BAD_REG(addr);
2265 return;
2266 }
2267 }
2268
2269 static const MemoryRegionOps omap_uwire_ops = {
2270 .read = omap_uwire_read,
2271 .write = omap_uwire_write,
2272 .endianness = DEVICE_NATIVE_ENDIAN,
2273 };
2274
2275 static void omap_uwire_reset(struct omap_uwire_s *s)
2276 {
2277 s->control = 0;
2278 s->setup[0] = 0;
2279 s->setup[1] = 0;
2280 s->setup[2] = 0;
2281 s->setup[3] = 0;
2282 s->setup[4] = 0;
2283 }
2284
2285 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
2286 hwaddr base,
2287 qemu_irq txirq, qemu_irq rxirq,
2288 qemu_irq dma,
2289 omap_clk clk)
2290 {
2291 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
2292
2293 s->txirq = txirq;
2294 s->rxirq = rxirq;
2295 s->txdrq = dma;
2296 omap_uwire_reset(s);
2297
2298 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
2299 memory_region_add_subregion(system_memory, base, &s->iomem);
2300
2301 return s;
2302 }
2303
2304 void omap_uwire_attach(struct omap_uwire_s *s,
2305 uWireSlave *slave, int chipselect)
2306 {
2307 if (chipselect < 0 || chipselect > 3) {
2308 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
2309 exit(-1);
2310 }
2311
2312 s->chip[chipselect] = slave;
2313 }
2314
2315 /* Pseudonoise Pulse-Width Light Modulator */
2316 struct omap_pwl_s {
2317 MemoryRegion iomem;
2318 uint8_t output;
2319 uint8_t level;
2320 uint8_t enable;
2321 int clk;
2322 };
2323
2324 static void omap_pwl_update(struct omap_pwl_s *s)
2325 {
2326 int output = (s->clk && s->enable) ? s->level : 0;
2327
2328 if (output != s->output) {
2329 s->output = output;
2330 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
2331 }
2332 }
2333
2334 static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
2335 unsigned size)
2336 {
2337 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
2338 int offset = addr & OMAP_MPUI_REG_MASK;
2339
2340 if (size != 1) {
2341 return omap_badwidth_read8(opaque, addr);
2342 }
2343
2344 switch (offset) {
2345 case 0x00: /* PWL_LEVEL */
2346 return s->level;
2347 case 0x04: /* PWL_CTRL */
2348 return s->enable;
2349 }
2350 OMAP_BAD_REG(addr);
2351 return 0;
2352 }
2353
2354 static void omap_pwl_write(void *opaque, hwaddr addr,
2355 uint64_t value, unsigned size)
2356 {
2357 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
2358 int offset = addr & OMAP_MPUI_REG_MASK;
2359
2360 if (size != 1) {
2361 omap_badwidth_write8(opaque, addr, value);
2362 return;
2363 }
2364
2365 switch (offset) {
2366 case 0x00: /* PWL_LEVEL */
2367 s->level = value;
2368 omap_pwl_update(s);
2369 break;
2370 case 0x04: /* PWL_CTRL */
2371 s->enable = value & 1;
2372 omap_pwl_update(s);
2373 break;
2374 default:
2375 OMAP_BAD_REG(addr);
2376 return;
2377 }
2378 }
2379
2380 static const MemoryRegionOps omap_pwl_ops = {
2381 .read = omap_pwl_read,
2382 .write = omap_pwl_write,
2383 .endianness = DEVICE_NATIVE_ENDIAN,
2384 };
2385
2386 static void omap_pwl_reset(struct omap_pwl_s *s)
2387 {
2388 s->output = 0;
2389 s->level = 0;
2390 s->enable = 0;
2391 s->clk = 1;
2392 omap_pwl_update(s);
2393 }
2394
2395 static void omap_pwl_clk_update(void *opaque, int line, int on)
2396 {
2397 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
2398
2399 s->clk = on;
2400 omap_pwl_update(s);
2401 }
2402
2403 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
2404 hwaddr base,
2405 omap_clk clk)
2406 {
2407 struct omap_pwl_s *s = g_malloc0(sizeof(*s));
2408
2409 omap_pwl_reset(s);
2410
2411 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
2412 "omap-pwl", 0x800);
2413 memory_region_add_subregion(system_memory, base, &s->iomem);
2414
2415 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0));
2416 return s;
2417 }
2418
2419 /* Pulse-Width Tone module */
2420 struct omap_pwt_s {
2421 MemoryRegion iomem;
2422 uint8_t frc;
2423 uint8_t vrc;
2424 uint8_t gcr;
2425 omap_clk clk;
2426 };
2427
2428 static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
2429 unsigned size)
2430 {
2431 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
2432 int offset = addr & OMAP_MPUI_REG_MASK;
2433
2434 if (size != 1) {
2435 return omap_badwidth_read8(opaque, addr);
2436 }
2437
2438 switch (offset) {
2439 case 0x00: /* FRC */
2440 return s->frc;
2441 case 0x04: /* VCR */
2442 return s->vrc;
2443 case 0x08: /* GCR */
2444 return s->gcr;
2445 }
2446 OMAP_BAD_REG(addr);
2447 return 0;
2448 }
2449
2450 static void omap_pwt_write(void *opaque, hwaddr addr,
2451 uint64_t value, unsigned size)
2452 {
2453 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
2454 int offset = addr & OMAP_MPUI_REG_MASK;
2455
2456 if (size != 1) {
2457 omap_badwidth_write8(opaque, addr, value);
2458 return;
2459 }
2460
2461 switch (offset) {
2462 case 0x00: /* FRC */
2463 s->frc = value & 0x3f;
2464 break;
2465 case 0x04: /* VRC */
2466 if ((value ^ s->vrc) & 1) {
2467 if (value & 1)
2468 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
2469 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2470 ((omap_clk_getrate(s->clk) >> 3) /
2471 /* Pre-multiplexer divider */
2472 ((s->gcr & 2) ? 1 : 154) /
2473 /* Octave multiplexer */
2474 (2 << (value & 3)) *
2475 /* 101/107 divider */
2476 ((value & (1 << 2)) ? 101 : 107) *
2477 /* 49/55 divider */
2478 ((value & (1 << 3)) ? 49 : 55) *
2479 /* 50/63 divider */
2480 ((value & (1 << 4)) ? 50 : 63) *
2481 /* 80/127 divider */
2482 ((value & (1 << 5)) ? 80 : 127) /
2483 (107 * 55 * 63 * 127)));
2484 else
2485 printf("%s: silence!\n", __FUNCTION__);
2486 }
2487 s->vrc = value & 0x7f;
2488 break;
2489 case 0x08: /* GCR */
2490 s->gcr = value & 3;
2491 break;
2492 default:
2493 OMAP_BAD_REG(addr);
2494 return;
2495 }
2496 }
2497
2498 static const MemoryRegionOps omap_pwt_ops = {
2499 .read =omap_pwt_read,
2500 .write = omap_pwt_write,
2501 .endianness = DEVICE_NATIVE_ENDIAN,
2502 };
2503
2504 static void omap_pwt_reset(struct omap_pwt_s *s)
2505 {
2506 s->frc = 0;
2507 s->vrc = 0;
2508 s->gcr = 0;
2509 }
2510
2511 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
2512 hwaddr base,
2513 omap_clk clk)
2514 {
2515 struct omap_pwt_s *s = g_malloc0(sizeof(*s));
2516 s->clk = clk;
2517 omap_pwt_reset(s);
2518
2519 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
2520 "omap-pwt", 0x800);
2521 memory_region_add_subregion(system_memory, base, &s->iomem);
2522 return s;
2523 }
2524
2525 /* Real-time Clock module */
2526 struct omap_rtc_s {
2527 MemoryRegion iomem;
2528 qemu_irq irq;
2529 qemu_irq alarm;
2530 QEMUTimer *clk;
2531
2532 uint8_t interrupts;
2533 uint8_t status;
2534 int16_t comp_reg;
2535 int running;
2536 int pm_am;
2537 int auto_comp;
2538 int round;
2539 struct tm alarm_tm;
2540 time_t alarm_ti;
2541
2542 struct tm current_tm;
2543 time_t ti;
2544 uint64_t tick;
2545 };
2546
2547 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2548 {
2549 /* s->alarm is level-triggered */
2550 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2551 }
2552
2553 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2554 {
2555 s->alarm_ti = mktimegm(&s->alarm_tm);
2556 if (s->alarm_ti == -1)
2557 printf("%s: conversion failed\n", __FUNCTION__);
2558 }
2559
2560 static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
2561 unsigned size)
2562 {
2563 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
2564 int offset = addr & OMAP_MPUI_REG_MASK;
2565 uint8_t i;
2566
2567 if (size != 1) {
2568 return omap_badwidth_read8(opaque, addr);
2569 }
2570
2571 switch (offset) {
2572 case 0x00: /* SECONDS_REG */
2573 return to_bcd(s->current_tm.tm_sec);
2574
2575 case 0x04: /* MINUTES_REG */
2576 return to_bcd(s->current_tm.tm_min);
2577
2578 case 0x08: /* HOURS_REG */
2579 if (s->pm_am)
2580 return ((s->current_tm.tm_hour > 11) << 7) |
2581 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
2582 else
2583 return to_bcd(s->current_tm.tm_hour);
2584
2585 case 0x0c: /* DAYS_REG */
2586 return to_bcd(s->current_tm.tm_mday);
2587
2588 case 0x10: /* MONTHS_REG */
2589 return to_bcd(s->current_tm.tm_mon + 1);
2590
2591 case 0x14: /* YEARS_REG */
2592 return to_bcd(s->current_tm.tm_year % 100);
2593
2594 case 0x18: /* WEEK_REG */
2595 return s->current_tm.tm_wday;
2596
2597 case 0x20: /* ALARM_SECONDS_REG */
2598 return to_bcd(s->alarm_tm.tm_sec);
2599
2600 case 0x24: /* ALARM_MINUTES_REG */
2601 return to_bcd(s->alarm_tm.tm_min);
2602
2603 case 0x28: /* ALARM_HOURS_REG */
2604 if (s->pm_am)
2605 return ((s->alarm_tm.tm_hour > 11) << 7) |
2606 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
2607 else
2608 return to_bcd(s->alarm_tm.tm_hour);
2609
2610 case 0x2c: /* ALARM_DAYS_REG */
2611 return to_bcd(s->alarm_tm.tm_mday);
2612
2613 case 0x30: /* ALARM_MONTHS_REG */
2614 return to_bcd(s->alarm_tm.tm_mon + 1);
2615
2616 case 0x34: /* ALARM_YEARS_REG */
2617 return to_bcd(s->alarm_tm.tm_year % 100);
2618
2619 case 0x40: /* RTC_CTRL_REG */
2620 return (s->pm_am << 3) | (s->auto_comp << 2) |
2621 (s->round << 1) | s->running;
2622
2623 case 0x44: /* RTC_STATUS_REG */
2624 i = s->status;
2625 s->status &= ~0x3d;
2626 return i;
2627
2628 case 0x48: /* RTC_INTERRUPTS_REG */
2629 return s->interrupts;
2630
2631 case 0x4c: /* RTC_COMP_LSB_REG */
2632 return ((uint16_t) s->comp_reg) & 0xff;
2633
2634 case 0x50: /* RTC_COMP_MSB_REG */
2635 return ((uint16_t) s->comp_reg) >> 8;
2636 }
2637
2638 OMAP_BAD_REG(addr);
2639 return 0;
2640 }
2641
2642 static void omap_rtc_write(void *opaque, hwaddr addr,
2643 uint64_t value, unsigned size)
2644 {
2645 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
2646 int offset = addr & OMAP_MPUI_REG_MASK;
2647 struct tm new_tm;
2648 time_t ti[2];
2649
2650 if (size != 1) {
2651 omap_badwidth_write8(opaque, addr, value);
2652 return;
2653 }
2654
2655 switch (offset) {
2656 case 0x00: /* SECONDS_REG */
2657 #ifdef ALMDEBUG
2658 printf("RTC SEC_REG <-- %02x\n", value);
2659 #endif
2660 s->ti -= s->current_tm.tm_sec;
2661 s->ti += from_bcd(value);
2662 return;
2663
2664 case 0x04: /* MINUTES_REG */
2665 #ifdef ALMDEBUG
2666 printf("RTC MIN_REG <-- %02x\n", value);
2667 #endif
2668 s->ti -= s->current_tm.tm_min * 60;
2669 s->ti += from_bcd(value) * 60;
2670 return;
2671
2672 case 0x08: /* HOURS_REG */
2673 #ifdef ALMDEBUG
2674 printf("RTC HRS_REG <-- %02x\n", value);
2675 #endif
2676 s->ti -= s->current_tm.tm_hour * 3600;
2677 if (s->pm_am) {
2678 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
2679 s->ti += ((value >> 7) & 1) * 43200;
2680 } else
2681 s->ti += from_bcd(value & 0x3f) * 3600;
2682 return;
2683
2684 case 0x0c: /* DAYS_REG */
2685 #ifdef ALMDEBUG
2686 printf("RTC DAY_REG <-- %02x\n", value);
2687 #endif
2688 s->ti -= s->current_tm.tm_mday * 86400;
2689 s->ti += from_bcd(value) * 86400;
2690 return;
2691
2692 case 0x10: /* MONTHS_REG */
2693 #ifdef ALMDEBUG
2694 printf("RTC MTH_REG <-- %02x\n", value);
2695 #endif
2696 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2697 new_tm.tm_mon = from_bcd(value);
2698 ti[0] = mktimegm(&s->current_tm);
2699 ti[1] = mktimegm(&new_tm);
2700
2701 if (ti[0] != -1 && ti[1] != -1) {
2702 s->ti -= ti[0];
2703 s->ti += ti[1];
2704 } else {
2705 /* A less accurate version */
2706 s->ti -= s->current_tm.tm_mon * 2592000;
2707 s->ti += from_bcd(value) * 2592000;
2708 }
2709 return;
2710
2711 case 0x14: /* YEARS_REG */
2712 #ifdef ALMDEBUG
2713 printf("RTC YRS_REG <-- %02x\n", value);
2714 #endif
2715 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2716 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
2717 ti[0] = mktimegm(&s->current_tm);
2718 ti[1] = mktimegm(&new_tm);
2719
2720 if (ti[0] != -1 && ti[1] != -1) {
2721 s->ti -= ti[0];
2722 s->ti += ti[1];
2723 } else {
2724 /* A less accurate version */
2725 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000;
2726 s->ti += (time_t)from_bcd(value) * 31536000;
2727 }
2728 return;
2729
2730 case 0x18: /* WEEK_REG */
2731 return; /* Ignored */
2732
2733 case 0x20: /* ALARM_SECONDS_REG */
2734 #ifdef ALMDEBUG
2735 printf("ALM SEC_REG <-- %02x\n", value);
2736 #endif
2737 s->alarm_tm.tm_sec = from_bcd(value);
2738 omap_rtc_alarm_update(s);
2739 return;
2740
2741 case 0x24: /* ALARM_MINUTES_REG */
2742 #ifdef ALMDEBUG
2743 printf("ALM MIN_REG <-- %02x\n", value);
2744 #endif
2745 s->alarm_tm.tm_min = from_bcd(value);
2746 omap_rtc_alarm_update(s);
2747 return;
2748
2749 case 0x28: /* ALARM_HOURS_REG */
2750 #ifdef ALMDEBUG
2751 printf("ALM HRS_REG <-- %02x\n", value);
2752 #endif
2753 if (s->pm_am)
2754 s->alarm_tm.tm_hour =
2755 ((from_bcd(value & 0x3f)) % 12) +
2756 ((value >> 7) & 1) * 12;
2757 else
2758 s->alarm_tm.tm_hour = from_bcd(value);
2759 omap_rtc_alarm_update(s);
2760 return;
2761
2762 case 0x2c: /* ALARM_DAYS_REG */
2763 #ifdef ALMDEBUG
2764 printf("ALM DAY_REG <-- %02x\n", value);
2765 #endif
2766 s->alarm_tm.tm_mday = from_bcd(value);
2767 omap_rtc_alarm_update(s);
2768 return;
2769
2770 case 0x30: /* ALARM_MONTHS_REG */
2771 #ifdef ALMDEBUG
2772 printf("ALM MON_REG <-- %02x\n", value);
2773 #endif
2774 s->alarm_tm.tm_mon = from_bcd(value);
2775 omap_rtc_alarm_update(s);
2776 return;
2777
2778 case 0x34: /* ALARM_YEARS_REG */
2779 #ifdef ALMDEBUG
2780 printf("ALM YRS_REG <-- %02x\n", value);
2781 #endif
2782 s->alarm_tm.tm_year = from_bcd(value);
2783 omap_rtc_alarm_update(s);
2784 return;
2785
2786 case 0x40: /* RTC_CTRL_REG */
2787 #ifdef ALMDEBUG
2788 printf("RTC CONTROL <-- %02x\n", value);
2789 #endif
2790 s->pm_am = (value >> 3) & 1;
2791 s->auto_comp = (value >> 2) & 1;
2792 s->round = (value >> 1) & 1;
2793 s->running = value & 1;
2794 s->status &= 0xfd;
2795 s->status |= s->running << 1;
2796 return;
2797
2798 case 0x44: /* RTC_STATUS_REG */
2799 #ifdef ALMDEBUG
2800 printf("RTC STATUSL <-- %02x\n", value);
2801 #endif
2802 s->status &= ~((value & 0xc0) ^ 0x80);
2803 omap_rtc_interrupts_update(s);
2804 return;
2805
2806 case 0x48: /* RTC_INTERRUPTS_REG */
2807 #ifdef ALMDEBUG
2808 printf("RTC INTRS <-- %02x\n", value);
2809 #endif
2810 s->interrupts = value;
2811 return;
2812
2813 case 0x4c: /* RTC_COMP_LSB_REG */
2814 #ifdef ALMDEBUG
2815 printf("RTC COMPLSB <-- %02x\n", value);
2816 #endif
2817 s->comp_reg &= 0xff00;
2818 s->comp_reg |= 0x00ff & value;
2819 return;
2820
2821 case 0x50: /* RTC_COMP_MSB_REG */
2822 #ifdef ALMDEBUG
2823 printf("RTC COMPMSB <-- %02x\n", value);
2824 #endif
2825 s->comp_reg &= 0x00ff;
2826 s->comp_reg |= 0xff00 & (value << 8);
2827 return;
2828
2829 default:
2830 OMAP_BAD_REG(addr);
2831 return;
2832 }
2833 }
2834
2835 static const MemoryRegionOps omap_rtc_ops = {
2836 .read = omap_rtc_read,
2837 .write = omap_rtc_write,
2838 .endianness = DEVICE_NATIVE_ENDIAN,
2839 };
2840
2841 static void omap_rtc_tick(void *opaque)
2842 {
2843 struct omap_rtc_s *s = opaque;
2844
2845 if (s->round) {
2846 /* Round to nearest full minute. */
2847 if (s->current_tm.tm_sec < 30)
2848 s->ti -= s->current_tm.tm_sec;
2849 else
2850 s->ti += 60 - s->current_tm.tm_sec;
2851
2852 s->round = 0;
2853 }
2854
2855 localtime_r(&s->ti, &s->current_tm);
2856
2857 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2858 s->status |= 0x40;
2859 omap_rtc_interrupts_update(s);
2860 }
2861
2862 if (s->interrupts & 0x04)
2863 switch (s->interrupts & 3) {
2864 case 0:
2865 s->status |= 0x04;
2866 qemu_irq_pulse(s->irq);
2867 break;
2868 case 1:
2869 if (s->current_tm.tm_sec)
2870 break;
2871 s->status |= 0x08;
2872 qemu_irq_pulse(s->irq);
2873 break;
2874 case 2:
2875 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2876 break;
2877 s->status |= 0x10;
2878 qemu_irq_pulse(s->irq);
2879 break;
2880 case 3:
2881 if (s->current_tm.tm_sec ||
2882 s->current_tm.tm_min || s->current_tm.tm_hour)
2883 break;
2884 s->status |= 0x20;
2885 qemu_irq_pulse(s->irq);
2886 break;
2887 }
2888
2889 /* Move on */
2890 if (s->running)
2891 s->ti ++;
2892 s->tick += 1000;
2893
2894 /*
2895 * Every full hour add a rough approximation of the compensation
2896 * register to the 32kHz Timer (which drives the RTC) value.
2897 */
2898 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2899 s->tick += s->comp_reg * 1000 / 32768;
2900
2901 timer_mod(s->clk, s->tick);
2902 }
2903
2904 static void omap_rtc_reset(struct omap_rtc_s *s)
2905 {
2906 struct tm tm;
2907
2908 s->interrupts = 0;
2909 s->comp_reg = 0;
2910 s->running = 0;
2911 s->pm_am = 0;
2912 s->auto_comp = 0;
2913 s->round = 0;
2914 s->tick = qemu_clock_get_ms(rtc_clock);
2915 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2916 s->alarm_tm.tm_mday = 0x01;
2917 s->status = 1 << 7;
2918 qemu_get_timedate(&tm, 0);
2919 s->ti = mktimegm(&tm);
2920
2921 omap_rtc_alarm_update(s);
2922 omap_rtc_tick(s);
2923 }
2924
2925 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
2926 hwaddr base,
2927 qemu_irq timerirq, qemu_irq alarmirq,
2928 omap_clk clk)
2929 {
2930 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1);
2931
2932 s->irq = timerirq;
2933 s->alarm = alarmirq;
2934 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);
2935
2936 omap_rtc_reset(s);
2937
2938 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
2939 "omap-rtc", 0x800);
2940 memory_region_add_subregion(system_memory, base, &s->iomem);
2941
2942 return s;
2943 }
2944
2945 /* Multi-channel Buffered Serial Port interfaces */
2946 struct omap_mcbsp_s {
2947 MemoryRegion iomem;
2948 qemu_irq txirq;
2949 qemu_irq rxirq;
2950 qemu_irq txdrq;
2951 qemu_irq rxdrq;
2952
2953 uint16_t spcr[2];
2954 uint16_t rcr[2];
2955 uint16_t xcr[2];
2956 uint16_t srgr[2];
2957 uint16_t mcr[2];
2958 uint16_t pcr;
2959 uint16_t rcer[8];
2960 uint16_t xcer[8];
2961 int tx_rate;
2962 int rx_rate;
2963 int tx_req;
2964 int rx_req;
2965
2966 I2SCodec *codec;
2967 QEMUTimer *source_timer;
2968 QEMUTimer *sink_timer;
2969 };
2970
2971 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2972 {
2973 int irq;
2974
2975 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2976 case 0:
2977 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2978 break;
2979 case 3:
2980 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
2981 break;
2982 default:
2983 irq = 0;
2984 break;
2985 }
2986
2987 if (irq)
2988 qemu_irq_pulse(s->rxirq);
2989
2990 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
2991 case 0:
2992 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
2993 break;
2994 case 3:
2995 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
2996 break;
2997 default:
2998 irq = 0;
2999 break;
3000 }
3001
3002 if (irq)
3003 qemu_irq_pulse(s->txirq);
3004 }
3005
3006 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
3007 {
3008 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3009 s->spcr[0] |= 1 << 2; /* RFULL */
3010 s->spcr[0] |= 1 << 1; /* RRDY */
3011 qemu_irq_raise(s->rxdrq);
3012 omap_mcbsp_intr_update(s);
3013 }
3014
3015 static void omap_mcbsp_source_tick(void *opaque)
3016 {
3017 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3018 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3019
3020 if (!s->rx_rate)
3021 return;
3022 if (s->rx_req)
3023 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
3024
3025 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
3026
3027 omap_mcbsp_rx_newdata(s);
3028 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
3029 get_ticks_per_sec());
3030 }
3031
3032 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3033 {
3034 if (!s->codec || !s->codec->rts)
3035 omap_mcbsp_source_tick(s);
3036 else if (s->codec->in.len) {
3037 s->rx_req = s->codec->in.len;
3038 omap_mcbsp_rx_newdata(s);
3039 }
3040 }
3041
3042 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
3043 {
3044 timer_del(s->source_timer);
3045 }
3046
3047 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
3048 {
3049 s->spcr[0] &= ~(1 << 1); /* RRDY */
3050 qemu_irq_lower(s->rxdrq);
3051 omap_mcbsp_intr_update(s);
3052 }
3053
3054 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3055 {
3056 s->spcr[1] |= 1 << 1; /* XRDY */
3057 qemu_irq_raise(s->txdrq);
3058 omap_mcbsp_intr_update(s);
3059 }
3060
3061 static void omap_mcbsp_sink_tick(void *opaque)
3062 {
3063 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3064 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3065
3066 if (!s->tx_rate)
3067 return;
3068 if (s->tx_req)
3069 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3070
3071 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3072
3073 omap_mcbsp_tx_newdata(s);
3074 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
3075 get_ticks_per_sec());
3076 }
3077
3078 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3079 {
3080 if (!s->codec || !s->codec->cts)
3081 omap_mcbsp_sink_tick(s);
3082 else if (s->codec->out.size) {
3083 s->tx_req = s->codec->out.size;
3084 omap_mcbsp_tx_newdata(s);
3085 }
3086 }
3087
3088 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3089 {
3090 s->spcr[1] &= ~(1 << 1); /* XRDY */
3091 qemu_irq_lower(s->txdrq);
3092 omap_mcbsp_intr_update(s);
3093 if (s->codec && s->codec->cts)
3094 s->codec->tx_swallow(s->codec->opaque);
3095 }
3096
3097 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3098 {
3099 s->tx_req = 0;
3100 omap_mcbsp_tx_done(s);
3101 timer_del(s->sink_timer);
3102 }
3103
3104 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3105 {
3106 int prev_rx_rate, prev_tx_rate;
3107 int rx_rate = 0, tx_rate = 0;
3108 int cpu_rate = 1500000; /* XXX */
3109
3110 /* TODO: check CLKSTP bit */
3111 if (s->spcr[1] & (1 << 6)) { /* GRST */
3112 if (s->spcr[0] & (1 << 0)) { /* RRST */
3113 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3114 (s->pcr & (1 << 8))) { /* CLKRM */
3115 if (~s->pcr & (1 << 7)) /* SCLKME */
3116 rx_rate = cpu_rate /
3117 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3118 } else
3119 if (s->codec)
3120 rx_rate = s->codec->rx_rate;
3121 }
3122
3123 if (s->spcr[1] & (1 << 0)) { /* XRST */
3124 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3125 (s->pcr & (1 << 9))) { /* CLKXM */
3126 if (~s->pcr & (1 << 7)) /* SCLKME */
3127 tx_rate = cpu_rate /
3128 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3129 } else
3130 if (s->codec)
3131 tx_rate = s->codec->tx_rate;
3132 }
3133 }
3134 prev_tx_rate = s->tx_rate;
3135 prev_rx_rate = s->rx_rate;
3136 s->tx_rate = tx_rate;
3137 s->rx_rate = rx_rate;
3138
3139 if (s->codec)
3140 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3141
3142 if (!prev_tx_rate && tx_rate)
3143 omap_mcbsp_tx_start(s);
3144 else if (s->tx_rate && !tx_rate)
3145 omap_mcbsp_tx_stop(s);
3146
3147 if (!prev_rx_rate && rx_rate)
3148 omap_mcbsp_rx_start(s);
3149 else if (prev_tx_rate && !tx_rate)
3150 omap_mcbsp_rx_stop(s);
3151 }
3152
3153 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
3154 unsigned size)
3155 {
3156 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3157 int offset = addr & OMAP_MPUI_REG_MASK;
3158 uint16_t ret;
3159
3160 if (size != 2) {
3161 return omap_badwidth_read16(opaque, addr);
3162 }
3163
3164 switch (offset) {
3165 case 0x00: /* DRR2 */
3166 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3167 return 0x0000;
3168 /* Fall through. */
3169 case 0x02: /* DRR1 */
3170 if (s->rx_req < 2) {
3171 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
3172 omap_mcbsp_rx_done(s);
3173 } else {
3174 s->tx_req -= 2;
3175 if (s->codec && s->codec->in.len >= 2) {
3176 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3177 ret |= s->codec->in.fifo[s->codec->in.start ++];
3178 s->codec->in.len -= 2;
3179 } else
3180 ret = 0x0000;
3181 if (!s->tx_req)
3182 omap_mcbsp_rx_done(s);
3183 return ret;
3184 }
3185 return 0x0000;
3186
3187 case 0x04: /* DXR2 */
3188 case 0x06: /* DXR1 */
3189 return 0x0000;
3190
3191 case 0x08: /* SPCR2 */
3192 return s->spcr[1];
3193 case 0x0a: /* SPCR1 */
3194 return s->spcr[0];
3195 case 0x0c: /* RCR2 */
3196 return s->rcr[1];
3197 case 0x0e: /* RCR1 */
3198 return s->rcr[0];
3199 case 0x10: /* XCR2 */
3200 return s->xcr[1];
3201 case 0x12: /* XCR1 */
3202 return s->xcr[0];
3203 case 0x14: /* SRGR2 */
3204 return s->srgr[1];
3205 case 0x16: /* SRGR1 */
3206 return s->srgr[0];
3207 case 0x18: /* MCR2 */
3208 return s->mcr[1];
3209 case 0x1a: /* MCR1 */
3210 return s->mcr[0];
3211 case 0x1c: /* RCERA */
3212 return s->rcer[0];
3213 case 0x1e: /* RCERB */
3214 return s->rcer[1];
3215 case 0x20: /* XCERA */
3216 return s->xcer[0];
3217 case 0x22: /* XCERB */
3218 return s->xcer[1];
3219 case 0x24: /* PCR0 */
3220 return s->pcr;
3221 case 0x26: /* RCERC */
3222 return s->rcer[2];
3223 case 0x28: /* RCERD */
3224 return s->rcer[3];
3225 case 0x2a: /* XCERC */
3226 return s->xcer[2];
3227 case 0x2c: /* XCERD */
3228 return s->xcer[3];
3229 case 0x2e: /* RCERE */
3230 return s->rcer[4];
3231 case 0x30: /* RCERF */
3232 return s->rcer[5];
3233 case 0x32: /* XCERE */
3234 return s->xcer[4];
3235 case 0x34: /* XCERF */
3236 return s->xcer[5];
3237 case 0x36: /* RCERG */
3238 return s->rcer[6];
3239 case 0x38: /* RCERH */
3240 return s->rcer[7];
3241 case 0x3a: /* XCERG */
3242 return s->xcer[6];
3243 case 0x3c: /* XCERH */
3244 return s->xcer[7];
3245 }
3246
3247 OMAP_BAD_REG(addr);
3248 return 0;
3249 }
3250
3251 static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
3252 uint32_t value)
3253 {
3254 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3255 int offset = addr & OMAP_MPUI_REG_MASK;
3256
3257 switch (offset) {
3258 case 0x00: /* DRR2 */
3259 case 0x02: /* DRR1 */
3260 OMAP_RO_REG(addr);
3261 return;
3262
3263 case 0x04: /* DXR2 */
3264 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3265 return;
3266 /* Fall through. */
3267 case 0x06: /* DXR1 */
3268 if (s->tx_req > 1) {
3269 s->tx_req -= 2;
3270 if (s->codec && s->codec->cts) {
3271 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3272 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
3273 }
3274 if (s->tx_req < 2)
3275 omap_mcbsp_tx_done(s);
3276 } else
3277 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3278 return;
3279
3280 case 0x08: /* SPCR2 */
3281 s->spcr[1] &= 0x0002;
3282 s->spcr[1] |= 0x03f9 & value;
3283 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
3284 if (~value & 1) /* XRST */
3285 s->spcr[1] &= ~6;
3286 omap_mcbsp_req_update(s);
3287 return;
3288 case 0x0a: /* SPCR1 */
3289 s->spcr[0] &= 0x0006;
3290 s->spcr[0] |= 0xf8f9 & value;
3291 if (value & (1 << 15)) /* DLB */
3292 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
3293 if (~value & 1) { /* RRST */
3294 s->spcr[0] &= ~6;
3295 s->rx_req = 0;
3296 omap_mcbsp_rx_done(s);
3297 }
3298 omap_mcbsp_req_update(s);
3299 return;
3300
3301 case 0x0c: /* RCR2 */
3302 s->rcr[1] = value & 0xffff;
3303 return;
3304 case 0x0e: /* RCR1 */
3305 s->rcr[0] = value & 0x7fe0;
3306 return;
3307 case 0x10: /* XCR2 */
3308 s->xcr[1] = value & 0xffff;
3309 return;
3310 case 0x12: /* XCR1 */
3311 s->xcr[0] = value & 0x7fe0;
3312 return;
3313 case 0x14: /* SRGR2 */
3314 s->srgr[1] = value & 0xffff;
3315 omap_mcbsp_req_update(s);
3316 return;
3317 case 0x16: /* SRGR1 */
3318 s->srgr[0] = value & 0xffff;
3319 omap_mcbsp_req_update(s);
3320 return;
3321 case 0x18: /* MCR2 */
3322 s->mcr[1] = value & 0x03e3;
3323 if (value & 3) /* XMCM */
3324 printf("%s: Tx channel selection mode enable attempt\n",
3325 __FUNCTION__);
3326 return;
3327 case 0x1a: /* MCR1 */
3328 s->mcr[0] = value & 0x03e1;
3329 if (value & 1) /* RMCM */
3330 printf("%s: Rx channel selection mode enable attempt\n",
3331 __FUNCTION__);
3332 return;
3333 case 0x1c: /* RCERA */
3334 s->rcer[0] = value & 0xffff;
3335 return;
3336 case 0x1e: /* RCERB */
3337 s->rcer[1] = value & 0xffff;
3338 return;
3339 case 0x20: /* XCERA */
3340 s->xcer[0] = value & 0xffff;
3341 return;
3342 case 0x22: /* XCERB */
3343 s->xcer[1] = value & 0xffff;
3344 return;
3345 case 0x24: /* PCR0 */
3346 s->pcr = value & 0x7faf;
3347 return;
3348 case 0x26: /* RCERC */
3349 s->rcer[2] = value & 0xffff;
3350 return;
3351 case 0x28: /* RCERD */
3352 s->rcer[3] = value & 0xffff;
3353 return;
3354 case 0x2a: /* XCERC */
3355 s->xcer[2] = value & 0xffff;
3356 return;
3357 case 0x2c: /* XCERD */
3358 s->xcer[3] = value & 0xffff;
3359 return;
3360 case 0x2e: /* RCERE */
3361 s->rcer[4] = value & 0xffff;
3362 return;
3363 case 0x30: /* RCERF */
3364 s->rcer[5] = value & 0xffff;
3365 return;
3366 case 0x32: /* XCERE */
3367 s->xcer[4] = value & 0xffff;
3368 return;
3369 case 0x34: /* XCERF */
3370 s->xcer[5] = value & 0xffff;
3371 return;
3372 case 0x36: /* RCERG */
3373 s->rcer[6] = value & 0xffff;
3374 return;
3375 case 0x38: /* RCERH */
3376 s->rcer[7] = value & 0xffff;
3377 return;
3378 case 0x3a: /* XCERG */
3379 s->xcer[6] = value & 0xffff;
3380 return;
3381 case 0x3c: /* XCERH */
3382 s->xcer[7] = value & 0xffff;
3383 return;
3384 }
3385
3386 OMAP_BAD_REG(addr);
3387 }
3388
3389 static void omap_mcbsp_writew(void *opaque, hwaddr addr,
3390 uint32_t value)
3391 {
3392 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3393 int offset = addr & OMAP_MPUI_REG_MASK;
3394
3395 if (offset == 0x04) { /* DXR */
3396 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3397 return;
3398 if (s->tx_req > 3) {
3399 s->tx_req -= 4;
3400 if (s->codec && s->codec->cts) {
3401 s->codec->out.fifo[s->codec->out.len ++] =
3402 (value >> 24) & 0xff;
3403 s->codec->out.fifo[s->codec->out.len ++] =
3404 (value >> 16) & 0xff;
3405 s->codec->out.fifo[s->codec->out.len ++] =
3406 (value >> 8) & 0xff;
3407 s->codec->out.fifo[s->codec->out.len ++] =
3408 (value >> 0) & 0xff;
3409 }
3410 if (s->tx_req < 4)
3411 omap_mcbsp_tx_done(s);
3412 } else
3413 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3414 return;
3415 }
3416
3417 omap_badwidth_write16(opaque, addr, value);
3418 }
3419
3420 static void omap_mcbsp_write(void *opaque, hwaddr addr,
3421 uint64_t value, unsigned size)
3422 {
3423 switch (size) {
3424 case 2:
3425 omap_mcbsp_writeh(opaque, addr, value);
3426 break;
3427 case 4:
3428 omap_mcbsp_writew(opaque, addr, value);
3429 break;
3430 default:
3431 omap_badwidth_write16(opaque, addr, value);
3432 }
3433 }
3434
3435 static const MemoryRegionOps omap_mcbsp_ops = {
3436 .read = omap_mcbsp_read,
3437 .write = omap_mcbsp_write,
3438 .endianness = DEVICE_NATIVE_ENDIAN,
3439 };
3440
3441 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3442 {
3443 memset(&s->spcr, 0, sizeof(s->spcr));
3444 memset(&s->rcr, 0, sizeof(s->rcr));
3445 memset(&s->xcr, 0, sizeof(s->xcr));
3446 s->srgr[0] = 0x0001;
3447 s->srgr[1] = 0x2000;
3448 memset(&s->mcr, 0, sizeof(s->mcr));
3449 memset(&s->pcr, 0, sizeof(s->pcr));
3450 memset(&s->rcer, 0, sizeof(s->rcer));
3451 memset(&s->xcer, 0, sizeof(s->xcer));
3452 s->tx_req = 0;
3453 s->rx_req = 0;
3454 s->tx_rate = 0;
3455 s->rx_rate = 0;
3456 timer_del(s->source_timer);
3457 timer_del(s->sink_timer);
3458 }
3459
3460 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
3461 hwaddr base,
3462 qemu_irq txirq, qemu_irq rxirq,
3463 qemu_irq *dma, omap_clk clk)
3464 {
3465 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1);
3466
3467 s->txirq = txirq;
3468 s->rxirq = rxirq;
3469 s->txdrq = dma[0];
3470 s->rxdrq = dma[1];
3471 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s);
3472 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s);
3473 omap_mcbsp_reset(s);
3474
3475 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
3476 memory_region_add_subregion(system_memory, base, &s->iomem);
3477
3478 return s;
3479 }
3480
3481 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
3482 {
3483 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3484
3485 if (s->rx_rate) {
3486 s->rx_req = s->codec->in.len;
3487 omap_mcbsp_rx_newdata(s);
3488 }
3489 }
3490
3491 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
3492 {
3493 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3494
3495 if (s->tx_rate) {
3496 s->tx_req = s->codec->out.size;
3497 omap_mcbsp_tx_newdata(s);
3498 }
3499 }
3500
3501 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
3502 {
3503 s->codec = slave;
3504 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0);
3505 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0);
3506 }
3507
3508 /* LED Pulse Generators */
3509 struct omap_lpg_s {
3510 MemoryRegion iomem;
3511 QEMUTimer *tm;
3512
3513 uint8_t control;
3514 uint8_t power;
3515 int64_t on;
3516 int64_t period;
3517 int clk;
3518 int cycle;
3519 };
3520
3521 static void omap_lpg_tick(void *opaque)
3522 {
3523 struct omap_lpg_s *s = opaque;
3524
3525 if (s->cycle)
3526 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on);
3527 else
3528 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on);
3529
3530 s->cycle = !s->cycle;
3531 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
3532 }
3533
3534 static void omap_lpg_update(struct omap_lpg_s *s)
3535 {
3536 int64_t on, period = 1, ticks = 1000;
3537 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3538
3539 if (~s->control & (1 << 6)) /* LPGRES */
3540 on = 0;
3541 else if (s->control & (1 << 7)) /* PERM_ON */
3542 on = period;
3543 else {
3544 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3545 256 / 32);
3546 on = (s->clk && s->power) ? muldiv64(ticks,
3547 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3548 }
3549
3550 timer_del(s->tm);
3551 if (on == period && s->on < s->period)
3552 printf("%s: LED is on\n", __FUNCTION__);
3553 else if (on == 0 && s->on)
3554 printf("%s: LED is off\n", __FUNCTION__);
3555 else if (on && (on != s->on || period != s->period)) {
3556 s->cycle = 0;
3557 s->on = on;
3558 s->period = period;
3559 omap_lpg_tick(s);
3560 return;
3561 }
3562
3563 s->on = on;
3564 s->period = period;
3565 }
3566
3567 static void omap_lpg_reset(struct omap_lpg_s *s)
3568 {
3569 s->control = 0x00;
3570 s->power = 0x00;
3571 s->clk = 1;
3572 omap_lpg_update(s);
3573 }
3574
3575 static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
3576 unsigned size)
3577 {
3578 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3579 int offset = addr & OMAP_MPUI_REG_MASK;
3580
3581 if (size != 1) {
3582 return omap_badwidth_read8(opaque, addr);
3583 }
3584
3585 switch (offset) {
3586 case 0x00: /* LCR */
3587 return s->control;
3588
3589 case 0x04: /* PMR */
3590 return s->power;
3591 }
3592
3593 OMAP_BAD_REG(addr);
3594 return 0;
3595 }
3596
3597 static void omap_lpg_write(void *opaque, hwaddr addr,
3598 uint64_t value, unsigned size)
3599 {
3600 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3601 int offset = addr & OMAP_MPUI_REG_MASK;
3602
3603 if (size != 1) {
3604 omap_badwidth_write8(opaque, addr, value);
3605 return;
3606 }
3607
3608 switch (offset) {
3609 case 0x00: /* LCR */
3610 if (~value & (1 << 6)) /* LPGRES */
3611 omap_lpg_reset(s);
3612 s->control = value & 0xff;
3613 omap_lpg_update(s);
3614 return;
3615
3616 case 0x04: /* PMR */
3617 s->power = value & 0x01;
3618 omap_lpg_update(s);
3619 return;
3620
3621 default:
3622 OMAP_BAD_REG(addr);
3623 return;
3624 }
3625 }
3626
3627 static const MemoryRegionOps omap_lpg_ops = {
3628 .read = omap_lpg_read,
3629 .write = omap_lpg_write,
3630 .endianness = DEVICE_NATIVE_ENDIAN,
3631 };
3632
3633 static void omap_lpg_clk_update(void *opaque, int line, int on)
3634 {
3635 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3636
3637 s->clk = on;
3638 omap_lpg_update(s);
3639 }
3640
3641 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
3642 hwaddr base, omap_clk clk)
3643 {
3644 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1);
3645
3646 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
3647
3648 omap_lpg_reset(s);
3649
3650 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
3651 memory_region_add_subregion(system_memory, base, &s->iomem);
3652
3653 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0));
3654
3655 return s;
3656 }
3657
3658 /* MPUI Peripheral Bridge configuration */
3659 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
3660 unsigned size)
3661 {
3662 if (size != 2) {
3663 return omap_badwidth_read16(opaque, addr);
3664 }
3665
3666 if (addr == OMAP_MPUI_BASE) /* CMR */
3667 return 0xfe4d;
3668
3669 OMAP_BAD_REG(addr);
3670 return 0;
3671 }
3672
3673 static void omap_mpui_io_write(void *opaque, hwaddr addr,
3674 uint64_t value, unsigned size)
3675 {
3676 /* FIXME: infinite loop */
3677 omap_badwidth_write16(opaque, addr, value);
3678 }
3679
3680 static const MemoryRegionOps omap_mpui_io_ops = {
3681 .read = omap_mpui_io_read,
3682 .write = omap_mpui_io_write,
3683 .endianness = DEVICE_NATIVE_ENDIAN,
3684 };
3685
3686 static void omap_setup_mpui_io(MemoryRegion *system_memory,
3687 struct omap_mpu_state_s *mpu)
3688 {
3689 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
3690 "omap-mpui-io", 0x7fff);
3691 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
3692 &mpu->mpui_io_iomem);
3693 }
3694
3695 /* General chip reset */
3696 static void omap1_mpu_reset(void *opaque)
3697 {
3698 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3699
3700 omap_dma_reset(mpu->dma);
3701 omap_mpu_timer_reset(mpu->timer[0]);
3702 omap_mpu_timer_reset(mpu->timer[1]);
3703 omap_mpu_timer_reset(mpu->timer[2]);
3704 omap_wd_timer_reset(mpu->wdt);
3705 omap_os_timer_reset(mpu->os_timer);
3706 omap_lcdc_reset(mpu->lcd);
3707 omap_ulpd_pm_reset(mpu);
3708 omap_pin_cfg_reset(mpu);
3709 omap_mpui_reset(mpu);
3710 omap_tipb_bridge_reset(mpu->private_tipb);
3711 omap_tipb_bridge_reset(mpu->public_tipb);
3712 omap_dpll_reset(mpu->dpll[0]);
3713 omap_dpll_reset(mpu->dpll[1]);
3714 omap_dpll_reset(mpu->dpll[2]);
3715 omap_uart_reset(mpu->uart[0]);
3716 omap_uart_reset(mpu->uart[1]);
3717 omap_uart_reset(mpu->uart[2]);
3718 omap_mmc_reset(mpu->mmc);
3719 omap_mpuio_reset(mpu->mpuio);
3720 omap_uwire_reset(mpu->microwire);
3721 omap_pwl_reset(mpu->pwl);
3722 omap_pwt_reset(mpu->pwt);
3723 omap_rtc_reset(mpu->rtc);
3724 omap_mcbsp_reset(mpu->mcbsp1);
3725 omap_mcbsp_reset(mpu->mcbsp2);
3726 omap_mcbsp_reset(mpu->mcbsp3);
3727 omap_lpg_reset(mpu->led[0]);
3728 omap_lpg_reset(mpu->led[1]);
3729 omap_clkm_reset(mpu);
3730 cpu_reset(CPU(mpu->cpu));
3731 }
3732
3733 static const struct omap_map_s {
3734 hwaddr phys_dsp;
3735 hwaddr phys_mpu;
3736 uint32_t size;
3737 const char *name;
3738 } omap15xx_dsp_mm[] = {
3739 /* Strobe 0 */
3740 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3741 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3742 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3743 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3744 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3745 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3746 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3747 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3748 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3749 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3750 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3751 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3752 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3753 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3754 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3755 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3756 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3757 /* Strobe 1 */
3758 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3759
3760 { 0 }
3761 };
3762
3763 static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
3764 const struct omap_map_s *map)
3765 {
3766 MemoryRegion *io;
3767
3768 for (; map->phys_dsp; map ++) {
3769 io = g_new(MemoryRegion, 1);
3770 memory_region_init_alias(io, NULL, map->name,
3771 system_memory, map->phys_mpu, map->size);
3772 memory_region_add_subregion(system_memory, map->phys_dsp, io);
3773 }
3774 }
3775
3776 void omap_mpu_wakeup(void *opaque, int irq, int req)
3777 {
3778 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3779 CPUState *cpu = CPU(mpu->cpu);
3780
3781 if (cpu->halted) {
3782 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
3783 }
3784 }
3785
3786 static const struct dma_irq_map omap1_dma_irq_map[] = {
3787 { 0, OMAP_INT_DMA_CH0_6 },
3788 { 0, OMAP_INT_DMA_CH1_7 },
3789 { 0, OMAP_INT_DMA_CH2_8 },
3790 { 0, OMAP_INT_DMA_CH3 },
3791 { 0, OMAP_INT_DMA_CH4 },
3792 { 0, OMAP_INT_DMA_CH5 },
3793 { 1, OMAP_INT_1610_DMA_CH6 },
3794 { 1, OMAP_INT_1610_DMA_CH7 },
3795 { 1, OMAP_INT_1610_DMA_CH8 },
3796 { 1, OMAP_INT_1610_DMA_CH9 },
3797 { 1, OMAP_INT_1610_DMA_CH10 },
3798 { 1, OMAP_INT_1610_DMA_CH11 },
3799 { 1, OMAP_INT_1610_DMA_CH12 },
3800 { 1, OMAP_INT_1610_DMA_CH13 },
3801 { 1, OMAP_INT_1610_DMA_CH14 },
3802 { 1, OMAP_INT_1610_DMA_CH15 }
3803 };
3804
3805 /* DMA ports for OMAP1 */
3806 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
3807 hwaddr addr)
3808 {
3809 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
3810 }
3811
3812 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
3813 hwaddr addr)
3814 {
3815 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3816 addr);
3817 }
3818
3819 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
3820 hwaddr addr)
3821 {
3822 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
3823 }
3824
3825 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
3826 hwaddr addr)
3827 {
3828 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
3829 }
3830
3831 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
3832 hwaddr addr)
3833 {
3834 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
3835 }
3836
3837 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
3838 hwaddr addr)
3839 {
3840 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
3841 }
3842
3843 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
3844 unsigned long sdram_size,
3845 const char *core)
3846 {
3847 int i;
3848 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
3849 qemu_irq dma_irqs[6];
3850 DriveInfo *dinfo;
3851 SysBusDevice *busdev;
3852
3853 if (!core)
3854 core = "ti925t";
3855
3856 /* Core */
3857 s->mpu_model = omap310;
3858 s->cpu = cpu_arm_init(core);
3859 if (s->cpu == NULL) {
3860 fprintf(stderr, "Unable to find CPU definition\n");
3861 exit(1);
3862 }
3863 s->sdram_size = sdram_size;
3864 s->sram_size = OMAP15XX_SRAM_SIZE;
3865
3866 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
3867
3868 /* Clocks */
3869 omap_clk_init(s);
3870
3871 /* Memory-mapped stuff */
3872 memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram",
3873 s->sdram_size);
3874 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
3875 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
3876 &error_fatal);
3877 vmstate_register_ram_global(&s->imif_ram);
3878 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
3879
3880 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
3881
3882 s->ih[0] = qdev_create(NULL, "omap-intc");
3883 qdev_prop_set_uint32(s->ih[0], "size", 0x100);
3884 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
3885 qdev_init_nofail(s->ih[0]);
3886 busdev = SYS_BUS_DEVICE(s->ih[0]);
3887 sysbus_connect_irq(busdev, 0,
3888 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
3889 sysbus_connect_irq(busdev, 1,
3890 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
3891 sysbus_mmio_map(busdev, 0, 0xfffecb00);
3892 s->ih[1] = qdev_create(NULL, "omap-intc");
3893 qdev_prop_set_uint32(s->ih[1], "size", 0x800);
3894 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck"));
3895 qdev_init_nofail(s->ih[1]);
3896 busdev = SYS_BUS_DEVICE(s->ih[1]);
3897 sysbus_connect_irq(busdev, 0,
3898 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
3899 /* The second interrupt controller's FIQ output is not wired up */
3900 sysbus_mmio_map(busdev, 0, 0xfffe0000);
3901
3902 for (i = 0; i < 6; i++) {
3903 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
3904 omap1_dma_irq_map[i].intr);
3905 }
3906 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
3907 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
3908 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
3909
3910 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3911 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3912 s->port[imif ].addr_valid = omap_validate_imif_addr;
3913 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3914 s->port[local ].addr_valid = omap_validate_local_addr;
3915 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3916
3917 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3918 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
3919 OMAP_EMIFF_BASE, s->sdram_size);
3920 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
3921 OMAP_IMIF_BASE, s->sram_size);
3922
3923 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
3924 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
3925 omap_findclk(s, "mputim_ck"));
3926 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
3927 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
3928 omap_findclk(s, "mputim_ck"));
3929 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
3930 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
3931 omap_findclk(s, "mputim_ck"));
3932
3933 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
3934 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
3935 omap_findclk(s, "armwdt_ck"));
3936
3937 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
3938 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
3939 omap_findclk(s, "clk32-kHz"));
3940
3941 s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
3942 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
3943 omap_dma_get_lcdch(s->dma),
3944 omap_findclk(s, "lcd_ck"));
3945
3946 omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
3947 omap_pin_cfg_init(system_memory, 0xfffe1000, s);
3948 omap_id_init(system_memory, s);
3949
3950 omap_mpui_init(system_memory, 0xfffec900, s);
3951
3952 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
3953 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
3954 omap_findclk(s, "tipb_ck"));
3955 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
3956 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
3957 omap_findclk(s, "tipb_ck"));
3958
3959 omap_tcmi_init(system_memory, 0xfffecc00, s);
3960
3961 s->uart[0] = omap_uart_init(0xfffb0000,
3962 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
3963 omap_findclk(s, "uart1_ck"),
3964 omap_findclk(s, "uart1_ck"),
3965 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
3966 "uart1",
3967 serial_hds[0]);
3968 s->uart[1] = omap_uart_init(0xfffb0800,
3969 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
3970 omap_findclk(s, "uart2_ck"),
3971 omap_findclk(s, "uart2_ck"),
3972 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
3973 "uart2",
3974 serial_hds[0] ? serial_hds[1] : NULL);
3975 s->uart[2] = omap_uart_init(0xfffb9800,
3976 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
3977 omap_findclk(s, "uart3_ck"),
3978 omap_findclk(s, "uart3_ck"),
3979 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
3980 "uart3",
3981 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
3982
3983 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00,
3984 omap_findclk(s, "dpll1"));
3985 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000,
3986 omap_findclk(s, "dpll2"));
3987 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100,
3988 omap_findclk(s, "dpll3"));
3989
3990 dinfo = drive_get(IF_SD, 0, 0);
3991 if (!dinfo) {
3992 fprintf(stderr, "qemu: missing SecureDigital device\n");
3993 exit(1);
3994 }
3995 s->mmc = omap_mmc_init(0xfffb7800, system_memory,
3996 blk_by_legacy_dinfo(dinfo),
3997 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
3998 &s->drq[OMAP_DMA_MMC_TX],
3999 omap_findclk(s, "mmc_ck"));
4000
4001 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
4002 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
4003 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
4004 s->wakeup, omap_findclk(s, "clk32-kHz"));
4005
4006 s->gpio = qdev_create(NULL, "omap-gpio");
4007 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
4008 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck"));
4009 qdev_init_nofail(s->gpio);
4010 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
4011 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
4012 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
4013
4014 s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
4015 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
4016 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
4017 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4018
4019 s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
4020 omap_findclk(s, "armxor_ck"));
4021 s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
4022 omap_findclk(s, "armxor_ck"));
4023
4024 s->i2c[0] = qdev_create(NULL, "omap_i2c");
4025 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
4026 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck"));
4027 qdev_init_nofail(s->i2c[0]);
4028 busdev = SYS_BUS_DEVICE(s->i2c[0]);
4029 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
4030 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
4031 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
4032 sysbus_mmio_map(busdev, 0, 0xfffb3800);
4033
4034 s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
4035 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
4036 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
4037 omap_findclk(s, "clk32-kHz"));
4038
4039 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
4040 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
4041 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
4042 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4043 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
4044 qdev_get_gpio_in(s->ih[0],
4045 OMAP_INT_310_McBSP2_TX),
4046 qdev_get_gpio_in(s->ih[0],
4047 OMAP_INT_310_McBSP2_RX),
4048 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4049 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
4050 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
4051 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
4052 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4053
4054 s->led[0] = omap_lpg_init(system_memory,
4055 0xfffbd000, omap_findclk(s, "clk32-kHz"));
4056 s->led[1] = omap_lpg_init(system_memory,
4057 0xfffbd800, omap_findclk(s, "clk32-kHz"));
4058
4059 /* Register mappings not currenlty implemented:
4060 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4061 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4062 * USB W2FC fffb4000 - fffb47ff
4063 * Camera Interface fffb6800 - fffb6fff
4064 * USB Host fffba000 - fffba7ff
4065 * FAC fffba800 - fffbafff
4066 * HDQ/1-Wire fffbc000 - fffbc7ff
4067 * TIPB switches fffbc800 - fffbcfff
4068 * Mailbox fffcf000 - fffcf7ff
4069 * Local bus IF fffec100 - fffec1ff
4070 * Local bus MMU fffec200 - fffec2ff
4071 * DSP MMU fffed200 - fffed2ff
4072 */
4073
4074 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
4075 omap_setup_mpui_io(system_memory, s);
4076
4077 qemu_register_reset(omap1_mpu_reset, s);
4078
4079 return s;
4080 }
AR7 emulation for QEMU