target/avr/cpu.c

   1 /*
   2  * QEMU AVR CPU
   3  *
   4  * Copyright (c) 2019-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/qemu-print.h"
  24 #include "exec/exec-all.h"
  25 #include "cpu.h"
  26 #include "disas/dis-asm.h"
  27
  28 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     AVRCPU *cpu = AVR_CPU(cs);
  31
  32     cpu->env.pc_w = value / 2; /* internally PC points to words */
  33 }
  34
  35 static bool avr_cpu_has_work(CPUState *cs)
  36 {
  37     AVRCPU *cpu = AVR_CPU(cs);
  38     CPUAVRState *env = &cpu->env;
  39
  40     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
  41             && cpu_interrupts_enabled(env);
  42 }
  43
  44 static void avr_cpu_synchronize_from_tb(CPUState *cs,
  45                                         const TranslationBlock *tb)
  46 {
  47     AVRCPU *cpu = AVR_CPU(cs);
  48     CPUAVRState *env = &cpu->env;
  49
  50     env->pc_w = tb->pc / 2; /* internally PC points to words */
  51 }
  52
  53 static void avr_cpu_reset(DeviceState *ds)
  54 {
  55     CPUState *cs = CPU(ds);
  56     AVRCPU *cpu = AVR_CPU(cs);
  57     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
  58     CPUAVRState *env = &cpu->env;
  59
  60     mcc->parent_reset(ds);
  61
  62     env->pc_w = 0;
  63     env->sregI = 1;
  64     env->sregC = 0;
  65     env->sregZ = 0;
  66     env->sregN = 0;
  67     env->sregV = 0;
  68     env->sregS = 0;
  69     env->sregH = 0;
  70     env->sregT = 0;
  71
  72     env->rampD = 0;
  73     env->rampX = 0;
  74     env->rampY = 0;
  75     env->rampZ = 0;
  76     env->eind = 0;
  77     env->sp = 0;
  78
  79     env->skip = 0;
  80
  81     memset(env->r, 0, sizeof(env->r));
  82 }
  83
  84 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  85 {
  86     info->mach = bfd_arch_avr;
  87     info->print_insn = avr_print_insn;
  88 }
  89
  90 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
  91 {
  92     CPUState *cs = CPU(dev);
  93     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
  94     Error *local_err = NULL;
  95
  96     cpu_exec_realizefn(cs, &local_err);
  97     if (local_err != NULL) {
  98         error_propagate(errp, local_err);
  99         return;
 100     }
 101     qemu_init_vcpu(cs);
 102     cpu_reset(cs);
 103
 104     mcc->parent_realize(dev, errp);
 105 }
 106
 107 static void avr_cpu_set_int(void *opaque, int irq, int level)
 108 {
 109     AVRCPU *cpu = opaque;
 110     CPUAVRState *env = &cpu->env;
 111     CPUState *cs = CPU(cpu);
 112     uint64_t mask = (1ull << irq);
 113
 114     if (level) {
 115         env->intsrc |= mask;
 116         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 117     } else {
 118         env->intsrc &= ~mask;
 119         if (env->intsrc == 0) {
 120             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 121         }
 122     }
 123 }
 124
 125 static void avr_cpu_initfn(Object *obj)
 126 {
 127     AVRCPU *cpu = AVR_CPU(obj);
 128
 129     cpu_set_cpustate_pointers(cpu);
 130
 131     /* Set the number of interrupts supported by the CPU. */
 132     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
 133                       sizeof(cpu->env.intsrc) * 8);
 134 }
 135
 136 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 137 {
 138     ObjectClass *oc;
 139
 140     oc = object_class_by_name(cpu_model);
 141     if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
 142         object_class_is_abstract(oc)) {
 143         oc = NULL;
 144     }
 145     return oc;
 146 }
 147
 148 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 149 {
 150     AVRCPU *cpu = AVR_CPU(cs);
 151     CPUAVRState *env = &cpu->env;
 152     int i;
 153
 154     qemu_fprintf(f, "\n");
 155     qemu_fprintf(f, "PC:    %06x\n", env->pc_w * 2); /* PC points to words */
 156     qemu_fprintf(f, "SP:      %04x\n", env->sp);
 157     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
 158     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
 159     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
 160     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
 161     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
 162     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
 163     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
 164     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
 165     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
 166                  env->sregI ? 'I' : '-',
 167                  env->sregT ? 'T' : '-',
 168                  env->sregH ? 'H' : '-',
 169                  env->sregS ? 'S' : '-',
 170                  env->sregV ? 'V' : '-',
 171                  env->sregN ? '-' : 'N', /* Zf has negative logic */
 172                  env->sregZ ? 'Z' : '-',
 173                  env->sregC ? 'I' : '-');
 174     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
 175
 176     qemu_fprintf(f, "\n");
 177     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
 178         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
 179
 180         if ((i % 8) == 7) {
 181             qemu_fprintf(f, "\n");
 182         }
 183     }
 184     qemu_fprintf(f, "\n");
 185 }
 186
 187 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 188 {
 189     DeviceClass *dc = DEVICE_CLASS(oc);
 190     CPUClass *cc = CPU_CLASS(oc);
 191     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 192
 193     mcc->parent_realize = dc->realize;
 194     dc->realize = avr_cpu_realizefn;
 195
 196     device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
 197
 198     cc->class_by_name = avr_cpu_class_by_name;
 199
 200     cc->has_work = avr_cpu_has_work;
 201     cc->do_interrupt = avr_cpu_do_interrupt;
 202     cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
 203     cc->dump_state = avr_cpu_dump_state;
 204     cc->set_pc = avr_cpu_set_pc;
 205     cc->memory_rw_debug = avr_cpu_memory_rw_debug;
 206     cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
 207     cc->tlb_fill = avr_cpu_tlb_fill;
 208     cc->vmsd = &vms_avr_cpu;
 209     cc->disas_set_info = avr_cpu_disas_set_info;
 210     cc->tcg_initialize = avr_cpu_tcg_init;
 211     cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
 212     cc->gdb_read_register = avr_cpu_gdb_read_register;
 213     cc->gdb_write_register = avr_cpu_gdb_write_register;
 214     cc->gdb_num_core_regs = 35;
 215     cc->gdb_core_xml_file = "avr-cpu.xml";
 216 }
 217
 218 /*
 219  * Setting features of AVR core type avr5
 220  * --------------------------------------
 221  *
 222  * This type of AVR core is present in the following AVR MCUs:
 223  *
 224  * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
 225  * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
 226  * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
 227  * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
 228  * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
 229  * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
 230  * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
 231  * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
 232  * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
 233  * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
 234  * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
 235  * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
 236  * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
 237  * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
 238  * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
 239  * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
 240  * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
 241  */
 242 static void avr_avr5_initfn(Object *obj)
 243 {
 244     AVRCPU *cpu = AVR_CPU(obj);
 245     CPUAVRState *env = &cpu->env;
 246
 247     set_avr_feature(env, AVR_FEATURE_LPM);
 248     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 249     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 250     set_avr_feature(env, AVR_FEATURE_SRAM);
 251     set_avr_feature(env, AVR_FEATURE_BREAK);
 252
 253     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 254     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 255     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 256     set_avr_feature(env, AVR_FEATURE_LPMX);
 257     set_avr_feature(env, AVR_FEATURE_MOVW);
 258     set_avr_feature(env, AVR_FEATURE_MUL);
 259 }
 260
 261 /*
 262  * Setting features of AVR core type avr51
 263  * --------------------------------------
 264  *
 265  * This type of AVR core is present in the following AVR MCUs:
 266  *
 267  * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
 268  * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
 269  * at90usb1287
 270  */
 271 static void avr_avr51_initfn(Object *obj)
 272 {
 273     AVRCPU *cpu = AVR_CPU(obj);
 274     CPUAVRState *env = &cpu->env;
 275
 276     set_avr_feature(env, AVR_FEATURE_LPM);
 277     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 278     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 279     set_avr_feature(env, AVR_FEATURE_SRAM);
 280     set_avr_feature(env, AVR_FEATURE_BREAK);
 281
 282     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 283     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 284     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 285     set_avr_feature(env, AVR_FEATURE_ELPMX);
 286     set_avr_feature(env, AVR_FEATURE_ELPM);
 287     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 288     set_avr_feature(env, AVR_FEATURE_LPMX);
 289     set_avr_feature(env, AVR_FEATURE_MOVW);
 290     set_avr_feature(env, AVR_FEATURE_MUL);
 291 }
 292
 293 /*
 294  * Setting features of AVR core type avr6
 295  * --------------------------------------
 296  *
 297  * This type of AVR core is present in the following AVR MCUs:
 298  *
 299  * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
 300  */
 301 static void avr_avr6_initfn(Object *obj)
 302 {
 303     AVRCPU *cpu = AVR_CPU(obj);
 304     CPUAVRState *env = &cpu->env;
 305
 306     set_avr_feature(env, AVR_FEATURE_LPM);
 307     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 308     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 309     set_avr_feature(env, AVR_FEATURE_SRAM);
 310     set_avr_feature(env, AVR_FEATURE_BREAK);
 311
 312     set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
 313     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 314     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 315     set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
 316     set_avr_feature(env, AVR_FEATURE_ELPMX);
 317     set_avr_feature(env, AVR_FEATURE_ELPM);
 318     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 319     set_avr_feature(env, AVR_FEATURE_LPMX);
 320     set_avr_feature(env, AVR_FEATURE_MOVW);
 321     set_avr_feature(env, AVR_FEATURE_MUL);
 322 }
 323
 324 typedef struct AVRCPUInfo {
 325     const char *name;
 326     void (*initfn)(Object *obj);
 327 } AVRCPUInfo;
 328
 329
 330 static void avr_cpu_list_entry(gpointer data, gpointer user_data)
 331 {
 332     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 333
 334     qemu_printf("%s\n", typename);
 335 }
 336
 337 void avr_cpu_list(void)
 338 {
 339     GSList *list;
 340     list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
 341     g_slist_foreach(list, avr_cpu_list_entry, NULL);
 342     g_slist_free(list);
 343 }
 344
 345 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
 346     { \
 347         .parent = TYPE_AVR_CPU, \
 348         .instance_init = initfn, \
 349         .name = AVR_CPU_TYPE_NAME(model), \
 350     }
 351
 352 static const TypeInfo avr_cpu_type_info[] = {
 353     {
 354         .name = TYPE_AVR_CPU,
 355         .parent = TYPE_CPU,
 356         .instance_size = sizeof(AVRCPU),
 357         .instance_init = avr_cpu_initfn,
 358         .class_size = sizeof(AVRCPUClass),
 359         .class_init = avr_cpu_class_init,
 360         .abstract = true,
 361     },
 362     DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
 363     DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
 364     DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
 365 };
 366
 367 DEFINE_TYPES(avr_cpu_type_info)