hw/net/ftgmac100.c

   1 /*
   2  * Faraday FTGMAC100 Gigabit Ethernet
   3  *
   4  * Copyright (C) 2016-2017, IBM Corporation.
   5  *
   6  * Based on Coldfire Fast Ethernet Controller emulation.
   7  *
   8  * Copyright (c) 2007 CodeSourcery.
   9  *
  10  * This code is licensed under the GPL version 2 or later. See the
  11  * COPYING file in the top-level directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/irq.h"
  16 #include "hw/net/ftgmac100.h"
  17 #include "sysemu/dma.h"
  18 #include "qapi/error.h"
  19 #include "qemu/log.h"
  20 #include "qemu/module.h"
  21 #include "net/checksum.h"
  22 #include "net/eth.h"
  23 #include "hw/net/mii.h"
  24 #include "hw/qdev-properties.h"
  25 #include "migration/vmstate.h"
  26
  27 /* For crc32 */
  28 #include <zlib.h>
  29
  30 /*
  31  * FTGMAC100 registers
  32  */
  33 #define FTGMAC100_ISR             0x00
  34 #define FTGMAC100_IER             0x04
  35 #define FTGMAC100_MAC_MADR        0x08
  36 #define FTGMAC100_MAC_LADR        0x0c
  37 #define FTGMAC100_MATH0           0x10
  38 #define FTGMAC100_MATH1           0x14
  39 #define FTGMAC100_NPTXPD          0x18
  40 #define FTGMAC100_RXPD            0x1C
  41 #define FTGMAC100_NPTXR_BADR      0x20
  42 #define FTGMAC100_RXR_BADR        0x24
  43 #define FTGMAC100_HPTXPD          0x28
  44 #define FTGMAC100_HPTXR_BADR      0x2c
  45 #define FTGMAC100_ITC             0x30
  46 #define FTGMAC100_APTC            0x34
  47 #define FTGMAC100_DBLAC           0x38
  48 #define FTGMAC100_REVR            0x40
  49 #define FTGMAC100_FEAR1           0x44
  50 #define FTGMAC100_RBSR            0x4c
  51 #define FTGMAC100_TPAFCR          0x48
  52
  53 #define FTGMAC100_MACCR           0x50
  54 #define FTGMAC100_MACSR           0x54
  55 #define FTGMAC100_PHYCR           0x60
  56 #define FTGMAC100_PHYDATA         0x64
  57 #define FTGMAC100_FCR             0x68
  58
  59 /*
  60  * Interrupt status register & interrupt enable register
  61  */
  62 #define FTGMAC100_INT_RPKT_BUF    (1 << 0)
  63 #define FTGMAC100_INT_RPKT_FIFO   (1 << 1)
  64 #define FTGMAC100_INT_NO_RXBUF    (1 << 2)
  65 #define FTGMAC100_INT_RPKT_LOST   (1 << 3)
  66 #define FTGMAC100_INT_XPKT_ETH    (1 << 4)
  67 #define FTGMAC100_INT_XPKT_FIFO   (1 << 5)
  68 #define FTGMAC100_INT_NO_NPTXBUF  (1 << 6)
  69 #define FTGMAC100_INT_XPKT_LOST   (1 << 7)
  70 #define FTGMAC100_INT_AHB_ERR     (1 << 8)
  71 #define FTGMAC100_INT_PHYSTS_CHG  (1 << 9)
  72 #define FTGMAC100_INT_NO_HPTXBUF  (1 << 10)
  73
  74 /*
  75  * Automatic polling timer control register
  76  */
  77 #define FTGMAC100_APTC_RXPOLL_CNT(x)        ((x) & 0xf)
  78 #define FTGMAC100_APTC_RXPOLL_TIME_SEL      (1 << 4)
  79 #define FTGMAC100_APTC_TXPOLL_CNT(x)        (((x) >> 8) & 0xf)
  80 #define FTGMAC100_APTC_TXPOLL_TIME_SEL      (1 << 12)
  81
  82 /*
  83  * PHY control register
  84  */
  85 #define FTGMAC100_PHYCR_MIIRD               (1 << 26)
  86 #define FTGMAC100_PHYCR_MIIWR               (1 << 27)
  87
  88 #define FTGMAC100_PHYCR_DEV(x)              (((x) >> 16) & 0x1f)
  89 #define FTGMAC100_PHYCR_REG(x)              (((x) >> 21) & 0x1f)
  90
  91 /*
  92  * PHY data register
  93  */
  94 #define FTGMAC100_PHYDATA_MIIWDATA(x)       ((x) & 0xffff)
  95 #define FTGMAC100_PHYDATA_MIIRDATA(x)       (((x) >> 16) & 0xffff)
  96
  97 /*
  98  * PHY control register - New MDC/MDIO interface
  99  */
 100 #define FTGMAC100_PHYCR_NEW_DATA(x)     (((x) >> 16) & 0xffff)
 101 #define FTGMAC100_PHYCR_NEW_FIRE        (1 << 15)
 102 #define FTGMAC100_PHYCR_NEW_ST_22       (1 << 12)
 103 #define FTGMAC100_PHYCR_NEW_OP(x)       (((x) >> 10) & 3)
 104 #define   FTGMAC100_PHYCR_NEW_OP_WRITE    0x1
 105 #define   FTGMAC100_PHYCR_NEW_OP_READ     0x2
 106 #define FTGMAC100_PHYCR_NEW_DEV(x)      (((x) >> 5) & 0x1f)
 107 #define FTGMAC100_PHYCR_NEW_REG(x)      ((x) & 0x1f)
 108
 109 /*
 110  * Feature Register
 111  */
 112 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE   (1 << 31)
 113
 114 /*
 115  * MAC control register
 116  */
 117 #define FTGMAC100_MACCR_TXDMA_EN         (1 << 0)
 118 #define FTGMAC100_MACCR_RXDMA_EN         (1 << 1)
 119 #define FTGMAC100_MACCR_TXMAC_EN         (1 << 2)
 120 #define FTGMAC100_MACCR_RXMAC_EN         (1 << 3)
 121 #define FTGMAC100_MACCR_RM_VLAN          (1 << 4)
 122 #define FTGMAC100_MACCR_HPTXR_EN         (1 << 5)
 123 #define FTGMAC100_MACCR_LOOP_EN          (1 << 6)
 124 #define FTGMAC100_MACCR_ENRX_IN_HALFTX   (1 << 7)
 125 #define FTGMAC100_MACCR_FULLDUP          (1 << 8)
 126 #define FTGMAC100_MACCR_GIGA_MODE        (1 << 9)
 127 #define FTGMAC100_MACCR_CRC_APD          (1 << 10) /* not needed */
 128 #define FTGMAC100_MACCR_RX_RUNT          (1 << 12)
 129 #define FTGMAC100_MACCR_JUMBO_LF         (1 << 13)
 130 #define FTGMAC100_MACCR_RX_ALL           (1 << 14)
 131 #define FTGMAC100_MACCR_HT_MULTI_EN      (1 << 15)
 132 #define FTGMAC100_MACCR_RX_MULTIPKT      (1 << 16)
 133 #define FTGMAC100_MACCR_RX_BROADPKT      (1 << 17)
 134 #define FTGMAC100_MACCR_DISCARD_CRCERR   (1 << 18)
 135 #define FTGMAC100_MACCR_FAST_MODE        (1 << 19)
 136 #define FTGMAC100_MACCR_SW_RST           (1 << 31)
 137
 138 /*
 139  * Transmit descriptor
 140  */
 141 #define FTGMAC100_TXDES0_TXBUF_SIZE(x)   ((x) & 0x3fff)
 142 #define FTGMAC100_TXDES0_EDOTR           (1 << 15)
 143 #define FTGMAC100_TXDES0_CRC_ERR         (1 << 19)
 144 #define FTGMAC100_TXDES0_LTS             (1 << 28)
 145 #define FTGMAC100_TXDES0_FTS             (1 << 29)
 146 #define FTGMAC100_TXDES0_EDOTR_ASPEED    (1 << 30)
 147 #define FTGMAC100_TXDES0_TXDMA_OWN       (1 << 31)
 148
 149 #define FTGMAC100_TXDES1_VLANTAG_CI(x)   ((x) & 0xffff)
 150 #define FTGMAC100_TXDES1_INS_VLANTAG     (1 << 16)
 151 #define FTGMAC100_TXDES1_TCP_CHKSUM      (1 << 17)
 152 #define FTGMAC100_TXDES1_UDP_CHKSUM      (1 << 18)
 153 #define FTGMAC100_TXDES1_IP_CHKSUM       (1 << 19)
 154 #define FTGMAC100_TXDES1_LLC             (1 << 22)
 155 #define FTGMAC100_TXDES1_TX2FIC          (1 << 30)
 156 #define FTGMAC100_TXDES1_TXIC            (1 << 31)
 157
 158 /*
 159  * Receive descriptor
 160  */
 161 #define FTGMAC100_RXDES0_VDBC            0x3fff
 162 #define FTGMAC100_RXDES0_EDORR           (1 << 15)
 163 #define FTGMAC100_RXDES0_MULTICAST       (1 << 16)
 164 #define FTGMAC100_RXDES0_BROADCAST       (1 << 17)
 165 #define FTGMAC100_RXDES0_RX_ERR          (1 << 18)
 166 #define FTGMAC100_RXDES0_CRC_ERR         (1 << 19)
 167 #define FTGMAC100_RXDES0_FTL             (1 << 20)
 168 #define FTGMAC100_RXDES0_RUNT            (1 << 21)
 169 #define FTGMAC100_RXDES0_RX_ODD_NB       (1 << 22)
 170 #define FTGMAC100_RXDES0_FIFO_FULL       (1 << 23)
 171 #define FTGMAC100_RXDES0_PAUSE_OPCODE    (1 << 24)
 172 #define FTGMAC100_RXDES0_PAUSE_FRAME     (1 << 25)
 173 #define FTGMAC100_RXDES0_LRS             (1 << 28)
 174 #define FTGMAC100_RXDES0_FRS             (1 << 29)
 175 #define FTGMAC100_RXDES0_EDORR_ASPEED    (1 << 30)
 176 #define FTGMAC100_RXDES0_RXPKT_RDY       (1 << 31)
 177
 178 #define FTGMAC100_RXDES1_VLANTAG_CI      0xffff
 179 #define FTGMAC100_RXDES1_PROT_MASK       (0x3 << 20)
 180 #define FTGMAC100_RXDES1_PROT_NONIP      (0x0 << 20)
 181 #define FTGMAC100_RXDES1_PROT_IP         (0x1 << 20)
 182 #define FTGMAC100_RXDES1_PROT_TCPIP      (0x2 << 20)
 183 #define FTGMAC100_RXDES1_PROT_UDPIP      (0x3 << 20)
 184 #define FTGMAC100_RXDES1_LLC             (1 << 22)
 185 #define FTGMAC100_RXDES1_DF              (1 << 23)
 186 #define FTGMAC100_RXDES1_VLANTAG_AVAIL   (1 << 24)
 187 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR  (1 << 25)
 188 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR  (1 << 26)
 189 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR   (1 << 27)
 190
 191 /*
 192  * Receive and transmit Buffer Descriptor
 193  */
 194 typedef struct {
 195     uint32_t        des0;
 196     uint32_t        des1;
 197     uint32_t        des2;        /* not used by HW */
 198     uint32_t        des3;
 199 } FTGMAC100Desc;
 200
 201 /*
 202  * Specific RTL8211E MII Registers
 203  */
 204 #define RTL8211E_MII_PHYCR        16 /* PHY Specific Control */
 205 #define RTL8211E_MII_PHYSR        17 /* PHY Specific Status */
 206 #define RTL8211E_MII_INER         18 /* Interrupt Enable */
 207 #define RTL8211E_MII_INSR         19 /* Interrupt Status */
 208 #define RTL8211E_MII_RXERC        24 /* Receive Error Counter */
 209 #define RTL8211E_MII_LDPSR        27 /* Link Down Power Saving */
 210 #define RTL8211E_MII_EPAGSR       30 /* Extension Page Select */
 211 #define RTL8211E_MII_PAGSEL       31 /* Page Select */
 212
 213 /*
 214  * RTL8211E Interrupt Status
 215  */
 216 #define PHY_INT_AUTONEG_ERROR       (1 << 15)
 217 #define PHY_INT_PAGE_RECV           (1 << 12)
 218 #define PHY_INT_AUTONEG_COMPLETE    (1 << 11)
 219 #define PHY_INT_LINK_STATUS         (1 << 10)
 220 #define PHY_INT_ERROR               (1 << 9)
 221 #define PHY_INT_DOWN                (1 << 8)
 222 #define PHY_INT_JABBER              (1 << 0)
 223
 224 /*
 225  * Max frame size for the receiving buffer
 226  */
 227 #define FTGMAC100_MAX_FRAME_SIZE    9220
 228
 229 /* Limits depending on the type of the frame
 230  *
 231  *   9216 for Jumbo frames (+ 4 for VLAN)
 232  *   1518 for other frames (+ 4 for VLAN)
 233  */
 234 static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
 235 {
 236     int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
 237
 238     return max + (proto == ETH_P_VLAN ? 4 : 0);
 239 }
 240
 241 static void ftgmac100_update_irq(FTGMAC100State *s)
 242 {
 243     qemu_set_irq(s->irq, s->isr & s->ier);
 244 }
 245
 246 /*
 247  * The MII phy could raise a GPIO to the processor which in turn
 248  * could be handled as an interrpt by the OS.
 249  * For now we don't handle any GPIO/interrupt line, so the OS will
 250  * have to poll for the PHY status.
 251  */
 252 static void phy_update_irq(FTGMAC100State *s)
 253 {
 254     ftgmac100_update_irq(s);
 255 }
 256
 257 static void phy_update_link(FTGMAC100State *s)
 258 {
 259     /* Autonegotiation status mirrors link status.  */
 260     if (qemu_get_queue(s->nic)->link_down) {
 261         s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
 262         s->phy_int |= PHY_INT_DOWN;
 263     } else {
 264         s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
 265         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
 266     }
 267     phy_update_irq(s);
 268 }
 269
 270 static void ftgmac100_set_link(NetClientState *nc)
 271 {
 272     phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc)));
 273 }
 274
 275 static void phy_reset(FTGMAC100State *s)
 276 {
 277     s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
 278                      MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS |
 279                      MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST |
 280                      MII_BMSR_EXTCAP);
 281     s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000);
 282     s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD |
 283                         MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
 284                         MII_ANAR_CSMACD);
 285     s->phy_int_mask = 0;
 286     s->phy_int = 0;
 287 }
 288
 289 static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg)
 290 {
 291     uint16_t val;
 292
 293     switch (reg) {
 294     case MII_BMCR: /* Basic Control */
 295         val = s->phy_control;
 296         break;
 297     case MII_BMSR: /* Basic Status */
 298         val = s->phy_status;
 299         break;
 300     case MII_PHYID1: /* ID1 */
 301         val = RTL8211E_PHYID1;
 302         break;
 303     case MII_PHYID2: /* ID2 */
 304         val = RTL8211E_PHYID2;
 305         break;
 306     case MII_ANAR: /* Auto-neg advertisement */
 307         val = s->phy_advertise;
 308         break;
 309     case MII_ANLPAR: /* Auto-neg Link Partner Ability */
 310         val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD |
 311                MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 |
 312                MII_ANLPAR_CSMACD);
 313         break;
 314     case MII_ANER: /* Auto-neg Expansion */
 315         val = MII_ANER_NWAY;
 316         break;
 317     case MII_CTRL1000: /* 1000BASE-T control  */
 318         val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL);
 319         break;
 320     case MII_STAT1000: /* 1000BASE-T status  */
 321         val = MII_STAT1000_FULL;
 322         break;
 323     case RTL8211E_MII_INSR:  /* Interrupt status.  */
 324         val = s->phy_int;
 325         s->phy_int = 0;
 326         phy_update_irq(s);
 327         break;
 328     case RTL8211E_MII_INER:  /* Interrupt enable */
 329         val = s->phy_int_mask;
 330         break;
 331     case RTL8211E_MII_PHYCR:
 332     case RTL8211E_MII_PHYSR:
 333     case RTL8211E_MII_RXERC:
 334     case RTL8211E_MII_LDPSR:
 335     case RTL8211E_MII_EPAGSR:
 336     case RTL8211E_MII_PAGSEL:
 337         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
 338                       __func__, reg);
 339         val = 0;
 340         break;
 341     default:
 342         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
 343                       __func__, reg);
 344         val = 0;
 345         break;
 346     }
 347
 348     return val;
 349 }
 350
 351 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |          \
 352                        MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
 353                        MII_BMCR_FD | MII_BMCR_CTST)
 354 #define MII_ANAR_MASK 0x2d7f
 355
 356 static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val)
 357 {
 358     switch (reg) {
 359     case MII_BMCR:     /* Basic Control */
 360         if (val & MII_BMCR_RESET) {
 361             phy_reset(s);
 362         } else {
 363             s->phy_control = val & MII_BMCR_MASK;
 364             /* Complete autonegotiation immediately.  */
 365             if (val & MII_BMCR_AUTOEN) {
 366                 s->phy_status |= MII_BMSR_AN_COMP;
 367             }
 368         }
 369         break;
 370     case MII_ANAR:     /* Auto-neg advertisement */
 371         s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX;
 372         break;
 373     case RTL8211E_MII_INER: /* Interrupt enable */
 374         s->phy_int_mask = val & 0xff;
 375         phy_update_irq(s);
 376         break;
 377     case RTL8211E_MII_PHYCR:
 378     case RTL8211E_MII_PHYSR:
 379     case RTL8211E_MII_RXERC:
 380     case RTL8211E_MII_LDPSR:
 381     case RTL8211E_MII_EPAGSR:
 382     case RTL8211E_MII_PAGSEL:
 383         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
 384                       __func__, reg);
 385         break;
 386     default:
 387         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
 388                       __func__, reg);
 389         break;
 390     }
 391 }
 392
 393 static void do_phy_new_ctl(FTGMAC100State *s)
 394 {
 395     uint8_t reg;
 396     uint16_t data;
 397
 398     if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) {
 399         qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
 400         return;
 401     }
 402
 403     /* Nothing to do */
 404     if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) {
 405         return;
 406     }
 407
 408     reg = FTGMAC100_PHYCR_NEW_REG(s->phycr);
 409     data = FTGMAC100_PHYCR_NEW_DATA(s->phycr);
 410
 411     switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) {
 412     case FTGMAC100_PHYCR_NEW_OP_WRITE:
 413         do_phy_write(s, reg, data);
 414         break;
 415     case FTGMAC100_PHYCR_NEW_OP_READ:
 416         s->phydata = do_phy_read(s, reg) & 0xffff;
 417         break;
 418     default:
 419         qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
 420                       __func__, s->phycr);
 421     }
 422
 423     s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE;
 424 }
 425
 426 static void do_phy_ctl(FTGMAC100State *s)
 427 {
 428     uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr);
 429
 430     if (s->phycr & FTGMAC100_PHYCR_MIIWR) {
 431         do_phy_write(s, reg, s->phydata & 0xffff);
 432         s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
 433     } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) {
 434         s->phydata = do_phy_read(s, reg) << 16;
 435         s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
 436     } else {
 437         qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n",
 438                       __func__, s->phycr);
 439     }
 440 }
 441
 442 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
 443 {
 444     if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
 445         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
 446                       HWADDR_PRIx "\n", __func__, addr);
 447         return -1;
 448     }
 449     bd->des0 = le32_to_cpu(bd->des0);
 450     bd->des1 = le32_to_cpu(bd->des1);
 451     bd->des2 = le32_to_cpu(bd->des2);
 452     bd->des3 = le32_to_cpu(bd->des3);
 453     return 0;
 454 }
 455
 456 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
 457 {
 458     FTGMAC100Desc lebd;
 459
 460     lebd.des0 = cpu_to_le32(bd->des0);
 461     lebd.des1 = cpu_to_le32(bd->des1);
 462     lebd.des2 = cpu_to_le32(bd->des2);
 463     lebd.des3 = cpu_to_le32(bd->des3);
 464     if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) {
 465         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
 466                       HWADDR_PRIx "\n", __func__, addr);
 467         return -1;
 468     }
 469     return 0;
 470 }
 471
 472 static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
 473                             uint32_t tx_descriptor)
 474 {
 475     int frame_size = 0;
 476     uint8_t *ptr = s->frame;
 477     uint32_t addr = tx_descriptor;
 478     uint32_t flags = 0;
 479
 480     while (1) {
 481         FTGMAC100Desc bd;
 482         int len;
 483
 484         if (ftgmac100_read_bd(&bd, addr) ||
 485             ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) {
 486             /* Run out of descriptors to transmit.  */
 487             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
 488             break;
 489         }
 490
 491         /* record transmit flags as they are valid only on the first
 492          * segment */
 493         if (bd.des0 & FTGMAC100_TXDES0_FTS) {
 494             flags = bd.des1;
 495         }
 496
 497         len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
 498         if (frame_size + len > sizeof(s->frame)) {
 499             qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
 500                           __func__, len);
 501             s->isr |= FTGMAC100_INT_XPKT_LOST;
 502             len =  sizeof(s->frame) - frame_size;
 503         }
 504
 505         if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
 506             qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
 507                           __func__, bd.des3);
 508             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
 509             break;
 510         }
 511
 512         /* Check for VLAN */
 513         if (bd.des0 & FTGMAC100_TXDES0_FTS &&
 514             bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
 515             be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
 516             if (frame_size + len + 4 > sizeof(s->frame)) {
 517                 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
 518                               __func__, len);
 519                 s->isr |= FTGMAC100_INT_XPKT_LOST;
 520                 len =  sizeof(s->frame) - frame_size - 4;
 521             }
 522             memmove(ptr + 16, ptr + 12, len - 12);
 523             stw_be_p(ptr + 12, ETH_P_VLAN);
 524             stw_be_p(ptr + 14, bd.des1);
 525             len += 4;
 526         }
 527
 528         ptr += len;
 529         frame_size += len;
 530         if (bd.des0 & FTGMAC100_TXDES0_LTS) {
 531             if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
 532                 net_checksum_calculate(s->frame, frame_size);
 533             }
 534             /* Last buffer in frame.  */
 535             qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
 536             ptr = s->frame;
 537             frame_size = 0;
 538             if (flags & FTGMAC100_TXDES1_TXIC) {
 539                 s->isr |= FTGMAC100_INT_XPKT_ETH;
 540             }
 541         }
 542
 543         if (flags & FTGMAC100_TXDES1_TX2FIC) {
 544             s->isr |= FTGMAC100_INT_XPKT_FIFO;
 545         }
 546         bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
 547
 548         /* Write back the modified descriptor.  */
 549         ftgmac100_write_bd(&bd, addr);
 550         /* Advance to the next descriptor.  */
 551         if (bd.des0 & s->txdes0_edotr) {
 552             addr = tx_ring;
 553         } else {
 554             addr += sizeof(FTGMAC100Desc);
 555         }
 556     }
 557
 558     s->tx_descriptor = addr;
 559
 560     ftgmac100_update_irq(s);
 561 }
 562
 563 static int ftgmac100_can_receive(NetClientState *nc)
 564 {
 565     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 566     FTGMAC100Desc bd;
 567
 568     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
 569          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
 570         return 0;
 571     }
 572
 573     if (ftgmac100_read_bd(&bd, s->rx_descriptor)) {
 574         return 0;
 575     }
 576     return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
 577 }
 578
 579 /*
 580  * This is purely informative. The HW can poll the RW (and RX) ring
 581  * buffers for available descriptors but we don't need to trigger a
 582  * timer for that in qemu.
 583  */
 584 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
 585 {
 586     /* Polling times :
 587      *
 588      * Speed      TIME_SEL=0    TIME_SEL=1
 589      *
 590      *    10         51.2 ms      819.2 ms
 591      *   100         5.12 ms      81.92 ms
 592      *  1000        1.024 ms     16.384 ms
 593      */
 594     static const int div[] = { 20, 200, 1000 };
 595
 596     uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr);
 597     uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0;
 598
 599     if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) {
 600         cnt <<= 4;
 601     }
 602
 603     if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) {
 604         speed = 2;
 605     }
 606
 607     return cnt / div[speed];
 608 }
 609
 610 static void ftgmac100_reset(DeviceState *d)
 611 {
 612     FTGMAC100State *s = FTGMAC100(d);
 613
 614     /* Reset the FTGMAC100 */
 615     s->isr = 0;
 616     s->ier = 0;
 617     s->rx_enabled = 0;
 618     s->rx_ring = 0;
 619     s->rbsr = 0x640;
 620     s->rx_descriptor = 0;
 621     s->tx_ring = 0;
 622     s->tx_descriptor = 0;
 623     s->math[0] = 0;
 624     s->math[1] = 0;
 625     s->itc = 0;
 626     s->aptcr = 1;
 627     s->dblac = 0x00022f00;
 628     s->revr = 0;
 629     s->fear1 = 0;
 630     s->tpafcr = 0xf1;
 631
 632     s->maccr = 0;
 633     s->phycr = 0;
 634     s->phydata = 0;
 635     s->fcr = 0x400;
 636
 637     /* and the PHY */
 638     phy_reset(s);
 639 }
 640
 641 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
 642 {
 643     FTGMAC100State *s = FTGMAC100(opaque);
 644
 645     switch (addr & 0xff) {
 646     case FTGMAC100_ISR:
 647         return s->isr;
 648     case FTGMAC100_IER:
 649         return s->ier;
 650     case FTGMAC100_MAC_MADR:
 651         return (s->conf.macaddr.a[0] << 8)  | s->conf.macaddr.a[1];
 652     case FTGMAC100_MAC_LADR:
 653         return ((uint32_t) s->conf.macaddr.a[2] << 24) |
 654             (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) |
 655             s->conf.macaddr.a[5];
 656     case FTGMAC100_MATH0:
 657         return s->math[0];
 658     case FTGMAC100_MATH1:
 659         return s->math[1];
 660     case FTGMAC100_ITC:
 661         return s->itc;
 662     case FTGMAC100_DBLAC:
 663         return s->dblac;
 664     case FTGMAC100_REVR:
 665         return s->revr;
 666     case FTGMAC100_FEAR1:
 667         return s->fear1;
 668     case FTGMAC100_TPAFCR:
 669         return s->tpafcr;
 670     case FTGMAC100_FCR:
 671         return s->fcr;
 672     case FTGMAC100_MACCR:
 673         return s->maccr;
 674     case FTGMAC100_PHYCR:
 675         return s->phycr;
 676     case FTGMAC100_PHYDATA:
 677         return s->phydata;
 678
 679         /* We might want to support these one day */
 680     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
 681     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
 682     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
 683         qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
 684                       HWADDR_PRIx "\n", __func__, addr);
 685         return 0;
 686     default:
 687         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
 688                       HWADDR_PRIx "\n", __func__, addr);
 689         return 0;
 690     }
 691 }
 692
 693 static void ftgmac100_write(void *opaque, hwaddr addr,
 694                           uint64_t value, unsigned size)
 695 {
 696     FTGMAC100State *s = FTGMAC100(opaque);
 697
 698     switch (addr & 0xff) {
 699     case FTGMAC100_ISR: /* Interrupt status */
 700         s->isr &= ~value;
 701         break;
 702     case FTGMAC100_IER: /* Interrupt control */
 703         s->ier = value;
 704         break;
 705     case FTGMAC100_MAC_MADR: /* MAC */
 706         s->conf.macaddr.a[0] = value >> 8;
 707         s->conf.macaddr.a[1] = value;
 708         break;
 709     case FTGMAC100_MAC_LADR:
 710         s->conf.macaddr.a[2] = value >> 24;
 711         s->conf.macaddr.a[3] = value >> 16;
 712         s->conf.macaddr.a[4] = value >> 8;
 713         s->conf.macaddr.a[5] = value;
 714         break;
 715     case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */
 716         s->math[0] = value;
 717         break;
 718     case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */
 719         s->math[1] = value;
 720         break;
 721     case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */
 722         s->itc = value;
 723         break;
 724     case FTGMAC100_RXR_BADR: /* Ring buffer address */
 725         s->rx_ring = value;
 726         s->rx_descriptor = s->rx_ring;
 727         break;
 728
 729     case FTGMAC100_RBSR: /* DMA buffer size */
 730         s->rbsr = value;
 731         break;
 732
 733     case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
 734         s->tx_ring = value;
 735         s->tx_descriptor = s->tx_ring;
 736         break;
 737
 738     case FTGMAC100_NPTXPD: /* Trigger transmit */
 739         if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN))
 740             == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) {
 741             /* TODO: high priority tx ring */
 742             ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor);
 743         }
 744         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 745             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 746         }
 747         break;
 748
 749     case FTGMAC100_RXPD: /* Receive Poll Demand Register */
 750         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 751             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 752         }
 753         break;
 754
 755     case FTGMAC100_APTC: /* Automatic polling */
 756         s->aptcr = value;
 757
 758         if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) {
 759             ftgmac100_rxpoll(s);
 760         }
 761
 762         if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) {
 763             qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__);
 764         }
 765         break;
 766
 767     case FTGMAC100_MACCR: /* MAC Device control */
 768         s->maccr = value;
 769         if (value & FTGMAC100_MACCR_SW_RST) {
 770             ftgmac100_reset(DEVICE(s));
 771         }
 772
 773         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 774             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 775         }
 776         break;
 777
 778     case FTGMAC100_PHYCR:  /* PHY Device control */
 779         s->phycr = value;
 780         if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) {
 781             do_phy_new_ctl(s);
 782         } else {
 783             do_phy_ctl(s);
 784         }
 785         break;
 786     case FTGMAC100_PHYDATA:
 787         s->phydata = value & 0xffff;
 788         break;
 789     case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */
 790         s->dblac = value;
 791         break;
 792     case FTGMAC100_REVR:  /* Feature Register */
 793         s->revr = value;
 794         break;
 795     case FTGMAC100_FEAR1: /* Feature Register 1 */
 796         s->fear1 = value;
 797         break;
 798     case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */
 799         s->tpafcr = value;
 800         break;
 801     case FTGMAC100_FCR: /* Flow Control  */
 802         s->fcr  = value;
 803         break;
 804
 805     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
 806     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
 807     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
 808         qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
 809                       HWADDR_PRIx "\n", __func__, addr);
 810         break;
 811     default:
 812         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
 813                       HWADDR_PRIx "\n", __func__, addr);
 814         break;
 815     }
 816
 817     ftgmac100_update_irq(s);
 818 }
 819
 820 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
 821 {
 822     unsigned mcast_idx;
 823
 824     if (s->maccr & FTGMAC100_MACCR_RX_ALL) {
 825         return 1;
 826     }
 827
 828     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
 829     case ETH_PKT_BCAST:
 830         if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) {
 831             return 0;
 832         }
 833         break;
 834     case ETH_PKT_MCAST:
 835         if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) {
 836             if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) {
 837                 return 0;
 838             }
 839
 840             mcast_idx = net_crc32_le(buf, ETH_ALEN);
 841             mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
 842             if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
 843                 return 0;
 844             }
 845         }
 846         break;
 847     case ETH_PKT_UCAST:
 848         if (memcmp(s->conf.macaddr.a, buf, 6)) {
 849             return 0;
 850         }
 851         break;
 852     }
 853
 854     return 1;
 855 }
 856
 857 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
 858                                  size_t len)
 859 {
 860     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 861     FTGMAC100Desc bd;
 862     uint32_t flags = 0;
 863     uint32_t addr;
 864     uint32_t crc;
 865     uint32_t buf_addr;
 866     uint8_t *crc_ptr;
 867     uint32_t buf_len;
 868     size_t size = len;
 869     uint32_t first = FTGMAC100_RXDES0_FRS;
 870     uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
 871     int max_frame_size = ftgmac100_max_frame_size(s, proto);
 872
 873     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
 874          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
 875         return -1;
 876     }
 877
 878     /* TODO : Pad to minimum Ethernet frame length */
 879     /* handle small packets.  */
 880     if (size < 10) {
 881         qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n",
 882                       __func__, size);
 883         return size;
 884     }
 885
 886     if (!ftgmac100_filter(s, buf, size)) {
 887         return size;
 888     }
 889
 890     /* 4 bytes for the CRC.  */
 891     size += 4;
 892     crc = cpu_to_be32(crc32(~0, buf, size));
 893     crc_ptr = (uint8_t *) &crc;
 894
 895     /* Huge frames are truncated.  */
 896     if (size > max_frame_size) {
 897         qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
 898                       __func__, size);
 899         size = max_frame_size;
 900         flags |= FTGMAC100_RXDES0_FTL;
 901     }
 902
 903     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
 904     case ETH_PKT_BCAST:
 905         flags |= FTGMAC100_RXDES0_BROADCAST;
 906         break;
 907     case ETH_PKT_MCAST:
 908         flags |= FTGMAC100_RXDES0_MULTICAST;
 909         break;
 910     case ETH_PKT_UCAST:
 911         break;
 912     }
 913
 914     addr = s->rx_descriptor;
 915     while (size > 0) {
 916         if (!ftgmac100_can_receive(nc)) {
 917             qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
 918             return -1;
 919         }
 920
 921         if (ftgmac100_read_bd(&bd, addr) ||
 922             (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) {
 923             /* No descriptors available.  Bail out.  */
 924             qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n",
 925                           __func__);
 926             s->isr |= FTGMAC100_INT_NO_RXBUF;
 927             break;
 928         }
 929         buf_len = (size <= s->rbsr) ? size : s->rbsr;
 930         bd.des0 |= buf_len & 0x3fff;
 931         size -= buf_len;
 932
 933         /* The last 4 bytes are the CRC.  */
 934         if (size < 4) {
 935             buf_len += size - 4;
 936         }
 937         buf_addr = bd.des3;
 938         if (first && proto == ETH_P_VLAN && buf_len >= 18) {
 939             bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
 940
 941             if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
 942                 dma_memory_write(&address_space_memory, buf_addr, buf, 12);
 943                 dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
 944                                  buf_len - 16);
 945             } else {
 946                 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
 947             }
 948         } else {
 949             bd.des1 = 0;
 950             dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
 951         }
 952         buf += buf_len;
 953         if (size < 4) {
 954             dma_memory_write(&address_space_memory, buf_addr + buf_len,
 955                              crc_ptr, 4 - size);
 956             crc_ptr += 4 - size;
 957         }
 958
 959         bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY;
 960         first = 0;
 961         if (size == 0) {
 962             /* Last buffer in frame.  */
 963             bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
 964             s->isr |= FTGMAC100_INT_RPKT_BUF;
 965         } else {
 966             s->isr |= FTGMAC100_INT_RPKT_FIFO;
 967         }
 968         ftgmac100_write_bd(&bd, addr);
 969         if (bd.des0 & s->rxdes0_edorr) {
 970             addr = s->rx_ring;
 971         } else {
 972             addr += sizeof(FTGMAC100Desc);
 973         }
 974     }
 975     s->rx_descriptor = addr;
 976
 977     ftgmac100_update_irq(s);
 978     return len;
 979 }
 980
 981 static const MemoryRegionOps ftgmac100_ops = {
 982     .read = ftgmac100_read,
 983     .write = ftgmac100_write,
 984     .valid.min_access_size = 4,
 985     .valid.max_access_size = 4,
 986     .endianness = DEVICE_LITTLE_ENDIAN,
 987 };
 988
 989 static void ftgmac100_cleanup(NetClientState *nc)
 990 {
 991     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 992
 993     s->nic = NULL;
 994 }
 995
 996 static NetClientInfo net_ftgmac100_info = {
 997     .type = NET_CLIENT_DRIVER_NIC,
 998     .size = sizeof(NICState),
 999     .can_receive = ftgmac100_can_receive,
1000     .receive = ftgmac100_receive,
1001     .cleanup = ftgmac100_cleanup,
1002     .link_status_changed = ftgmac100_set_link,
1003 };
1004
1005 static void ftgmac100_realize(DeviceState *dev, Error **errp)
1006 {
1007     FTGMAC100State *s = FTGMAC100(dev);
1008     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1009
1010     if (s->aspeed) {
1011         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
1012         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
1013     } else {
1014         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
1015         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
1016     }
1017
1018     memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
1019                           TYPE_FTGMAC100, 0x2000);
1020     sysbus_init_mmio(sbd, &s->iomem);
1021     sysbus_init_irq(sbd, &s->irq);
1022     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1023
1024     s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
1025                           object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
1026                           s);
1027     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1028 }
1029
1030 static const VMStateDescription vmstate_ftgmac100 = {
1031     .name = TYPE_FTGMAC100,
1032     .version_id = 1,
1033     .minimum_version_id = 1,
1034     .fields = (VMStateField[]) {
1035         VMSTATE_UINT32(irq_state, FTGMAC100State),
1036         VMSTATE_UINT32(isr, FTGMAC100State),
1037         VMSTATE_UINT32(ier, FTGMAC100State),
1038         VMSTATE_UINT32(rx_enabled, FTGMAC100State),
1039         VMSTATE_UINT32(rx_ring, FTGMAC100State),
1040         VMSTATE_UINT32(rbsr, FTGMAC100State),
1041         VMSTATE_UINT32(tx_ring, FTGMAC100State),
1042         VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
1043         VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
1044         VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
1045         VMSTATE_UINT32(itc, FTGMAC100State),
1046         VMSTATE_UINT32(aptcr, FTGMAC100State),
1047         VMSTATE_UINT32(dblac, FTGMAC100State),
1048         VMSTATE_UINT32(revr, FTGMAC100State),
1049         VMSTATE_UINT32(fear1, FTGMAC100State),
1050         VMSTATE_UINT32(tpafcr, FTGMAC100State),
1051         VMSTATE_UINT32(maccr, FTGMAC100State),
1052         VMSTATE_UINT32(phycr, FTGMAC100State),
1053         VMSTATE_UINT32(phydata, FTGMAC100State),
1054         VMSTATE_UINT32(fcr, FTGMAC100State),
1055         VMSTATE_UINT32(phy_status, FTGMAC100State),
1056         VMSTATE_UINT32(phy_control, FTGMAC100State),
1057         VMSTATE_UINT32(phy_advertise, FTGMAC100State),
1058         VMSTATE_UINT32(phy_int, FTGMAC100State),
1059         VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
1060         VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
1061         VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
1062         VMSTATE_END_OF_LIST()
1063     }
1064 };
1065
1066 static Property ftgmac100_properties[] = {
1067     DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
1068     DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
1069     DEFINE_PROP_END_OF_LIST(),
1070 };
1071
1072 static void ftgmac100_class_init(ObjectClass *klass, void *data)
1073 {
1074     DeviceClass *dc = DEVICE_CLASS(klass);
1075
1076     dc->vmsd = &vmstate_ftgmac100;
1077     dc->reset = ftgmac100_reset;
1078     dc->props = ftgmac100_properties;
1079     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1080     dc->realize = ftgmac100_realize;
1081     dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
1082 }
1083
1084 static const TypeInfo ftgmac100_info = {
1085     .name = TYPE_FTGMAC100,
1086     .parent = TYPE_SYS_BUS_DEVICE,
1087     .instance_size = sizeof(FTGMAC100State),
1088     .class_init = ftgmac100_class_init,
1089 };
1090
1091 /*
1092  * AST2600 MII controller
1093  */
1094 #define ASPEED_MII_PHYCR_FIRE        BIT(31)
1095 #define ASPEED_MII_PHYCR_ST_22       BIT(28)
1096 #define ASPEED_MII_PHYCR_OP(x)       ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \
1097                                              ASPEED_MII_PHYCR_OP_READ))
1098 #define ASPEED_MII_PHYCR_OP_WRITE    BIT(26)
1099 #define ASPEED_MII_PHYCR_OP_READ     BIT(27)
1100 #define ASPEED_MII_PHYCR_DATA(x)     (x & 0xffff)
1101 #define ASPEED_MII_PHYCR_PHY(x)      (((x) >> 21) & 0x1f)
1102 #define ASPEED_MII_PHYCR_REG(x)      (((x) >> 16) & 0x1f)
1103
1104 #define ASPEED_MII_PHYDATA_IDLE      BIT(16)
1105
1106 static void aspeed_mii_transition(AspeedMiiState *s, bool fire)
1107 {
1108     if (fire) {
1109         s->phycr |= ASPEED_MII_PHYCR_FIRE;
1110         s->phydata &= ~ASPEED_MII_PHYDATA_IDLE;
1111     } else {
1112         s->phycr &= ~ASPEED_MII_PHYCR_FIRE;
1113         s->phydata |= ASPEED_MII_PHYDATA_IDLE;
1114     }
1115 }
1116
1117 static void aspeed_mii_do_phy_ctl(AspeedMiiState *s)
1118 {
1119     uint8_t reg;
1120     uint16_t data;
1121
1122     if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) {
1123         aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
1124         qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
1125         return;
1126     }
1127
1128     /* Nothing to do */
1129     if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) {
1130         return;
1131     }
1132
1133     reg = ASPEED_MII_PHYCR_REG(s->phycr);
1134     data = ASPEED_MII_PHYCR_DATA(s->phycr);
1135
1136     switch (ASPEED_MII_PHYCR_OP(s->phycr)) {
1137     case ASPEED_MII_PHYCR_OP_WRITE:
1138         do_phy_write(s->nic, reg, data);
1139         break;
1140     case ASPEED_MII_PHYCR_OP_READ:
1141         s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg);
1142         break;
1143     default:
1144         qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
1145                       __func__, s->phycr);
1146     }
1147
1148     aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
1149 }
1150
1151 static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size)
1152 {
1153     AspeedMiiState *s = ASPEED_MII(opaque);
1154
1155     switch (addr) {
1156     case 0x0:
1157         return s->phycr;
1158     case 0x4:
1159         return s->phydata;
1160     default:
1161         g_assert_not_reached();
1162     }
1163 }
1164
1165 static void aspeed_mii_write(void *opaque, hwaddr addr,
1166                              uint64_t value, unsigned size)
1167 {
1168     AspeedMiiState *s = ASPEED_MII(opaque);
1169
1170     switch (addr) {
1171     case 0x0:
1172         s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE);
1173         break;
1174     case 0x4:
1175         s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE);
1176         break;
1177     default:
1178         g_assert_not_reached();
1179     }
1180
1181     aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
1182     aspeed_mii_do_phy_ctl(s);
1183 }
1184
1185 static const MemoryRegionOps aspeed_mii_ops = {
1186     .read = aspeed_mii_read,
1187     .write = aspeed_mii_write,
1188     .valid.min_access_size = 4,
1189     .valid.max_access_size = 4,
1190     .endianness = DEVICE_LITTLE_ENDIAN,
1191 };
1192
1193 static void aspeed_mii_reset(DeviceState *dev)
1194 {
1195     AspeedMiiState *s = ASPEED_MII(dev);
1196
1197     s->phycr = 0;
1198     s->phydata = 0;
1199
1200     aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
1201 };
1202
1203 static void aspeed_mii_realize(DeviceState *dev, Error **errp)
1204 {
1205     AspeedMiiState *s = ASPEED_MII(dev);
1206     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1207
1208     assert(s->nic);
1209
1210     memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s,
1211                           TYPE_ASPEED_MII, 0x8);
1212     sysbus_init_mmio(sbd, &s->iomem);
1213 }
1214
1215 static const VMStateDescription vmstate_aspeed_mii = {
1216     .name = TYPE_ASPEED_MII,
1217     .version_id = 1,
1218     .minimum_version_id = 1,
1219     .fields = (VMStateField[]) {
1220         VMSTATE_UINT32(phycr, FTGMAC100State),
1221         VMSTATE_UINT32(phydata, FTGMAC100State),
1222         VMSTATE_END_OF_LIST()
1223     }
1224 };
1225
1226 static Property aspeed_mii_properties[] = {
1227     DEFINE_PROP_LINK("nic", AspeedMiiState, nic, TYPE_FTGMAC100,
1228                      FTGMAC100State *),
1229     DEFINE_PROP_END_OF_LIST(),
1230 };
1231
1232 static void aspeed_mii_class_init(ObjectClass *klass, void *data)
1233 {
1234     DeviceClass *dc = DEVICE_CLASS(klass);
1235
1236     dc->vmsd = &vmstate_aspeed_mii;
1237     dc->reset = aspeed_mii_reset;
1238     dc->realize = aspeed_mii_realize;
1239     dc->desc = "Aspeed MII controller";
1240     dc->props = aspeed_mii_properties;
1241 }
1242
1243 static const TypeInfo aspeed_mii_info = {
1244     .name = TYPE_ASPEED_MII,
1245     .parent = TYPE_SYS_BUS_DEVICE,
1246     .instance_size = sizeof(AspeedMiiState),
1247     .class_init = aspeed_mii_class_init,
1248 };
1249
1250 static void ftgmac100_register_types(void)
1251 {
1252     type_register_static(&ftgmac100_info);
1253     type_register_static(&aspeed_mii_info);
1254 }
1255
1256 type_init(ftgmac100_register_types)