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ppc/pnv: Link "chip" property to PnvCore::chip pointer
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob12ff55fcfb543208c18ba44d569e4d8382cc038c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "hw/core/cpu.h"
31 #include "target/i386/cpu.h"
32 #include "hw/misc/pvpanic.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/block/fdc.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "hw/acpi/vmgenid.h"
45 #include "hw/boards.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/rtc/mc146818rtc_regs.h"
48 #include "migration/vmstate.h"
49 #include "hw/mem/memory-device.h"
50 #include "sysemu/numa.h"
51 #include "sysemu/reset.h"
52
53 /* Supported chipsets: */
54 #include "hw/southbridge/piix.h"
55 #include "hw/acpi/pcihp.h"
56 #include "hw/i386/ich9.h"
57 #include "hw/pci/pci_bus.h"
58 #include "hw/pci-host/q35.h"
59 #include "hw/i386/x86-iommu.h"
60
61 #include "hw/acpi/aml-build.h"
62 #include "hw/acpi/utils.h"
63 #include "hw/acpi/pci.h"
64
65 #include "qom/qom-qobject.h"
66 #include "hw/i386/amd_iommu.h"
67 #include "hw/i386/intel_iommu.h"
68
69 #include "hw/acpi/ipmi.h"
70
71 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
72 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
73 * a little bit, there should be plenty of free space since the DSDT
74 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
75 */
76 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
77 #define ACPI_BUILD_ALIGN_SIZE 0x1000
78
79 #define ACPI_BUILD_TABLE_SIZE 0x20000
80
81 /* #define DEBUG_ACPI_BUILD */
82 #ifdef DEBUG_ACPI_BUILD
83 #define ACPI_BUILD_DPRINTF(fmt, ...) \
84 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
85 #else
86 #define ACPI_BUILD_DPRINTF(fmt, ...)
87 #endif
88
89 /* Default IOAPIC ID */
90 #define ACPI_BUILD_IOAPIC_ID 0x0
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 AcpiFadtData fadt;
98 uint16_t cpu_hp_io_base;
99 uint16_t pcihp_io_base;
100 uint16_t pcihp_io_len;
101 } AcpiPmInfo;
102
103 typedef struct AcpiMiscInfo {
104 bool is_piix4;
105 bool has_hpet;
106 TPMVersion tpm_version;
107 const unsigned char *dsdt_code;
108 unsigned dsdt_size;
109 uint16_t pvpanic_port;
110 uint16_t applesmc_io_base;
111 } AcpiMiscInfo;
112
113 typedef struct AcpiBuildPciBusHotplugState {
114 GArray *device_table;
115 GArray *notify_table;
116 struct AcpiBuildPciBusHotplugState *parent;
117 bool pcihp_bridge_en;
118 } AcpiBuildPciBusHotplugState;
119
120 typedef struct FwCfgTPMConfig {
121 uint32_t tpmppi_address;
122 uint8_t tpm_version;
123 uint8_t tpmppi_version;
124 } QEMU_PACKED FwCfgTPMConfig;
125
126 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
127
128 static void init_common_fadt_data(MachineState *ms, Object *o,
129 AcpiFadtData *data)
130 {
131 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
132 AmlAddressSpace as = AML_AS_SYSTEM_IO;
133 AcpiFadtData fadt = {
134 .rev = 3,
135 .flags =
136 (1 << ACPI_FADT_F_WBINVD) |
137 (1 << ACPI_FADT_F_PROC_C1) |
138 (1 << ACPI_FADT_F_SLP_BUTTON) |
139 (1 << ACPI_FADT_F_RTC_S4) |
140 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
141 /* APIC destination mode ("Flat Logical") has an upper limit of 8
142 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
143 * used
144 */
145 ((ms->smp.max_cpus > 8) ?
146 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
147 .int_model = 1 /* Multiple APIC */,
148 .rtc_century = RTC_CENTURY,
149 .plvl2_lat = 0xfff /* C2 state not supported */,
150 .plvl3_lat = 0xfff /* C3 state not supported */,
151 .smi_cmd = ACPI_PORT_SMI_CMD,
152 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
153 .acpi_enable_cmd =
154 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
155 .acpi_disable_cmd =
156 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
157 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
158 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
159 .address = io + 0x04 },
160 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
161 .gpe0_blk = { .space_id = as, .bit_width =
162 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
163 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
164 },
165 };
166 *data = fadt;
167 }
168
169 static Object *object_resolve_type_unambiguous(const char *typename)
170 {
171 bool ambig;
172 Object *o = object_resolve_path_type("", typename, &ambig);
173
174 if (ambig || !o) {
175 return NULL;
176 }
177 return o;
178 }
179
180 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
181 {
182 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
183 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
184 Object *obj = piix ? piix : lpc;
185 QObject *o;
186 pm->cpu_hp_io_base = 0;
187 pm->pcihp_io_base = 0;
188 pm->pcihp_io_len = 0;
189
190 assert(obj);
191 init_common_fadt_data(machine, obj, &pm->fadt);
192 if (piix) {
193 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
194 pm->fadt.rev = 1;
195 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
196 pm->pcihp_io_base =
197 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
198 pm->pcihp_io_len =
199 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
200 }
201 if (lpc) {
202 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
203 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
204 pm->fadt.reset_reg = r;
205 pm->fadt.reset_val = 0xf;
206 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
207 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
208 }
209
210 /* The above need not be conditional on machine type because the reset port
211 * happens to be the same on PIIX (pc) and ICH9 (q35). */
212 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
213
214 /* Fill in optional s3/s4 related properties */
215 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
216 if (o) {
217 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
218 } else {
219 pm->s3_disabled = false;
220 }
221 qobject_unref(o);
222 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
223 if (o) {
224 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
225 } else {
226 pm->s4_disabled = false;
227 }
228 qobject_unref(o);
229 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
230 if (o) {
231 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
232 } else {
233 pm->s4_val = false;
234 }
235 qobject_unref(o);
236
237 pm->pcihp_bridge_en =
238 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
239 NULL);
240 }
241
242 static void acpi_get_misc_info(AcpiMiscInfo *info)
243 {
244 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
245 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
246 assert(!!piix != !!lpc);
247
248 if (piix) {
249 info->is_piix4 = true;
250 }
251 if (lpc) {
252 info->is_piix4 = false;
253 }
254
255 info->has_hpet = hpet_find();
256 info->tpm_version = tpm_get_version(tpm_find());
257 info->pvpanic_port = pvpanic_port();
258 info->applesmc_io_base = applesmc_port();
259 }
260
261 /*
262 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
263 * On i386 arch we only have two pci hosts, so we can look only for them.
264 */
265 static Object *acpi_get_i386_pci_host(void)
266 {
267 PCIHostState *host;
268
269 host = OBJECT_CHECK(PCIHostState,
270 object_resolve_path("/machine/i440fx", NULL),
271 TYPE_PCI_HOST_BRIDGE);
272 if (!host) {
273 host = OBJECT_CHECK(PCIHostState,
274 object_resolve_path("/machine/q35", NULL),
275 TYPE_PCI_HOST_BRIDGE);
276 }
277
278 return OBJECT(host);
279 }
280
281 static void acpi_get_pci_holes(Range *hole, Range *hole64)
282 {
283 Object *pci_host;
284
285 pci_host = acpi_get_i386_pci_host();
286 g_assert(pci_host);
287
288 range_set_bounds1(hole,
289 object_property_get_uint(pci_host,
290 PCI_HOST_PROP_PCI_HOLE_START,
291 NULL),
292 object_property_get_uint(pci_host,
293 PCI_HOST_PROP_PCI_HOLE_END,
294 NULL));
295 range_set_bounds1(hole64,
296 object_property_get_uint(pci_host,
297 PCI_HOST_PROP_PCI_HOLE64_START,
298 NULL),
299 object_property_get_uint(pci_host,
300 PCI_HOST_PROP_PCI_HOLE64_END,
301 NULL));
302 }
303
304 static void acpi_align_size(GArray *blob, unsigned align)
305 {
306 /* Align size to multiple of given size. This reduces the chance
307 * we need to change size in the future (breaking cross version migration).
308 */
309 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
310 }
311
312 /* FACS */
313 static void
314 build_facs(GArray *table_data)
315 {
316 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
317 memcpy(&facs->signature, "FACS", 4);
318 facs->length = cpu_to_le32(sizeof(*facs));
319 }
320
321 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
322 const CPUArchIdList *apic_ids, GArray *entry)
323 {
324 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
325
326 /* ACPI spec says that LAPIC entry for non present
327 * CPU may be omitted from MADT or it must be marked
328 * as disabled. However omitting non present CPU from
329 * MADT breaks hotplug on linux. So possible CPUs
330 * should be put in MADT but kept disabled.
331 */
332 if (apic_id < 255) {
333 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
334
335 apic->type = ACPI_APIC_PROCESSOR;
336 apic->length = sizeof(*apic);
337 apic->processor_id = uid;
338 apic->local_apic_id = apic_id;
339 if (apic_ids->cpus[uid].cpu != NULL) {
340 apic->flags = cpu_to_le32(1);
341 } else {
342 apic->flags = cpu_to_le32(0);
343 }
344 } else {
345 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
346
347 apic->type = ACPI_APIC_LOCAL_X2APIC;
348 apic->length = sizeof(*apic);
349 apic->uid = cpu_to_le32(uid);
350 apic->x2apic_id = cpu_to_le32(apic_id);
351 if (apic_ids->cpus[uid].cpu != NULL) {
352 apic->flags = cpu_to_le32(1);
353 } else {
354 apic->flags = cpu_to_le32(0);
355 }
356 }
357 }
358
359 static void
360 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
361 {
362 MachineClass *mc = MACHINE_GET_CLASS(pcms);
363 X86MachineState *x86ms = X86_MACHINE(pcms);
364 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
365 int madt_start = table_data->len;
366 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
367 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
368 bool x2apic_mode = false;
369
370 AcpiMultipleApicTable *madt;
371 AcpiMadtIoApic *io_apic;
372 AcpiMadtIntsrcovr *intsrcovr;
373 int i;
374
375 madt = acpi_data_push(table_data, sizeof *madt);
376 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
377 madt->flags = cpu_to_le32(1);
378
379 for (i = 0; i < apic_ids->len; i++) {
380 adevc->madt_cpu(adev, i, apic_ids, table_data);
381 if (apic_ids->cpus[i].arch_id > 254) {
382 x2apic_mode = true;
383 }
384 }
385
386 io_apic = acpi_data_push(table_data, sizeof *io_apic);
387 io_apic->type = ACPI_APIC_IO;
388 io_apic->length = sizeof(*io_apic);
389 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
390 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
391 io_apic->interrupt = cpu_to_le32(0);
392
393 if (x86ms->apic_xrupt_override) {
394 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
395 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
396 intsrcovr->length = sizeof(*intsrcovr);
397 intsrcovr->source = 0;
398 intsrcovr->gsi = cpu_to_le32(2);
399 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
400 }
401 for (i = 1; i < 16; i++) {
402 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
403 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
404 /* No need for a INT source override structure. */
405 continue;
406 }
407 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
408 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
409 intsrcovr->length = sizeof(*intsrcovr);
410 intsrcovr->source = i;
411 intsrcovr->gsi = cpu_to_le32(i);
412 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
413 }
414
415 if (x2apic_mode) {
416 AcpiMadtLocalX2ApicNmi *local_nmi;
417
418 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
419 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
420 local_nmi->length = sizeof(*local_nmi);
421 local_nmi->uid = 0xFFFFFFFF; /* all processors */
422 local_nmi->flags = cpu_to_le16(0);
423 local_nmi->lint = 1; /* ACPI_LINT1 */
424 } else {
425 AcpiMadtLocalNmi *local_nmi;
426
427 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
428 local_nmi->type = ACPI_APIC_LOCAL_NMI;
429 local_nmi->length = sizeof(*local_nmi);
430 local_nmi->processor_id = 0xff; /* all processors */
431 local_nmi->flags = cpu_to_le16(0);
432 local_nmi->lint = 1; /* ACPI_LINT1 */
433 }
434
435 build_header(linker, table_data,
436 (void *)(table_data->data + madt_start), "APIC",
437 table_data->len - madt_start, 1, NULL, NULL);
438 }
439
440 static void build_append_pcihp_notify_entry(Aml *method, int slot)
441 {
442 Aml *if_ctx;
443 int32_t devfn = PCI_DEVFN(slot, 0);
444
445 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
446 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
447 aml_append(method, if_ctx);
448 }
449
450 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
451 bool pcihp_bridge_en)
452 {
453 Aml *dev, *notify_method = NULL, *method;
454 QObject *bsel;
455 PCIBus *sec;
456 int i;
457
458 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
459 if (bsel) {
460 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
461
462 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
463 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
464 }
465
466 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
467 DeviceClass *dc;
468 PCIDeviceClass *pc;
469 PCIDevice *pdev = bus->devices[i];
470 int slot = PCI_SLOT(i);
471 bool hotplug_enabled_dev;
472 bool bridge_in_acpi;
473
474 if (!pdev) {
475 if (bsel) { /* add hotplug slots for non present devices */
476 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
477 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
478 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
479 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
480 aml_append(method,
481 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
482 );
483 aml_append(dev, method);
484 aml_append(parent_scope, dev);
485
486 build_append_pcihp_notify_entry(notify_method, slot);
487 }
488 continue;
489 }
490
491 pc = PCI_DEVICE_GET_CLASS(pdev);
492 dc = DEVICE_GET_CLASS(pdev);
493
494 /* When hotplug for bridges is enabled, bridges are
495 * described in ACPI separately (see build_pci_bus_end).
496 * In this case they aren't themselves hot-pluggable.
497 * Hotplugged bridges *are* hot-pluggable.
498 */
499 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
500 !DEVICE(pdev)->hotplugged;
501
502 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
503
504 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
505 continue;
506 }
507
508 /* start to compose PCI slot descriptor */
509 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
510 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
511
512 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
513 /* add VGA specific AML methods */
514 int s3d;
515
516 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
517 s3d = 3;
518 } else {
519 s3d = 0;
520 }
521
522 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
523 aml_append(method, aml_return(aml_int(0)));
524 aml_append(dev, method);
525
526 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
527 aml_append(method, aml_return(aml_int(0)));
528 aml_append(dev, method);
529
530 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
531 aml_append(method, aml_return(aml_int(s3d)));
532 aml_append(dev, method);
533 } else if (hotplug_enabled_dev) {
534 /* add _SUN/_EJ0 to make slot hotpluggable */
535 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
536
537 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
538 aml_append(method,
539 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
540 );
541 aml_append(dev, method);
542
543 if (bsel) {
544 build_append_pcihp_notify_entry(notify_method, slot);
545 }
546 } else if (bridge_in_acpi) {
547 /*
548 * device is coldplugged bridge,
549 * add child device descriptions into its scope
550 */
551 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
552
553 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
554 }
555 /* slot descriptor has been composed, add it into parent context */
556 aml_append(parent_scope, dev);
557 }
558
559 if (bsel) {
560 aml_append(parent_scope, notify_method);
561 }
562
563 /* Append PCNT method to notify about events on local and child buses.
564 * Add unconditionally for root since DSDT expects it.
565 */
566 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
567
568 /* If bus supports hotplug select it and notify about local events */
569 if (bsel) {
570 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
571
572 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
573 aml_append(method,
574 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
575 );
576 aml_append(method,
577 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
578 );
579 }
580
581 /* Notify about child bus events in any case */
582 if (pcihp_bridge_en) {
583 QLIST_FOREACH(sec, &bus->child, sibling) {
584 int32_t devfn = sec->parent_dev->devfn;
585
586 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
587 continue;
588 }
589
590 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
591 }
592 }
593 aml_append(parent_scope, method);
594 qobject_unref(bsel);
595 }
596
597 /**
598 * build_prt_entry:
599 * @link_name: link name for PCI route entry
600 *
601 * build AML package containing a PCI route entry for @link_name
602 */
603 static Aml *build_prt_entry(const char *link_name)
604 {
605 Aml *a_zero = aml_int(0);
606 Aml *pkg = aml_package(4);
607 aml_append(pkg, a_zero);
608 aml_append(pkg, a_zero);
609 aml_append(pkg, aml_name("%s", link_name));
610 aml_append(pkg, a_zero);
611 return pkg;
612 }
613
614 /*
615 * initialize_route - Initialize the interrupt routing rule
616 * through a specific LINK:
617 * if (lnk_idx == idx)
618 * route using link 'link_name'
619 */
620 static Aml *initialize_route(Aml *route, const char *link_name,
621 Aml *lnk_idx, int idx)
622 {
623 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
624 Aml *pkg = build_prt_entry(link_name);
625
626 aml_append(if_ctx, aml_store(pkg, route));
627
628 return if_ctx;
629 }
630
631 /*
632 * build_prt - Define interrupt rounting rules
633 *
634 * Returns an array of 128 routes, one for each device,
635 * based on device location.
636 * The main goal is to equaly distribute the interrupts
637 * over the 4 existing ACPI links (works only for i440fx).
638 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
639 *
640 */
641 static Aml *build_prt(bool is_pci0_prt)
642 {
643 Aml *method, *while_ctx, *pin, *res;
644
645 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
646 res = aml_local(0);
647 pin = aml_local(1);
648 aml_append(method, aml_store(aml_package(128), res));
649 aml_append(method, aml_store(aml_int(0), pin));
650
651 /* while (pin < 128) */
652 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
653 {
654 Aml *slot = aml_local(2);
655 Aml *lnk_idx = aml_local(3);
656 Aml *route = aml_local(4);
657
658 /* slot = pin >> 2 */
659 aml_append(while_ctx,
660 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
661 /* lnk_idx = (slot + pin) & 3 */
662 aml_append(while_ctx,
663 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
664 lnk_idx));
665
666 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
667 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
668 if (is_pci0_prt) {
669 Aml *if_device_1, *if_pin_4, *else_pin_4;
670
671 /* device 1 is the power-management device, needs SCI */
672 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
673 {
674 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
675 {
676 aml_append(if_pin_4,
677 aml_store(build_prt_entry("LNKS"), route));
678 }
679 aml_append(if_device_1, if_pin_4);
680 else_pin_4 = aml_else();
681 {
682 aml_append(else_pin_4,
683 aml_store(build_prt_entry("LNKA"), route));
684 }
685 aml_append(if_device_1, else_pin_4);
686 }
687 aml_append(while_ctx, if_device_1);
688 } else {
689 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
690 }
691 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
692 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
693
694 /* route[0] = 0x[slot]FFFF */
695 aml_append(while_ctx,
696 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
697 NULL),
698 aml_index(route, aml_int(0))));
699 /* route[1] = pin & 3 */
700 aml_append(while_ctx,
701 aml_store(aml_and(pin, aml_int(3), NULL),
702 aml_index(route, aml_int(1))));
703 /* res[pin] = route */
704 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
705 /* pin++ */
706 aml_append(while_ctx, aml_increment(pin));
707 }
708 aml_append(method, while_ctx);
709 /* return res*/
710 aml_append(method, aml_return(res));
711
712 return method;
713 }
714
715 typedef struct CrsRangeEntry {
716 uint64_t base;
717 uint64_t limit;
718 } CrsRangeEntry;
719
720 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
721 {
722 CrsRangeEntry *entry;
723
724 entry = g_malloc(sizeof(*entry));
725 entry->base = base;
726 entry->limit = limit;
727
728 g_ptr_array_add(ranges, entry);
729 }
730
731 static void crs_range_free(gpointer data)
732 {
733 CrsRangeEntry *entry = (CrsRangeEntry *)data;
734 g_free(entry);
735 }
736
737 typedef struct CrsRangeSet {
738 GPtrArray *io_ranges;
739 GPtrArray *mem_ranges;
740 GPtrArray *mem_64bit_ranges;
741 } CrsRangeSet;
742
743 static void crs_range_set_init(CrsRangeSet *range_set)
744 {
745 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
746 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
747 range_set->mem_64bit_ranges =
748 g_ptr_array_new_with_free_func(crs_range_free);
749 }
750
751 static void crs_range_set_free(CrsRangeSet *range_set)
752 {
753 g_ptr_array_free(range_set->io_ranges, true);
754 g_ptr_array_free(range_set->mem_ranges, true);
755 g_ptr_array_free(range_set->mem_64bit_ranges, true);
756 }
757
758 static gint crs_range_compare(gconstpointer a, gconstpointer b)
759 {
760 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
761 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
762
763 if (entry_a->base < entry_b->base) {
764 return -1;
765 } else if (entry_a->base > entry_b->base) {
766 return 1;
767 } else {
768 return 0;
769 }
770 }
771
772 /*
773 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
774 * interval, computes the 'free' ranges from the same interval.
775 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
776 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
777 */
778 static void crs_replace_with_free_ranges(GPtrArray *ranges,
779 uint64_t start, uint64_t end)
780 {
781 GPtrArray *free_ranges = g_ptr_array_new();
782 uint64_t free_base = start;
783 int i;
784
785 g_ptr_array_sort(ranges, crs_range_compare);
786 for (i = 0; i < ranges->len; i++) {
787 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
788
789 if (free_base < used->base) {
790 crs_range_insert(free_ranges, free_base, used->base - 1);
791 }
792
793 free_base = used->limit + 1;
794 }
795
796 if (free_base < end) {
797 crs_range_insert(free_ranges, free_base, end);
798 }
799
800 g_ptr_array_set_size(ranges, 0);
801 for (i = 0; i < free_ranges->len; i++) {
802 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
803 }
804
805 g_ptr_array_free(free_ranges, true);
806 }
807
808 /*
809 * crs_range_merge - merges adjacent ranges in the given array.
810 * Array elements are deleted and replaced with the merged ranges.
811 */
812 static void crs_range_merge(GPtrArray *range)
813 {
814 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
815 CrsRangeEntry *entry;
816 uint64_t range_base, range_limit;
817 int i;
818
819 if (!range->len) {
820 return;
821 }
822
823 g_ptr_array_sort(range, crs_range_compare);
824
825 entry = g_ptr_array_index(range, 0);
826 range_base = entry->base;
827 range_limit = entry->limit;
828 for (i = 1; i < range->len; i++) {
829 entry = g_ptr_array_index(range, i);
830 if (entry->base - 1 == range_limit) {
831 range_limit = entry->limit;
832 } else {
833 crs_range_insert(tmp, range_base, range_limit);
834 range_base = entry->base;
835 range_limit = entry->limit;
836 }
837 }
838 crs_range_insert(tmp, range_base, range_limit);
839
840 g_ptr_array_set_size(range, 0);
841 for (i = 0; i < tmp->len; i++) {
842 entry = g_ptr_array_index(tmp, i);
843 crs_range_insert(range, entry->base, entry->limit);
844 }
845 g_ptr_array_free(tmp, true);
846 }
847
848 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
849 {
850 Aml *crs = aml_resource_template();
851 CrsRangeSet temp_range_set;
852 CrsRangeEntry *entry;
853 uint8_t max_bus = pci_bus_num(host->bus);
854 uint8_t type;
855 int devfn;
856 int i;
857
858 crs_range_set_init(&temp_range_set);
859 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
860 uint64_t range_base, range_limit;
861 PCIDevice *dev = host->bus->devices[devfn];
862
863 if (!dev) {
864 continue;
865 }
866
867 for (i = 0; i < PCI_NUM_REGIONS; i++) {
868 PCIIORegion *r = &dev->io_regions[i];
869
870 range_base = r->addr;
871 range_limit = r->addr + r->size - 1;
872
873 /*
874 * Work-around for old bioses
875 * that do not support multiple root buses
876 */
877 if (!range_base || range_base > range_limit) {
878 continue;
879 }
880
881 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
882 crs_range_insert(temp_range_set.io_ranges,
883 range_base, range_limit);
884 } else { /* "memory" */
885 crs_range_insert(temp_range_set.mem_ranges,
886 range_base, range_limit);
887 }
888 }
889
890 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
891 if (type == PCI_HEADER_TYPE_BRIDGE) {
892 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
893 if (subordinate > max_bus) {
894 max_bus = subordinate;
895 }
896
897 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
898 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
899
900 /*
901 * Work-around for old bioses
902 * that do not support multiple root buses
903 */
904 if (range_base && range_base <= range_limit) {
905 crs_range_insert(temp_range_set.io_ranges,
906 range_base, range_limit);
907 }
908
909 range_base =
910 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
911 range_limit =
912 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
913
914 /*
915 * Work-around for old bioses
916 * that do not support multiple root buses
917 */
918 if (range_base && range_base <= range_limit) {
919 uint64_t length = range_limit - range_base + 1;
920 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
921 crs_range_insert(temp_range_set.mem_ranges,
922 range_base, range_limit);
923 } else {
924 crs_range_insert(temp_range_set.mem_64bit_ranges,
925 range_base, range_limit);
926 }
927 }
928
929 range_base =
930 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
931 range_limit =
932 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
933
934 /*
935 * Work-around for old bioses
936 * that do not support multiple root buses
937 */
938 if (range_base && range_base <= range_limit) {
939 uint64_t length = range_limit - range_base + 1;
940 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
941 crs_range_insert(temp_range_set.mem_ranges,
942 range_base, range_limit);
943 } else {
944 crs_range_insert(temp_range_set.mem_64bit_ranges,
945 range_base, range_limit);
946 }
947 }
948 }
949 }
950
951 crs_range_merge(temp_range_set.io_ranges);
952 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
953 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
954 aml_append(crs,
955 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
956 AML_POS_DECODE, AML_ENTIRE_RANGE,
957 0, entry->base, entry->limit, 0,
958 entry->limit - entry->base + 1));
959 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
960 }
961
962 crs_range_merge(temp_range_set.mem_ranges);
963 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
964 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
965 aml_append(crs,
966 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
967 AML_MAX_FIXED, AML_NON_CACHEABLE,
968 AML_READ_WRITE,
969 0, entry->base, entry->limit, 0,
970 entry->limit - entry->base + 1));
971 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
972 }
973
974 crs_range_merge(temp_range_set.mem_64bit_ranges);
975 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
976 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
977 aml_append(crs,
978 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
979 AML_MAX_FIXED, AML_NON_CACHEABLE,
980 AML_READ_WRITE,
981 0, entry->base, entry->limit, 0,
982 entry->limit - entry->base + 1));
983 crs_range_insert(range_set->mem_64bit_ranges,
984 entry->base, entry->limit);
985 }
986
987 crs_range_set_free(&temp_range_set);
988
989 aml_append(crs,
990 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
991 0,
992 pci_bus_num(host->bus),
993 max_bus,
994 0,
995 max_bus - pci_bus_num(host->bus) + 1));
996
997 return crs;
998 }
999
1000 static void build_hpet_aml(Aml *table)
1001 {
1002 Aml *crs;
1003 Aml *field;
1004 Aml *method;
1005 Aml *if_ctx;
1006 Aml *scope = aml_scope("_SB");
1007 Aml *dev = aml_device("HPET");
1008 Aml *zero = aml_int(0);
1009 Aml *id = aml_local(0);
1010 Aml *period = aml_local(1);
1011
1012 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1013 aml_append(dev, aml_name_decl("_UID", zero));
1014
1015 aml_append(dev,
1016 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1017 HPET_LEN));
1018 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1019 aml_append(field, aml_named_field("VEND", 32));
1020 aml_append(field, aml_named_field("PRD", 32));
1021 aml_append(dev, field);
1022
1023 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1024 aml_append(method, aml_store(aml_name("VEND"), id));
1025 aml_append(method, aml_store(aml_name("PRD"), period));
1026 aml_append(method, aml_shiftright(id, aml_int(16), id));
1027 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1028 aml_equal(id, aml_int(0xffff))));
1029 {
1030 aml_append(if_ctx, aml_return(zero));
1031 }
1032 aml_append(method, if_ctx);
1033
1034 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1035 aml_lgreater(period, aml_int(100000000))));
1036 {
1037 aml_append(if_ctx, aml_return(zero));
1038 }
1039 aml_append(method, if_ctx);
1040
1041 aml_append(method, aml_return(aml_int(0x0F)));
1042 aml_append(dev, method);
1043
1044 crs = aml_resource_template();
1045 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1046 aml_append(dev, aml_name_decl("_CRS", crs));
1047
1048 aml_append(scope, dev);
1049 aml_append(table, scope);
1050 }
1051
1052 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1053 {
1054 Aml *dev, *fdi;
1055 uint8_t maxc, maxh, maxs;
1056
1057 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1058
1059 dev = aml_device("FLP%c", 'A' + idx);
1060
1061 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1062
1063 fdi = aml_package(16);
1064 aml_append(fdi, aml_int(idx)); /* Drive Number */
1065 aml_append(fdi,
1066 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1067 /*
1068 * the values below are the limits of the drive, and are thus independent
1069 * of the inserted media
1070 */
1071 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1072 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1073 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1074 /*
1075 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1076 * the drive type, so shall we
1077 */
1078 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1079 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1080 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1081 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1082 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1083 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1084 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1085 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1086 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1087 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1088 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1089
1090 aml_append(dev, aml_name_decl("_FDI", fdi));
1091 return dev;
1092 }
1093
1094 static Aml *build_fdc_device_aml(ISADevice *fdc)
1095 {
1096 int i;
1097 Aml *dev;
1098 Aml *crs;
1099
1100 #define ACPI_FDE_MAX_FD 4
1101 uint32_t fde_buf[5] = {
1102 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1103 cpu_to_le32(2) /* tape presence (2 == never present) */
1104 };
1105
1106 dev = aml_device("FDC0");
1107 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1108
1109 crs = aml_resource_template();
1110 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1111 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1112 aml_append(crs, aml_irq_no_flags(6));
1113 aml_append(crs,
1114 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1115 aml_append(dev, aml_name_decl("_CRS", crs));
1116
1117 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1118 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1119
1120 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1121 fde_buf[i] = cpu_to_le32(1); /* drive present */
1122 aml_append(dev, build_fdinfo_aml(i, type));
1123 }
1124 }
1125 aml_append(dev, aml_name_decl("_FDE",
1126 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1127
1128 return dev;
1129 }
1130
1131 static Aml *build_rtc_device_aml(void)
1132 {
1133 Aml *dev;
1134 Aml *crs;
1135
1136 dev = aml_device("RTC");
1137 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1138 crs = aml_resource_template();
1139 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1140 aml_append(crs, aml_irq_no_flags(8));
1141 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1142 aml_append(dev, aml_name_decl("_CRS", crs));
1143
1144 return dev;
1145 }
1146
1147 static Aml *build_kbd_device_aml(void)
1148 {
1149 Aml *dev;
1150 Aml *crs;
1151 Aml *method;
1152
1153 dev = aml_device("KBD");
1154 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1155
1156 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1157 aml_append(method, aml_return(aml_int(0x0f)));
1158 aml_append(dev, method);
1159
1160 crs = aml_resource_template();
1161 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1162 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1163 aml_append(crs, aml_irq_no_flags(1));
1164 aml_append(dev, aml_name_decl("_CRS", crs));
1165
1166 return dev;
1167 }
1168
1169 static Aml *build_mouse_device_aml(void)
1170 {
1171 Aml *dev;
1172 Aml *crs;
1173 Aml *method;
1174
1175 dev = aml_device("MOU");
1176 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1177
1178 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1179 aml_append(method, aml_return(aml_int(0x0f)));
1180 aml_append(dev, method);
1181
1182 crs = aml_resource_template();
1183 aml_append(crs, aml_irq_no_flags(12));
1184 aml_append(dev, aml_name_decl("_CRS", crs));
1185
1186 return dev;
1187 }
1188
1189 static Aml *build_lpt_device_aml(void)
1190 {
1191 Aml *dev;
1192 Aml *crs;
1193 Aml *method;
1194 Aml *if_ctx;
1195 Aml *else_ctx;
1196 Aml *zero = aml_int(0);
1197 Aml *is_present = aml_local(0);
1198
1199 dev = aml_device("LPT");
1200 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1201
1202 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1203 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1204 if_ctx = aml_if(aml_equal(is_present, zero));
1205 {
1206 aml_append(if_ctx, aml_return(aml_int(0x00)));
1207 }
1208 aml_append(method, if_ctx);
1209 else_ctx = aml_else();
1210 {
1211 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1212 }
1213 aml_append(method, else_ctx);
1214 aml_append(dev, method);
1215
1216 crs = aml_resource_template();
1217 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1218 aml_append(crs, aml_irq_no_flags(7));
1219 aml_append(dev, aml_name_decl("_CRS", crs));
1220
1221 return dev;
1222 }
1223
1224 static Aml *build_com_device_aml(uint8_t uid)
1225 {
1226 Aml *dev;
1227 Aml *crs;
1228 Aml *method;
1229 Aml *if_ctx;
1230 Aml *else_ctx;
1231 Aml *zero = aml_int(0);
1232 Aml *is_present = aml_local(0);
1233 const char *enabled_field = "CAEN";
1234 uint8_t irq = 4;
1235 uint16_t io_port = 0x03F8;
1236
1237 assert(uid == 1 || uid == 2);
1238 if (uid == 2) {
1239 enabled_field = "CBEN";
1240 irq = 3;
1241 io_port = 0x02F8;
1242 }
1243
1244 dev = aml_device("COM%d", uid);
1245 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1246 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1247
1248 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1249 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1250 if_ctx = aml_if(aml_equal(is_present, zero));
1251 {
1252 aml_append(if_ctx, aml_return(aml_int(0x00)));
1253 }
1254 aml_append(method, if_ctx);
1255 else_ctx = aml_else();
1256 {
1257 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1258 }
1259 aml_append(method, else_ctx);
1260 aml_append(dev, method);
1261
1262 crs = aml_resource_template();
1263 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1264 aml_append(crs, aml_irq_no_flags(irq));
1265 aml_append(dev, aml_name_decl("_CRS", crs));
1266
1267 return dev;
1268 }
1269
1270 static void build_isa_devices_aml(Aml *table)
1271 {
1272 ISADevice *fdc = pc_find_fdc0();
1273 bool ambiguous;
1274
1275 Aml *scope = aml_scope("_SB.PCI0.ISA");
1276 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1277
1278 aml_append(scope, build_rtc_device_aml());
1279 aml_append(scope, build_kbd_device_aml());
1280 aml_append(scope, build_mouse_device_aml());
1281 if (fdc) {
1282 aml_append(scope, build_fdc_device_aml(fdc));
1283 }
1284 aml_append(scope, build_lpt_device_aml());
1285 aml_append(scope, build_com_device_aml(1));
1286 aml_append(scope, build_com_device_aml(2));
1287
1288 if (ambiguous) {
1289 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1290 } else if (!obj) {
1291 error_report("No ISA bus, unable to define IPMI ACPI data");
1292 } else {
1293 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
1294 }
1295
1296 aml_append(table, scope);
1297 }
1298
1299 static void build_dbg_aml(Aml *table)
1300 {
1301 Aml *field;
1302 Aml *method;
1303 Aml *while_ctx;
1304 Aml *scope = aml_scope("\\");
1305 Aml *buf = aml_local(0);
1306 Aml *len = aml_local(1);
1307 Aml *idx = aml_local(2);
1308
1309 aml_append(scope,
1310 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1311 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1312 aml_append(field, aml_named_field("DBGB", 8));
1313 aml_append(scope, field);
1314
1315 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1316
1317 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1318 aml_append(method, aml_to_buffer(buf, buf));
1319 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1320 aml_append(method, aml_store(aml_int(0), idx));
1321
1322 while_ctx = aml_while(aml_lless(idx, len));
1323 aml_append(while_ctx,
1324 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1325 aml_append(while_ctx, aml_increment(idx));
1326 aml_append(method, while_ctx);
1327
1328 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1329 aml_append(scope, method);
1330
1331 aml_append(table, scope);
1332 }
1333
1334 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1335 {
1336 Aml *dev;
1337 Aml *crs;
1338 Aml *method;
1339 uint32_t irqs[] = {5, 10, 11};
1340
1341 dev = aml_device("%s", name);
1342 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1343 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1344
1345 crs = aml_resource_template();
1346 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1347 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1348 aml_append(dev, aml_name_decl("_PRS", crs));
1349
1350 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1351 aml_append(method, aml_return(aml_call1("IQST", reg)));
1352 aml_append(dev, method);
1353
1354 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1355 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1356 aml_append(dev, method);
1357
1358 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1359 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1360 aml_append(dev, method);
1361
1362 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1363 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1364 aml_append(method, aml_store(aml_name("PRRI"), reg));
1365 aml_append(dev, method);
1366
1367 return dev;
1368 }
1369
1370 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1371 {
1372 Aml *dev;
1373 Aml *crs;
1374 Aml *method;
1375 uint32_t irqs;
1376
1377 dev = aml_device("%s", name);
1378 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1379 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1380
1381 crs = aml_resource_template();
1382 irqs = gsi;
1383 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1384 AML_SHARED, &irqs, 1));
1385 aml_append(dev, aml_name_decl("_PRS", crs));
1386
1387 aml_append(dev, aml_name_decl("_CRS", crs));
1388
1389 /*
1390 * _DIS can be no-op because the interrupt cannot be disabled.
1391 */
1392 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1393 aml_append(dev, method);
1394
1395 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1396 aml_append(dev, method);
1397
1398 return dev;
1399 }
1400
1401 /* _CRS method - get current settings */
1402 static Aml *build_iqcr_method(bool is_piix4)
1403 {
1404 Aml *if_ctx;
1405 uint32_t irqs;
1406 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1407 Aml *crs = aml_resource_template();
1408
1409 irqs = 0;
1410 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1411 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1412 aml_append(method, aml_name_decl("PRR0", crs));
1413
1414 aml_append(method,
1415 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1416
1417 if (is_piix4) {
1418 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1419 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1420 aml_append(method, if_ctx);
1421 } else {
1422 aml_append(method,
1423 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1424 aml_name("PRRI")));
1425 }
1426
1427 aml_append(method, aml_return(aml_name("PRR0")));
1428 return method;
1429 }
1430
1431 /* _STA method - get status */
1432 static Aml *build_irq_status_method(void)
1433 {
1434 Aml *if_ctx;
1435 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1436
1437 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1438 aml_append(if_ctx, aml_return(aml_int(0x09)));
1439 aml_append(method, if_ctx);
1440 aml_append(method, aml_return(aml_int(0x0B)));
1441 return method;
1442 }
1443
1444 static void build_piix4_pci0_int(Aml *table)
1445 {
1446 Aml *dev;
1447 Aml *crs;
1448 Aml *field;
1449 Aml *method;
1450 uint32_t irqs;
1451 Aml *sb_scope = aml_scope("_SB");
1452 Aml *pci0_scope = aml_scope("PCI0");
1453
1454 aml_append(pci0_scope, build_prt(true));
1455 aml_append(sb_scope, pci0_scope);
1456
1457 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1458 aml_append(field, aml_named_field("PRQ0", 8));
1459 aml_append(field, aml_named_field("PRQ1", 8));
1460 aml_append(field, aml_named_field("PRQ2", 8));
1461 aml_append(field, aml_named_field("PRQ3", 8));
1462 aml_append(sb_scope, field);
1463
1464 aml_append(sb_scope, build_irq_status_method());
1465 aml_append(sb_scope, build_iqcr_method(true));
1466
1467 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1468 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1469 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1470 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1471
1472 dev = aml_device("LNKS");
1473 {
1474 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1475 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1476
1477 crs = aml_resource_template();
1478 irqs = 9;
1479 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1480 AML_ACTIVE_HIGH, AML_SHARED,
1481 &irqs, 1));
1482 aml_append(dev, aml_name_decl("_PRS", crs));
1483
1484 /* The SCI cannot be disabled and is always attached to GSI 9,
1485 * so these are no-ops. We only need this link to override the
1486 * polarity to active high and match the content of the MADT.
1487 */
1488 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1489 aml_append(method, aml_return(aml_int(0x0b)));
1490 aml_append(dev, method);
1491
1492 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1493 aml_append(dev, method);
1494
1495 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1496 aml_append(method, aml_return(aml_name("_PRS")));
1497 aml_append(dev, method);
1498
1499 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1500 aml_append(dev, method);
1501 }
1502 aml_append(sb_scope, dev);
1503
1504 aml_append(table, sb_scope);
1505 }
1506
1507 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1508 {
1509 int i;
1510 int head;
1511 Aml *pkg;
1512 char base = name[3] < 'E' ? 'A' : 'E';
1513 char *s = g_strdup(name);
1514 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1515
1516 assert(strlen(s) == 4);
1517
1518 head = name[3] - base;
1519 for (i = 0; i < 4; i++) {
1520 if (head + i > 3) {
1521 head = i * -1;
1522 }
1523 s[3] = base + head + i;
1524 pkg = aml_package(4);
1525 aml_append(pkg, a_nr);
1526 aml_append(pkg, aml_int(i));
1527 aml_append(pkg, aml_name("%s", s));
1528 aml_append(pkg, aml_int(0));
1529 aml_append(ctx, pkg);
1530 }
1531 g_free(s);
1532 }
1533
1534 static Aml *build_q35_routing_table(const char *str)
1535 {
1536 int i;
1537 Aml *pkg;
1538 char *name = g_strdup_printf("%s ", str);
1539
1540 pkg = aml_package(128);
1541 for (i = 0; i < 0x18; i++) {
1542 name[3] = 'E' + (i & 0x3);
1543 append_q35_prt_entry(pkg, i, name);
1544 }
1545
1546 name[3] = 'E';
1547 append_q35_prt_entry(pkg, 0x18, name);
1548
1549 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1550 for (i = 0x0019; i < 0x1e; i++) {
1551 name[3] = 'A';
1552 append_q35_prt_entry(pkg, i, name);
1553 }
1554
1555 /* PCIe->PCI bridge. use PIRQ[E-H] */
1556 name[3] = 'E';
1557 append_q35_prt_entry(pkg, 0x1e, name);
1558 name[3] = 'A';
1559 append_q35_prt_entry(pkg, 0x1f, name);
1560
1561 g_free(name);
1562 return pkg;
1563 }
1564
1565 static void build_q35_pci0_int(Aml *table)
1566 {
1567 Aml *field;
1568 Aml *method;
1569 Aml *sb_scope = aml_scope("_SB");
1570 Aml *pci0_scope = aml_scope("PCI0");
1571
1572 /* Zero => PIC mode, One => APIC Mode */
1573 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1574 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1575 {
1576 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1577 }
1578 aml_append(table, method);
1579
1580 aml_append(pci0_scope,
1581 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1582 aml_append(pci0_scope,
1583 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1584
1585 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1586 {
1587 Aml *if_ctx;
1588 Aml *else_ctx;
1589
1590 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1591 section 6.2.8.1 */
1592 /* Note: we provide the same info as the PCI routing
1593 table of the Bochs BIOS */
1594 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1595 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1596 aml_append(method, if_ctx);
1597 else_ctx = aml_else();
1598 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1599 aml_append(method, else_ctx);
1600 }
1601 aml_append(pci0_scope, method);
1602 aml_append(sb_scope, pci0_scope);
1603
1604 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1605 aml_append(field, aml_named_field("PRQA", 8));
1606 aml_append(field, aml_named_field("PRQB", 8));
1607 aml_append(field, aml_named_field("PRQC", 8));
1608 aml_append(field, aml_named_field("PRQD", 8));
1609 aml_append(field, aml_reserved_field(0x20));
1610 aml_append(field, aml_named_field("PRQE", 8));
1611 aml_append(field, aml_named_field("PRQF", 8));
1612 aml_append(field, aml_named_field("PRQG", 8));
1613 aml_append(field, aml_named_field("PRQH", 8));
1614 aml_append(sb_scope, field);
1615
1616 aml_append(sb_scope, build_irq_status_method());
1617 aml_append(sb_scope, build_iqcr_method(false));
1618
1619 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1620 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1621 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1622 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1623 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1624 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1625 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1626 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1627
1628 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1629 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1630 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1631 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1632 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1633 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1634 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1635 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1636
1637 aml_append(table, sb_scope);
1638 }
1639
1640 static void build_q35_isa_bridge(Aml *table)
1641 {
1642 Aml *dev;
1643 Aml *scope;
1644 Aml *field;
1645
1646 scope = aml_scope("_SB.PCI0");
1647 dev = aml_device("ISA");
1648 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1649
1650 /* ICH9 PCI to ISA irq remapping */
1651 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1652 aml_int(0x60), 0x0C));
1653
1654 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1655 aml_int(0x80), 0x02));
1656 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1657 aml_append(field, aml_named_field("COMA", 3));
1658 aml_append(field, aml_reserved_field(1));
1659 aml_append(field, aml_named_field("COMB", 3));
1660 aml_append(field, aml_reserved_field(1));
1661 aml_append(field, aml_named_field("LPTD", 2));
1662 aml_append(dev, field);
1663
1664 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1665 aml_int(0x82), 0x02));
1666 /* enable bits */
1667 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1668 aml_append(field, aml_named_field("CAEN", 1));
1669 aml_append(field, aml_named_field("CBEN", 1));
1670 aml_append(field, aml_named_field("LPEN", 1));
1671 aml_append(dev, field);
1672
1673 aml_append(scope, dev);
1674 aml_append(table, scope);
1675 }
1676
1677 static void build_piix4_pm(Aml *table)
1678 {
1679 Aml *dev;
1680 Aml *scope;
1681
1682 scope = aml_scope("_SB.PCI0");
1683 dev = aml_device("PX13");
1684 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1685
1686 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1687 aml_int(0x00), 0xff));
1688 aml_append(scope, dev);
1689 aml_append(table, scope);
1690 }
1691
1692 static void build_piix4_isa_bridge(Aml *table)
1693 {
1694 Aml *dev;
1695 Aml *scope;
1696 Aml *field;
1697
1698 scope = aml_scope("_SB.PCI0");
1699 dev = aml_device("ISA");
1700 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1701
1702 /* PIIX PCI to ISA irq remapping */
1703 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1704 aml_int(0x60), 0x04));
1705 /* enable bits */
1706 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1707 /* Offset(0x5f),, 7, */
1708 aml_append(field, aml_reserved_field(0x2f8));
1709 aml_append(field, aml_reserved_field(7));
1710 aml_append(field, aml_named_field("LPEN", 1));
1711 /* Offset(0x67),, 3, */
1712 aml_append(field, aml_reserved_field(0x38));
1713 aml_append(field, aml_reserved_field(3));
1714 aml_append(field, aml_named_field("CAEN", 1));
1715 aml_append(field, aml_reserved_field(3));
1716 aml_append(field, aml_named_field("CBEN", 1));
1717 aml_append(dev, field);
1718
1719 aml_append(scope, dev);
1720 aml_append(table, scope);
1721 }
1722
1723 static void build_piix4_pci_hotplug(Aml *table)
1724 {
1725 Aml *scope;
1726 Aml *field;
1727 Aml *method;
1728
1729 scope = aml_scope("_SB.PCI0");
1730
1731 aml_append(scope,
1732 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1733 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1734 aml_append(field, aml_named_field("PCIU", 32));
1735 aml_append(field, aml_named_field("PCID", 32));
1736 aml_append(scope, field);
1737
1738 aml_append(scope,
1739 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1740 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1741 aml_append(field, aml_named_field("B0EJ", 32));
1742 aml_append(scope, field);
1743
1744 aml_append(scope,
1745 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1746 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1747 aml_append(field, aml_named_field("BNUM", 32));
1748 aml_append(scope, field);
1749
1750 aml_append(scope, aml_mutex("BLCK", 0));
1751
1752 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1753 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1754 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1755 aml_append(method,
1756 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1757 aml_append(method, aml_release(aml_name("BLCK")));
1758 aml_append(method, aml_return(aml_int(0)));
1759 aml_append(scope, method);
1760
1761 aml_append(table, scope);
1762 }
1763
1764 static Aml *build_q35_osc_method(void)
1765 {
1766 Aml *if_ctx;
1767 Aml *if_ctx2;
1768 Aml *else_ctx;
1769 Aml *method;
1770 Aml *a_cwd1 = aml_name("CDW1");
1771 Aml *a_ctrl = aml_local(0);
1772
1773 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1774 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1775
1776 if_ctx = aml_if(aml_equal(
1777 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1778 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1779 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1780
1781 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1782
1783 /*
1784 * Always allow native PME, AER (no dependencies)
1785 * Allow SHPC (PCI bridges can have SHPC controller)
1786 */
1787 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1788
1789 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1790 /* Unknown revision */
1791 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1792 aml_append(if_ctx, if_ctx2);
1793
1794 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1795 /* Capabilities bits were masked */
1796 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1797 aml_append(if_ctx, if_ctx2);
1798
1799 /* Update DWORD3 in the buffer */
1800 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1801 aml_append(method, if_ctx);
1802
1803 else_ctx = aml_else();
1804 /* Unrecognized UUID */
1805 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1806 aml_append(method, else_ctx);
1807
1808 aml_append(method, aml_return(aml_arg(3)));
1809 return method;
1810 }
1811
1812 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1813 {
1814 Aml *scope = aml_scope("_SB.PCI0");
1815 Aml *dev = aml_device("SMB0");
1816
1817 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0005")));
1818 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1819 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1820 aml_append(scope, dev);
1821 aml_append(table, scope);
1822 }
1823
1824 static void
1825 build_dsdt(GArray *table_data, BIOSLinker *linker,
1826 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1827 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1828 {
1829 CrsRangeEntry *entry;
1830 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1831 CrsRangeSet crs_range_set;
1832 PCMachineState *pcms = PC_MACHINE(machine);
1833 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1834 X86MachineState *x86ms = X86_MACHINE(machine);
1835 AcpiMcfgInfo mcfg;
1836 uint32_t nr_mem = machine->ram_slots;
1837 int root_bus_limit = 0xFF;
1838 PCIBus *bus = NULL;
1839 TPMIf *tpm = tpm_find();
1840 int i;
1841
1842 dsdt = init_aml_allocator();
1843
1844 /* Reserve space for header */
1845 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1846
1847 build_dbg_aml(dsdt);
1848 if (misc->is_piix4) {
1849 sb_scope = aml_scope("_SB");
1850 dev = aml_device("PCI0");
1851 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1852 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1853 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1854 aml_append(sb_scope, dev);
1855 aml_append(dsdt, sb_scope);
1856
1857 build_hpet_aml(dsdt);
1858 build_piix4_pm(dsdt);
1859 build_piix4_isa_bridge(dsdt);
1860 build_isa_devices_aml(dsdt);
1861 build_piix4_pci_hotplug(dsdt);
1862 build_piix4_pci0_int(dsdt);
1863 } else {
1864 sb_scope = aml_scope("_SB");
1865 dev = aml_device("PCI0");
1866 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1867 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1868 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1869 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1870 aml_append(dev, build_q35_osc_method());
1871 aml_append(sb_scope, dev);
1872 aml_append(dsdt, sb_scope);
1873
1874 build_hpet_aml(dsdt);
1875 build_q35_isa_bridge(dsdt);
1876 build_isa_devices_aml(dsdt);
1877 build_q35_pci0_int(dsdt);
1878 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1879 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1880 }
1881 }
1882
1883 if (pcmc->legacy_cpu_hotplug) {
1884 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1885 } else {
1886 CPUHotplugFeatures opts = {
1887 .acpi_1_compatible = true, .has_legacy_cphp = true
1888 };
1889 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1890 "\\_SB.PCI0", "\\_GPE._E02");
1891 }
1892
1893 if (pcms->memhp_io_base && nr_mem) {
1894 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1895 "\\_GPE._E03", AML_SYSTEM_IO,
1896 pcms->memhp_io_base);
1897 }
1898
1899 scope = aml_scope("_GPE");
1900 {
1901 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1902
1903 if (misc->is_piix4) {
1904 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1905 aml_append(method,
1906 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1907 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1908 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1909 aml_append(scope, method);
1910 }
1911
1912 if (machine->nvdimms_state->is_enabled) {
1913 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1914 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1915 aml_int(0x80)));
1916 aml_append(scope, method);
1917 }
1918 }
1919 aml_append(dsdt, scope);
1920
1921 crs_range_set_init(&crs_range_set);
1922 bus = PC_MACHINE(machine)->bus;
1923 if (bus) {
1924 QLIST_FOREACH(bus, &bus->child, sibling) {
1925 uint8_t bus_num = pci_bus_num(bus);
1926 uint8_t numa_node = pci_bus_numa_node(bus);
1927
1928 /* look only for expander root buses */
1929 if (!pci_bus_is_root(bus)) {
1930 continue;
1931 }
1932
1933 if (bus_num < root_bus_limit) {
1934 root_bus_limit = bus_num - 1;
1935 }
1936
1937 scope = aml_scope("\\_SB");
1938 dev = aml_device("PC%.02X", bus_num);
1939 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1940 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1941 if (pci_bus_is_express(bus)) {
1942 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1943 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1944 aml_append(dev, build_q35_osc_method());
1945 } else {
1946 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1947 }
1948
1949 if (numa_node != NUMA_NODE_UNASSIGNED) {
1950 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1951 }
1952
1953 aml_append(dev, build_prt(false));
1954 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1955 aml_append(dev, aml_name_decl("_CRS", crs));
1956 aml_append(scope, dev);
1957 aml_append(dsdt, scope);
1958 }
1959 }
1960
1961 /*
1962 * At this point crs_range_set has all the ranges used by pci
1963 * busses *other* than PCI0. These ranges will be excluded from
1964 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1965 * too.
1966 */
1967 if (acpi_get_mcfg(&mcfg)) {
1968 crs_range_insert(crs_range_set.mem_ranges,
1969 mcfg.base, mcfg.base + mcfg.size - 1);
1970 }
1971
1972 scope = aml_scope("\\_SB.PCI0");
1973 /* build PCI0._CRS */
1974 crs = aml_resource_template();
1975 aml_append(crs,
1976 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1977 0x0000, 0x0, root_bus_limit,
1978 0x0000, root_bus_limit + 1));
1979 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1980
1981 aml_append(crs,
1982 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1983 AML_POS_DECODE, AML_ENTIRE_RANGE,
1984 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1985
1986 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1987 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1988 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1989 aml_append(crs,
1990 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1991 AML_POS_DECODE, AML_ENTIRE_RANGE,
1992 0x0000, entry->base, entry->limit,
1993 0x0000, entry->limit - entry->base + 1));
1994 }
1995
1996 aml_append(crs,
1997 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1998 AML_CACHEABLE, AML_READ_WRITE,
1999 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2000
2001 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2002 range_lob(pci_hole),
2003 range_upb(pci_hole));
2004 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2005 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2006 aml_append(crs,
2007 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2008 AML_NON_CACHEABLE, AML_READ_WRITE,
2009 0, entry->base, entry->limit,
2010 0, entry->limit - entry->base + 1));
2011 }
2012
2013 if (!range_is_empty(pci_hole64)) {
2014 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2015 range_lob(pci_hole64),
2016 range_upb(pci_hole64));
2017 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2018 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2019 aml_append(crs,
2020 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2021 AML_MAX_FIXED,
2022 AML_CACHEABLE, AML_READ_WRITE,
2023 0, entry->base, entry->limit,
2024 0, entry->limit - entry->base + 1));
2025 }
2026 }
2027
2028 if (TPM_IS_TIS(tpm_find())) {
2029 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2030 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2031 }
2032 aml_append(scope, aml_name_decl("_CRS", crs));
2033
2034 /* reserve GPE0 block resources */
2035 dev = aml_device("GPE0");
2036 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2037 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2038 /* device present, functioning, decoding, not shown in UI */
2039 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2040 crs = aml_resource_template();
2041 aml_append(crs,
2042 aml_io(
2043 AML_DECODE16,
2044 pm->fadt.gpe0_blk.address,
2045 pm->fadt.gpe0_blk.address,
2046 1,
2047 pm->fadt.gpe0_blk.bit_width / 8)
2048 );
2049 aml_append(dev, aml_name_decl("_CRS", crs));
2050 aml_append(scope, dev);
2051
2052 crs_range_set_free(&crs_range_set);
2053
2054 /* reserve PCIHP resources */
2055 if (pm->pcihp_io_len) {
2056 dev = aml_device("PHPR");
2057 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2058 aml_append(dev,
2059 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2060 /* device present, functioning, decoding, not shown in UI */
2061 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2062 crs = aml_resource_template();
2063 aml_append(crs,
2064 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2065 pm->pcihp_io_len)
2066 );
2067 aml_append(dev, aml_name_decl("_CRS", crs));
2068 aml_append(scope, dev);
2069 }
2070 aml_append(dsdt, scope);
2071
2072 /* create S3_ / S4_ / S5_ packages if necessary */
2073 scope = aml_scope("\\");
2074 if (!pm->s3_disabled) {
2075 pkg = aml_package(4);
2076 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2077 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2078 aml_append(pkg, aml_int(0)); /* reserved */
2079 aml_append(pkg, aml_int(0)); /* reserved */
2080 aml_append(scope, aml_name_decl("_S3", pkg));
2081 }
2082
2083 if (!pm->s4_disabled) {
2084 pkg = aml_package(4);
2085 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2086 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2087 aml_append(pkg, aml_int(pm->s4_val));
2088 aml_append(pkg, aml_int(0)); /* reserved */
2089 aml_append(pkg, aml_int(0)); /* reserved */
2090 aml_append(scope, aml_name_decl("_S4", pkg));
2091 }
2092
2093 pkg = aml_package(4);
2094 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2095 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2096 aml_append(pkg, aml_int(0)); /* reserved */
2097 aml_append(pkg, aml_int(0)); /* reserved */
2098 aml_append(scope, aml_name_decl("_S5", pkg));
2099 aml_append(dsdt, scope);
2100
2101 /* create fw_cfg node, unconditionally */
2102 {
2103 /* when using port i/o, the 8-bit data register *always* overlaps
2104 * with half of the 16-bit control register. Hence, the total size
2105 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2106 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2107 uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg),
2108 "dma_enabled", NULL) ?
2109 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2110 FW_CFG_CTL_SIZE;
2111
2112 scope = aml_scope("\\_SB.PCI0");
2113 dev = aml_device("FWCF");
2114
2115 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2116
2117 /* device present, functioning, decoding, not shown in UI */
2118 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2119
2120 crs = aml_resource_template();
2121 aml_append(crs,
2122 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2123 );
2124 aml_append(dev, aml_name_decl("_CRS", crs));
2125
2126 aml_append(scope, dev);
2127 aml_append(dsdt, scope);
2128 }
2129
2130 if (misc->applesmc_io_base) {
2131 scope = aml_scope("\\_SB.PCI0.ISA");
2132 dev = aml_device("SMC");
2133
2134 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2135 /* device present, functioning, decoding, not shown in UI */
2136 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2137
2138 crs = aml_resource_template();
2139 aml_append(crs,
2140 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2141 0x01, APPLESMC_MAX_DATA_LENGTH)
2142 );
2143 aml_append(crs, aml_irq_no_flags(6));
2144 aml_append(dev, aml_name_decl("_CRS", crs));
2145
2146 aml_append(scope, dev);
2147 aml_append(dsdt, scope);
2148 }
2149
2150 if (misc->pvpanic_port) {
2151 scope = aml_scope("\\_SB.PCI0.ISA");
2152
2153 dev = aml_device("PEVT");
2154 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2155
2156 crs = aml_resource_template();
2157 aml_append(crs,
2158 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2159 );
2160 aml_append(dev, aml_name_decl("_CRS", crs));
2161
2162 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2163 aml_int(misc->pvpanic_port), 1));
2164 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2165 aml_append(field, aml_named_field("PEPT", 8));
2166 aml_append(dev, field);
2167
2168 /* device present, functioning, decoding, shown in UI */
2169 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2170
2171 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2172 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2173 aml_append(method, aml_return(aml_local(0)));
2174 aml_append(dev, method);
2175
2176 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2177 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2178 aml_append(dev, method);
2179
2180 aml_append(scope, dev);
2181 aml_append(dsdt, scope);
2182 }
2183
2184 sb_scope = aml_scope("\\_SB");
2185 {
2186 Object *pci_host;
2187 PCIBus *bus = NULL;
2188
2189 pci_host = acpi_get_i386_pci_host();
2190 if (pci_host) {
2191 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2192 }
2193
2194 if (bus) {
2195 Aml *scope = aml_scope("PCI0");
2196 /* Scan all PCI buses. Generate tables to support hotplug. */
2197 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2198
2199 if (TPM_IS_TIS(tpm)) {
2200 if (misc->tpm_version == TPM_VERSION_2_0) {
2201 dev = aml_device("TPM");
2202 aml_append(dev, aml_name_decl("_HID",
2203 aml_string("MSFT0101")));
2204 } else {
2205 dev = aml_device("ISA.TPM");
2206 aml_append(dev, aml_name_decl("_HID",
2207 aml_eisaid("PNP0C31")));
2208 }
2209
2210 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2211 crs = aml_resource_template();
2212 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2213 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2214 /*
2215 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2216 Rewrite to take IRQ from TPM device model and
2217 fix default IRQ value there to use some unused IRQ
2218 */
2219 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2220 aml_append(dev, aml_name_decl("_CRS", crs));
2221
2222 tpm_build_ppi_acpi(tpm, dev);
2223
2224 aml_append(scope, dev);
2225 }
2226
2227 aml_append(sb_scope, scope);
2228 }
2229 }
2230
2231 if (TPM_IS_CRB(tpm)) {
2232 dev = aml_device("TPM");
2233 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2234 crs = aml_resource_template();
2235 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2236 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2237 aml_append(dev, aml_name_decl("_CRS", crs));
2238
2239 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2240 aml_append(method, aml_return(aml_int(0x0f)));
2241 aml_append(dev, method);
2242
2243 tpm_build_ppi_acpi(tpm, dev);
2244
2245 aml_append(sb_scope, dev);
2246 }
2247
2248 aml_append(dsdt, sb_scope);
2249
2250 /* copy AML table into ACPI tables blob and patch header there */
2251 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2252 build_header(linker, table_data,
2253 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2254 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2255 free_aml_allocator();
2256 }
2257
2258 static void
2259 build_hpet(GArray *table_data, BIOSLinker *linker)
2260 {
2261 Acpi20Hpet *hpet;
2262
2263 hpet = acpi_data_push(table_data, sizeof(*hpet));
2264 /* Note timer_block_id value must be kept in sync with value advertised by
2265 * emulated hpet
2266 */
2267 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2268 hpet->addr.address = cpu_to_le64(HPET_BASE);
2269 build_header(linker, table_data,
2270 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2271 }
2272
2273 static void
2274 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2275 {
2276 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2277 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2278 unsigned log_addr_offset =
2279 (char *)&tcpa->log_area_start_address - table_data->data;
2280
2281 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2282 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2283 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2284
2285 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2286 false /* high memory */);
2287
2288 /* log area start address to be filled by Guest linker */
2289 bios_linker_loader_add_pointer(linker,
2290 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2291 ACPI_BUILD_TPMLOG_FILE, 0);
2292
2293 build_header(linker, table_data,
2294 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2295 }
2296
2297 static void
2298 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2299 {
2300 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2301 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2302 unsigned log_addr_offset =
2303 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2304
2305 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2306 if (TPM_IS_TIS(tpm_find())) {
2307 tpm2_ptr->control_area_address = cpu_to_le64(0);
2308 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2309 } else if (TPM_IS_CRB(tpm_find())) {
2310 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2311 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2312 } else {
2313 g_warn_if_reached();
2314 }
2315
2316 tpm2_ptr->log_area_minimum_length =
2317 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2318
2319 /* log area start address to be filled by Guest linker */
2320 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2321 log_addr_offset, log_addr_size,
2322 ACPI_BUILD_TPMLOG_FILE, 0);
2323 build_header(linker, table_data,
2324 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2325 }
2326
2327 #define HOLE_640K_START (640 * KiB)
2328 #define HOLE_640K_END (1 * MiB)
2329
2330 static void
2331 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2332 {
2333 AcpiSystemResourceAffinityTable *srat;
2334 AcpiSratMemoryAffinity *numamem;
2335
2336 int i;
2337 int srat_start, numa_start, slots;
2338 uint64_t mem_len, mem_base, next_base;
2339 MachineClass *mc = MACHINE_GET_CLASS(machine);
2340 X86MachineState *x86ms = X86_MACHINE(machine);
2341 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2342 PCMachineState *pcms = PC_MACHINE(machine);
2343 ram_addr_t hotplugabble_address_space_size =
2344 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
2345 NULL);
2346
2347 srat_start = table_data->len;
2348
2349 srat = acpi_data_push(table_data, sizeof *srat);
2350 srat->reserved1 = cpu_to_le32(1);
2351
2352 for (i = 0; i < apic_ids->len; i++) {
2353 int node_id = apic_ids->cpus[i].props.node_id;
2354 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2355
2356 if (apic_id < 255) {
2357 AcpiSratProcessorAffinity *core;
2358
2359 core = acpi_data_push(table_data, sizeof *core);
2360 core->type = ACPI_SRAT_PROCESSOR_APIC;
2361 core->length = sizeof(*core);
2362 core->local_apic_id = apic_id;
2363 core->proximity_lo = node_id;
2364 memset(core->proximity_hi, 0, 3);
2365 core->local_sapic_eid = 0;
2366 core->flags = cpu_to_le32(1);
2367 } else {
2368 AcpiSratProcessorX2ApicAffinity *core;
2369
2370 core = acpi_data_push(table_data, sizeof *core);
2371 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2372 core->length = sizeof(*core);
2373 core->x2apic_id = cpu_to_le32(apic_id);
2374 core->proximity_domain = cpu_to_le32(node_id);
2375 core->flags = cpu_to_le32(1);
2376 }
2377 }
2378
2379
2380 /* the memory map is a bit tricky, it contains at least one hole
2381 * from 640k-1M and possibly another one from 3.5G-4G.
2382 */
2383 next_base = 0;
2384 numa_start = table_data->len;
2385
2386 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2387 mem_base = next_base;
2388 mem_len = pcms->node_mem[i - 1];
2389 next_base = mem_base + mem_len;
2390
2391 /* Cut out the 640K hole */
2392 if (mem_base <= HOLE_640K_START &&
2393 next_base > HOLE_640K_START) {
2394 mem_len -= next_base - HOLE_640K_START;
2395 if (mem_len > 0) {
2396 numamem = acpi_data_push(table_data, sizeof *numamem);
2397 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2398 MEM_AFFINITY_ENABLED);
2399 }
2400
2401 /* Check for the rare case: 640K < RAM < 1M */
2402 if (next_base <= HOLE_640K_END) {
2403 next_base = HOLE_640K_END;
2404 continue;
2405 }
2406 mem_base = HOLE_640K_END;
2407 mem_len = next_base - HOLE_640K_END;
2408 }
2409
2410 /* Cut out the ACPI_PCI hole */
2411 if (mem_base <= x86ms->below_4g_mem_size &&
2412 next_base > x86ms->below_4g_mem_size) {
2413 mem_len -= next_base - x86ms->below_4g_mem_size;
2414 if (mem_len > 0) {
2415 numamem = acpi_data_push(table_data, sizeof *numamem);
2416 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2417 MEM_AFFINITY_ENABLED);
2418 }
2419 mem_base = 1ULL << 32;
2420 mem_len = next_base - x86ms->below_4g_mem_size;
2421 next_base = mem_base + mem_len;
2422 }
2423
2424 if (mem_len > 0) {
2425 numamem = acpi_data_push(table_data, sizeof *numamem);
2426 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2427 MEM_AFFINITY_ENABLED);
2428 }
2429 }
2430 slots = (table_data->len - numa_start) / sizeof *numamem;
2431 for (; slots < pcms->numa_nodes + 2; slots++) {
2432 numamem = acpi_data_push(table_data, sizeof *numamem);
2433 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2434 }
2435
2436 /*
2437 * Entry is required for Windows to enable memory hotplug in OS
2438 * and for Linux to enable SWIOTLB when booted with less than
2439 * 4G of RAM. Windows works better if the entry sets proximity
2440 * to the highest NUMA node in the machine.
2441 * Memory devices may override proximity set by this entry,
2442 * providing _PXM method if necessary.
2443 */
2444 if (hotplugabble_address_space_size) {
2445 numamem = acpi_data_push(table_data, sizeof *numamem);
2446 build_srat_memory(numamem, machine->device_memory->base,
2447 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2448 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2449 }
2450
2451 build_header(linker, table_data,
2452 (void *)(table_data->data + srat_start),
2453 "SRAT",
2454 table_data->len - srat_start, 1, NULL, NULL);
2455 }
2456
2457 /*
2458 * VT-d spec 8.1 DMA Remapping Reporting Structure
2459 * (version Oct. 2014 or later)
2460 */
2461 static void
2462 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2463 {
2464 int dmar_start = table_data->len;
2465
2466 AcpiTableDmar *dmar;
2467 AcpiDmarHardwareUnit *drhd;
2468 AcpiDmarRootPortATS *atsr;
2469 uint8_t dmar_flags = 0;
2470 X86IOMMUState *iommu = x86_iommu_get_default();
2471 AcpiDmarDeviceScope *scope = NULL;
2472 /* Root complex IOAPIC use one path[0] only */
2473 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2474 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2475
2476 assert(iommu);
2477 if (x86_iommu_ir_supported(iommu)) {
2478 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2479 }
2480
2481 dmar = acpi_data_push(table_data, sizeof(*dmar));
2482 dmar->host_address_width = intel_iommu->aw_bits - 1;
2483 dmar->flags = dmar_flags;
2484
2485 /* DMAR Remapping Hardware Unit Definition structure */
2486 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2487 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2488 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2489 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2490 drhd->pci_segment = cpu_to_le16(0);
2491 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2492
2493 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2494 * 8.3.1 (version Oct. 2014 or later). */
2495 scope = &drhd->scope[0];
2496 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2497 scope->length = ioapic_scope_size;
2498 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2499 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2500 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2501 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2502
2503 if (iommu->dt_supported) {
2504 atsr = acpi_data_push(table_data, sizeof(*atsr));
2505 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2506 atsr->length = cpu_to_le16(sizeof(*atsr));
2507 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2508 atsr->pci_segment = cpu_to_le16(0);
2509 }
2510
2511 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2512 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2513 }
2514 /*
2515 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2516 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2517 */
2518 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2519
2520 /*
2521 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2522 * necessary for the PCI topology.
2523 */
2524 static void
2525 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2526 {
2527 GArray *table_data = opaque;
2528 uint32_t entry;
2529
2530 /* "Select" IVHD entry, type 0x2 */
2531 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2532 build_append_int_noprefix(table_data, entry, 4);
2533
2534 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2535 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2536 uint8_t sec = pci_bus_num(sec_bus);
2537 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2538
2539 if (pci_bus_is_express(sec_bus)) {
2540 /*
2541 * Walk the bus if there are subordinates, otherwise use a range
2542 * to cover an entire leaf bus. We could potentially also use a
2543 * range for traversed buses, but we'd need to take care not to
2544 * create both Select and Range entries covering the same device.
2545 * This is easier and potentially more compact.
2546 *
2547 * An example bare metal system seems to use Select entries for
2548 * root ports without a slot (ie. built-ins) and Range entries
2549 * when there is a slot. The same system also only hard-codes
2550 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2551 * making no effort to support nested bridges. We attempt to
2552 * be more thorough here.
2553 */
2554 if (sec == sub) { /* leaf bus */
2555 /* "Start of Range" IVHD entry, type 0x3 */
2556 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2557 build_append_int_noprefix(table_data, entry, 4);
2558 /* "End of Range" IVHD entry, type 0x4 */
2559 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2560 build_append_int_noprefix(table_data, entry, 4);
2561 } else {
2562 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2563 }
2564 } else {
2565 /*
2566 * If the secondary bus is conventional, then we need to create an
2567 * Alias range for everything downstream. The range covers the
2568 * first devfn on the secondary bus to the last devfn on the
2569 * subordinate bus. The alias target depends on legacy versus
2570 * express bridges, just as in pci_device_iommu_address_space().
2571 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2572 */
2573 uint16_t dev_id_a, dev_id_b;
2574
2575 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2576
2577 if (pci_is_express(dev) &&
2578 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2579 dev_id_b = dev_id_a;
2580 } else {
2581 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2582 }
2583
2584 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2585 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2586 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2587
2588 /* "End of Range" IVHD entry, type 0x4 */
2589 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2590 build_append_int_noprefix(table_data, entry, 4);
2591 }
2592 }
2593 }
2594
2595 /* For all PCI host bridges, walk and insert IVHD entries */
2596 static int
2597 ivrs_host_bridges(Object *obj, void *opaque)
2598 {
2599 GArray *ivhd_blob = opaque;
2600
2601 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2602 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2603
2604 if (bus) {
2605 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2606 }
2607 }
2608
2609 return 0;
2610 }
2611
2612 static void
2613 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2614 {
2615 int ivhd_table_len = 24;
2616 int iommu_start = table_data->len;
2617 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2618 GArray *ivhd_blob = g_array_new(false, true, 1);
2619
2620 /* IVRS header */
2621 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2622 /* IVinfo - IO virtualization information common to all
2623 * IOMMU units in a system
2624 */
2625 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2626 /* reserved */
2627 build_append_int_noprefix(table_data, 0, 8);
2628
2629 /* IVHD definition - type 10h */
2630 build_append_int_noprefix(table_data, 0x10, 1);
2631 /* virtualization flags */
2632 build_append_int_noprefix(table_data,
2633 (1UL << 0) | /* HtTunEn */
2634 (1UL << 4) | /* iotblSup */
2635 (1UL << 6) | /* PrefSup */
2636 (1UL << 7), /* PPRSup */
2637 1);
2638
2639 /*
2640 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2641 * complete set of IVHD entries. Do this into a separate blob so that we
2642 * can calculate the total IVRS table length here and then append the new
2643 * blob further below. Fall back to an entry covering all devices, which
2644 * is sufficient when no aliases are present.
2645 */
2646 object_child_foreach_recursive(object_get_root(),
2647 ivrs_host_bridges, ivhd_blob);
2648
2649 if (!ivhd_blob->len) {
2650 /*
2651 * Type 1 device entry reporting all devices
2652 * These are 4-byte device entries currently reporting the range of
2653 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2654 */
2655 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2656 }
2657
2658 ivhd_table_len += ivhd_blob->len;
2659
2660 /*
2661 * When interrupt remapping is supported, we add a special IVHD device
2662 * for type IO-APIC.
2663 */
2664 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2665 ivhd_table_len += 8;
2666 }
2667
2668 /* IVHD length */
2669 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2670 /* DeviceID */
2671 build_append_int_noprefix(table_data, s->devid, 2);
2672 /* Capability offset */
2673 build_append_int_noprefix(table_data, s->capab_offset, 2);
2674 /* IOMMU base address */
2675 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2676 /* PCI Segment Group */
2677 build_append_int_noprefix(table_data, 0, 2);
2678 /* IOMMU info */
2679 build_append_int_noprefix(table_data, 0, 2);
2680 /* IOMMU Feature Reporting */
2681 build_append_int_noprefix(table_data,
2682 (48UL << 30) | /* HATS */
2683 (48UL << 28) | /* GATS */
2684 (1UL << 2) | /* GTSup */
2685 (1UL << 6), /* GASup */
2686 4);
2687
2688 /* IVHD entries as found above */
2689 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2690 g_array_free(ivhd_blob, TRUE);
2691
2692 /*
2693 * Add a special IVHD device type.
2694 * Refer to spec - Table 95: IVHD device entry type codes
2695 *
2696 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2697 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2698 */
2699 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2700 build_append_int_noprefix(table_data,
2701 (0x1ull << 56) | /* type IOAPIC */
2702 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2703 0x48, /* special device */
2704 8);
2705 }
2706
2707 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2708 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2709 }
2710
2711 typedef
2712 struct AcpiBuildState {
2713 /* Copy of table in RAM (for patching). */
2714 MemoryRegion *table_mr;
2715 /* Is table patched? */
2716 uint8_t patched;
2717 void *rsdp;
2718 MemoryRegion *rsdp_mr;
2719 MemoryRegion *linker_mr;
2720 } AcpiBuildState;
2721
2722 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2723 {
2724 Object *pci_host;
2725 QObject *o;
2726
2727 pci_host = acpi_get_i386_pci_host();
2728 g_assert(pci_host);
2729
2730 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2731 if (!o) {
2732 return false;
2733 }
2734 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2735 qobject_unref(o);
2736 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2737 return false;
2738 }
2739
2740 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2741 assert(o);
2742 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2743 qobject_unref(o);
2744 return true;
2745 }
2746
2747 static
2748 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2749 {
2750 PCMachineState *pcms = PC_MACHINE(machine);
2751 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2752 X86MachineState *x86ms = X86_MACHINE(machine);
2753 GArray *table_offsets;
2754 unsigned facs, dsdt, rsdt, fadt;
2755 AcpiPmInfo pm;
2756 AcpiMiscInfo misc;
2757 AcpiMcfgInfo mcfg;
2758 Range pci_hole, pci_hole64;
2759 uint8_t *u;
2760 size_t aml_len = 0;
2761 GArray *tables_blob = tables->table_data;
2762 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2763 Object *vmgenid_dev;
2764
2765 acpi_get_pm_info(machine, &pm);
2766 acpi_get_misc_info(&misc);
2767 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2768 acpi_get_slic_oem(&slic_oem);
2769
2770 table_offsets = g_array_new(false, true /* clear */,
2771 sizeof(uint32_t));
2772 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2773
2774 bios_linker_loader_alloc(tables->linker,
2775 ACPI_BUILD_TABLE_FILE, tables_blob,
2776 64 /* Ensure FACS is aligned */,
2777 false /* high memory */);
2778
2779 /*
2780 * FACS is pointed to by FADT.
2781 * We place it first since it's the only table that has alignment
2782 * requirements.
2783 */
2784 facs = tables_blob->len;
2785 build_facs(tables_blob);
2786
2787 /* DSDT is pointed to by FADT */
2788 dsdt = tables_blob->len;
2789 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2790 &pci_hole, &pci_hole64, machine);
2791
2792 /* Count the size of the DSDT and SSDT, we will need it for legacy
2793 * sizing of ACPI tables.
2794 */
2795 aml_len += tables_blob->len - dsdt;
2796
2797 /* ACPI tables pointed to by RSDT */
2798 fadt = tables_blob->len;
2799 acpi_add_table(table_offsets, tables_blob);
2800 pm.fadt.facs_tbl_offset = &facs;
2801 pm.fadt.dsdt_tbl_offset = &dsdt;
2802 pm.fadt.xdsdt_tbl_offset = &dsdt;
2803 build_fadt(tables_blob, tables->linker, &pm.fadt,
2804 slic_oem.id, slic_oem.table_id);
2805 aml_len += tables_blob->len - fadt;
2806
2807 acpi_add_table(table_offsets, tables_blob);
2808 build_madt(tables_blob, tables->linker, pcms);
2809
2810 vmgenid_dev = find_vmgenid_dev();
2811 if (vmgenid_dev) {
2812 acpi_add_table(table_offsets, tables_blob);
2813 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2814 tables->vmgenid, tables->linker);
2815 }
2816
2817 if (misc.has_hpet) {
2818 acpi_add_table(table_offsets, tables_blob);
2819 build_hpet(tables_blob, tables->linker);
2820 }
2821 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2822 acpi_add_table(table_offsets, tables_blob);
2823 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2824
2825 if (misc.tpm_version == TPM_VERSION_2_0) {
2826 acpi_add_table(table_offsets, tables_blob);
2827 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2828 }
2829 }
2830 if (pcms->numa_nodes) {
2831 acpi_add_table(table_offsets, tables_blob);
2832 build_srat(tables_blob, tables->linker, machine);
2833 if (machine->numa_state->have_numa_distance) {
2834 acpi_add_table(table_offsets, tables_blob);
2835 build_slit(tables_blob, tables->linker, machine);
2836 }
2837 }
2838 if (acpi_get_mcfg(&mcfg)) {
2839 acpi_add_table(table_offsets, tables_blob);
2840 build_mcfg(tables_blob, tables->linker, &mcfg);
2841 }
2842 if (x86_iommu_get_default()) {
2843 IommuType IOMMUType = x86_iommu_get_type();
2844 if (IOMMUType == TYPE_AMD) {
2845 acpi_add_table(table_offsets, tables_blob);
2846 build_amd_iommu(tables_blob, tables->linker);
2847 } else if (IOMMUType == TYPE_INTEL) {
2848 acpi_add_table(table_offsets, tables_blob);
2849 build_dmar_q35(tables_blob, tables->linker);
2850 }
2851 }
2852 if (machine->nvdimms_state->is_enabled) {
2853 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2854 machine->nvdimms_state, machine->ram_slots);
2855 }
2856
2857 /* Add tables supplied by user (if any) */
2858 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2859 unsigned len = acpi_table_len(u);
2860
2861 acpi_add_table(table_offsets, tables_blob);
2862 g_array_append_vals(tables_blob, u, len);
2863 }
2864
2865 /* RSDT is pointed to by RSDP */
2866 rsdt = tables_blob->len;
2867 build_rsdt(tables_blob, tables->linker, table_offsets,
2868 slic_oem.id, slic_oem.table_id);
2869
2870 /* RSDP is in FSEG memory, so allocate it separately */
2871 {
2872 AcpiRsdpData rsdp_data = {
2873 .revision = 0,
2874 .oem_id = ACPI_BUILD_APPNAME6,
2875 .xsdt_tbl_offset = NULL,
2876 .rsdt_tbl_offset = &rsdt,
2877 };
2878 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2879 if (!pcmc->rsdp_in_ram) {
2880 /* We used to allocate some extra space for RSDP revision 2 but
2881 * only used the RSDP revision 0 space. The extra bytes were
2882 * zeroed out and not used.
2883 * Here we continue wasting those extra 16 bytes to make sure we
2884 * don't break migration for machine types 2.2 and older due to
2885 * RSDP blob size mismatch.
2886 */
2887 build_append_int_noprefix(tables->rsdp, 0, 16);
2888 }
2889 }
2890
2891 /* We'll expose it all to Guest so we want to reduce
2892 * chance of size changes.
2893 *
2894 * We used to align the tables to 4k, but of course this would
2895 * too simple to be enough. 4k turned out to be too small an
2896 * alignment very soon, and in fact it is almost impossible to
2897 * keep the table size stable for all (max_cpus, max_memory_slots)
2898 * combinations. So the table size is always 64k for pc-i440fx-2.1
2899 * and we give an error if the table grows beyond that limit.
2900 *
2901 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2902 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2903 * than 2.0 and we can always pad the smaller tables with zeros. We can
2904 * then use the exact size of the 2.0 tables.
2905 *
2906 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2907 */
2908 if (pcmc->legacy_acpi_table_size) {
2909 /* Subtracting aml_len gives the size of fixed tables. Then add the
2910 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2911 */
2912 int legacy_aml_len =
2913 pcmc->legacy_acpi_table_size +
2914 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2915 int legacy_table_size =
2916 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2917 ACPI_BUILD_ALIGN_SIZE);
2918 if (tables_blob->len > legacy_table_size) {
2919 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2920 warn_report("ACPI table size %u exceeds %d bytes,"
2921 " migration may not work",
2922 tables_blob->len, legacy_table_size);
2923 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2924 " or PCI bridges.");
2925 }
2926 g_array_set_size(tables_blob, legacy_table_size);
2927 } else {
2928 /* Make sure we have a buffer in case we need to resize the tables. */
2929 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2930 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2931 warn_report("ACPI table size %u exceeds %d bytes,"
2932 " migration may not work",
2933 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2934 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2935 " or PCI bridges.");
2936 }
2937 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2938 }
2939
2940 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2941
2942 /* Cleanup memory that's no longer used. */
2943 g_array_free(table_offsets, true);
2944 }
2945
2946 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2947 {
2948 uint32_t size = acpi_data_len(data);
2949
2950 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2951 memory_region_ram_resize(mr, size, &error_abort);
2952
2953 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2954 memory_region_set_dirty(mr, 0, size);
2955 }
2956
2957 static void acpi_build_update(void *build_opaque)
2958 {
2959 AcpiBuildState *build_state = build_opaque;
2960 AcpiBuildTables tables;
2961
2962 /* No state to update or already patched? Nothing to do. */
2963 if (!build_state || build_state->patched) {
2964 return;
2965 }
2966 build_state->patched = 1;
2967
2968 acpi_build_tables_init(&tables);
2969
2970 acpi_build(&tables, MACHINE(qdev_get_machine()));
2971
2972 acpi_ram_update(build_state->table_mr, tables.table_data);
2973
2974 if (build_state->rsdp) {
2975 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2976 } else {
2977 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2978 }
2979
2980 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2981 acpi_build_tables_cleanup(&tables, true);
2982 }
2983
2984 static void acpi_build_reset(void *build_opaque)
2985 {
2986 AcpiBuildState *build_state = build_opaque;
2987 build_state->patched = 0;
2988 }
2989
2990 static const VMStateDescription vmstate_acpi_build = {
2991 .name = "acpi_build",
2992 .version_id = 1,
2993 .minimum_version_id = 1,
2994 .fields = (VMStateField[]) {
2995 VMSTATE_UINT8(patched, AcpiBuildState),
2996 VMSTATE_END_OF_LIST()
2997 },
2998 };
2999
3000 void acpi_setup(void)
3001 {
3002 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
3003 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3004 X86MachineState *x86ms = X86_MACHINE(pcms);
3005 AcpiBuildTables tables;
3006 AcpiBuildState *build_state;
3007 Object *vmgenid_dev;
3008 TPMIf *tpm;
3009 static FwCfgTPMConfig tpm_config;
3010
3011 if (!x86ms->fw_cfg) {
3012 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
3013 return;
3014 }
3015
3016 if (!pcms->acpi_build_enabled) {
3017 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
3018 return;
3019 }
3020
3021 if (!acpi_enabled) {
3022 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
3023 return;
3024 }
3025
3026 build_state = g_malloc0(sizeof *build_state);
3027
3028 acpi_build_tables_init(&tables);
3029 acpi_build(&tables, MACHINE(pcms));
3030
3031 /* Now expose it all to Guest */
3032 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
3033 build_state, tables.table_data,
3034 ACPI_BUILD_TABLE_FILE,
3035 ACPI_BUILD_TABLE_MAX_SIZE);
3036 assert(build_state->table_mr != NULL);
3037
3038 build_state->linker_mr =
3039 acpi_add_rom_blob(acpi_build_update, build_state,
3040 tables.linker->cmd_blob, "etc/table-loader", 0);
3041
3042 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
3043 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
3044
3045 tpm = tpm_find();
3046 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
3047 tpm_config = (FwCfgTPMConfig) {
3048 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
3049 .tpm_version = tpm_get_version(tpm),
3050 .tpmppi_version = TPM_PPI_VERSION_1_30
3051 };
3052 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
3053 &tpm_config, sizeof tpm_config);
3054 }
3055
3056 vmgenid_dev = find_vmgenid_dev();
3057 if (vmgenid_dev) {
3058 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
3059 tables.vmgenid);
3060 }
3061
3062 if (!pcmc->rsdp_in_ram) {
3063 /*
3064 * Keep for compatibility with old machine types.
3065 * Though RSDP is small, its contents isn't immutable, so
3066 * we'll update it along with the rest of tables on guest access.
3067 */
3068 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
3069
3070 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
3071 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
3072 acpi_build_update, NULL, build_state,
3073 build_state->rsdp, rsdp_size, true);
3074 build_state->rsdp_mr = NULL;
3075 } else {
3076 build_state->rsdp = NULL;
3077 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
3078 build_state, tables.rsdp,
3079 ACPI_BUILD_RSDP_FILE, 0);
3080 }
3081
3082 qemu_register_reset(acpi_build_reset, build_state);
3083 acpi_build_reset(build_state);
3084 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
3085
3086 /* Cleanup tables but don't free the memory: we track it
3087 * in build_state.
3088 */
3089 acpi_build_tables_cleanup(&tables, false);
3090 }
AR7 emulation for QEMU