hw/dma/rc4030.c

   1 /*
   2  * QEMU JAZZ RC4030 chipset
   3  *
   4  * Copyright (c) 2007-2013 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/irq.h"
  28 #include "hw/mips/mips.h"
  29 #include "hw/sysbus.h"
  30 #include "migration/vmstate.h"
  31 #include "qemu/timer.h"
  32 #include "qemu/log.h"
  33 #include "qemu/module.h"
  34 #include "exec/address-spaces.h"
  35 #include "trace.h"
  36
  37 /********************************************************/
  38 /* rc4030 emulation                                     */
  39
  40 typedef struct dma_pagetable_entry {
  41     int32_t frame;
  42     int32_t owner;
  43 } QEMU_PACKED dma_pagetable_entry;
  44
  45 #define DMA_PAGESIZE    4096
  46 #define DMA_REG_ENABLE  1
  47 #define DMA_REG_COUNT   2
  48 #define DMA_REG_ADDRESS 3
  49
  50 #define DMA_FLAG_ENABLE     0x0001
  51 #define DMA_FLAG_MEM_TO_DEV 0x0002
  52 #define DMA_FLAG_TC_INTR    0x0100
  53 #define DMA_FLAG_MEM_INTR   0x0200
  54 #define DMA_FLAG_ADDR_INTR  0x0400
  55
  56 #define TYPE_RC4030 "rc4030"
  57 #define RC4030(obj) \
  58     OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030)
  59
  60 #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
  61
  62 typedef struct rc4030State {
  63
  64     SysBusDevice parent;
  65
  66     uint32_t config; /* 0x0000: RC4030 config register */
  67     uint32_t revision; /* 0x0008: RC4030 Revision register */
  68     uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
  69
  70     /* DMA */
  71     uint32_t dma_regs[8][4];
  72     uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
  73     uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
  74
  75     /* cache */
  76     uint32_t cache_maint; /* 0x0030: Cache Maintenance */
  77     uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
  78     uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
  79     uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
  80     uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
  81     uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
  82
  83     uint32_t nmi_interrupt; /* 0x0200: interrupt source */
  84     uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */
  85     uint32_t nvram_protect; /* 0x0220: NV ram protect register */
  86     uint32_t rem_speed[16];
  87     uint32_t imr_jazz; /* Local bus int enable mask */
  88     uint32_t isr_jazz; /* Local bus int source */
  89
  90     /* timer */
  91     QEMUTimer *periodic_timer;
  92     uint32_t itr; /* Interval timer reload */
  93
  94     qemu_irq timer_irq;
  95     qemu_irq jazz_bus_irq;
  96
  97     /* whole DMA memory region, root of DMA address space */
  98     IOMMUMemoryRegion dma_mr;
  99     AddressSpace dma_as;
 100
 101     MemoryRegion iomem_chipset;
 102     MemoryRegion iomem_jazzio;
 103 } rc4030State;
 104
 105 static void set_next_tick(rc4030State *s)
 106 {
 107     uint32_t tm_hz;
 108     qemu_irq_lower(s->timer_irq);
 109
 110     tm_hz = 1000 / (s->itr + 1);
 111
 112     timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 113                    NANOSECONDS_PER_SECOND / tm_hz);
 114 }
 115
 116 /* called for accesses to rc4030 */
 117 static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size)
 118 {
 119     rc4030State *s = opaque;
 120     uint32_t val;
 121
 122     addr &= 0x3fff;
 123     switch (addr & ~0x3) {
 124     /* Global config register */
 125     case 0x0000:
 126         val = s->config;
 127         break;
 128     /* Revision register */
 129     case 0x0008:
 130         val = s->revision;
 131         break;
 132     /* Invalid Address register */
 133     case 0x0010:
 134         val = s->invalid_address_register;
 135         break;
 136     /* DMA transl. table base */
 137     case 0x0018:
 138         val = s->dma_tl_base;
 139         break;
 140     /* DMA transl. table limit */
 141     case 0x0020:
 142         val = s->dma_tl_limit;
 143         break;
 144     /* Remote Failed Address */
 145     case 0x0038:
 146         val = s->remote_failed_address;
 147         break;
 148     /* Memory Failed Address */
 149     case 0x0040:
 150         val = s->memory_failed_address;
 151         break;
 152     /* I/O Cache Byte Mask */
 153     case 0x0058:
 154         val = s->cache_bmask;
 155         /* HACK */
 156         if (s->cache_bmask == (uint32_t)-1) {
 157             s->cache_bmask = 0;
 158         }
 159         break;
 160     /* Remote Speed Registers */
 161     case 0x0070:
 162     case 0x0078:
 163     case 0x0080:
 164     case 0x0088:
 165     case 0x0090:
 166     case 0x0098:
 167     case 0x00a0:
 168     case 0x00a8:
 169     case 0x00b0:
 170     case 0x00b8:
 171     case 0x00c0:
 172     case 0x00c8:
 173     case 0x00d0:
 174     case 0x00d8:
 175     case 0x00e0:
 176     case 0x00e8:
 177         val = s->rem_speed[(addr - 0x0070) >> 3];
 178         break;
 179     /* DMA channel base address */
 180     case 0x0100:
 181     case 0x0108:
 182     case 0x0110:
 183     case 0x0118:
 184     case 0x0120:
 185     case 0x0128:
 186     case 0x0130:
 187     case 0x0138:
 188     case 0x0140:
 189     case 0x0148:
 190     case 0x0150:
 191     case 0x0158:
 192     case 0x0160:
 193     case 0x0168:
 194     case 0x0170:
 195     case 0x0178:
 196     case 0x0180:
 197     case 0x0188:
 198     case 0x0190:
 199     case 0x0198:
 200     case 0x01a0:
 201     case 0x01a8:
 202     case 0x01b0:
 203     case 0x01b8:
 204     case 0x01c0:
 205     case 0x01c8:
 206     case 0x01d0:
 207     case 0x01d8:
 208     case 0x01e0:
 209     case 0x01e8:
 210     case 0x01f0:
 211     case 0x01f8:
 212         {
 213             int entry = (addr - 0x0100) >> 5;
 214             int idx = (addr & 0x1f) >> 3;
 215             val = s->dma_regs[entry][idx];
 216         }
 217         break;
 218     /* Interrupt source */
 219     case 0x0200:
 220         val = s->nmi_interrupt;
 221         break;
 222     /* Error type */
 223     case 0x0208:
 224         val = 0;
 225         break;
 226     /* Memory refresh rate */
 227     case 0x0210:
 228         val = s->memory_refresh_rate;
 229         break;
 230     /* NV ram protect register */
 231     case 0x0220:
 232         val = s->nvram_protect;
 233         break;
 234     /* Interval timer count */
 235     case 0x0230:
 236         val = 0;
 237         qemu_irq_lower(s->timer_irq);
 238         break;
 239     /* EISA interrupt */
 240     case 0x0238:
 241         val = 7; /* FIXME: should be read from EISA controller */
 242         break;
 243     default:
 244         qemu_log_mask(LOG_GUEST_ERROR,
 245                       "rc4030: invalid read at 0x%x", (int)addr);
 246         val = 0;
 247         break;
 248     }
 249
 250     if ((addr & ~3) != 0x230) {
 251         trace_rc4030_read(addr, val);
 252     }
 253
 254     return val;
 255 }
 256
 257 static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
 258                          unsigned int size)
 259 {
 260     rc4030State *s = opaque;
 261     uint32_t val = data;
 262     addr &= 0x3fff;
 263
 264     trace_rc4030_write(addr, val);
 265
 266     switch (addr & ~0x3) {
 267     /* Global config register */
 268     case 0x0000:
 269         s->config = val;
 270         break;
 271     /* DMA transl. table base */
 272     case 0x0018:
 273         s->dma_tl_base = val;
 274         break;
 275     /* DMA transl. table limit */
 276     case 0x0020:
 277         s->dma_tl_limit = val;
 278         break;
 279     /* DMA transl. table invalidated */
 280     case 0x0028:
 281         break;
 282     /* Cache Maintenance */
 283     case 0x0030:
 284         s->cache_maint = val;
 285         break;
 286     /* I/O Cache Physical Tag */
 287     case 0x0048:
 288         s->cache_ptag = val;
 289         break;
 290     /* I/O Cache Logical Tag */
 291     case 0x0050:
 292         s->cache_ltag = val;
 293         break;
 294     /* I/O Cache Byte Mask */
 295     case 0x0058:
 296         s->cache_bmask |= val; /* HACK */
 297         break;
 298     /* I/O Cache Buffer Window */
 299     case 0x0060:
 300         /* HACK */
 301         if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
 302             hwaddr dest = s->cache_ptag & ~0x1;
 303             dest += (s->cache_maint & 0x3) << 3;
 304             cpu_physical_memory_write(dest, &val, 4);
 305         }
 306         break;
 307     /* Remote Speed Registers */
 308     case 0x0070:
 309     case 0x0078:
 310     case 0x0080:
 311     case 0x0088:
 312     case 0x0090:
 313     case 0x0098:
 314     case 0x00a0:
 315     case 0x00a8:
 316     case 0x00b0:
 317     case 0x00b8:
 318     case 0x00c0:
 319     case 0x00c8:
 320     case 0x00d0:
 321     case 0x00d8:
 322     case 0x00e0:
 323     case 0x00e8:
 324         s->rem_speed[(addr - 0x0070) >> 3] = val;
 325         break;
 326     /* DMA channel base address */
 327     case 0x0100:
 328     case 0x0108:
 329     case 0x0110:
 330     case 0x0118:
 331     case 0x0120:
 332     case 0x0128:
 333     case 0x0130:
 334     case 0x0138:
 335     case 0x0140:
 336     case 0x0148:
 337     case 0x0150:
 338     case 0x0158:
 339     case 0x0160:
 340     case 0x0168:
 341     case 0x0170:
 342     case 0x0178:
 343     case 0x0180:
 344     case 0x0188:
 345     case 0x0190:
 346     case 0x0198:
 347     case 0x01a0:
 348     case 0x01a8:
 349     case 0x01b0:
 350     case 0x01b8:
 351     case 0x01c0:
 352     case 0x01c8:
 353     case 0x01d0:
 354     case 0x01d8:
 355     case 0x01e0:
 356     case 0x01e8:
 357     case 0x01f0:
 358     case 0x01f8:
 359         {
 360             int entry = (addr - 0x0100) >> 5;
 361             int idx = (addr & 0x1f) >> 3;
 362             s->dma_regs[entry][idx] = val;
 363         }
 364         break;
 365     /* Memory refresh rate */
 366     case 0x0210:
 367         s->memory_refresh_rate = val;
 368         break;
 369     /* Interval timer reload */
 370     case 0x0228:
 371         s->itr = val & 0x01FF;
 372         qemu_irq_lower(s->timer_irq);
 373         set_next_tick(s);
 374         break;
 375     /* EISA interrupt */
 376     case 0x0238:
 377         break;
 378     default:
 379         qemu_log_mask(LOG_GUEST_ERROR,
 380                       "rc4030: invalid write of 0x%02x at 0x%x",
 381                       val, (int)addr);
 382         break;
 383     }
 384 }
 385
 386 static const MemoryRegionOps rc4030_ops = {
 387     .read = rc4030_read,
 388     .write = rc4030_write,
 389     .impl.min_access_size = 4,
 390     .impl.max_access_size = 4,
 391     .endianness = DEVICE_NATIVE_ENDIAN,
 392 };
 393
 394 static void update_jazz_irq(rc4030State *s)
 395 {
 396     uint16_t pending;
 397
 398     pending = s->isr_jazz & s->imr_jazz;
 399
 400     if (pending != 0) {
 401         qemu_irq_raise(s->jazz_bus_irq);
 402     } else {
 403         qemu_irq_lower(s->jazz_bus_irq);
 404     }
 405 }
 406
 407 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
 408 {
 409     rc4030State *s = opaque;
 410
 411     if (level) {
 412         s->isr_jazz |= 1 << irq;
 413     } else {
 414         s->isr_jazz &= ~(1 << irq);
 415     }
 416
 417     update_jazz_irq(s);
 418 }
 419
 420 static void rc4030_periodic_timer(void *opaque)
 421 {
 422     rc4030State *s = opaque;
 423
 424     set_next_tick(s);
 425     qemu_irq_raise(s->timer_irq);
 426 }
 427
 428 static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size)
 429 {
 430     rc4030State *s = opaque;
 431     uint32_t val;
 432     uint32_t irq;
 433     addr &= 0xfff;
 434
 435     switch (addr) {
 436     /* Local bus int source */
 437     case 0x00: {
 438         uint32_t pending = s->isr_jazz & s->imr_jazz;
 439         val = 0;
 440         irq = 0;
 441         while (pending) {
 442             if (pending & 1) {
 443                 val = (irq + 1) << 2;
 444                 break;
 445             }
 446             irq++;
 447             pending >>= 1;
 448         }
 449         break;
 450     }
 451     /* Local bus int enable mask */
 452     case 0x02:
 453         val = s->imr_jazz;
 454         break;
 455     default:
 456         qemu_log_mask(LOG_GUEST_ERROR,
 457                       "rc4030/jazzio: invalid read at 0x%x", (int)addr);
 458         val = 0;
 459         break;
 460     }
 461
 462     trace_jazzio_read(addr, val);
 463
 464     return val;
 465 }
 466
 467 static void jazzio_write(void *opaque, hwaddr addr, uint64_t data,
 468                          unsigned int size)
 469 {
 470     rc4030State *s = opaque;
 471     uint32_t val = data;
 472     addr &= 0xfff;
 473
 474     trace_jazzio_write(addr, val);
 475
 476     switch (addr) {
 477     /* Local bus int enable mask */
 478     case 0x02:
 479         s->imr_jazz = val;
 480         update_jazz_irq(s);
 481         break;
 482     default:
 483         qemu_log_mask(LOG_GUEST_ERROR,
 484                       "rc4030/jazzio: invalid write of 0x%02x at 0x%x",
 485                       val, (int)addr);
 486         break;
 487     }
 488 }
 489
 490 static const MemoryRegionOps jazzio_ops = {
 491     .read = jazzio_read,
 492     .write = jazzio_write,
 493     .impl.min_access_size = 2,
 494     .impl.max_access_size = 2,
 495     .endianness = DEVICE_NATIVE_ENDIAN,
 496 };
 497
 498 static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
 499                                           IOMMUAccessFlags flag, int iommu_idx)
 500 {
 501     rc4030State *s = container_of(iommu, rc4030State, dma_mr);
 502     IOMMUTLBEntry ret = {
 503         .target_as = &address_space_memory,
 504         .iova = addr & ~(DMA_PAGESIZE - 1),
 505         .translated_addr = 0,
 506         .addr_mask = DMA_PAGESIZE - 1,
 507         .perm = IOMMU_NONE,
 508     };
 509     uint64_t i, entry_address;
 510     dma_pagetable_entry entry;
 511
 512     i = addr / DMA_PAGESIZE;
 513     if (i < s->dma_tl_limit / sizeof(entry)) {
 514         entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
 515         if (address_space_read(ret.target_as, entry_address,
 516                                MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry,
 517                                sizeof(entry)) == MEMTX_OK) {
 518             ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
 519             ret.perm = IOMMU_RW;
 520         }
 521     }
 522
 523     return ret;
 524 }
 525
 526 static void rc4030_reset(DeviceState *dev)
 527 {
 528     rc4030State *s = RC4030(dev);
 529     int i;
 530
 531     s->config = 0x410; /* some boards seem to accept 0x104 too */
 532     s->revision = 1;
 533     s->invalid_address_register = 0;
 534
 535     memset(s->dma_regs, 0, sizeof(s->dma_regs));
 536
 537     s->remote_failed_address = s->memory_failed_address = 0;
 538     s->cache_maint = 0;
 539     s->cache_ptag = s->cache_ltag = 0;
 540     s->cache_bmask = 0;
 541
 542     s->memory_refresh_rate = 0x18186;
 543     s->nvram_protect = 7;
 544     for (i = 0; i < 15; i++) {
 545         s->rem_speed[i] = 7;
 546     }
 547     s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
 548     s->isr_jazz = 0;
 549
 550     s->itr = 0;
 551
 552     qemu_irq_lower(s->timer_irq);
 553     qemu_irq_lower(s->jazz_bus_irq);
 554 }
 555
 556 static int rc4030_post_load(void *opaque, int version_id)
 557 {
 558     rc4030State *s = opaque;
 559
 560     set_next_tick(s);
 561     update_jazz_irq(s);
 562
 563     return 0;
 564 }
 565
 566 static const VMStateDescription vmstate_rc4030 = {
 567     .name = "rc4030",
 568     .version_id = 3,
 569     .post_load = rc4030_post_load,
 570     .fields = (VMStateField []) {
 571         VMSTATE_UINT32(config, rc4030State),
 572         VMSTATE_UINT32(invalid_address_register, rc4030State),
 573         VMSTATE_UINT32_2DARRAY(dma_regs, rc4030State, 8, 4),
 574         VMSTATE_UINT32(dma_tl_base, rc4030State),
 575         VMSTATE_UINT32(dma_tl_limit, rc4030State),
 576         VMSTATE_UINT32(cache_maint, rc4030State),
 577         VMSTATE_UINT32(remote_failed_address, rc4030State),
 578         VMSTATE_UINT32(memory_failed_address, rc4030State),
 579         VMSTATE_UINT32(cache_ptag, rc4030State),
 580         VMSTATE_UINT32(cache_ltag, rc4030State),
 581         VMSTATE_UINT32(cache_bmask, rc4030State),
 582         VMSTATE_UINT32(memory_refresh_rate, rc4030State),
 583         VMSTATE_UINT32(nvram_protect, rc4030State),
 584         VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16),
 585         VMSTATE_UINT32(imr_jazz, rc4030State),
 586         VMSTATE_UINT32(isr_jazz, rc4030State),
 587         VMSTATE_UINT32(itr, rc4030State),
 588         VMSTATE_END_OF_LIST()
 589     }
 590 };
 591
 592 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf,
 593                           int len, int is_write)
 594 {
 595     rc4030State *s = opaque;
 596     hwaddr dma_addr;
 597     int dev_to_mem;
 598
 599     s->dma_regs[n][DMA_REG_ENABLE] &=
 600            ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
 601
 602     /* Check DMA channel consistency */
 603     dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
 604     if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
 605         (is_write != dev_to_mem)) {
 606         s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
 607         s->nmi_interrupt |= 1 << n;
 608         return;
 609     }
 610
 611     /* Get start address and len */
 612     if (len > s->dma_regs[n][DMA_REG_COUNT]) {
 613         len = s->dma_regs[n][DMA_REG_COUNT];
 614     }
 615     dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
 616
 617     /* Read/write data at right place */
 618     address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED,
 619                      buf, len, is_write);
 620
 621     s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
 622     s->dma_regs[n][DMA_REG_COUNT] -= len;
 623 }
 624
 625 struct rc4030DMAState {
 626     void *opaque;
 627     int n;
 628 };
 629
 630 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
 631 {
 632     rc4030_dma s = dma;
 633     rc4030_do_dma(s->opaque, s->n, buf, len, 0);
 634 }
 635
 636 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
 637 {
 638     rc4030_dma s = dma;
 639     rc4030_do_dma(s->opaque, s->n, buf, len, 1);
 640 }
 641
 642 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
 643 {
 644     rc4030_dma *s;
 645     struct rc4030DMAState *p;
 646     int i;
 647
 648     s = (rc4030_dma *)g_new0(rc4030_dma, n);
 649     p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n);
 650     for (i = 0; i < n; i++) {
 651         p->opaque = opaque;
 652         p->n = i;
 653         s[i] = p;
 654         p++;
 655     }
 656     return s;
 657 }
 658
 659 static void rc4030_initfn(Object *obj)
 660 {
 661     DeviceState *dev = DEVICE(obj);
 662     rc4030State *s = RC4030(obj);
 663     SysBusDevice *sysbus = SYS_BUS_DEVICE(obj);
 664
 665     qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16);
 666
 667     sysbus_init_irq(sysbus, &s->timer_irq);
 668     sysbus_init_irq(sysbus, &s->jazz_bus_irq);
 669
 670     sysbus_init_mmio(sysbus, &s->iomem_chipset);
 671     sysbus_init_mmio(sysbus, &s->iomem_jazzio);
 672 }
 673
 674 static void rc4030_realize(DeviceState *dev, Error **errp)
 675 {
 676     rc4030State *s = RC4030(dev);
 677     Object *o = OBJECT(dev);
 678
 679     s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 680                                      rc4030_periodic_timer, s);
 681
 682     memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
 683                           "rc4030.chipset", 0x300);
 684     memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
 685                           "rc4030.jazzio", 0x00001000);
 686
 687     memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),
 688                              TYPE_RC4030_IOMMU_MEMORY_REGION,
 689                              o, "rc4030.dma", 4 * GiB);
 690     address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma");
 691 }
 692
 693 static void rc4030_unrealize(DeviceState *dev, Error **errp)
 694 {
 695     rc4030State *s = RC4030(dev);
 696
 697     timer_free(s->periodic_timer);
 698
 699     address_space_destroy(&s->dma_as);
 700     object_unparent(OBJECT(&s->dma_mr));
 701 }
 702
 703 static void rc4030_class_init(ObjectClass *klass, void *class_data)
 704 {
 705     DeviceClass *dc = DEVICE_CLASS(klass);
 706
 707     dc->realize = rc4030_realize;
 708     dc->unrealize = rc4030_unrealize;
 709     dc->reset = rc4030_reset;
 710     dc->vmsd = &vmstate_rc4030;
 711 }
 712
 713 static const TypeInfo rc4030_info = {
 714     .name = TYPE_RC4030,
 715     .parent = TYPE_SYS_BUS_DEVICE,
 716     .instance_size = sizeof(rc4030State),
 717     .instance_init = rc4030_initfn,
 718     .class_init = rc4030_class_init,
 719 };
 720
 721 static void rc4030_iommu_memory_region_class_init(ObjectClass *klass,
 722                                                   void *data)
 723 {
 724     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 725
 726     imrc->translate = rc4030_dma_translate;
 727 }
 728
 729 static const TypeInfo rc4030_iommu_memory_region_info = {
 730     .parent = TYPE_IOMMU_MEMORY_REGION,
 731     .name = TYPE_RC4030_IOMMU_MEMORY_REGION,
 732     .class_init = rc4030_iommu_memory_region_class_init,
 733 };
 734
 735 static void rc4030_register_types(void)
 736 {
 737     type_register_static(&rc4030_info);
 738     type_register_static(&rc4030_iommu_memory_region_info);
 739 }
 740
 741 type_init(rc4030_register_types)
 742
 743 DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr)
 744 {
 745     DeviceState *dev;
 746
 747     dev = qdev_create(NULL, TYPE_RC4030);
 748     qdev_init_nofail(dev);
 749
 750     *dmas = rc4030_allocate_dmas(dev, 4);
 751     *dma_mr = &RC4030(dev)->dma_mr;
 752     return dev;
 753 }