target/mips/mips-defs.h

   1 #ifndef QEMU_MIPS_DEFS_H
   2 #define QEMU_MIPS_DEFS_H
   3
   4 /* If we want to use host float regs... */
   5 //#define USE_HOST_FLOAT_REGS
   6
   7 /* Real pages are variable size... */
   8 #define MIPS_TLB_MAX 128
   9
  10 /*
  11  * bit definitions for insn_flags (ISAs/ASEs flags)
  12  * ------------------------------------------------
  13  */
  14 /*
  15  *   bits 0-31: MIPS base instruction sets
  16  */
  17 #define ISA_MIPS1         0x0000000000000001ULL
  18 #define ISA_MIPS2         0x0000000000000002ULL
  19 #define ISA_MIPS3         0x0000000000000004ULL
  20 #define ISA_MIPS4         0x0000000000000008ULL
  21 #define ISA_MIPS5         0x0000000000000010ULL
  22 #define ISA_MIPS32        0x0000000000000020ULL
  23 #define ISA_MIPS32R2      0x0000000000000040ULL
  24 #define ISA_MIPS64        0x0000000000000080ULL
  25 #define ISA_MIPS64R2      0x0000000000000100ULL
  26 #define ISA_MIPS32R3      0x0000000000000200ULL
  27 #define ISA_MIPS64R3      0x0000000000000400ULL
  28 #define ISA_MIPS32R5      0x0000000000000800ULL
  29 #define ISA_MIPS64R5      0x0000000000001000ULL
  30 #define ISA_MIPS32R6      0x0000000000002000ULL
  31 #define ISA_MIPS64R6      0x0000000000004000ULL
  32 #define ISA_NANOMIPS32    0x0000000000008000ULL
  33 /*
  34  *   bits 32-47: MIPS ASEs
  35  */
  36 #define ASE_MIPS16        0x0000000100000000ULL
  37 #define ASE_MIPS3D        0x0000000200000000ULL
  38 #define ASE_MDMX          0x0000000400000000ULL
  39 #define ASE_DSP           0x0000000800000000ULL
  40 #define ASE_DSP_R2        0x0000001000000000ULL
  41 #define ASE_DSP_R3        0x0000002000000000ULL
  42 #define ASE_MT            0x0000004000000000ULL
  43 #define ASE_SMARTMIPS     0x0000008000000000ULL
  44 #define ASE_MICROMIPS     0x0000010000000000ULL
  45 #define ASE_MSA           0x0000020000000000ULL
  46 /*
  47  *   bits 48-55: vendor-specific base instruction sets
  48  */
  49 #define INSN_LOONGSON2E   0x0001000000000000ULL
  50 #define INSN_LOONGSON2F   0x0002000000000000ULL
  51 #define INSN_VR54XX       0x0004000000000000ULL
  52 #define INSN_R5900        0x0008000000000000ULL
  53 /*
  54  *   bits 56-63: vendor-specific ASEs
  55  */
  56 #define ASE_MMI           0x0100000000000000ULL
  57 #define ASE_MXU           0x0200000000000000ULL
  58
  59 /* MIPS CPU defines. */
  60 #define         CPU_MIPS1       (ISA_MIPS1)
  61 #define         CPU_MIPS2       (CPU_MIPS1 | ISA_MIPS2)
  62 #define         CPU_MIPS3       (CPU_MIPS2 | ISA_MIPS3)
  63 #define         CPU_MIPS4       (CPU_MIPS3 | ISA_MIPS4)
  64 #define         CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
  65 #define         CPU_R5900       (CPU_MIPS3 | INSN_R5900)
  66 #define         CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
  67 #define         CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
  68
  69 #define         CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
  70
  71 /* MIPS Technologies "Release 1" */
  72 #define         CPU_MIPS32      (CPU_MIPS2 | ISA_MIPS32)
  73 #define         CPU_MIPS64      (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
  74
  75 /* MIPS Technologies "Release 2" */
  76 #define         CPU_MIPS32R2    (CPU_MIPS32 | ISA_MIPS32R2)
  77 #define         CPU_MIPS64R2    (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
  78
  79 /* MIPS Technologies "Release 3" */
  80 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
  81 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
  82
  83 /* MIPS Technologies "Release 5" */
  84 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
  85 #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
  86
  87 /* MIPS Technologies "Release 6" */
  88 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
  89 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
  90
  91 /* Wave Computing: "nanoMIPS" */
  92 #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
  93
  94 /* Strictly follow the architecture standard:
  95    - Disallow "special" instruction handling for PMON/SPIM.
  96    Note that we still maintain Count/Compare to match the host clock. */
  97 //#define MIPS_STRICT_STANDARD 1
  98
  99 #endif /* QEMU_MIPS_DEFS_H */