include/hw/ppc/pnv.h

   1 /*
   2  * QEMU PowerPC PowerNV various definitions
   3  *
   4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef _PPC_PNV_H
  20 #define _PPC_PNV_H
  21
  22 #include "hw/boards.h"
  23 #include "hw/sysbus.h"
  24 #include "hw/ipmi/ipmi.h"
  25 #include "hw/ppc/pnv_lpc.h"
  26 #include "hw/ppc/pnv_psi.h"
  27 #include "hw/ppc/pnv_occ.h"
  28 #include "hw/ppc/pnv_xive.h"
  29
  30 #define TYPE_PNV_CHIP "pnv-chip"
  31 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
  32 #define PNV_CHIP_CLASS(klass) \
  33      OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
  34 #define PNV_CHIP_GET_CLASS(obj) \
  35      OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
  36
  37 typedef enum PnvChipType {
  38     PNV_CHIP_POWER8E,     /* AKA Murano (default) */
  39     PNV_CHIP_POWER8,      /* AKA Venice */
  40     PNV_CHIP_POWER8NVL,   /* AKA Naples */
  41     PNV_CHIP_POWER9,      /* AKA Nimbus */
  42 } PnvChipType;
  43
  44 typedef struct PnvChip {
  45     /*< private >*/
  46     SysBusDevice parent_obj;
  47
  48     /*< public >*/
  49     uint32_t     chip_id;
  50     uint64_t     ram_start;
  51     uint64_t     ram_size;
  52
  53     uint32_t     nr_cores;
  54     uint64_t     cores_mask;
  55     void         *cores;
  56
  57     hwaddr       xscom_base;
  58     MemoryRegion xscom_mmio;
  59     MemoryRegion xscom;
  60     AddressSpace xscom_as;
  61
  62     gchar        *dt_isa_nodename;
  63 } PnvChip;
  64
  65 #define TYPE_PNV8_CHIP "pnv8-chip"
  66 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
  67
  68 typedef struct Pnv8Chip {
  69     /*< private >*/
  70     PnvChip      parent_obj;
  71
  72     /*< public >*/
  73     MemoryRegion icp_mmio;
  74
  75     PnvLpcController lpc;
  76     Pnv8Psi      psi;
  77     PnvOCC       occ;
  78 } Pnv8Chip;
  79
  80 #define TYPE_PNV9_CHIP "pnv9-chip"
  81 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
  82
  83 typedef struct Pnv9Chip {
  84     /*< private >*/
  85     PnvChip      parent_obj;
  86
  87     /*< public >*/
  88     PnvXive      xive;
  89     Pnv9Psi      psi;
  90     PnvLpcController lpc;
  91 } Pnv9Chip;
  92
  93 typedef struct PnvChipClass {
  94     /*< private >*/
  95     SysBusDeviceClass parent_class;
  96
  97     /*< public >*/
  98     PnvChipType  chip_type;
  99     uint64_t     chip_cfam_id;
 100     uint64_t     cores_mask;
 101
 102     hwaddr       xscom_base;
 103
 104     DeviceRealize parent_realize;
 105
 106     uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
 107     void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
 108     ISABus *(*isa_create)(PnvChip *chip, Error **errp);
 109     void (*dt_populate)(PnvChip *chip, void *fdt);
 110     void (*pic_print_info)(PnvChip *chip, Monitor *mon);
 111 } PnvChipClass;
 112
 113 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
 114 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
 115
 116 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
 117 #define PNV_CHIP_POWER8E(obj) \
 118     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
 119
 120 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
 121 #define PNV_CHIP_POWER8(obj) \
 122     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
 123
 124 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
 125 #define PNV_CHIP_POWER8NVL(obj) \
 126     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
 127
 128 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
 129 #define PNV_CHIP_POWER9(obj) \
 130     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
 131
 132 /*
 133  * This generates a HW chip id depending on an index, as found on a
 134  * two socket system with dual chip modules :
 135  *
 136  *    0x0, 0x1, 0x10, 0x11
 137  *
 138  * 4 chips should be the maximum
 139  *
 140  * TODO: use a machine property to define the chip ids
 141  */
 142 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
 143
 144 /*
 145  * Converts back a HW chip id to an index. This is useful to calculate
 146  * the MMIO addresses of some controllers which depend on the chip id.
 147  */
 148 #define PNV_CHIP_INDEX(chip)                                    \
 149     (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
 150
 151 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
 152 #define PNV_MACHINE(obj) \
 153     OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
 154
 155 typedef struct PnvMachineState {
 156     /*< private >*/
 157     MachineState parent_obj;
 158
 159     uint32_t     initrd_base;
 160     long         initrd_size;
 161
 162     uint32_t     num_chips;
 163     PnvChip      **chips;
 164
 165     ISABus       *isa_bus;
 166     uint32_t     cpld_irqstate;
 167
 168     IPMIBmc      *bmc;
 169     Notifier     powerdown_notifier;
 170 } PnvMachineState;
 171
 172 static inline bool pnv_chip_is_power9(const PnvChip *chip)
 173 {
 174     return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
 175 }
 176
 177 static inline bool pnv_is_power9(PnvMachineState *pnv)
 178 {
 179     return pnv_chip_is_power9(pnv->chips[0]);
 180 }
 181
 182 #define PNV_FDT_ADDR          0x01000000
 183 #define PNV_TIMEBASE_FREQ     512000000ULL
 184
 185 /*
 186  * BMC helpers
 187  */
 188 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
 189 void pnv_bmc_powerdown(IPMIBmc *bmc);
 190
 191 /*
 192  * POWER8 MMIO base addresses
 193  */
 194 #define PNV_XSCOM_SIZE        0x800000000ull
 195 #define PNV_XSCOM_BASE(chip)                                            \
 196     (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
 197
 198 /*
 199  * XSCOM 0x20109CA defines the ICP BAR:
 200  *
 201  * 0:29   : bits 14 to 43 of address to define 1 MB region.
 202  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
 203  * 31:63  : Constant 0
 204  *
 205  * Usually defined as :
 206  *
 207  *      0xffffe00200000000 -> 0x0003ffff80000000
 208  *      0xffffe00600000000 -> 0x0003ffff80100000
 209  *      0xffffe02200000000 -> 0x0003ffff80800000
 210  *      0xffffe02600000000 -> 0x0003ffff80900000
 211  */
 212 #define PNV_ICP_SIZE         0x0000000000100000ull
 213 #define PNV_ICP_BASE(chip)                                              \
 214     (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
 215
 216
 217 #define PNV_PSIHB_SIZE       0x0000000000100000ull
 218 #define PNV_PSIHB_BASE(chip) \
 219     (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
 220
 221 #define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
 222 #define PNV_PSIHB_FSP_BASE(chip) \
 223     (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
 224      PNV_PSIHB_FSP_SIZE)
 225
 226 /*
 227  * POWER9 MMIO base addresses
 228  */
 229 #define PNV9_CHIP_BASE(chip, base)   \
 230     ((base) + ((uint64_t) (chip)->chip_id << 42))
 231
 232 #define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
 233 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
 234
 235 #define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
 236 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
 237
 238 #define PNV9_LPCM_SIZE               0x0000000100000000ull
 239 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
 240
 241 #define PNV9_PSIHB_SIZE              0x0000000000100000ull
 242 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
 243
 244 #define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
 245 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
 246
 247 #define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
 248 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
 249
 250 #define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
 251 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
 252
 253 #endif /* _PPC_PNV_H */