hw/ppc/pnv_lpc.c

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "sysemu/sysemu.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qapi/error.h"
  24 #include "qemu/log.h"
  25 #include "hw/isa/isa.h"
  26
  27 #include "hw/ppc/pnv.h"
  28 #include "hw/ppc/pnv_lpc.h"
  29 #include "hw/ppc/pnv_xscom.h"
  30 #include "hw/ppc/fdt.h"
  31
  32 #include <libfdt.h>
  33
  34 enum {
  35     ECCB_CTL    = 0,
  36     ECCB_RESET  = 1,
  37     ECCB_STAT   = 2,
  38     ECCB_DATA   = 3,
  39 };
  40
  41 /* OPB Master LS registers */
  42 #define OPB_MASTER_LS_IRQ_STAT  0x50
  43 #define   OPB_MASTER_IRQ_LPC            0x00000800
  44 #define OPB_MASTER_LS_IRQ_MASK  0x54
  45 #define OPB_MASTER_LS_IRQ_POL   0x58
  46 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
  47
  48 /* LPC HC registers */
  49 #define LPC_HC_FW_SEG_IDSEL     0x24
  50 #define LPC_HC_FW_RD_ACC_SIZE   0x28
  51 #define   LPC_HC_FW_RD_1B               0x00000000
  52 #define   LPC_HC_FW_RD_2B               0x01000000
  53 #define   LPC_HC_FW_RD_4B               0x02000000
  54 #define   LPC_HC_FW_RD_16B              0x04000000
  55 #define   LPC_HC_FW_RD_128B             0x07000000
  56 #define LPC_HC_IRQSER_CTRL      0x30
  57 #define   LPC_HC_IRQSER_EN              0x80000000
  58 #define   LPC_HC_IRQSER_QMODE           0x40000000
  59 #define   LPC_HC_IRQSER_START_MASK      0x03000000
  60 #define   LPC_HC_IRQSER_START_4CLK      0x00000000
  61 #define   LPC_HC_IRQSER_START_6CLK      0x01000000
  62 #define   LPC_HC_IRQSER_START_8CLK      0x02000000
  63 #define LPC_HC_IRQMASK          0x34    /* same bit defs as LPC_HC_IRQSTAT */
  64 #define LPC_HC_IRQSTAT          0x38
  65 #define   LPC_HC_IRQ_SERIRQ0            0x80000000 /* all bits down to ... */
  66 #define   LPC_HC_IRQ_SERIRQ16           0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
  67 #define   LPC_HC_IRQ_SERIRQ_ALL         0xffff8000
  68 #define   LPC_HC_IRQ_LRESET             0x00000400
  69 #define   LPC_HC_IRQ_SYNC_ABNORM_ERR    0x00000080
  70 #define   LPC_HC_IRQ_SYNC_NORESP_ERR    0x00000040
  71 #define   LPC_HC_IRQ_SYNC_NORM_ERR      0x00000020
  72 #define   LPC_HC_IRQ_SYNC_TIMEOUT_ERR   0x00000010
  73 #define   LPC_HC_IRQ_SYNC_TARG_TAR_ERR  0x00000008
  74 #define   LPC_HC_IRQ_SYNC_BM_TAR_ERR    0x00000004
  75 #define   LPC_HC_IRQ_SYNC_BM0_REQ       0x00000002
  76 #define   LPC_HC_IRQ_SYNC_BM1_REQ       0x00000001
  77 #define LPC_HC_ERROR_ADDRESS    0x40
  78
  79 #define LPC_OPB_SIZE            0x100000000ull
  80
  81 #define ISA_IO_SIZE             0x00010000
  82 #define ISA_MEM_SIZE            0x10000000
  83 #define ISA_FW_SIZE             0x10000000
  84 #define LPC_IO_OPB_ADDR         0xd0010000
  85 #define LPC_IO_OPB_SIZE         0x00010000
  86 #define LPC_MEM_OPB_ADDR        0xe0010000
  87 #define LPC_MEM_OPB_SIZE        0x10000000
  88 #define LPC_FW_OPB_ADDR         0xf0000000
  89 #define LPC_FW_OPB_SIZE         0x10000000
  90
  91 #define LPC_OPB_REGS_OPB_ADDR   0xc0010000
  92 #define LPC_OPB_REGS_OPB_SIZE   0x00000060
  93 #define LPC_OPB_REGS_OPBA_ADDR  0xc0011000
  94 #define LPC_OPB_REGS_OPBA_SIZE  0x00000008
  95 #define LPC_HC_REGS_OPB_ADDR    0xc0012000
  96 #define LPC_HC_REGS_OPB_SIZE    0x00000100
  97
  98 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
  99 {
 100     const char compat[] = "ibm,power8-lpc\0ibm,lpc";
 101     char *name;
 102     int offset;
 103     uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
 104     uint32_t reg[] = {
 105         cpu_to_be32(lpc_pcba),
 106         cpu_to_be32(PNV_XSCOM_LPC_SIZE)
 107     };
 108
 109     name = g_strdup_printf("isa@%x", lpc_pcba);
 110     offset = fdt_add_subnode(fdt, xscom_offset, name);
 111     _FDT(offset);
 112     g_free(name);
 113
 114     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 115     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 116     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 117     _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
 118     return 0;
 119 }
 120
 121 /* POWER9 only */
 122 int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
 123 {
 124     const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
 125     const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
 126     char *name;
 127     int offset, lpcm_offset;
 128     uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
 129     uint32_t opb_ranges[8] = { 0,
 130                                cpu_to_be32(lpcm_addr >> 32),
 131                                cpu_to_be32((uint32_t)lpcm_addr),
 132                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 133                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 134                                cpu_to_be32(lpcm_addr >> 32),
 135                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 136                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 137     };
 138     uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
 139                             cpu_to_be32((uint32_t)lpcm_addr),
 140                             cpu_to_be32(PNV9_LPCM_SIZE >> 32),
 141                             cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
 142     };
 143     uint32_t reg[2];
 144
 145     /*
 146      * OPB bus
 147      */
 148     name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr);
 149     lpcm_offset = fdt_add_subnode(fdt, root_offset, name);
 150     _FDT(lpcm_offset);
 151     g_free(name);
 152
 153     _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg))));
 154     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1)));
 155     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1)));
 156     _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat))));
 157     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id)));
 158     _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges,
 159                       sizeof(opb_ranges))));
 160
 161     /*
 162      * OPB Master registers
 163      */
 164     name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR);
 165     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 166     _FDT(offset);
 167     g_free(name);
 168
 169     reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR);
 170     reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE);
 171     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 172     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 173                              "ibm,power9-lpcm-opb-master")));
 174
 175     /*
 176      * OPB arbitrer registers
 177      */
 178     name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR);
 179     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 180     _FDT(offset);
 181     g_free(name);
 182
 183     reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR);
 184     reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE);
 185     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 186     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 187                              "ibm,power9-lpcm-opb-arbiter")));
 188
 189     /*
 190      * LPC Host Controller registers
 191      */
 192     name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR);
 193     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 194     _FDT(offset);
 195     g_free(name);
 196
 197     reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR);
 198     reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE);
 199     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 200     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 201                              "ibm,power9-lpc-controller")));
 202
 203     name = g_strdup_printf("lpc@0");
 204     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 205     _FDT(offset);
 206     g_free(name);
 207     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 208     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 209     _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
 210                       sizeof(lpc_compat))));
 211
 212     return 0;
 213 }
 214
 215 /*
 216  * These read/write handlers of the OPB address space should be common
 217  * with the P9 LPC Controller which uses direct MMIOs.
 218  *
 219  * TODO: rework to use address_space_stq() and address_space_ldq()
 220  * instead.
 221  */
 222 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 223                      int sz)
 224 {
 225     /* XXX Handle access size limits and FW read caching here */
 226     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 227                              data, sz, false);
 228 }
 229
 230 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 231                       int sz)
 232 {
 233     /* XXX Handle access size limits here */
 234     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 235                              data, sz, true);
 236 }
 237
 238 #define ECCB_CTL_READ           PPC_BIT(15)
 239 #define ECCB_CTL_SZ_LSH         (63 - 7)
 240 #define ECCB_CTL_SZ_MASK        PPC_BITMASK(4, 7)
 241 #define ECCB_CTL_ADDR_MASK      PPC_BITMASK(32, 63)
 242
 243 #define ECCB_STAT_OP_DONE       PPC_BIT(52)
 244 #define ECCB_STAT_OP_ERR        PPC_BIT(52)
 245 #define ECCB_STAT_RD_DATA_LSH   (63 - 37)
 246 #define ECCB_STAT_RD_DATA_MASK  (0xffffffff << ECCB_STAT_RD_DATA_LSH)
 247
 248 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
 249 {
 250     /* XXX Check for magic bits at the top, addr size etc... */
 251     unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
 252     uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
 253     uint8_t data[8];
 254     bool success;
 255
 256     if (sz > sizeof(data)) {
 257         qemu_log_mask(LOG_GUEST_ERROR,
 258             "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz);
 259         return;
 260     }
 261
 262     if (cmd & ECCB_CTL_READ) {
 263         success = opb_read(lpc, opb_addr, data, sz);
 264         if (success) {
 265             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 266                     (((uint64_t)data[0]) << 24 |
 267                      ((uint64_t)data[1]) << 16 |
 268                      ((uint64_t)data[2]) <<  8 |
 269                      ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
 270         } else {
 271             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 272                     (0xffffffffull << ECCB_STAT_RD_DATA_LSH);
 273         }
 274     } else {
 275         data[0] = lpc->eccb_data_reg >> 24;
 276         data[1] = lpc->eccb_data_reg >> 16;
 277         data[2] = lpc->eccb_data_reg >>  8;
 278         data[3] = lpc->eccb_data_reg;
 279
 280         success = opb_write(lpc, opb_addr, data, sz);
 281         lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
 282     }
 283     /* XXX Which error bit (if any) to signal OPB error ? */
 284 }
 285
 286 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
 287 {
 288     PnvLpcController *lpc = PNV_LPC(opaque);
 289     uint32_t offset = addr >> 3;
 290     uint64_t val = 0;
 291
 292     switch (offset & 3) {
 293     case ECCB_CTL:
 294     case ECCB_RESET:
 295         val = 0;
 296         break;
 297     case ECCB_STAT:
 298         val = lpc->eccb_stat_reg;
 299         lpc->eccb_stat_reg = 0;
 300         break;
 301     case ECCB_DATA:
 302         val = ((uint64_t)lpc->eccb_data_reg) << 32;
 303         break;
 304     }
 305     return val;
 306 }
 307
 308 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
 309                                 uint64_t val, unsigned size)
 310 {
 311     PnvLpcController *lpc = PNV_LPC(opaque);
 312     uint32_t offset = addr >> 3;
 313
 314     switch (offset & 3) {
 315     case ECCB_CTL:
 316         pnv_lpc_do_eccb(lpc, val);
 317         break;
 318     case ECCB_RESET:
 319         /*  XXXX  */
 320         break;
 321     case ECCB_STAT:
 322         break;
 323     case ECCB_DATA:
 324         lpc->eccb_data_reg = val >> 32;
 325         break;
 326     }
 327 }
 328
 329 static const MemoryRegionOps pnv_lpc_xscom_ops = {
 330     .read = pnv_lpc_xscom_read,
 331     .write = pnv_lpc_xscom_write,
 332     .valid.min_access_size = 8,
 333     .valid.max_access_size = 8,
 334     .impl.min_access_size = 8,
 335     .impl.max_access_size = 8,
 336     .endianness = DEVICE_BIG_ENDIAN,
 337 };
 338
 339 static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
 340 {
 341     PnvLpcController *lpc = PNV_LPC(opaque);
 342     uint64_t val = 0;
 343     uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
 344     MemTxResult result;
 345
 346     switch (size) {
 347     case 4:
 348         val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
 349                                 &result);
 350         break;
 351     case 1:
 352         val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
 353                                  &result);
 354         break;
 355     default:
 356         qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
 357                       HWADDR_PRIx " invalid size %d\n", addr, size);
 358         return 0;
 359     }
 360
 361     if (result != MEMTX_OK) {
 362         qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
 363                       HWADDR_PRIx "\n", addr);
 364     }
 365
 366     return val;
 367 }
 368
 369 static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
 370                                 uint64_t val, unsigned size)
 371 {
 372     PnvLpcController *lpc = PNV_LPC(opaque);
 373     uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
 374     MemTxResult result;
 375
 376     switch (size) {
 377     case 4:
 378         address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
 379                           &result);
 380          break;
 381     case 1:
 382         address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
 383                           &result);
 384         break;
 385     default:
 386         qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
 387                       HWADDR_PRIx " invalid size %d\n", addr, size);
 388         return;
 389     }
 390
 391     if (result != MEMTX_OK) {
 392         qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
 393                       HWADDR_PRIx "\n", addr);
 394     }
 395 }
 396
 397 static const MemoryRegionOps pnv_lpc_mmio_ops = {
 398     .read = pnv_lpc_mmio_read,
 399     .write = pnv_lpc_mmio_write,
 400     .impl = {
 401         .min_access_size = 1,
 402         .max_access_size = 4,
 403     },
 404     .endianness = DEVICE_BIG_ENDIAN,
 405 };
 406
 407 static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
 408 {
 409     bool lpc_to_opb_irq = false;
 410     PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
 411
 412     /* Update LPC controller to OPB line */
 413     if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
 414         uint32_t irqs;
 415
 416         irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
 417         lpc_to_opb_irq = (irqs != 0);
 418     }
 419
 420     /* We don't honor the polarity register, it's pointless and unused
 421      * anyway
 422      */
 423     if (lpc_to_opb_irq) {
 424         lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
 425     } else {
 426         lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
 427     }
 428
 429     /* Update OPB internal latch */
 430     lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
 431
 432     /* Reflect the interrupt */
 433     pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
 434 }
 435
 436 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
 437 {
 438     PnvLpcController *lpc = opaque;
 439     uint64_t val = 0xfffffffffffffffful;
 440
 441     switch (addr) {
 442     case LPC_HC_FW_SEG_IDSEL:
 443         val =  lpc->lpc_hc_fw_seg_idsel;
 444         break;
 445     case LPC_HC_FW_RD_ACC_SIZE:
 446         val =  lpc->lpc_hc_fw_rd_acc_size;
 447         break;
 448     case LPC_HC_IRQSER_CTRL:
 449         val =  lpc->lpc_hc_irqser_ctrl;
 450         break;
 451     case LPC_HC_IRQMASK:
 452         val =  lpc->lpc_hc_irqmask;
 453         break;
 454     case LPC_HC_IRQSTAT:
 455         val =  lpc->lpc_hc_irqstat;
 456         break;
 457     case LPC_HC_ERROR_ADDRESS:
 458         val =  lpc->lpc_hc_error_addr;
 459         break;
 460     default:
 461         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
 462                       HWADDR_PRIx "\n", addr);
 463     }
 464     return val;
 465 }
 466
 467 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
 468                          unsigned size)
 469 {
 470     PnvLpcController *lpc = opaque;
 471
 472     /* XXX Filter out reserved bits */
 473
 474     switch (addr) {
 475     case LPC_HC_FW_SEG_IDSEL:
 476         /* XXX Actually figure out how that works as this impact
 477          * memory regions/aliases
 478          */
 479         lpc->lpc_hc_fw_seg_idsel = val;
 480         break;
 481     case LPC_HC_FW_RD_ACC_SIZE:
 482         lpc->lpc_hc_fw_rd_acc_size = val;
 483         break;
 484     case LPC_HC_IRQSER_CTRL:
 485         lpc->lpc_hc_irqser_ctrl = val;
 486         pnv_lpc_eval_irqs(lpc);
 487         break;
 488     case LPC_HC_IRQMASK:
 489         lpc->lpc_hc_irqmask = val;
 490         pnv_lpc_eval_irqs(lpc);
 491         break;
 492     case LPC_HC_IRQSTAT:
 493         lpc->lpc_hc_irqstat &= ~val;
 494         pnv_lpc_eval_irqs(lpc);
 495         break;
 496     case LPC_HC_ERROR_ADDRESS:
 497         break;
 498     default:
 499         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
 500                       HWADDR_PRIx "\n", addr);
 501     }
 502 }
 503
 504 static const MemoryRegionOps lpc_hc_ops = {
 505     .read = lpc_hc_read,
 506     .write = lpc_hc_write,
 507     .endianness = DEVICE_BIG_ENDIAN,
 508     .valid = {
 509         .min_access_size = 4,
 510         .max_access_size = 4,
 511     },
 512     .impl = {
 513         .min_access_size = 4,
 514         .max_access_size = 4,
 515     },
 516 };
 517
 518 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
 519 {
 520     PnvLpcController *lpc = opaque;
 521     uint64_t val = 0xfffffffffffffffful;
 522
 523     switch (addr) {
 524     case OPB_MASTER_LS_IRQ_STAT:
 525         val = lpc->opb_irq_stat;
 526         break;
 527     case OPB_MASTER_LS_IRQ_MASK:
 528         val = lpc->opb_irq_mask;
 529         break;
 530     case OPB_MASTER_LS_IRQ_POL:
 531         val = lpc->opb_irq_pol;
 532         break;
 533     case OPB_MASTER_LS_IRQ_INPUT:
 534         val = lpc->opb_irq_input;
 535         break;
 536     default:
 537         qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
 538                       HWADDR_PRIx "\n", addr);
 539     }
 540
 541     return val;
 542 }
 543
 544 static void opb_master_write(void *opaque, hwaddr addr,
 545                              uint64_t val, unsigned size)
 546 {
 547     PnvLpcController *lpc = opaque;
 548
 549     switch (addr) {
 550     case OPB_MASTER_LS_IRQ_STAT:
 551         lpc->opb_irq_stat &= ~val;
 552         pnv_lpc_eval_irqs(lpc);
 553         break;
 554     case OPB_MASTER_LS_IRQ_MASK:
 555         lpc->opb_irq_mask = val;
 556         pnv_lpc_eval_irqs(lpc);
 557         break;
 558     case OPB_MASTER_LS_IRQ_POL:
 559         lpc->opb_irq_pol = val;
 560         pnv_lpc_eval_irqs(lpc);
 561         break;
 562     case OPB_MASTER_LS_IRQ_INPUT:
 563         /* Read only */
 564         break;
 565     default:
 566         qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
 567                       HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
 568     }
 569 }
 570
 571 static const MemoryRegionOps opb_master_ops = {
 572     .read = opb_master_read,
 573     .write = opb_master_write,
 574     .endianness = DEVICE_BIG_ENDIAN,
 575     .valid = {
 576         .min_access_size = 4,
 577         .max_access_size = 4,
 578     },
 579     .impl = {
 580         .min_access_size = 4,
 581         .max_access_size = 4,
 582     },
 583 };
 584
 585 static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp)
 586 {
 587     PnvLpcController *lpc = PNV_LPC(dev);
 588     PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
 589     Error *local_err = NULL;
 590
 591     plc->parent_realize(dev, &local_err);
 592     if (local_err) {
 593         error_propagate(errp, local_err);
 594         return;
 595     }
 596
 597     /* P8 uses a XSCOM region for LPC registers */
 598     pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc),
 599                           &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
 600                           PNV_XSCOM_LPC_SIZE);
 601 }
 602
 603 static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
 604 {
 605     DeviceClass *dc = DEVICE_CLASS(klass);
 606     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 607     PnvLpcClass *plc = PNV_LPC_CLASS(klass);
 608
 609     dc->desc = "PowerNV LPC Controller POWER8";
 610
 611     xdc->dt_xscom = pnv_lpc_dt_xscom;
 612
 613     plc->psi_irq = PSIHB_IRQ_LPC_I2C;
 614
 615     device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
 616                                     &plc->parent_realize);
 617 }
 618
 619 static const TypeInfo pnv_lpc_power8_info = {
 620     .name          = TYPE_PNV8_LPC,
 621     .parent        = TYPE_PNV_LPC,
 622     .instance_size = sizeof(PnvLpcController),
 623     .class_init    = pnv_lpc_power8_class_init,
 624     .interfaces = (InterfaceInfo[]) {
 625         { TYPE_PNV_XSCOM_INTERFACE },
 626         { }
 627     }
 628 };
 629
 630 static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp)
 631 {
 632     PnvLpcController *lpc = PNV_LPC(dev);
 633     PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
 634     Error *local_err = NULL;
 635
 636     plc->parent_realize(dev, &local_err);
 637     if (local_err) {
 638         error_propagate(errp, local_err);
 639         return;
 640     }
 641
 642     /* P9 uses a MMIO region */
 643     memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops,
 644                           lpc, "lpcm", PNV9_LPCM_SIZE);
 645 }
 646
 647 static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
 648 {
 649     DeviceClass *dc = DEVICE_CLASS(klass);
 650     PnvLpcClass *plc = PNV_LPC_CLASS(klass);
 651
 652     dc->desc = "PowerNV LPC Controller POWER9";
 653
 654     plc->psi_irq = PSIHB9_IRQ_LPCHC;
 655
 656     device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
 657                                     &plc->parent_realize);
 658 }
 659
 660 static const TypeInfo pnv_lpc_power9_info = {
 661     .name          = TYPE_PNV9_LPC,
 662     .parent        = TYPE_PNV_LPC,
 663     .instance_size = sizeof(PnvLpcController),
 664     .class_init    = pnv_lpc_power9_class_init,
 665 };
 666
 667 static void pnv_lpc_realize(DeviceState *dev, Error **errp)
 668 {
 669     PnvLpcController *lpc = PNV_LPC(dev);
 670     Object *obj;
 671     Error *local_err = NULL;
 672
 673     obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
 674     if (!obj) {
 675         error_propagate(errp, local_err);
 676         error_prepend(errp, "required link 'psi' not found: ");
 677         return;
 678     }
 679     /* The LPC controller needs PSI to generate interrupts  */
 680     lpc->psi = PNV_PSI(obj);
 681
 682     /* Reg inits */
 683     lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
 684
 685     /* Create address space and backing MR for the OPB bus */
 686     memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
 687     address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
 688
 689     /* Create ISA IO and Mem space regions which are the root of
 690      * the ISA bus (ie, ISA address spaces). We don't create a
 691      * separate one for FW which we alias to memory.
 692      */
 693     memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
 694     memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
 695     memory_region_init(&lpc->isa_fw, OBJECT(dev),  "isa-fw", ISA_FW_SIZE);
 696
 697     /* Create windows from the OPB space to the ISA space */
 698     memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
 699                              &lpc->isa_io, 0, LPC_IO_OPB_SIZE);
 700     memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
 701                                 &lpc->opb_isa_io);
 702     memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
 703                              &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
 704     memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
 705                                 &lpc->opb_isa_mem);
 706     memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
 707                              &lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
 708     memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
 709                                 &lpc->opb_isa_fw);
 710
 711     /* Create MMIO regions for LPC HC and OPB registers */
 712     memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
 713                           lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
 714     memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
 715                                 &lpc->opb_master_regs);
 716     memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
 717                           "lpc-hc", LPC_HC_REGS_OPB_SIZE);
 718     memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
 719                                 &lpc->lpc_hc_regs);
 720 }
 721
 722 static void pnv_lpc_class_init(ObjectClass *klass, void *data)
 723 {
 724     DeviceClass *dc = DEVICE_CLASS(klass);
 725
 726     dc->realize = pnv_lpc_realize;
 727     dc->desc = "PowerNV LPC Controller";
 728 }
 729
 730 static const TypeInfo pnv_lpc_info = {
 731     .name          = TYPE_PNV_LPC,
 732     .parent        = TYPE_DEVICE,
 733     .class_init    = pnv_lpc_class_init,
 734     .class_size    = sizeof(PnvLpcClass),
 735     .abstract      = true,
 736 };
 737
 738 static void pnv_lpc_register_types(void)
 739 {
 740     type_register_static(&pnv_lpc_info);
 741     type_register_static(&pnv_lpc_power8_info);
 742     type_register_static(&pnv_lpc_power9_info);
 743 }
 744
 745 type_init(pnv_lpc_register_types)
 746
 747 /* If we don't use the built-in LPC interrupt deserializer, we need
 748  * to provide a set of qirqs for the ISA bus or things will go bad.
 749  *
 750  * Most machines using pre-Naples chips (without said deserializer)
 751  * have a CPLD that will collect the SerIRQ and shoot them as a
 752  * single level interrupt to the P8 chip. So let's setup a hook
 753  * for doing just that.
 754  */
 755 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 756 {
 757     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
 758     uint32_t old_state = pnv->cpld_irqstate;
 759     PnvLpcController *lpc = PNV_LPC(opaque);
 760
 761     if (level) {
 762         pnv->cpld_irqstate |= 1u << n;
 763     } else {
 764         pnv->cpld_irqstate &= ~(1u << n);
 765     }
 766
 767     if (pnv->cpld_irqstate != old_state) {
 768         pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
 769     }
 770 }
 771
 772 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 773 {
 774     PnvLpcController *lpc = PNV_LPC(opaque);
 775
 776     /* The Naples HW latches the 1 levels, clearing is done by SW */
 777     if (level) {
 778         lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
 779         pnv_lpc_eval_irqs(lpc);
 780     }
 781 }
 782
 783 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
 784 {
 785     Error *local_err = NULL;
 786     ISABus *isa_bus;
 787     qemu_irq *irqs;
 788     qemu_irq_handler handler;
 789
 790     /* let isa_bus_new() create its own bridge on SysBus otherwise
 791      * devices speficied on the command line won't find the bus and
 792      * will fail to create.
 793      */
 794     isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
 795     if (local_err) {
 796         error_propagate(errp, local_err);
 797         return NULL;
 798     }
 799
 800     /* Not all variants have a working serial irq decoder. If not,
 801      * handling of LPC interrupts becomes a platform issue (some
 802      * platforms have a CPLD to do it).
 803      */
 804     if (use_cpld) {
 805         handler = pnv_lpc_isa_irq_handler_cpld;
 806     } else {
 807         handler = pnv_lpc_isa_irq_handler;
 808     }
 809
 810     irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
 811
 812     isa_bus_irqs(isa_bus, irqs);
 813     return isa_bus;
 814 }