target/arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "qemu/module.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "sysemu/kvm.h"
  29 #include "kvm_arm.h"
  30 #include "qapi/visitor.h"
  31
  32 static inline void set_feature(CPUARMState *env, int feature)
  33 {
  34     env->features |= 1ULL << feature;
  35 }
  36
  37 static inline void unset_feature(CPUARMState *env, int feature)
  38 {
  39     env->features &= ~(1ULL << feature);
  40 }
  41
  42 #ifndef CONFIG_USER_ONLY
  43 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  44 {
  45     ARMCPU *cpu = env_archcpu(env);
  46
  47     /* Number of cores is in [25:24]; otherwise we RAZ */
  48     return (cpu->core_count - 1) << 24;
  49 }
  50 #endif
  51
  52 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
  53 #ifndef CONFIG_USER_ONLY
  54     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  55       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  56       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  57       .writefn = arm_cp_write_ignore },
  58     { .name = "L2CTLR",
  59       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  60       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  61       .writefn = arm_cp_write_ignore },
  62 #endif
  63     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  64       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  65       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  66     { .name = "L2ECTLR",
  67       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  68       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  69     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  70       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  71       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  72     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  73       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  74       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  75     { .name = "CPUACTLR",
  76       .cp = 15, .opc1 = 0, .crm = 15,
  77       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  78     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  79       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  80       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  81     { .name = "CPUECTLR",
  82       .cp = 15, .opc1 = 1, .crm = 15,
  83       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  84     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  85       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  86       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  87     { .name = "CPUMERRSR",
  88       .cp = 15, .opc1 = 2, .crm = 15,
  89       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  90     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  91       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  92       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  93     { .name = "L2MERRSR",
  94       .cp = 15, .opc1 = 3, .crm = 15,
  95       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  96     REGINFO_SENTINEL
  97 };
  98
  99 static void aarch64_a57_initfn(Object *obj)
 100 {
 101     ARMCPU *cpu = ARM_CPU(obj);
 102
 103     cpu->dtb_compatible = "arm,cortex-a57";
 104     set_feature(&cpu->env, ARM_FEATURE_V8);
 105     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 106     set_feature(&cpu->env, ARM_FEATURE_NEON);
 107     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 108     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 109     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 110     set_feature(&cpu->env, ARM_FEATURE_EL2);
 111     set_feature(&cpu->env, ARM_FEATURE_EL3);
 112     set_feature(&cpu->env, ARM_FEATURE_PMU);
 113     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 114     cpu->midr = 0x411fd070;
 115     cpu->revidr = 0x00000000;
 116     cpu->reset_fpsid = 0x41034070;
 117     cpu->isar.mvfr0 = 0x10110222;
 118     cpu->isar.mvfr1 = 0x12111111;
 119     cpu->isar.mvfr2 = 0x00000043;
 120     cpu->ctr = 0x8444c004;
 121     cpu->reset_sctlr = 0x00c50838;
 122     cpu->id_pfr0 = 0x00000131;
 123     cpu->id_pfr1 = 0x00011011;
 124     cpu->id_dfr0 = 0x03010066;
 125     cpu->id_afr0 = 0x00000000;
 126     cpu->id_mmfr0 = 0x10101105;
 127     cpu->id_mmfr1 = 0x40000000;
 128     cpu->id_mmfr2 = 0x01260000;
 129     cpu->id_mmfr3 = 0x02102211;
 130     cpu->isar.id_isar0 = 0x02101110;
 131     cpu->isar.id_isar1 = 0x13112111;
 132     cpu->isar.id_isar2 = 0x21232042;
 133     cpu->isar.id_isar3 = 0x01112131;
 134     cpu->isar.id_isar4 = 0x00011142;
 135     cpu->isar.id_isar5 = 0x00011121;
 136     cpu->isar.id_isar6 = 0;
 137     cpu->isar.id_aa64pfr0 = 0x00002222;
 138     cpu->id_aa64dfr0 = 0x10305106;
 139     cpu->isar.id_aa64isar0 = 0x00011120;
 140     cpu->isar.id_aa64mmfr0 = 0x00001124;
 141     cpu->dbgdidr = 0x3516d000;
 142     cpu->clidr = 0x0a200023;
 143     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 144     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 145     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 146     cpu->dcz_blocksize = 4; /* 64 bytes */
 147     cpu->gic_num_lrs = 4;
 148     cpu->gic_vpribits = 5;
 149     cpu->gic_vprebits = 5;
 150     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 151 }
 152
 153 static void aarch64_a53_initfn(Object *obj)
 154 {
 155     ARMCPU *cpu = ARM_CPU(obj);
 156
 157     cpu->dtb_compatible = "arm,cortex-a53";
 158     set_feature(&cpu->env, ARM_FEATURE_V8);
 159     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 160     set_feature(&cpu->env, ARM_FEATURE_NEON);
 161     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 162     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 163     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 164     set_feature(&cpu->env, ARM_FEATURE_EL2);
 165     set_feature(&cpu->env, ARM_FEATURE_EL3);
 166     set_feature(&cpu->env, ARM_FEATURE_PMU);
 167     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 168     cpu->midr = 0x410fd034;
 169     cpu->revidr = 0x00000000;
 170     cpu->reset_fpsid = 0x41034070;
 171     cpu->isar.mvfr0 = 0x10110222;
 172     cpu->isar.mvfr1 = 0x12111111;
 173     cpu->isar.mvfr2 = 0x00000043;
 174     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 175     cpu->reset_sctlr = 0x00c50838;
 176     cpu->id_pfr0 = 0x00000131;
 177     cpu->id_pfr1 = 0x00011011;
 178     cpu->id_dfr0 = 0x03010066;
 179     cpu->id_afr0 = 0x00000000;
 180     cpu->id_mmfr0 = 0x10101105;
 181     cpu->id_mmfr1 = 0x40000000;
 182     cpu->id_mmfr2 = 0x01260000;
 183     cpu->id_mmfr3 = 0x02102211;
 184     cpu->isar.id_isar0 = 0x02101110;
 185     cpu->isar.id_isar1 = 0x13112111;
 186     cpu->isar.id_isar2 = 0x21232042;
 187     cpu->isar.id_isar3 = 0x01112131;
 188     cpu->isar.id_isar4 = 0x00011142;
 189     cpu->isar.id_isar5 = 0x00011121;
 190     cpu->isar.id_isar6 = 0;
 191     cpu->isar.id_aa64pfr0 = 0x00002222;
 192     cpu->id_aa64dfr0 = 0x10305106;
 193     cpu->isar.id_aa64isar0 = 0x00011120;
 194     cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 195     cpu->dbgdidr = 0x3516d000;
 196     cpu->clidr = 0x0a200023;
 197     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 198     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 199     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 200     cpu->dcz_blocksize = 4; /* 64 bytes */
 201     cpu->gic_num_lrs = 4;
 202     cpu->gic_vpribits = 5;
 203     cpu->gic_vprebits = 5;
 204     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 205 }
 206
 207 static void aarch64_a72_initfn(Object *obj)
 208 {
 209     ARMCPU *cpu = ARM_CPU(obj);
 210
 211     cpu->dtb_compatible = "arm,cortex-a72";
 212     set_feature(&cpu->env, ARM_FEATURE_V8);
 213     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 214     set_feature(&cpu->env, ARM_FEATURE_NEON);
 215     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 216     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 217     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 218     set_feature(&cpu->env, ARM_FEATURE_EL2);
 219     set_feature(&cpu->env, ARM_FEATURE_EL3);
 220     set_feature(&cpu->env, ARM_FEATURE_PMU);
 221     cpu->midr = 0x410fd083;
 222     cpu->revidr = 0x00000000;
 223     cpu->reset_fpsid = 0x41034080;
 224     cpu->isar.mvfr0 = 0x10110222;
 225     cpu->isar.mvfr1 = 0x12111111;
 226     cpu->isar.mvfr2 = 0x00000043;
 227     cpu->ctr = 0x8444c004;
 228     cpu->reset_sctlr = 0x00c50838;
 229     cpu->id_pfr0 = 0x00000131;
 230     cpu->id_pfr1 = 0x00011011;
 231     cpu->id_dfr0 = 0x03010066;
 232     cpu->id_afr0 = 0x00000000;
 233     cpu->id_mmfr0 = 0x10201105;
 234     cpu->id_mmfr1 = 0x40000000;
 235     cpu->id_mmfr2 = 0x01260000;
 236     cpu->id_mmfr3 = 0x02102211;
 237     cpu->isar.id_isar0 = 0x02101110;
 238     cpu->isar.id_isar1 = 0x13112111;
 239     cpu->isar.id_isar2 = 0x21232042;
 240     cpu->isar.id_isar3 = 0x01112131;
 241     cpu->isar.id_isar4 = 0x00011142;
 242     cpu->isar.id_isar5 = 0x00011121;
 243     cpu->isar.id_aa64pfr0 = 0x00002222;
 244     cpu->id_aa64dfr0 = 0x10305106;
 245     cpu->isar.id_aa64isar0 = 0x00011120;
 246     cpu->isar.id_aa64mmfr0 = 0x00001124;
 247     cpu->dbgdidr = 0x3516d000;
 248     cpu->clidr = 0x0a200023;
 249     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 250     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 251     cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 252     cpu->dcz_blocksize = 4; /* 64 bytes */
 253     cpu->gic_num_lrs = 4;
 254     cpu->gic_vpribits = 5;
 255     cpu->gic_vprebits = 5;
 256     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 257 }
 258
 259 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 260 {
 261     /*
 262      * If any vector lengths are explicitly enabled with sve<N> properties,
 263      * then all other lengths are implicitly disabled.  If sve-max-vq is
 264      * specified then it is the same as explicitly enabling all lengths
 265      * up to and including the specified maximum, which means all larger
 266      * lengths will be implicitly disabled.  If no sve<N> properties
 267      * are enabled and sve-max-vq is not specified, then all lengths not
 268      * explicitly disabled will be enabled.  Additionally, all power-of-two
 269      * vector lengths less than the maximum enabled length will be
 270      * automatically enabled and all vector lengths larger than the largest
 271      * disabled power-of-two vector length will be automatically disabled.
 272      * Errors are generated if the user provided input that interferes with
 273      * any of the above.  Finally, if SVE is not disabled, then at least one
 274      * vector length must be enabled.
 275      */
 276     DECLARE_BITMAP(tmp, ARM_MAX_VQ);
 277     uint32_t vq, max_vq = 0;
 278
 279     /*
 280      * Process explicit sve<N> properties.
 281      * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
 282      * Check first for any sve<N> enabled.
 283      */
 284     if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
 285         max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
 286
 287         if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
 288             error_setg(errp, "cannot enable sve%d", max_vq * 128);
 289             error_append_hint(errp, "sve%d is larger than the maximum vector "
 290                               "length, sve-max-vq=%d (%d bits)\n",
 291                               max_vq * 128, cpu->sve_max_vq,
 292                               cpu->sve_max_vq * 128);
 293             return;
 294         }
 295
 296         /* Propagate enabled bits down through required powers-of-two. */
 297         for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 298             if (!test_bit(vq - 1, cpu->sve_vq_init)) {
 299                 set_bit(vq - 1, cpu->sve_vq_map);
 300             }
 301         }
 302     } else if (cpu->sve_max_vq == 0) {
 303         /*
 304          * No explicit bits enabled, and no implicit bits from sve-max-vq.
 305          */
 306         if (!cpu_isar_feature(aa64_sve, cpu)) {
 307             /* SVE is disabled and so are all vector lengths.  Good. */
 308             return;
 309         }
 310
 311         /* Disabling a power-of-two disables all larger lengths. */
 312         if (test_bit(0, cpu->sve_vq_init)) {
 313             error_setg(errp, "cannot disable sve128");
 314             error_append_hint(errp, "Disabling sve128 results in all vector "
 315                               "lengths being disabled.\n");
 316             error_append_hint(errp, "With SVE enabled, at least one vector "
 317                               "length must be enabled.\n");
 318             return;
 319         }
 320         for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
 321             if (test_bit(vq - 1, cpu->sve_vq_init)) {
 322                 break;
 323             }
 324         }
 325         max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 326
 327         bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
 328         max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
 329     }
 330
 331     /*
 332      * Process the sve-max-vq property.
 333      * Note that we know from the above that no bit above
 334      * sve-max-vq is currently set.
 335      */
 336     if (cpu->sve_max_vq != 0) {
 337         max_vq = cpu->sve_max_vq;
 338
 339         if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
 340             test_bit(max_vq - 1, cpu->sve_vq_init)) {
 341             error_setg(errp, "cannot disable sve%d", max_vq * 128);
 342             error_append_hint(errp, "The maximum vector length must be "
 343                               "enabled, sve-max-vq=%d (%d bits)\n",
 344                               max_vq, max_vq * 128);
 345             return;
 346         }
 347
 348         /* Set all bits not explicitly set within sve-max-vq. */
 349         bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
 350         bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
 351     }
 352
 353     /*
 354      * We should know what max-vq is now.  Also, as we're done
 355      * manipulating sve-vq-map, we ensure any bits above max-vq
 356      * are clear, just in case anybody looks.
 357      */
 358     assert(max_vq != 0);
 359     bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
 360
 361     /* Ensure all required powers-of-two are enabled. */
 362     for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 363         if (!test_bit(vq - 1, cpu->sve_vq_map)) {
 364             error_setg(errp, "cannot disable sve%d", vq * 128);
 365             error_append_hint(errp, "sve%d is required as it "
 366                               "is a power-of-two length smaller than "
 367                               "the maximum, sve%d\n",
 368                               vq * 128, max_vq * 128);
 369             return;
 370         }
 371     }
 372
 373     /*
 374      * Now that we validated all our vector lengths, the only question
 375      * left to answer is if we even want SVE at all.
 376      */
 377     if (!cpu_isar_feature(aa64_sve, cpu)) {
 378         error_setg(errp, "cannot enable sve%d", max_vq * 128);
 379         error_append_hint(errp, "SVE must be enabled to enable vector "
 380                           "lengths.\n");
 381         error_append_hint(errp, "Add sve=on to the CPU property list.\n");
 382         return;
 383     }
 384
 385     /* From now on sve_max_vq is the actual maximum supported length. */
 386     cpu->sve_max_vq = max_vq;
 387 }
 388
 389 uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
 390 {
 391     uint32_t bitnum;
 392
 393     /*
 394      * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
 395      * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
 396      * function always returns the next smaller than the input.
 397      */
 398     assert(vq && vq <= ARM_MAX_VQ + 1);
 399
 400     bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
 401     return bitnum == vq - 1 ? 0 : bitnum + 1;
 402 }
 403
 404 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
 405                                    void *opaque, Error **errp)
 406 {
 407     ARMCPU *cpu = ARM_CPU(obj);
 408     uint32_t value;
 409
 410     /* All vector lengths are disabled when SVE is off. */
 411     if (!cpu_isar_feature(aa64_sve, cpu)) {
 412         value = 0;
 413     } else {
 414         value = cpu->sve_max_vq;
 415     }
 416     visit_type_uint32(v, name, &value, errp);
 417 }
 418
 419 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
 420                                    void *opaque, Error **errp)
 421 {
 422     ARMCPU *cpu = ARM_CPU(obj);
 423     Error *err = NULL;
 424
 425     visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 426
 427     if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
 428         error_setg(&err, "unsupported SVE vector length");
 429         error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
 430                           ARM_MAX_VQ);
 431     }
 432     error_propagate(errp, err);
 433 }
 434
 435 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
 436                                void *opaque, Error **errp)
 437 {
 438     ARMCPU *cpu = ARM_CPU(obj);
 439     uint32_t vq = atoi(&name[3]) / 128;
 440     bool value;
 441
 442     /* All vector lengths are disabled when SVE is off. */
 443     if (!cpu_isar_feature(aa64_sve, cpu)) {
 444         value = false;
 445     } else {
 446         value = test_bit(vq - 1, cpu->sve_vq_map);
 447     }
 448     visit_type_bool(v, name, &value, errp);
 449 }
 450
 451 static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
 452                                void *opaque, Error **errp)
 453 {
 454     ARMCPU *cpu = ARM_CPU(obj);
 455     uint32_t vq = atoi(&name[3]) / 128;
 456     Error *err = NULL;
 457     bool value;
 458
 459     visit_type_bool(v, name, &value, &err);
 460     if (err) {
 461         error_propagate(errp, err);
 462         return;
 463     }
 464
 465     if (value) {
 466         set_bit(vq - 1, cpu->sve_vq_map);
 467     } else {
 468         clear_bit(vq - 1, cpu->sve_vq_map);
 469     }
 470     set_bit(vq - 1, cpu->sve_vq_init);
 471 }
 472
 473 static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
 474                             void *opaque, Error **errp)
 475 {
 476     ARMCPU *cpu = ARM_CPU(obj);
 477     bool value = cpu_isar_feature(aa64_sve, cpu);
 478
 479     visit_type_bool(v, name, &value, errp);
 480 }
 481
 482 static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
 483                             void *opaque, Error **errp)
 484 {
 485     ARMCPU *cpu = ARM_CPU(obj);
 486     Error *err = NULL;
 487     bool value;
 488     uint64_t t;
 489
 490     visit_type_bool(v, name, &value, &err);
 491     if (err) {
 492         error_propagate(errp, err);
 493         return;
 494     }
 495
 496     if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
 497         error_setg(errp, "'sve' feature not supported by KVM on this host");
 498         return;
 499     }
 500
 501     t = cpu->isar.id_aa64pfr0;
 502     t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
 503     cpu->isar.id_aa64pfr0 = t;
 504 }
 505
 506 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 507  * otherwise, a CPU with as many features enabled as our emulation supports.
 508  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
 509  * this only needs to handle 64 bits.
 510  */
 511 static void aarch64_max_initfn(Object *obj)
 512 {
 513     ARMCPU *cpu = ARM_CPU(obj);
 514     uint32_t vq;
 515     uint64_t t;
 516
 517     if (kvm_enabled()) {
 518         kvm_arm_set_cpu_features_from_host(cpu);
 519         if (kvm_arm_sve_supported(CPU(cpu))) {
 520             t = cpu->isar.id_aa64pfr0;
 521             t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 522             cpu->isar.id_aa64pfr0 = t;
 523         }
 524     } else {
 525         uint32_t u;
 526         aarch64_a57_initfn(obj);
 527
 528         /*
 529          * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
 530          * one and try to apply errata workarounds or use impdef features we
 531          * don't provide.
 532          * An IMPLEMENTER field of 0 means "reserved for software use";
 533          * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
 534          * to see which features are present";
 535          * the VARIANT, PARTNUM and REVISION fields are all implementation
 536          * defined and we choose to define PARTNUM just in case guest
 537          * code needs to distinguish this QEMU CPU from other software
 538          * implementations, though this shouldn't be needed.
 539          */
 540         t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
 541         t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
 542         t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
 543         t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
 544         t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
 545         cpu->midr = t;
 546
 547         t = cpu->isar.id_aa64isar0;
 548         t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
 549         t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
 550         t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
 551         t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 552         t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 553         t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 554         t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 555         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 556         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 557         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 558         t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
 559         t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 560         t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
 561         cpu->isar.id_aa64isar0 = t;
 562
 563         t = cpu->isar.id_aa64isar1;
 564         t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
 565         t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 566         t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
 567         t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
 568         t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
 569         t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
 570         t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 571         t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 572         t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 573         cpu->isar.id_aa64isar1 = t;
 574
 575         t = cpu->isar.id_aa64pfr0;
 576         t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 577         t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 578         t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 579         cpu->isar.id_aa64pfr0 = t;
 580
 581         t = cpu->isar.id_aa64pfr1;
 582         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
 583         cpu->isar.id_aa64pfr1 = t;
 584
 585         t = cpu->isar.id_aa64mmfr1;
 586         t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
 587         t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
 588         cpu->isar.id_aa64mmfr1 = t;
 589
 590         /* Replicate the same data to the 32-bit id registers.  */
 591         u = cpu->isar.id_isar5;
 592         u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
 593         u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
 594         u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
 595         u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
 596         u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
 597         u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
 598         cpu->isar.id_isar5 = u;
 599
 600         u = cpu->isar.id_isar6;
 601         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
 602         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 603         u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
 604         u = FIELD_DP32(u, ID_ISAR6, SB, 1);
 605         u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
 606         cpu->isar.id_isar6 = u;
 607
 608         /*
 609          * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
 610          * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,
 611          * but it is also not legal to enable SVE without support for FP16,
 612          * and enabling SVE in system mode is more useful in the short term.
 613          */
 614
 615 #ifdef CONFIG_USER_ONLY
 616         /* For usermode -cpu max we can use a larger and more efficient DCZ
 617          * blocksize since we don't have to follow what the hardware does.
 618          */
 619         cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 620         cpu->dcz_blocksize = 7; /*  512 bytes */
 621 #endif
 622
 623         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
 624                             cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 625
 626         for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 627             char name[8];
 628             sprintf(name, "sve%d", vq * 128);
 629             object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 630                                 cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 631         }
 632     }
 633
 634     object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 635                         cpu_arm_set_sve, NULL, NULL, &error_fatal);
 636 }
 637
 638 struct ARMCPUInfo {
 639     const char *name;
 640     void (*initfn)(Object *obj);
 641     void (*class_init)(ObjectClass *oc, void *data);
 642 };
 643
 644 static const ARMCPUInfo aarch64_cpus[] = {
 645     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 646     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 647     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
 648     { .name = "max",                .initfn = aarch64_max_initfn },
 649     { .name = NULL }
 650 };
 651
 652 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 653 {
 654     ARMCPU *cpu = ARM_CPU(obj);
 655
 656     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 657 }
 658
 659 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 660 {
 661     ARMCPU *cpu = ARM_CPU(obj);
 662
 663     /* At this time, this property is only allowed if KVM is enabled.  This
 664      * restriction allows us to avoid fixing up functionality that assumes a
 665      * uniform execution state like do_interrupt.
 666      */
 667     if (value == false) {
 668         if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
 669             error_setg(errp, "'aarch64' feature cannot be disabled "
 670                              "unless KVM is enabled and 32-bit EL1 "
 671                              "is supported");
 672             return;
 673         }
 674         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 675     } else {
 676         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 677     }
 678 }
 679
 680 static void aarch64_cpu_initfn(Object *obj)
 681 {
 682     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 683                              aarch64_cpu_set_aarch64, NULL);
 684     object_property_set_description(obj, "aarch64",
 685                                     "Set on/off to enable/disable aarch64 "
 686                                     "execution state ",
 687                                     NULL);
 688 }
 689
 690 static void aarch64_cpu_finalizefn(Object *obj)
 691 {
 692 }
 693
 694 static gchar *aarch64_gdb_arch_name(CPUState *cs)
 695 {
 696     return g_strdup("aarch64");
 697 }
 698
 699 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 700 {
 701     CPUClass *cc = CPU_CLASS(oc);
 702
 703     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 704     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 705     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 706     cc->gdb_num_core_regs = 34;
 707     cc->gdb_core_xml_file = "aarch64-core.xml";
 708     cc->gdb_arch_name = aarch64_gdb_arch_name;
 709 }
 710
 711 static void aarch64_cpu_instance_init(Object *obj)
 712 {
 713     ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
 714
 715     acc->info->initfn(obj);
 716     arm_cpu_post_init(obj);
 717 }
 718
 719 static void cpu_register_class_init(ObjectClass *oc, void *data)
 720 {
 721     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 722
 723     acc->info = data;
 724 }
 725
 726 static void aarch64_cpu_register(const ARMCPUInfo *info)
 727 {
 728     TypeInfo type_info = {
 729         .parent = TYPE_AARCH64_CPU,
 730         .instance_size = sizeof(ARMCPU),
 731         .instance_init = aarch64_cpu_instance_init,
 732         .class_size = sizeof(ARMCPUClass),
 733         .class_init = info->class_init ?: cpu_register_class_init,
 734         .class_data = (void *)info,
 735     };
 736
 737     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 738     type_register(&type_info);
 739     g_free((void *)type_info.name);
 740 }
 741
 742 static const TypeInfo aarch64_cpu_type_info = {
 743     .name = TYPE_AARCH64_CPU,
 744     .parent = TYPE_ARM_CPU,
 745     .instance_size = sizeof(ARMCPU),
 746     .instance_init = aarch64_cpu_initfn,
 747     .instance_finalize = aarch64_cpu_finalizefn,
 748     .abstract = true,
 749     .class_size = sizeof(AArch64CPUClass),
 750     .class_init = aarch64_cpu_class_init,
 751 };
 752
 753 static void aarch64_cpu_register_types(void)
 754 {
 755     const ARMCPUInfo *info = aarch64_cpus;
 756
 757     type_register_static(&aarch64_cpu_type_info);
 758
 759     while (info->name) {
 760         aarch64_cpu_register(info);
 761         info++;
 762     }
 763 }
 764
 765 type_init(aarch64_cpu_register_types)