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*_run_on_cpu: introduce run_on_cpu_data type
[qemu/ar7.git] / hw / ppc / spapr.c
blob91989f028bcaf2ed1f94557dd977574117bdc77c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static XICSState *try_create_xics(const char *type, int nr_servers,
100 int nr_irqs, Error **errp)
101 {
102 Error *err = NULL;
103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
112 return NULL;
113 }
114 return XICS_COMMON(dev);
115 }
116
117 static XICSState *xics_system_init(MachineState *machine,
118 int nr_servers, int nr_irqs, Error **errp)
119 {
120 XICSState *xics = NULL;
121
122 if (kvm_enabled()) {
123 Error *err = NULL;
124
125 if (machine_kernel_irqchip_allowed(machine)) {
126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
128 }
129 if (machine_kernel_irqchip_required(machine) && !xics) {
130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
134 }
135 }
136
137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
139 }
140
141 return xics;
142 }
143
144 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146 {
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
152 if (cpu->cpu_version) {
153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
154 if (ret < 0) {
155 return ret;
156 }
157 }
158
159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175 }
176
177 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178 {
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196 }
197
198 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
199 {
200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
205
206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
245 ppc_get_compat_smt_threads(cpu));
246 if (ret < 0) {
247 return ret;
248 }
249 }
250 return ret;
251 }
252
253 static hwaddr spapr_node0_size(void)
254 {
255 MachineState *machine = MACHINE(qdev_get_machine());
256
257 if (nb_numa_nodes) {
258 int i;
259 for (i = 0; i < nb_numa_nodes; ++i) {
260 if (numa_info[i].node_mem) {
261 return MIN(pow2floor(numa_info[i].node_mem),
262 machine->ram_size);
263 }
264 }
265 }
266 return machine->ram_size;
267 }
268
269 static void add_str(GString *s, const gchar *s1)
270 {
271 g_string_append_len(s, s1, strlen(s1) + 1);
272 }
273
274 static void *spapr_create_fdt_skel(hwaddr initrd_base,
275 hwaddr initrd_size,
276 hwaddr kernel_size,
277 bool little_endian,
278 const char *kernel_cmdline,
279 uint32_t epow_irq)
280 {
281 void *fdt;
282 uint32_t start_prop = cpu_to_be32(initrd_base);
283 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
284 GString *hypertas = g_string_sized_new(256);
285 GString *qemu_hypertas = g_string_sized_new(256);
286 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
287 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
288 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
289 char *buf;
290
291 add_str(hypertas, "hcall-pft");
292 add_str(hypertas, "hcall-term");
293 add_str(hypertas, "hcall-dabr");
294 add_str(hypertas, "hcall-interrupt");
295 add_str(hypertas, "hcall-tce");
296 add_str(hypertas, "hcall-vio");
297 add_str(hypertas, "hcall-splpar");
298 add_str(hypertas, "hcall-bulk");
299 add_str(hypertas, "hcall-set-mode");
300 add_str(hypertas, "hcall-sprg0");
301 add_str(hypertas, "hcall-copy");
302 add_str(hypertas, "hcall-debug");
303 add_str(qemu_hypertas, "hcall-memop1");
304
305 fdt = g_malloc0(FDT_MAX_SIZE);
306 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
307
308 if (kernel_size) {
309 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
310 }
311 if (initrd_size) {
312 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
313 }
314 _FDT((fdt_finish_reservemap(fdt)));
315
316 /* Root node */
317 _FDT((fdt_begin_node(fdt, "")));
318 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
319 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
320 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
321
322 /*
323 * Add info to guest to indentify which host is it being run on
324 * and what is the uuid of the guest
325 */
326 if (kvmppc_get_host_model(&buf)) {
327 _FDT((fdt_property_string(fdt, "host-model", buf)));
328 g_free(buf);
329 }
330 if (kvmppc_get_host_serial(&buf)) {
331 _FDT((fdt_property_string(fdt, "host-serial", buf)));
332 g_free(buf);
333 }
334
335 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
336
337 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
338 if (qemu_uuid_set) {
339 _FDT((fdt_property_string(fdt, "system-id", buf)));
340 }
341 g_free(buf);
342
343 if (qemu_get_vm_name()) {
344 _FDT((fdt_property_string(fdt, "ibm,partition-name",
345 qemu_get_vm_name())));
346 }
347
348 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
349 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
350
351 /* /chosen */
352 _FDT((fdt_begin_node(fdt, "chosen")));
353
354 /* Set Form1_affinity */
355 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
356
357 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
358 _FDT((fdt_property(fdt, "linux,initrd-start",
359 &start_prop, sizeof(start_prop))));
360 _FDT((fdt_property(fdt, "linux,initrd-end",
361 &end_prop, sizeof(end_prop))));
362 if (kernel_size) {
363 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
364 cpu_to_be64(kernel_size) };
365
366 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
367 if (little_endian) {
368 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
369 }
370 }
371 if (boot_menu) {
372 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
373 }
374 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
375 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
376 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
377
378 _FDT((fdt_end_node(fdt)));
379
380 /* RTAS */
381 _FDT((fdt_begin_node(fdt, "rtas")));
382
383 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
384 add_str(hypertas, "hcall-multi-tce");
385 }
386 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
387 hypertas->len)));
388 g_string_free(hypertas, TRUE);
389 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
390 qemu_hypertas->len)));
391 g_string_free(qemu_hypertas, TRUE);
392
393 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
394 refpoints, sizeof(refpoints))));
395
396 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
397 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
398 RTAS_EVENT_SCAN_RATE)));
399
400 if (msi_nonbroken) {
401 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
402 }
403
404 /*
405 * According to PAPR, rtas ibm,os-term does not guarantee a return
406 * back to the guest cpu.
407 *
408 * While an additional ibm,extended-os-term property indicates that
409 * rtas call return will always occur. Set this property.
410 */
411 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
412
413 _FDT((fdt_end_node(fdt)));
414
415 /* interrupt controller */
416 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
417
418 _FDT((fdt_property_string(fdt, "device_type",
419 "PowerPC-External-Interrupt-Presentation")));
420 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
421 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
422 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
423 interrupt_server_ranges_prop,
424 sizeof(interrupt_server_ranges_prop))));
425 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
426 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
427 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
428
429 _FDT((fdt_end_node(fdt)));
430
431 /* vdevice */
432 _FDT((fdt_begin_node(fdt, "vdevice")));
433
434 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
435 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
436 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
437 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
438 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
439 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
440
441 _FDT((fdt_end_node(fdt)));
442
443 /* event-sources */
444 spapr_events_fdt_skel(fdt, epow_irq);
445
446 /* /hypervisor node */
447 if (kvm_enabled()) {
448 uint8_t hypercall[16];
449
450 /* indicate KVM hypercall interface */
451 _FDT((fdt_begin_node(fdt, "hypervisor")));
452 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
453 if (kvmppc_has_cap_fixup_hcalls()) {
454 /*
455 * Older KVM versions with older guest kernels were broken with the
456 * magic page, don't allow the guest to map it.
457 */
458 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
459 sizeof(hypercall))) {
460 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
461 sizeof(hypercall))));
462 }
463 }
464 _FDT((fdt_end_node(fdt)));
465 }
466
467 _FDT((fdt_end_node(fdt))); /* close root node */
468 _FDT((fdt_finish(fdt)));
469
470 return fdt;
471 }
472
473 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
474 hwaddr size)
475 {
476 uint32_t associativity[] = {
477 cpu_to_be32(0x4), /* length */
478 cpu_to_be32(0x0), cpu_to_be32(0x0),
479 cpu_to_be32(0x0), cpu_to_be32(nodeid)
480 };
481 char mem_name[32];
482 uint64_t mem_reg_property[2];
483 int off;
484
485 mem_reg_property[0] = cpu_to_be64(start);
486 mem_reg_property[1] = cpu_to_be64(size);
487
488 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
489 off = fdt_add_subnode(fdt, 0, mem_name);
490 _FDT(off);
491 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
492 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
493 sizeof(mem_reg_property))));
494 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
495 sizeof(associativity))));
496 return off;
497 }
498
499 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
500 {
501 MachineState *machine = MACHINE(spapr);
502 hwaddr mem_start, node_size;
503 int i, nb_nodes = nb_numa_nodes;
504 NodeInfo *nodes = numa_info;
505 NodeInfo ramnode;
506
507 /* No NUMA nodes, assume there is just one node with whole RAM */
508 if (!nb_numa_nodes) {
509 nb_nodes = 1;
510 ramnode.node_mem = machine->ram_size;
511 nodes = &ramnode;
512 }
513
514 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
515 if (!nodes[i].node_mem) {
516 continue;
517 }
518 if (mem_start >= machine->ram_size) {
519 node_size = 0;
520 } else {
521 node_size = nodes[i].node_mem;
522 if (node_size > machine->ram_size - mem_start) {
523 node_size = machine->ram_size - mem_start;
524 }
525 }
526 if (!mem_start) {
527 /* ppc_spapr_init() checks for rma_size <= node0_size already */
528 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
529 mem_start += spapr->rma_size;
530 node_size -= spapr->rma_size;
531 }
532 for ( ; node_size; ) {
533 hwaddr sizetmp = pow2floor(node_size);
534
535 /* mem_start != 0 here */
536 if (ctzl(mem_start) < ctzl(sizetmp)) {
537 sizetmp = 1ULL << ctzl(mem_start);
538 }
539
540 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
541 node_size -= sizetmp;
542 mem_start += sizetmp;
543 }
544 }
545
546 return 0;
547 }
548
549 /* Populate the "ibm,pa-features" property */
550 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
551 {
552 uint8_t pa_features_206[] = { 6, 0,
553 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
554 uint8_t pa_features_207[] = { 24, 0,
555 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
556 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
557 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
558 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
559 uint8_t *pa_features;
560 size_t pa_size;
561
562 switch (env->mmu_model) {
563 case POWERPC_MMU_2_06:
564 case POWERPC_MMU_2_06a:
565 pa_features = pa_features_206;
566 pa_size = sizeof(pa_features_206);
567 break;
568 case POWERPC_MMU_2_07:
569 case POWERPC_MMU_2_07a:
570 pa_features = pa_features_207;
571 pa_size = sizeof(pa_features_207);
572 break;
573 default:
574 return;
575 }
576
577 if (env->ci_large_pages) {
578 /*
579 * Note: we keep CI large pages off by default because a 64K capable
580 * guest provisioned with large pages might otherwise try to map a qemu
581 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
582 * even if that qemu runs on a 4k host.
583 * We dd this bit back here if we are confident this is not an issue
584 */
585 pa_features[3] |= 0x20;
586 }
587 if (kvmppc_has_cap_htm() && pa_size > 24) {
588 pa_features[24] |= 0x80; /* Transactional memory support */
589 }
590
591 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
592 }
593
594 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
595 sPAPRMachineState *spapr)
596 {
597 PowerPCCPU *cpu = POWERPC_CPU(cs);
598 CPUPPCState *env = &cpu->env;
599 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
600 int index = ppc_get_vcpu_dt_id(cpu);
601 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
602 0xffffffff, 0xffffffff};
603 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
604 : SPAPR_TIMEBASE_FREQ;
605 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
606 uint32_t page_sizes_prop[64];
607 size_t page_sizes_prop_size;
608 uint32_t vcpus_per_socket = smp_threads * smp_cores;
609 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
610 sPAPRDRConnector *drc;
611 sPAPRDRConnectorClass *drck;
612 int drc_index;
613
614 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
615 if (drc) {
616 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
617 drc_index = drck->get_index(drc);
618 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
619 }
620
621 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
622 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
623
624 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
625 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
626 env->dcache_line_size)));
627 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
628 env->dcache_line_size)));
629 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
630 env->icache_line_size)));
631 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
632 env->icache_line_size)));
633
634 if (pcc->l1_dcache_size) {
635 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
636 pcc->l1_dcache_size)));
637 } else {
638 error_report("Warning: Unknown L1 dcache size for cpu");
639 }
640 if (pcc->l1_icache_size) {
641 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
642 pcc->l1_icache_size)));
643 } else {
644 error_report("Warning: Unknown L1 icache size for cpu");
645 }
646
647 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
648 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
649 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
650 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
651 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
652 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
653
654 if (env->spr_cb[SPR_PURR].oea_read) {
655 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
656 }
657
658 if (env->mmu_model & POWERPC_MMU_1TSEG) {
659 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
660 segs, sizeof(segs))));
661 }
662
663 /* Advertise VMX/VSX (vector extensions) if available
664 * 0 / no property == no vector extensions
665 * 1 == VMX / Altivec available
666 * 2 == VSX available */
667 if (env->insns_flags & PPC_ALTIVEC) {
668 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
669
670 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
671 }
672
673 /* Advertise DFP (Decimal Floating Point) if available
674 * 0 / no property == no DFP
675 * 1 == DFP available */
676 if (env->insns_flags2 & PPC2_DFP) {
677 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
678 }
679
680 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
681 sizeof(page_sizes_prop));
682 if (page_sizes_prop_size) {
683 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
684 page_sizes_prop, page_sizes_prop_size)));
685 }
686
687 spapr_populate_pa_features(env, fdt, offset);
688
689 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
690 cs->cpu_index / vcpus_per_socket)));
691
692 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
693 pft_size_prop, sizeof(pft_size_prop))));
694
695 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
696
697 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
698 ppc_get_compat_smt_threads(cpu)));
699 }
700
701 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
702 {
703 CPUState *cs;
704 int cpus_offset;
705 char *nodename;
706 int smt = kvmppc_smt_threads();
707
708 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
709 _FDT(cpus_offset);
710 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
711 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
712
713 /*
714 * We walk the CPUs in reverse order to ensure that CPU DT nodes
715 * created by fdt_add_subnode() end up in the right order in FDT
716 * for the guest kernel the enumerate the CPUs correctly.
717 */
718 CPU_FOREACH_REVERSE(cs) {
719 PowerPCCPU *cpu = POWERPC_CPU(cs);
720 int index = ppc_get_vcpu_dt_id(cpu);
721 DeviceClass *dc = DEVICE_GET_CLASS(cs);
722 int offset;
723
724 if ((index % smt) != 0) {
725 continue;
726 }
727
728 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
729 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
730 g_free(nodename);
731 _FDT(offset);
732 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
733 }
734
735 }
736
737 /*
738 * Adds ibm,dynamic-reconfiguration-memory node.
739 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
740 * of this device tree node.
741 */
742 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
743 {
744 MachineState *machine = MACHINE(spapr);
745 int ret, i, offset;
746 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
747 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
748 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
749 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
750 memory_region_size(&spapr->hotplug_memory.mr)) /
751 lmb_size;
752 uint32_t *int_buf, *cur_index, buf_len;
753 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
754
755 /*
756 * Don't create the node if there is no hotpluggable memory
757 */
758 if (machine->ram_size == machine->maxram_size) {
759 return 0;
760 }
761
762 /*
763 * Allocate enough buffer size to fit in ibm,dynamic-memory
764 * or ibm,associativity-lookup-arrays
765 */
766 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
767 * sizeof(uint32_t);
768 cur_index = int_buf = g_malloc0(buf_len);
769
770 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
771
772 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
773 sizeof(prop_lmb_size));
774 if (ret < 0) {
775 goto out;
776 }
777
778 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
779 if (ret < 0) {
780 goto out;
781 }
782
783 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
784 if (ret < 0) {
785 goto out;
786 }
787
788 /* ibm,dynamic-memory */
789 int_buf[0] = cpu_to_be32(nr_lmbs);
790 cur_index++;
791 for (i = 0; i < nr_lmbs; i++) {
792 uint64_t addr = i * lmb_size;
793 uint32_t *dynamic_memory = cur_index;
794
795 if (i >= hotplug_lmb_start) {
796 sPAPRDRConnector *drc;
797 sPAPRDRConnectorClass *drck;
798
799 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
800 g_assert(drc);
801 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
802
803 dynamic_memory[0] = cpu_to_be32(addr >> 32);
804 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
805 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
806 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
807 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
808 if (memory_region_present(get_system_memory(), addr)) {
809 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
810 } else {
811 dynamic_memory[5] = cpu_to_be32(0);
812 }
813 } else {
814 /*
815 * LMB information for RMA, boot time RAM and gap b/n RAM and
816 * hotplug memory region -- all these are marked as reserved
817 * and as having no valid DRC.
818 */
819 dynamic_memory[0] = cpu_to_be32(addr >> 32);
820 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
821 dynamic_memory[2] = cpu_to_be32(0);
822 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
823 dynamic_memory[4] = cpu_to_be32(-1);
824 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
825 SPAPR_LMB_FLAGS_DRC_INVALID);
826 }
827
828 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
829 }
830 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
831 if (ret < 0) {
832 goto out;
833 }
834
835 /* ibm,associativity-lookup-arrays */
836 cur_index = int_buf;
837 int_buf[0] = cpu_to_be32(nr_nodes);
838 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
839 cur_index += 2;
840 for (i = 0; i < nr_nodes; i++) {
841 uint32_t associativity[] = {
842 cpu_to_be32(0x0),
843 cpu_to_be32(0x0),
844 cpu_to_be32(0x0),
845 cpu_to_be32(i)
846 };
847 memcpy(cur_index, associativity, sizeof(associativity));
848 cur_index += 4;
849 }
850 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
851 (cur_index - int_buf) * sizeof(uint32_t));
852 out:
853 g_free(int_buf);
854 return ret;
855 }
856
857 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
858 target_ulong addr, target_ulong size,
859 bool cpu_update, bool memory_update)
860 {
861 void *fdt, *fdt_skel;
862 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
863 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
864
865 size -= sizeof(hdr);
866
867 /* Create sceleton */
868 fdt_skel = g_malloc0(size);
869 _FDT((fdt_create(fdt_skel, size)));
870 _FDT((fdt_begin_node(fdt_skel, "")));
871 _FDT((fdt_end_node(fdt_skel)));
872 _FDT((fdt_finish(fdt_skel)));
873 fdt = g_malloc0(size);
874 _FDT((fdt_open_into(fdt_skel, fdt, size)));
875 g_free(fdt_skel);
876
877 /* Fixup cpu nodes */
878 if (cpu_update) {
879 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
880 }
881
882 /* Generate ibm,dynamic-reconfiguration-memory node if required */
883 if (memory_update && smc->dr_lmb_enabled) {
884 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
885 }
886
887 /* Pack resulting tree */
888 _FDT((fdt_pack(fdt)));
889
890 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
891 trace_spapr_cas_failed(size);
892 return -1;
893 }
894
895 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
896 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
897 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
898 g_free(fdt);
899
900 return 0;
901 }
902
903 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
904 hwaddr fdt_addr,
905 hwaddr rtas_addr,
906 hwaddr rtas_size)
907 {
908 MachineState *machine = MACHINE(qdev_get_machine());
909 MachineClass *mc = MACHINE_GET_CLASS(machine);
910 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
911 const char *boot_device = machine->boot_order;
912 int ret, i;
913 size_t cb = 0;
914 char *bootlist;
915 void *fdt;
916 sPAPRPHBState *phb;
917
918 fdt = g_malloc(FDT_MAX_SIZE);
919
920 /* open out the base tree into a temp buffer for the final tweaks */
921 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
922
923 ret = spapr_populate_memory(spapr, fdt);
924 if (ret < 0) {
925 error_report("couldn't setup memory nodes in fdt");
926 exit(1);
927 }
928
929 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
930 if (ret < 0) {
931 error_report("couldn't setup vio devices in fdt");
932 exit(1);
933 }
934
935 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
936 ret = spapr_rng_populate_dt(fdt);
937 if (ret < 0) {
938 error_report("could not set up rng device in the fdt");
939 exit(1);
940 }
941 }
942
943 QLIST_FOREACH(phb, &spapr->phbs, list) {
944 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
945 if (ret < 0) {
946 error_report("couldn't setup PCI devices in fdt");
947 exit(1);
948 }
949 }
950
951 /* RTAS */
952 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
953 if (ret < 0) {
954 error_report("Couldn't set up RTAS device tree properties");
955 }
956
957 /* cpus */
958 spapr_populate_cpus_dt_node(fdt, spapr);
959
960 bootlist = get_boot_devices_list(&cb, true);
961 if (cb && bootlist) {
962 int offset = fdt_path_offset(fdt, "/chosen");
963 if (offset < 0) {
964 exit(1);
965 }
966 for (i = 0; i < cb; i++) {
967 if (bootlist[i] == '\n') {
968 bootlist[i] = ' ';
969 }
970
971 }
972 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
973 }
974
975 if (boot_device && strlen(boot_device)) {
976 int offset = fdt_path_offset(fdt, "/chosen");
977
978 if (offset < 0) {
979 exit(1);
980 }
981 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
982 }
983
984 if (!spapr->has_graphics) {
985 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
986 }
987
988 if (smc->dr_lmb_enabled) {
989 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
990 }
991
992 if (mc->query_hotpluggable_cpus) {
993 int offset = fdt_path_offset(fdt, "/cpus");
994 ret = spapr_drc_populate_dt(fdt, offset, NULL,
995 SPAPR_DR_CONNECTOR_TYPE_CPU);
996 if (ret < 0) {
997 error_report("Couldn't set up CPU DR device tree properties");
998 exit(1);
999 }
1000 }
1001
1002 _FDT((fdt_pack(fdt)));
1003
1004 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1005 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1006 fdt_totalsize(fdt), FDT_MAX_SIZE);
1007 exit(1);
1008 }
1009
1010 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1011 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1012
1013 g_free(bootlist);
1014 g_free(fdt);
1015 }
1016
1017 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1018 {
1019 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1020 }
1021
1022 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1023 {
1024 CPUPPCState *env = &cpu->env;
1025
1026 if (msr_pr) {
1027 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1028 env->gpr[3] = H_PRIVILEGE;
1029 } else {
1030 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1031 }
1032 }
1033
1034 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1035 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1036 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1037 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1038 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1039
1040 /*
1041 * Get the fd to access the kernel htab, re-opening it if necessary
1042 */
1043 static int get_htab_fd(sPAPRMachineState *spapr)
1044 {
1045 if (spapr->htab_fd >= 0) {
1046 return spapr->htab_fd;
1047 }
1048
1049 spapr->htab_fd = kvmppc_get_htab_fd(false);
1050 if (spapr->htab_fd < 0) {
1051 error_report("Unable to open fd for reading hash table from KVM: %s",
1052 strerror(errno));
1053 }
1054
1055 return spapr->htab_fd;
1056 }
1057
1058 static void close_htab_fd(sPAPRMachineState *spapr)
1059 {
1060 if (spapr->htab_fd >= 0) {
1061 close(spapr->htab_fd);
1062 }
1063 spapr->htab_fd = -1;
1064 }
1065
1066 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1067 {
1068 int shift;
1069
1070 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1071 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1072 * that's much more than is needed for Linux guests */
1073 shift = ctz64(pow2ceil(ramsize)) - 7;
1074 shift = MAX(shift, 18); /* Minimum architected size */
1075 shift = MIN(shift, 46); /* Maximum architected size */
1076 return shift;
1077 }
1078
1079 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1080 Error **errp)
1081 {
1082 long rc;
1083
1084 /* Clean up any HPT info from a previous boot */
1085 g_free(spapr->htab);
1086 spapr->htab = NULL;
1087 spapr->htab_shift = 0;
1088 close_htab_fd(spapr);
1089
1090 rc = kvmppc_reset_htab(shift);
1091 if (rc < 0) {
1092 /* kernel-side HPT needed, but couldn't allocate one */
1093 error_setg_errno(errp, errno,
1094 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1095 shift);
1096 /* This is almost certainly fatal, but if the caller really
1097 * wants to carry on with shift == 0, it's welcome to try */
1098 } else if (rc > 0) {
1099 /* kernel-side HPT allocated */
1100 if (rc != shift) {
1101 error_setg(errp,
1102 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1103 shift, rc);
1104 }
1105
1106 spapr->htab_shift = shift;
1107 spapr->htab = NULL;
1108 } else {
1109 /* kernel-side HPT not needed, allocate in userspace instead */
1110 size_t size = 1ULL << shift;
1111 int i;
1112
1113 spapr->htab = qemu_memalign(size, size);
1114 if (!spapr->htab) {
1115 error_setg_errno(errp, errno,
1116 "Could not allocate HPT of order %d", shift);
1117 return;
1118 }
1119
1120 memset(spapr->htab, 0, size);
1121 spapr->htab_shift = shift;
1122
1123 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1124 DIRTY_HPTE(HPTE(spapr->htab, i));
1125 }
1126 }
1127 }
1128
1129 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1130 {
1131 bool matched = false;
1132
1133 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1134 matched = true;
1135 }
1136
1137 if (!matched) {
1138 error_report("Device %s is not supported by this machine yet.",
1139 qdev_fw_name(DEVICE(sbdev)));
1140 exit(1);
1141 }
1142 }
1143
1144 static void ppc_spapr_reset(void)
1145 {
1146 MachineState *machine = MACHINE(qdev_get_machine());
1147 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1148 PowerPCCPU *first_ppc_cpu;
1149 uint32_t rtas_limit;
1150
1151 /* Check for unknown sysbus devices */
1152 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1153
1154 /* Allocate and/or reset the hash page table */
1155 spapr_reallocate_hpt(spapr,
1156 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1157 &error_fatal);
1158
1159 /* Update the RMA size if necessary */
1160 if (spapr->vrma_adjust) {
1161 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1162 spapr->htab_shift);
1163 }
1164
1165 qemu_devices_reset();
1166
1167 /*
1168 * We place the device tree and RTAS just below either the top of the RMA,
1169 * or just below 2GB, whichever is lowere, so that it can be
1170 * processed with 32-bit real mode code if necessary
1171 */
1172 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1173 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1174 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1175
1176 /* Load the fdt */
1177 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1178 spapr->rtas_size);
1179
1180 /* Copy RTAS over */
1181 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1182 spapr->rtas_size);
1183
1184 /* Set up the entry state */
1185 first_ppc_cpu = POWERPC_CPU(first_cpu);
1186 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1187 first_ppc_cpu->env.gpr[5] = 0;
1188 first_cpu->halted = 0;
1189 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1190
1191 }
1192
1193 static void spapr_create_nvram(sPAPRMachineState *spapr)
1194 {
1195 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1196 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1197
1198 if (dinfo) {
1199 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1200 &error_fatal);
1201 }
1202
1203 qdev_init_nofail(dev);
1204
1205 spapr->nvram = (struct sPAPRNVRAM *)dev;
1206 }
1207
1208 static void spapr_rtc_create(sPAPRMachineState *spapr)
1209 {
1210 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1211
1212 qdev_init_nofail(dev);
1213 spapr->rtc = dev;
1214
1215 object_property_add_alias(qdev_get_machine(), "rtc-time",
1216 OBJECT(spapr->rtc), "date", NULL);
1217 }
1218
1219 /* Returns whether we want to use VGA or not */
1220 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1221 {
1222 switch (vga_interface_type) {
1223 case VGA_NONE:
1224 return false;
1225 case VGA_DEVICE:
1226 return true;
1227 case VGA_STD:
1228 case VGA_VIRTIO:
1229 return pci_vga_init(pci_bus) != NULL;
1230 default:
1231 error_setg(errp,
1232 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1233 return false;
1234 }
1235 }
1236
1237 static int spapr_post_load(void *opaque, int version_id)
1238 {
1239 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1240 int err = 0;
1241
1242 /* In earlier versions, there was no separate qdev for the PAPR
1243 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1244 * So when migrating from those versions, poke the incoming offset
1245 * value into the RTC device */
1246 if (version_id < 3) {
1247 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1248 }
1249
1250 return err;
1251 }
1252
1253 static bool version_before_3(void *opaque, int version_id)
1254 {
1255 return version_id < 3;
1256 }
1257
1258 static const VMStateDescription vmstate_spapr = {
1259 .name = "spapr",
1260 .version_id = 3,
1261 .minimum_version_id = 1,
1262 .post_load = spapr_post_load,
1263 .fields = (VMStateField[]) {
1264 /* used to be @next_irq */
1265 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1266
1267 /* RTC offset */
1268 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1269
1270 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1271 VMSTATE_END_OF_LIST()
1272 },
1273 };
1274
1275 static int htab_save_setup(QEMUFile *f, void *opaque)
1276 {
1277 sPAPRMachineState *spapr = opaque;
1278
1279 /* "Iteration" header */
1280 qemu_put_be32(f, spapr->htab_shift);
1281
1282 if (spapr->htab) {
1283 spapr->htab_save_index = 0;
1284 spapr->htab_first_pass = true;
1285 } else {
1286 assert(kvm_enabled());
1287 }
1288
1289
1290 return 0;
1291 }
1292
1293 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1294 int64_t max_ns)
1295 {
1296 bool has_timeout = max_ns != -1;
1297 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1298 int index = spapr->htab_save_index;
1299 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1300
1301 assert(spapr->htab_first_pass);
1302
1303 do {
1304 int chunkstart;
1305
1306 /* Consume invalid HPTEs */
1307 while ((index < htabslots)
1308 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1309 index++;
1310 CLEAN_HPTE(HPTE(spapr->htab, index));
1311 }
1312
1313 /* Consume valid HPTEs */
1314 chunkstart = index;
1315 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1316 && HPTE_VALID(HPTE(spapr->htab, index))) {
1317 index++;
1318 CLEAN_HPTE(HPTE(spapr->htab, index));
1319 }
1320
1321 if (index > chunkstart) {
1322 int n_valid = index - chunkstart;
1323
1324 qemu_put_be32(f, chunkstart);
1325 qemu_put_be16(f, n_valid);
1326 qemu_put_be16(f, 0);
1327 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1328 HASH_PTE_SIZE_64 * n_valid);
1329
1330 if (has_timeout &&
1331 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1332 break;
1333 }
1334 }
1335 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1336
1337 if (index >= htabslots) {
1338 assert(index == htabslots);
1339 index = 0;
1340 spapr->htab_first_pass = false;
1341 }
1342 spapr->htab_save_index = index;
1343 }
1344
1345 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1346 int64_t max_ns)
1347 {
1348 bool final = max_ns < 0;
1349 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1350 int examined = 0, sent = 0;
1351 int index = spapr->htab_save_index;
1352 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1353
1354 assert(!spapr->htab_first_pass);
1355
1356 do {
1357 int chunkstart, invalidstart;
1358
1359 /* Consume non-dirty HPTEs */
1360 while ((index < htabslots)
1361 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1362 index++;
1363 examined++;
1364 }
1365
1366 chunkstart = index;
1367 /* Consume valid dirty HPTEs */
1368 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1369 && HPTE_DIRTY(HPTE(spapr->htab, index))
1370 && HPTE_VALID(HPTE(spapr->htab, index))) {
1371 CLEAN_HPTE(HPTE(spapr->htab, index));
1372 index++;
1373 examined++;
1374 }
1375
1376 invalidstart = index;
1377 /* Consume invalid dirty HPTEs */
1378 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1379 && HPTE_DIRTY(HPTE(spapr->htab, index))
1380 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1381 CLEAN_HPTE(HPTE(spapr->htab, index));
1382 index++;
1383 examined++;
1384 }
1385
1386 if (index > chunkstart) {
1387 int n_valid = invalidstart - chunkstart;
1388 int n_invalid = index - invalidstart;
1389
1390 qemu_put_be32(f, chunkstart);
1391 qemu_put_be16(f, n_valid);
1392 qemu_put_be16(f, n_invalid);
1393 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1394 HASH_PTE_SIZE_64 * n_valid);
1395 sent += index - chunkstart;
1396
1397 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1398 break;
1399 }
1400 }
1401
1402 if (examined >= htabslots) {
1403 break;
1404 }
1405
1406 if (index >= htabslots) {
1407 assert(index == htabslots);
1408 index = 0;
1409 }
1410 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1411
1412 if (index >= htabslots) {
1413 assert(index == htabslots);
1414 index = 0;
1415 }
1416
1417 spapr->htab_save_index = index;
1418
1419 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1420 }
1421
1422 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1423 #define MAX_KVM_BUF_SIZE 2048
1424
1425 static int htab_save_iterate(QEMUFile *f, void *opaque)
1426 {
1427 sPAPRMachineState *spapr = opaque;
1428 int fd;
1429 int rc = 0;
1430
1431 /* Iteration header */
1432 qemu_put_be32(f, 0);
1433
1434 if (!spapr->htab) {
1435 assert(kvm_enabled());
1436
1437 fd = get_htab_fd(spapr);
1438 if (fd < 0) {
1439 return fd;
1440 }
1441
1442 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1443 if (rc < 0) {
1444 return rc;
1445 }
1446 } else if (spapr->htab_first_pass) {
1447 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1448 } else {
1449 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1450 }
1451
1452 /* End marker */
1453 qemu_put_be32(f, 0);
1454 qemu_put_be16(f, 0);
1455 qemu_put_be16(f, 0);
1456
1457 return rc;
1458 }
1459
1460 static int htab_save_complete(QEMUFile *f, void *opaque)
1461 {
1462 sPAPRMachineState *spapr = opaque;
1463 int fd;
1464
1465 /* Iteration header */
1466 qemu_put_be32(f, 0);
1467
1468 if (!spapr->htab) {
1469 int rc;
1470
1471 assert(kvm_enabled());
1472
1473 fd = get_htab_fd(spapr);
1474 if (fd < 0) {
1475 return fd;
1476 }
1477
1478 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1479 if (rc < 0) {
1480 return rc;
1481 }
1482 } else {
1483 if (spapr->htab_first_pass) {
1484 htab_save_first_pass(f, spapr, -1);
1485 }
1486 htab_save_later_pass(f, spapr, -1);
1487 }
1488
1489 /* End marker */
1490 qemu_put_be32(f, 0);
1491 qemu_put_be16(f, 0);
1492 qemu_put_be16(f, 0);
1493
1494 return 0;
1495 }
1496
1497 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1498 {
1499 sPAPRMachineState *spapr = opaque;
1500 uint32_t section_hdr;
1501 int fd = -1;
1502
1503 if (version_id < 1 || version_id > 1) {
1504 error_report("htab_load() bad version");
1505 return -EINVAL;
1506 }
1507
1508 section_hdr = qemu_get_be32(f);
1509
1510 if (section_hdr) {
1511 Error *local_err = NULL;
1512
1513 /* First section gives the htab size */
1514 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1515 if (local_err) {
1516 error_report_err(local_err);
1517 return -EINVAL;
1518 }
1519 return 0;
1520 }
1521
1522 if (!spapr->htab) {
1523 assert(kvm_enabled());
1524
1525 fd = kvmppc_get_htab_fd(true);
1526 if (fd < 0) {
1527 error_report("Unable to open fd to restore KVM hash table: %s",
1528 strerror(errno));
1529 }
1530 }
1531
1532 while (true) {
1533 uint32_t index;
1534 uint16_t n_valid, n_invalid;
1535
1536 index = qemu_get_be32(f);
1537 n_valid = qemu_get_be16(f);
1538 n_invalid = qemu_get_be16(f);
1539
1540 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1541 /* End of Stream */
1542 break;
1543 }
1544
1545 if ((index + n_valid + n_invalid) >
1546 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1547 /* Bad index in stream */
1548 error_report(
1549 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1550 index, n_valid, n_invalid, spapr->htab_shift);
1551 return -EINVAL;
1552 }
1553
1554 if (spapr->htab) {
1555 if (n_valid) {
1556 qemu_get_buffer(f, HPTE(spapr->htab, index),
1557 HASH_PTE_SIZE_64 * n_valid);
1558 }
1559 if (n_invalid) {
1560 memset(HPTE(spapr->htab, index + n_valid), 0,
1561 HASH_PTE_SIZE_64 * n_invalid);
1562 }
1563 } else {
1564 int rc;
1565
1566 assert(fd >= 0);
1567
1568 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1569 if (rc < 0) {
1570 return rc;
1571 }
1572 }
1573 }
1574
1575 if (!spapr->htab) {
1576 assert(fd >= 0);
1577 close(fd);
1578 }
1579
1580 return 0;
1581 }
1582
1583 static void htab_cleanup(void *opaque)
1584 {
1585 sPAPRMachineState *spapr = opaque;
1586
1587 close_htab_fd(spapr);
1588 }
1589
1590 static SaveVMHandlers savevm_htab_handlers = {
1591 .save_live_setup = htab_save_setup,
1592 .save_live_iterate = htab_save_iterate,
1593 .save_live_complete_precopy = htab_save_complete,
1594 .cleanup = htab_cleanup,
1595 .load_state = htab_load,
1596 };
1597
1598 static void spapr_boot_set(void *opaque, const char *boot_device,
1599 Error **errp)
1600 {
1601 MachineState *machine = MACHINE(qdev_get_machine());
1602 machine->boot_order = g_strdup(boot_device);
1603 }
1604
1605 /*
1606 * Reset routine for LMB DR devices.
1607 *
1608 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1609 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1610 * when it walks all its children devices. LMB devices reset occurs
1611 * as part of spapr_ppc_reset().
1612 */
1613 static void spapr_drc_reset(void *opaque)
1614 {
1615 sPAPRDRConnector *drc = opaque;
1616 DeviceState *d = DEVICE(drc);
1617
1618 if (d) {
1619 device_reset(d);
1620 }
1621 }
1622
1623 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1624 {
1625 MachineState *machine = MACHINE(spapr);
1626 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1627 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1628 int i;
1629
1630 for (i = 0; i < nr_lmbs; i++) {
1631 sPAPRDRConnector *drc;
1632 uint64_t addr;
1633
1634 addr = i * lmb_size + spapr->hotplug_memory.base;
1635 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1636 addr/lmb_size);
1637 qemu_register_reset(spapr_drc_reset, drc);
1638 }
1639 }
1640
1641 /*
1642 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1643 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1644 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1645 */
1646 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1647 {
1648 int i;
1649
1650 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1651 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1652 " is not aligned to %llu MiB",
1653 machine->ram_size,
1654 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1655 return;
1656 }
1657
1658 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1659 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1660 " is not aligned to %llu MiB",
1661 machine->ram_size,
1662 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1663 return;
1664 }
1665
1666 for (i = 0; i < nb_numa_nodes; i++) {
1667 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1668 error_setg(errp,
1669 "Node %d memory size 0x%" PRIx64
1670 " is not aligned to %llu MiB",
1671 i, numa_info[i].node_mem,
1672 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1673 return;
1674 }
1675 }
1676 }
1677
1678 /* pSeries LPAR / sPAPR hardware init */
1679 static void ppc_spapr_init(MachineState *machine)
1680 {
1681 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1682 MachineClass *mc = MACHINE_GET_CLASS(machine);
1683 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1684 const char *kernel_filename = machine->kernel_filename;
1685 const char *kernel_cmdline = machine->kernel_cmdline;
1686 const char *initrd_filename = machine->initrd_filename;
1687 PCIHostState *phb;
1688 int i;
1689 MemoryRegion *sysmem = get_system_memory();
1690 MemoryRegion *ram = g_new(MemoryRegion, 1);
1691 MemoryRegion *rma_region;
1692 void *rma = NULL;
1693 hwaddr rma_alloc_size;
1694 hwaddr node0_size = spapr_node0_size();
1695 uint32_t initrd_base = 0;
1696 long kernel_size = 0, initrd_size = 0;
1697 long load_limit, fw_size;
1698 bool kernel_le = false;
1699 char *filename;
1700 int smt = kvmppc_smt_threads();
1701 int spapr_cores = smp_cpus / smp_threads;
1702 int spapr_max_cores = max_cpus / smp_threads;
1703
1704 if (mc->query_hotpluggable_cpus) {
1705 if (smp_cpus % smp_threads) {
1706 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1707 smp_cpus, smp_threads);
1708 exit(1);
1709 }
1710 if (max_cpus % smp_threads) {
1711 error_report("max_cpus (%u) must be multiple of threads (%u)",
1712 max_cpus, smp_threads);
1713 exit(1);
1714 }
1715 }
1716
1717 msi_nonbroken = true;
1718
1719 QLIST_INIT(&spapr->phbs);
1720
1721 cpu_ppc_hypercall = emulate_spapr_hypercall;
1722
1723 /* Allocate RMA if necessary */
1724 rma_alloc_size = kvmppc_alloc_rma(&rma);
1725
1726 if (rma_alloc_size == -1) {
1727 error_report("Unable to create RMA");
1728 exit(1);
1729 }
1730
1731 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1732 spapr->rma_size = rma_alloc_size;
1733 } else {
1734 spapr->rma_size = node0_size;
1735
1736 /* With KVM, we don't actually know whether KVM supports an
1737 * unbounded RMA (PR KVM) or is limited by the hash table size
1738 * (HV KVM using VRMA), so we always assume the latter
1739 *
1740 * In that case, we also limit the initial allocations for RTAS
1741 * etc... to 256M since we have no way to know what the VRMA size
1742 * is going to be as it depends on the size of the hash table
1743 * isn't determined yet.
1744 */
1745 if (kvm_enabled()) {
1746 spapr->vrma_adjust = 1;
1747 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1748 }
1749
1750 /* Actually we don't support unbounded RMA anymore since we
1751 * added proper emulation of HV mode. The max we can get is
1752 * 16G which also happens to be what we configure for PAPR
1753 * mode so make sure we don't do anything bigger than that
1754 */
1755 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1756 }
1757
1758 if (spapr->rma_size > node0_size) {
1759 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1760 spapr->rma_size);
1761 exit(1);
1762 }
1763
1764 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1765 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1766
1767 /* Set up Interrupt Controller before we create the VCPUs */
1768 spapr->xics = xics_system_init(machine,
1769 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1770 XICS_IRQS_SPAPR, &error_fatal);
1771
1772 if (smc->dr_lmb_enabled) {
1773 spapr_validate_node_memory(machine, &error_fatal);
1774 }
1775
1776 /* init CPUs */
1777 if (machine->cpu_model == NULL) {
1778 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
1779 }
1780
1781 ppc_cpu_parse_features(machine->cpu_model);
1782
1783 if (mc->query_hotpluggable_cpus) {
1784 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1785
1786 if (type == NULL) {
1787 error_report("Unable to find sPAPR CPU Core definition");
1788 exit(1);
1789 }
1790
1791 spapr->cores = g_new0(Object *, spapr_max_cores);
1792 for (i = 0; i < spapr_max_cores; i++) {
1793 int core_id = i * smp_threads;
1794 sPAPRDRConnector *drc =
1795 spapr_dr_connector_new(OBJECT(spapr),
1796 SPAPR_DR_CONNECTOR_TYPE_CPU,
1797 (core_id / smp_threads) * smt);
1798
1799 qemu_register_reset(spapr_drc_reset, drc);
1800
1801 if (i < spapr_cores) {
1802 Object *core = object_new(type);
1803 object_property_set_int(core, smp_threads, "nr-threads",
1804 &error_fatal);
1805 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1806 &error_fatal);
1807 object_property_set_bool(core, true, "realized", &error_fatal);
1808 }
1809 }
1810 g_free(type);
1811 } else {
1812 for (i = 0; i < smp_cpus; i++) {
1813 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1814 if (cpu == NULL) {
1815 error_report("Unable to find PowerPC CPU definition");
1816 exit(1);
1817 }
1818 spapr_cpu_init(spapr, cpu, &error_fatal);
1819 }
1820 }
1821
1822 if (kvm_enabled()) {
1823 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1824 kvmppc_enable_logical_ci_hcalls();
1825 kvmppc_enable_set_mode_hcall();
1826
1827 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1828 kvmppc_enable_clear_ref_mod_hcalls();
1829 }
1830
1831 /* allocate RAM */
1832 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1833 machine->ram_size);
1834 memory_region_add_subregion(sysmem, 0, ram);
1835
1836 if (rma_alloc_size && rma) {
1837 rma_region = g_new(MemoryRegion, 1);
1838 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1839 rma_alloc_size, rma);
1840 vmstate_register_ram_global(rma_region);
1841 memory_region_add_subregion(sysmem, 0, rma_region);
1842 }
1843
1844 /* initialize hotplug memory address space */
1845 if (machine->ram_size < machine->maxram_size) {
1846 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1847 /*
1848 * Limit the number of hotpluggable memory slots to half the number
1849 * slots that KVM supports, leaving the other half for PCI and other
1850 * devices. However ensure that number of slots doesn't drop below 32.
1851 */
1852 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1853 SPAPR_MAX_RAM_SLOTS;
1854
1855 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1856 max_memslots = SPAPR_MAX_RAM_SLOTS;
1857 }
1858 if (machine->ram_slots > max_memslots) {
1859 error_report("Specified number of memory slots %"
1860 PRIu64" exceeds max supported %d",
1861 machine->ram_slots, max_memslots);
1862 exit(1);
1863 }
1864
1865 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1866 SPAPR_HOTPLUG_MEM_ALIGN);
1867 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1868 "hotplug-memory", hotplug_mem_size);
1869 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1870 &spapr->hotplug_memory.mr);
1871 }
1872
1873 if (smc->dr_lmb_enabled) {
1874 spapr_create_lmb_dr_connectors(spapr);
1875 }
1876
1877 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1878 if (!filename) {
1879 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1880 exit(1);
1881 }
1882 spapr->rtas_size = get_image_size(filename);
1883 if (spapr->rtas_size < 0) {
1884 error_report("Could not get size of LPAR rtas '%s'", filename);
1885 exit(1);
1886 }
1887 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1888 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1889 error_report("Could not load LPAR rtas '%s'", filename);
1890 exit(1);
1891 }
1892 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1893 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1894 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1895 exit(1);
1896 }
1897 g_free(filename);
1898
1899 /* Set up EPOW events infrastructure */
1900 spapr_events_init(spapr);
1901
1902 /* Set up the RTC RTAS interfaces */
1903 spapr_rtc_create(spapr);
1904
1905 /* Set up VIO bus */
1906 spapr->vio_bus = spapr_vio_bus_init();
1907
1908 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1909 if (serial_hds[i]) {
1910 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1911 }
1912 }
1913
1914 /* We always have at least the nvram device on VIO */
1915 spapr_create_nvram(spapr);
1916
1917 /* Set up PCI */
1918 spapr_pci_rtas_init();
1919
1920 phb = spapr_create_phb(spapr, 0);
1921
1922 for (i = 0; i < nb_nics; i++) {
1923 NICInfo *nd = &nd_table[i];
1924
1925 if (!nd->model) {
1926 nd->model = g_strdup("ibmveth");
1927 }
1928
1929 if (strcmp(nd->model, "ibmveth") == 0) {
1930 spapr_vlan_create(spapr->vio_bus, nd);
1931 } else {
1932 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1933 }
1934 }
1935
1936 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1937 spapr_vscsi_create(spapr->vio_bus);
1938 }
1939
1940 /* Graphics */
1941 if (spapr_vga_init(phb->bus, &error_fatal)) {
1942 spapr->has_graphics = true;
1943 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1944 }
1945
1946 if (machine->usb) {
1947 if (smc->use_ohci_by_default) {
1948 pci_create_simple(phb->bus, -1, "pci-ohci");
1949 } else {
1950 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1951 }
1952
1953 if (spapr->has_graphics) {
1954 USBBus *usb_bus = usb_bus_find(-1);
1955
1956 usb_create_simple(usb_bus, "usb-kbd");
1957 usb_create_simple(usb_bus, "usb-mouse");
1958 }
1959 }
1960
1961 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1962 error_report(
1963 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1964 MIN_RMA_SLOF);
1965 exit(1);
1966 }
1967
1968 if (kernel_filename) {
1969 uint64_t lowaddr = 0;
1970
1971 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1972 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1973 0, 0);
1974 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1975 kernel_size = load_elf(kernel_filename,
1976 translate_kernel_address, NULL,
1977 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1978 0, 0);
1979 kernel_le = kernel_size > 0;
1980 }
1981 if (kernel_size < 0) {
1982 error_report("error loading %s: %s",
1983 kernel_filename, load_elf_strerror(kernel_size));
1984 exit(1);
1985 }
1986
1987 /* load initrd */
1988 if (initrd_filename) {
1989 /* Try to locate the initrd in the gap between the kernel
1990 * and the firmware. Add a bit of space just in case
1991 */
1992 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1993 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1994 load_limit - initrd_base);
1995 if (initrd_size < 0) {
1996 error_report("could not load initial ram disk '%s'",
1997 initrd_filename);
1998 exit(1);
1999 }
2000 } else {
2001 initrd_base = 0;
2002 initrd_size = 0;
2003 }
2004 }
2005
2006 if (bios_name == NULL) {
2007 bios_name = FW_FILE_NAME;
2008 }
2009 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2010 if (!filename) {
2011 error_report("Could not find LPAR firmware '%s'", bios_name);
2012 exit(1);
2013 }
2014 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2015 if (fw_size <= 0) {
2016 error_report("Could not load LPAR firmware '%s'", filename);
2017 exit(1);
2018 }
2019 g_free(filename);
2020
2021 /* FIXME: Should register things through the MachineState's qdev
2022 * interface, this is a legacy from the sPAPREnvironment structure
2023 * which predated MachineState but had a similar function */
2024 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2025 register_savevm_live(NULL, "spapr/htab", -1, 1,
2026 &savevm_htab_handlers, spapr);
2027
2028 /* Prepare the device tree */
2029 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
2030 kernel_size, kernel_le,
2031 kernel_cmdline,
2032 spapr->check_exception_irq);
2033 assert(spapr->fdt_skel != NULL);
2034
2035 /* used by RTAS */
2036 QTAILQ_INIT(&spapr->ccs_list);
2037 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2038
2039 qemu_register_boot_set(spapr_boot_set, spapr);
2040 }
2041
2042 static int spapr_kvm_type(const char *vm_type)
2043 {
2044 if (!vm_type) {
2045 return 0;
2046 }
2047
2048 if (!strcmp(vm_type, "HV")) {
2049 return 1;
2050 }
2051
2052 if (!strcmp(vm_type, "PR")) {
2053 return 2;
2054 }
2055
2056 error_report("Unknown kvm-type specified '%s'", vm_type);
2057 exit(1);
2058 }
2059
2060 /*
2061 * Implementation of an interface to adjust firmware path
2062 * for the bootindex property handling.
2063 */
2064 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2065 DeviceState *dev)
2066 {
2067 #define CAST(type, obj, name) \
2068 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2069 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2070 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2071
2072 if (d) {
2073 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2074 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2075 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2076
2077 if (spapr) {
2078 /*
2079 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2080 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2081 * in the top 16 bits of the 64-bit LUN
2082 */
2083 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2084 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2085 (uint64_t)id << 48);
2086 } else if (virtio) {
2087 /*
2088 * We use SRP luns of the form 01000000 | (target << 8) | lun
2089 * in the top 32 bits of the 64-bit LUN
2090 * Note: the quote above is from SLOF and it is wrong,
2091 * the actual binding is:
2092 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2093 */
2094 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2095 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2096 (uint64_t)id << 32);
2097 } else if (usb) {
2098 /*
2099 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2100 * in the top 32 bits of the 64-bit LUN
2101 */
2102 unsigned usb_port = atoi(usb->port->path);
2103 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2104 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2105 (uint64_t)id << 32);
2106 }
2107 }
2108
2109 if (phb) {
2110 /* Replace "pci" with "pci@800000020000000" */
2111 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2112 }
2113
2114 return NULL;
2115 }
2116
2117 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2118 {
2119 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2120
2121 return g_strdup(spapr->kvm_type);
2122 }
2123
2124 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2125 {
2126 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2127
2128 g_free(spapr->kvm_type);
2129 spapr->kvm_type = g_strdup(value);
2130 }
2131
2132 static void spapr_machine_initfn(Object *obj)
2133 {
2134 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2135
2136 spapr->htab_fd = -1;
2137 object_property_add_str(obj, "kvm-type",
2138 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2139 object_property_set_description(obj, "kvm-type",
2140 "Specifies the KVM virtualization mode (HV, PR)",
2141 NULL);
2142 }
2143
2144 static void spapr_machine_finalizefn(Object *obj)
2145 {
2146 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2147
2148 g_free(spapr->kvm_type);
2149 }
2150
2151 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2152 {
2153 cpu_synchronize_state(cs);
2154 ppc_cpu_do_system_reset(cs);
2155 }
2156
2157 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2158 {
2159 CPUState *cs;
2160
2161 CPU_FOREACH(cs) {
2162 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2163 }
2164 }
2165
2166 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2167 uint32_t node, Error **errp)
2168 {
2169 sPAPRDRConnector *drc;
2170 sPAPRDRConnectorClass *drck;
2171 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2172 int i, fdt_offset, fdt_size;
2173 void *fdt;
2174
2175 for (i = 0; i < nr_lmbs; i++) {
2176 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2177 addr/SPAPR_MEMORY_BLOCK_SIZE);
2178 g_assert(drc);
2179
2180 fdt = create_device_tree(&fdt_size);
2181 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2182 SPAPR_MEMORY_BLOCK_SIZE);
2183
2184 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2185 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2186 addr += SPAPR_MEMORY_BLOCK_SIZE;
2187 }
2188 /* send hotplug notification to the
2189 * guest only in case of hotplugged memory
2190 */
2191 if (dev->hotplugged) {
2192 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2193 }
2194 }
2195
2196 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2197 uint32_t node, Error **errp)
2198 {
2199 Error *local_err = NULL;
2200 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2201 PCDIMMDevice *dimm = PC_DIMM(dev);
2202 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2203 MemoryRegion *mr = ddc->get_memory_region(dimm);
2204 uint64_t align = memory_region_get_alignment(mr);
2205 uint64_t size = memory_region_size(mr);
2206 uint64_t addr;
2207
2208 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2209 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2210 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2211 goto out;
2212 }
2213
2214 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2215 if (local_err) {
2216 goto out;
2217 }
2218
2219 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2220 if (local_err) {
2221 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2222 goto out;
2223 }
2224
2225 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2226
2227 out:
2228 error_propagate(errp, local_err);
2229 }
2230
2231 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2232 sPAPRMachineState *spapr)
2233 {
2234 PowerPCCPU *cpu = POWERPC_CPU(cs);
2235 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2236 int id = ppc_get_vcpu_dt_id(cpu);
2237 void *fdt;
2238 int offset, fdt_size;
2239 char *nodename;
2240
2241 fdt = create_device_tree(&fdt_size);
2242 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2243 offset = fdt_add_subnode(fdt, 0, nodename);
2244
2245 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2246 g_free(nodename);
2247
2248 *fdt_offset = offset;
2249 return fdt;
2250 }
2251
2252 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2253 DeviceState *dev, Error **errp)
2254 {
2255 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2256
2257 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2258 int node;
2259
2260 if (!smc->dr_lmb_enabled) {
2261 error_setg(errp, "Memory hotplug not supported for this machine");
2262 return;
2263 }
2264 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2265 if (*errp) {
2266 return;
2267 }
2268 if (node < 0 || node >= MAX_NODES) {
2269 error_setg(errp, "Invaild node %d", node);
2270 return;
2271 }
2272
2273 /*
2274 * Currently PowerPC kernel doesn't allow hot-adding memory to
2275 * memory-less node, but instead will silently add the memory
2276 * to the first node that has some memory. This causes two
2277 * unexpected behaviours for the user.
2278 *
2279 * - Memory gets hotplugged to a different node than what the user
2280 * specified.
2281 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2282 * to memory-less node, a reboot will set things accordingly
2283 * and the previously hotplugged memory now ends in the right node.
2284 * This appears as if some memory moved from one node to another.
2285 *
2286 * So until kernel starts supporting memory hotplug to memory-less
2287 * nodes, just prevent such attempts upfront in QEMU.
2288 */
2289 if (nb_numa_nodes && !numa_info[node].node_mem) {
2290 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2291 node);
2292 return;
2293 }
2294
2295 spapr_memory_plug(hotplug_dev, dev, node, errp);
2296 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2297 spapr_core_plug(hotplug_dev, dev, errp);
2298 }
2299 }
2300
2301 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2302 DeviceState *dev, Error **errp)
2303 {
2304 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2305
2306 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2307 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2308 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2309 if (!mc->query_hotpluggable_cpus) {
2310 error_setg(errp, "CPU hot unplug not supported on this machine");
2311 return;
2312 }
2313 spapr_core_unplug(hotplug_dev, dev, errp);
2314 }
2315 }
2316
2317 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2318 DeviceState *dev, Error **errp)
2319 {
2320 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2321 spapr_core_pre_plug(hotplug_dev, dev, errp);
2322 }
2323 }
2324
2325 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2326 DeviceState *dev)
2327 {
2328 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2329 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2330 return HOTPLUG_HANDLER(machine);
2331 }
2332 return NULL;
2333 }
2334
2335 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2336 {
2337 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2338 * socket means much for the paravirtualized PAPR platform) */
2339 return cpu_index / smp_threads / smp_cores;
2340 }
2341
2342 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2343 {
2344 int i;
2345 HotpluggableCPUList *head = NULL;
2346 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2347 int spapr_max_cores = max_cpus / smp_threads;
2348
2349 for (i = 0; i < spapr_max_cores; i++) {
2350 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2351 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2352 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2353
2354 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2355 cpu_item->vcpus_count = smp_threads;
2356 cpu_props->has_core_id = true;
2357 cpu_props->core_id = i * smp_threads;
2358 /* TODO: add 'has_node/node' here to describe
2359 to which node core belongs */
2360
2361 cpu_item->props = cpu_props;
2362 if (spapr->cores[i]) {
2363 cpu_item->has_qom_path = true;
2364 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2365 }
2366 list_item->value = cpu_item;
2367 list_item->next = head;
2368 head = list_item;
2369 }
2370 return head;
2371 }
2372
2373 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2374 uint64_t *buid, hwaddr *pio,
2375 hwaddr *mmio32, hwaddr *mmio64,
2376 unsigned n_dma, uint32_t *liobns, Error **errp)
2377 {
2378 /*
2379 * New-style PHB window placement.
2380 *
2381 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2382 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2383 * windows.
2384 *
2385 * Some guest kernels can't work with MMIO windows above 1<<46
2386 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2387 *
2388 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2389 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2390 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2391 * 1TiB 64-bit MMIO windows for each PHB.
2392 */
2393 const uint64_t base_buid = 0x800000020000000ULL;
2394 const int max_phbs =
2395 (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1;
2396 int i;
2397
2398 /* Sanity check natural alignments */
2399 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2400 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2401 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2402 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2403 /* Sanity check bounds */
2404 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE);
2405 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE);
2406
2407 if (index >= max_phbs) {
2408 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2409 max_phbs - 1);
2410 return;
2411 }
2412
2413 *buid = base_buid + index;
2414 for (i = 0; i < n_dma; ++i) {
2415 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2416 }
2417
2418 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
2419 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
2420 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
2421 }
2422
2423 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2424 {
2425 MachineClass *mc = MACHINE_CLASS(oc);
2426 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2427 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2428 NMIClass *nc = NMI_CLASS(oc);
2429 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2430
2431 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2432
2433 /*
2434 * We set up the default / latest behaviour here. The class_init
2435 * functions for the specific versioned machine types can override
2436 * these details for backwards compatibility
2437 */
2438 mc->init = ppc_spapr_init;
2439 mc->reset = ppc_spapr_reset;
2440 mc->block_default_type = IF_SCSI;
2441 mc->max_cpus = 255;
2442 mc->no_parallel = 1;
2443 mc->default_boot_order = "";
2444 mc->default_ram_size = 512 * M_BYTE;
2445 mc->kvm_type = spapr_kvm_type;
2446 mc->has_dynamic_sysbus = true;
2447 mc->pci_allow_0_address = true;
2448 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2449 hc->pre_plug = spapr_machine_device_pre_plug;
2450 hc->plug = spapr_machine_device_plug;
2451 hc->unplug = spapr_machine_device_unplug;
2452 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2453
2454 smc->dr_lmb_enabled = true;
2455 smc->tcg_default_cpu = "POWER8";
2456 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2457 fwc->get_dev_path = spapr_get_fw_dev_path;
2458 nc->nmi_monitor_handler = spapr_nmi;
2459 smc->phb_placement = spapr_phb_placement;
2460 }
2461
2462 static const TypeInfo spapr_machine_info = {
2463 .name = TYPE_SPAPR_MACHINE,
2464 .parent = TYPE_MACHINE,
2465 .abstract = true,
2466 .instance_size = sizeof(sPAPRMachineState),
2467 .instance_init = spapr_machine_initfn,
2468 .instance_finalize = spapr_machine_finalizefn,
2469 .class_size = sizeof(sPAPRMachineClass),
2470 .class_init = spapr_machine_class_init,
2471 .interfaces = (InterfaceInfo[]) {
2472 { TYPE_FW_PATH_PROVIDER },
2473 { TYPE_NMI },
2474 { TYPE_HOTPLUG_HANDLER },
2475 { }
2476 },
2477 };
2478
2479 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2480 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2481 void *data) \
2482 { \
2483 MachineClass *mc = MACHINE_CLASS(oc); \
2484 spapr_machine_##suffix##_class_options(mc); \
2485 if (latest) { \
2486 mc->alias = "pseries"; \
2487 mc->is_default = 1; \
2488 } \
2489 } \
2490 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2491 { \
2492 MachineState *machine = MACHINE(obj); \
2493 spapr_machine_##suffix##_instance_options(machine); \
2494 } \
2495 static const TypeInfo spapr_machine_##suffix##_info = { \
2496 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2497 .parent = TYPE_SPAPR_MACHINE, \
2498 .class_init = spapr_machine_##suffix##_class_init, \
2499 .instance_init = spapr_machine_##suffix##_instance_init, \
2500 }; \
2501 static void spapr_machine_register_##suffix(void) \
2502 { \
2503 type_register(&spapr_machine_##suffix##_info); \
2504 } \
2505 type_init(spapr_machine_register_##suffix)
2506
2507 /*
2508 * pseries-2.8
2509 */
2510 static void spapr_machine_2_8_instance_options(MachineState *machine)
2511 {
2512 }
2513
2514 static void spapr_machine_2_8_class_options(MachineClass *mc)
2515 {
2516 /* Defaults for the latest behaviour inherited from the base class */
2517 }
2518
2519 DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
2520
2521 /*
2522 * pseries-2.7
2523 */
2524 #define SPAPR_COMPAT_2_7 \
2525 HW_COMPAT_2_7 \
2526 { \
2527 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2528 .property = "mem_win_size", \
2529 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
2530 }, \
2531 { \
2532 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2533 .property = "mem64_win_size", \
2534 .value = "0", \
2535 },
2536
2537 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
2538 uint64_t *buid, hwaddr *pio,
2539 hwaddr *mmio32, hwaddr *mmio64,
2540 unsigned n_dma, uint32_t *liobns, Error **errp)
2541 {
2542 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
2543 const uint64_t base_buid = 0x800000020000000ULL;
2544 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
2545 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
2546 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
2547 const uint32_t max_index = 255;
2548 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
2549
2550 uint64_t ram_top = MACHINE(spapr)->ram_size;
2551 hwaddr phb0_base, phb_base;
2552 int i;
2553
2554 /* Do we have hotpluggable memory? */
2555 if (MACHINE(spapr)->maxram_size > ram_top) {
2556 /* Can't just use maxram_size, because there may be an
2557 * alignment gap between normal and hotpluggable memory
2558 * regions */
2559 ram_top = spapr->hotplug_memory.base +
2560 memory_region_size(&spapr->hotplug_memory.mr);
2561 }
2562
2563 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
2564
2565 if (index > max_index) {
2566 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2567 max_index);
2568 return;
2569 }
2570
2571 *buid = base_buid + index;
2572 for (i = 0; i < n_dma; ++i) {
2573 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2574 }
2575
2576 phb_base = phb0_base + index * phb_spacing;
2577 *pio = phb_base + pio_offset;
2578 *mmio32 = phb_base + mmio_offset;
2579 /*
2580 * We don't set the 64-bit MMIO window, relying on the PHB's
2581 * fallback behaviour of automatically splitting a large "32-bit"
2582 * window into contiguous 32-bit and 64-bit windows
2583 */
2584 }
2585
2586 static void spapr_machine_2_7_instance_options(MachineState *machine)
2587 {
2588 spapr_machine_2_8_instance_options(machine);
2589 }
2590
2591 static void spapr_machine_2_7_class_options(MachineClass *mc)
2592 {
2593 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2594
2595 spapr_machine_2_8_class_options(mc);
2596 smc->tcg_default_cpu = "POWER7";
2597 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
2598 smc->phb_placement = phb_placement_2_7;
2599 }
2600
2601 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
2602
2603 /*
2604 * pseries-2.6
2605 */
2606 #define SPAPR_COMPAT_2_6 \
2607 HW_COMPAT_2_6 \
2608 { \
2609 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2610 .property = "ddw",\
2611 .value = stringify(off),\
2612 },
2613
2614 static void spapr_machine_2_6_instance_options(MachineState *machine)
2615 {
2616 spapr_machine_2_7_instance_options(machine);
2617 }
2618
2619 static void spapr_machine_2_6_class_options(MachineClass *mc)
2620 {
2621 spapr_machine_2_7_class_options(mc);
2622 mc->query_hotpluggable_cpus = NULL;
2623 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2624 }
2625
2626 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2627
2628 /*
2629 * pseries-2.5
2630 */
2631 #define SPAPR_COMPAT_2_5 \
2632 HW_COMPAT_2_5 \
2633 { \
2634 .driver = "spapr-vlan", \
2635 .property = "use-rx-buffer-pools", \
2636 .value = "off", \
2637 },
2638
2639 static void spapr_machine_2_5_instance_options(MachineState *machine)
2640 {
2641 spapr_machine_2_6_instance_options(machine);
2642 }
2643
2644 static void spapr_machine_2_5_class_options(MachineClass *mc)
2645 {
2646 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2647
2648 spapr_machine_2_6_class_options(mc);
2649 smc->use_ohci_by_default = true;
2650 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2651 }
2652
2653 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2654
2655 /*
2656 * pseries-2.4
2657 */
2658 #define SPAPR_COMPAT_2_4 \
2659 HW_COMPAT_2_4
2660
2661 static void spapr_machine_2_4_instance_options(MachineState *machine)
2662 {
2663 spapr_machine_2_5_instance_options(machine);
2664 }
2665
2666 static void spapr_machine_2_4_class_options(MachineClass *mc)
2667 {
2668 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2669
2670 spapr_machine_2_5_class_options(mc);
2671 smc->dr_lmb_enabled = false;
2672 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2673 }
2674
2675 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2676
2677 /*
2678 * pseries-2.3
2679 */
2680 #define SPAPR_COMPAT_2_3 \
2681 HW_COMPAT_2_3 \
2682 {\
2683 .driver = "spapr-pci-host-bridge",\
2684 .property = "dynamic-reconfiguration",\
2685 .value = "off",\
2686 },
2687
2688 static void spapr_machine_2_3_instance_options(MachineState *machine)
2689 {
2690 spapr_machine_2_4_instance_options(machine);
2691 savevm_skip_section_footers();
2692 global_state_set_optional();
2693 savevm_skip_configuration();
2694 }
2695
2696 static void spapr_machine_2_3_class_options(MachineClass *mc)
2697 {
2698 spapr_machine_2_4_class_options(mc);
2699 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2700 }
2701 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2702
2703 /*
2704 * pseries-2.2
2705 */
2706
2707 #define SPAPR_COMPAT_2_2 \
2708 HW_COMPAT_2_2 \
2709 {\
2710 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2711 .property = "mem_win_size",\
2712 .value = "0x20000000",\
2713 },
2714
2715 static void spapr_machine_2_2_instance_options(MachineState *machine)
2716 {
2717 spapr_machine_2_3_instance_options(machine);
2718 machine->suppress_vmdesc = true;
2719 }
2720
2721 static void spapr_machine_2_2_class_options(MachineClass *mc)
2722 {
2723 spapr_machine_2_3_class_options(mc);
2724 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2725 }
2726 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2727
2728 /*
2729 * pseries-2.1
2730 */
2731 #define SPAPR_COMPAT_2_1 \
2732 HW_COMPAT_2_1
2733
2734 static void spapr_machine_2_1_instance_options(MachineState *machine)
2735 {
2736 spapr_machine_2_2_instance_options(machine);
2737 }
2738
2739 static void spapr_machine_2_1_class_options(MachineClass *mc)
2740 {
2741 spapr_machine_2_2_class_options(mc);
2742 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2743 }
2744 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2745
2746 static void spapr_machine_register_types(void)
2747 {
2748 type_register_static(&spapr_machine_info);
2749 }
2750
2751 type_init(spapr_machine_register_types)
AR7 emulation for QEMU