4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/helper-proto.h"
26 #include "exec/exec-all.h"
28 #include "exec/cpu_ldst.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
38 #define DYNAMIC_PC 1 /* dynamic pc value */
39 #define JUMP_PC 2 /* dynamic pc value which takes only two values
40 according to jump_pc[T2] */
42 /* global register indexes */
43 static TCGv_env cpu_env
;
44 static TCGv_ptr cpu_regwptr
;
45 static TCGv cpu_cc_src
, cpu_cc_src2
, cpu_cc_dst
;
46 static TCGv_i32 cpu_cc_op
;
47 static TCGv_i32 cpu_psr
;
48 static TCGv cpu_fsr
, cpu_pc
, cpu_npc
;
49 static TCGv cpu_regs
[32];
51 #ifndef CONFIG_USER_ONLY
56 static TCGv_i32 cpu_xcc
, cpu_asi
, cpu_fprs
;
58 static TCGv cpu_tick_cmpr
, cpu_stick_cmpr
, cpu_hstick_cmpr
;
59 static TCGv cpu_hintp
, cpu_htba
, cpu_hver
, cpu_ssr
, cpu_ver
;
60 static TCGv_i32 cpu_softint
;
64 /* Floating point registers */
65 static TCGv_i64 cpu_fpr
[TARGET_DPREGS
];
67 #include "exec/gen-icount.h"
69 typedef struct DisasContext
{
70 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
71 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
76 int address_mask_32bit
;
78 uint32_t cc_op
; /* current CC operation */
79 struct TranslationBlock
*tb
;
94 // This function uses non-native bit order
95 #define GET_FIELD(X, FROM, TO) \
96 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
98 // This function uses the order in the manuals, i.e. bit 0 is 2^0
99 #define GET_FIELD_SP(X, FROM, TO) \
100 GET_FIELD(X, 31 - (TO), 31 - (FROM))
102 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
103 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
105 #ifdef TARGET_SPARC64
106 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
107 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
109 #define DFPREG(r) (r & 0x1e)
110 #define QFPREG(r) (r & 0x1c)
113 #define UA2005_HTRAP_MASK 0xff
114 #define V8_TRAP_MASK 0x7f
116 static int sign_extend(int x
, int len
)
119 return (x
<< len
) >> len
;
122 #define IS_IMM (insn & (1<<13))
124 static inline TCGv_i32
get_temp_i32(DisasContext
*dc
)
127 assert(dc
->n_t32
< ARRAY_SIZE(dc
->t32
));
128 dc
->t32
[dc
->n_t32
++] = t
= tcg_temp_new_i32();
132 static inline TCGv
get_temp_tl(DisasContext
*dc
)
135 assert(dc
->n_ttl
< ARRAY_SIZE(dc
->ttl
));
136 dc
->ttl
[dc
->n_ttl
++] = t
= tcg_temp_new();
140 static inline void gen_update_fprs_dirty(int rd
)
142 #if defined(TARGET_SPARC64)
143 tcg_gen_ori_i32(cpu_fprs
, cpu_fprs
, (rd
< 32) ? 1 : 2);
147 /* floating point registers moves */
148 static TCGv_i32
gen_load_fpr_F(DisasContext
*dc
, unsigned int src
)
150 #if TCG_TARGET_REG_BITS == 32
152 return TCGV_LOW(cpu_fpr
[src
/ 2]);
154 return TCGV_HIGH(cpu_fpr
[src
/ 2]);
158 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr
[src
/ 2]));
160 TCGv_i32 ret
= get_temp_i32(dc
);
161 TCGv_i64 t
= tcg_temp_new_i64();
163 tcg_gen_shri_i64(t
, cpu_fpr
[src
/ 2], 32);
164 tcg_gen_extrl_i64_i32(ret
, t
);
165 tcg_temp_free_i64(t
);
172 static void gen_store_fpr_F(DisasContext
*dc
, unsigned int dst
, TCGv_i32 v
)
174 #if TCG_TARGET_REG_BITS == 32
176 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr
[dst
/ 2]), v
);
178 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr
[dst
/ 2]), v
);
181 TCGv_i64 t
= MAKE_TCGV_I64(GET_TCGV_I32(v
));
182 tcg_gen_deposit_i64(cpu_fpr
[dst
/ 2], cpu_fpr
[dst
/ 2], t
,
183 (dst
& 1 ? 0 : 32), 32);
185 gen_update_fprs_dirty(dst
);
188 static TCGv_i32
gen_dest_fpr_F(DisasContext
*dc
)
190 return get_temp_i32(dc
);
193 static TCGv_i64
gen_load_fpr_D(DisasContext
*dc
, unsigned int src
)
196 return cpu_fpr
[src
/ 2];
199 static void gen_store_fpr_D(DisasContext
*dc
, unsigned int dst
, TCGv_i64 v
)
202 tcg_gen_mov_i64(cpu_fpr
[dst
/ 2], v
);
203 gen_update_fprs_dirty(dst
);
206 static TCGv_i64
gen_dest_fpr_D(DisasContext
*dc
, unsigned int dst
)
208 return cpu_fpr
[DFPREG(dst
) / 2];
211 static void gen_op_load_fpr_QT0(unsigned int src
)
213 tcg_gen_st_i64(cpu_fpr
[src
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
214 offsetof(CPU_QuadU
, ll
.upper
));
215 tcg_gen_st_i64(cpu_fpr
[src
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
216 offsetof(CPU_QuadU
, ll
.lower
));
219 static void gen_op_load_fpr_QT1(unsigned int src
)
221 tcg_gen_st_i64(cpu_fpr
[src
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt1
) +
222 offsetof(CPU_QuadU
, ll
.upper
));
223 tcg_gen_st_i64(cpu_fpr
[src
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt1
) +
224 offsetof(CPU_QuadU
, ll
.lower
));
227 static void gen_op_store_QT0_fpr(unsigned int dst
)
229 tcg_gen_ld_i64(cpu_fpr
[dst
/ 2], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
230 offsetof(CPU_QuadU
, ll
.upper
));
231 tcg_gen_ld_i64(cpu_fpr
[dst
/2 + 1], cpu_env
, offsetof(CPUSPARCState
, qt0
) +
232 offsetof(CPU_QuadU
, ll
.lower
));
235 #ifdef TARGET_SPARC64
236 static void gen_move_Q(unsigned int rd
, unsigned int rs
)
241 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2], cpu_fpr
[rs
/ 2]);
242 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2 + 1], cpu_fpr
[rs
/ 2 + 1]);
243 gen_update_fprs_dirty(rd
);
248 #ifdef CONFIG_USER_ONLY
249 #define supervisor(dc) 0
250 #ifdef TARGET_SPARC64
251 #define hypervisor(dc) 0
254 #define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
255 #ifdef TARGET_SPARC64
256 #define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
261 #ifdef TARGET_SPARC64
263 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
265 #define AM_CHECK(dc) (1)
269 static inline void gen_address_mask(DisasContext
*dc
, TCGv addr
)
271 #ifdef TARGET_SPARC64
273 tcg_gen_andi_tl(addr
, addr
, 0xffffffffULL
);
277 static inline TCGv
gen_load_gpr(DisasContext
*dc
, int reg
)
281 return cpu_regs
[reg
];
283 TCGv t
= get_temp_tl(dc
);
284 tcg_gen_movi_tl(t
, 0);
289 static inline void gen_store_gpr(DisasContext
*dc
, int reg
, TCGv v
)
293 tcg_gen_mov_tl(cpu_regs
[reg
], v
);
297 static inline TCGv
gen_dest_gpr(DisasContext
*dc
, int reg
)
301 return cpu_regs
[reg
];
303 return get_temp_tl(dc
);
307 static inline bool use_goto_tb(DisasContext
*s
, target_ulong pc
,
310 if (unlikely(s
->singlestep
)) {
314 #ifndef CONFIG_USER_ONLY
315 return (pc
& TARGET_PAGE_MASK
) == (s
->tb
->pc
& TARGET_PAGE_MASK
) &&
316 (npc
& TARGET_PAGE_MASK
) == (s
->tb
->pc
& TARGET_PAGE_MASK
);
322 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
,
323 target_ulong pc
, target_ulong npc
)
325 if (use_goto_tb(s
, pc
, npc
)) {
326 /* jump to same page: we can use a direct jump */
327 tcg_gen_goto_tb(tb_num
);
328 tcg_gen_movi_tl(cpu_pc
, pc
);
329 tcg_gen_movi_tl(cpu_npc
, npc
);
330 tcg_gen_exit_tb((uintptr_t)s
->tb
+ tb_num
);
332 /* jump to another page: currently not optimized */
333 tcg_gen_movi_tl(cpu_pc
, pc
);
334 tcg_gen_movi_tl(cpu_npc
, npc
);
340 static inline void gen_mov_reg_N(TCGv reg
, TCGv_i32 src
)
342 tcg_gen_extu_i32_tl(reg
, src
);
343 tcg_gen_shri_tl(reg
, reg
, PSR_NEG_SHIFT
);
344 tcg_gen_andi_tl(reg
, reg
, 0x1);
347 static inline void gen_mov_reg_Z(TCGv reg
, TCGv_i32 src
)
349 tcg_gen_extu_i32_tl(reg
, src
);
350 tcg_gen_shri_tl(reg
, reg
, PSR_ZERO_SHIFT
);
351 tcg_gen_andi_tl(reg
, reg
, 0x1);
354 static inline void gen_mov_reg_V(TCGv reg
, TCGv_i32 src
)
356 tcg_gen_extu_i32_tl(reg
, src
);
357 tcg_gen_shri_tl(reg
, reg
, PSR_OVF_SHIFT
);
358 tcg_gen_andi_tl(reg
, reg
, 0x1);
361 static inline void gen_mov_reg_C(TCGv reg
, TCGv_i32 src
)
363 tcg_gen_extu_i32_tl(reg
, src
);
364 tcg_gen_shri_tl(reg
, reg
, PSR_CARRY_SHIFT
);
365 tcg_gen_andi_tl(reg
, reg
, 0x1);
368 static inline void gen_op_add_cc(TCGv dst
, TCGv src1
, TCGv src2
)
370 tcg_gen_mov_tl(cpu_cc_src
, src1
);
371 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
372 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
373 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
376 static TCGv_i32
gen_add32_carry32(void)
378 TCGv_i32 carry_32
, cc_src1_32
, cc_src2_32
;
380 /* Carry is computed from a previous add: (dst < src) */
381 #if TARGET_LONG_BITS == 64
382 cc_src1_32
= tcg_temp_new_i32();
383 cc_src2_32
= tcg_temp_new_i32();
384 tcg_gen_extrl_i64_i32(cc_src1_32
, cpu_cc_dst
);
385 tcg_gen_extrl_i64_i32(cc_src2_32
, cpu_cc_src
);
387 cc_src1_32
= cpu_cc_dst
;
388 cc_src2_32
= cpu_cc_src
;
391 carry_32
= tcg_temp_new_i32();
392 tcg_gen_setcond_i32(TCG_COND_LTU
, carry_32
, cc_src1_32
, cc_src2_32
);
394 #if TARGET_LONG_BITS == 64
395 tcg_temp_free_i32(cc_src1_32
);
396 tcg_temp_free_i32(cc_src2_32
);
402 static TCGv_i32
gen_sub32_carry32(void)
404 TCGv_i32 carry_32
, cc_src1_32
, cc_src2_32
;
406 /* Carry is computed from a previous borrow: (src1 < src2) */
407 #if TARGET_LONG_BITS == 64
408 cc_src1_32
= tcg_temp_new_i32();
409 cc_src2_32
= tcg_temp_new_i32();
410 tcg_gen_extrl_i64_i32(cc_src1_32
, cpu_cc_src
);
411 tcg_gen_extrl_i64_i32(cc_src2_32
, cpu_cc_src2
);
413 cc_src1_32
= cpu_cc_src
;
414 cc_src2_32
= cpu_cc_src2
;
417 carry_32
= tcg_temp_new_i32();
418 tcg_gen_setcond_i32(TCG_COND_LTU
, carry_32
, cc_src1_32
, cc_src2_32
);
420 #if TARGET_LONG_BITS == 64
421 tcg_temp_free_i32(cc_src1_32
);
422 tcg_temp_free_i32(cc_src2_32
);
428 static void gen_op_addx_int(DisasContext
*dc
, TCGv dst
, TCGv src1
,
429 TCGv src2
, int update_cc
)
437 /* Carry is known to be zero. Fall back to plain ADD. */
439 gen_op_add_cc(dst
, src1
, src2
);
441 tcg_gen_add_tl(dst
, src1
, src2
);
448 if (TARGET_LONG_BITS
== 32) {
449 /* We can re-use the host's hardware carry generation by using
450 an ADD2 opcode. We discard the low part of the output.
451 Ideally we'd combine this operation with the add that
452 generated the carry in the first place. */
453 carry
= tcg_temp_new();
454 tcg_gen_add2_tl(carry
, dst
, cpu_cc_src
, src1
, cpu_cc_src2
, src2
);
455 tcg_temp_free(carry
);
458 carry_32
= gen_add32_carry32();
464 carry_32
= gen_sub32_carry32();
468 /* We need external help to produce the carry. */
469 carry_32
= tcg_temp_new_i32();
470 gen_helper_compute_C_icc(carry_32
, cpu_env
);
474 #if TARGET_LONG_BITS == 64
475 carry
= tcg_temp_new();
476 tcg_gen_extu_i32_i64(carry
, carry_32
);
481 tcg_gen_add_tl(dst
, src1
, src2
);
482 tcg_gen_add_tl(dst
, dst
, carry
);
484 tcg_temp_free_i32(carry_32
);
485 #if TARGET_LONG_BITS == 64
486 tcg_temp_free(carry
);
491 tcg_gen_mov_tl(cpu_cc_src
, src1
);
492 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
493 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
494 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADDX
);
495 dc
->cc_op
= CC_OP_ADDX
;
499 static inline void gen_op_sub_cc(TCGv dst
, TCGv src1
, TCGv src2
)
501 tcg_gen_mov_tl(cpu_cc_src
, src1
);
502 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
503 tcg_gen_sub_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
504 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
507 static void gen_op_subx_int(DisasContext
*dc
, TCGv dst
, TCGv src1
,
508 TCGv src2
, int update_cc
)
516 /* Carry is known to be zero. Fall back to plain SUB. */
518 gen_op_sub_cc(dst
, src1
, src2
);
520 tcg_gen_sub_tl(dst
, src1
, src2
);
527 carry_32
= gen_add32_carry32();
533 if (TARGET_LONG_BITS
== 32) {
534 /* We can re-use the host's hardware carry generation by using
535 a SUB2 opcode. We discard the low part of the output.
536 Ideally we'd combine this operation with the add that
537 generated the carry in the first place. */
538 carry
= tcg_temp_new();
539 tcg_gen_sub2_tl(carry
, dst
, cpu_cc_src
, src1
, cpu_cc_src2
, src2
);
540 tcg_temp_free(carry
);
543 carry_32
= gen_sub32_carry32();
547 /* We need external help to produce the carry. */
548 carry_32
= tcg_temp_new_i32();
549 gen_helper_compute_C_icc(carry_32
, cpu_env
);
553 #if TARGET_LONG_BITS == 64
554 carry
= tcg_temp_new();
555 tcg_gen_extu_i32_i64(carry
, carry_32
);
560 tcg_gen_sub_tl(dst
, src1
, src2
);
561 tcg_gen_sub_tl(dst
, dst
, carry
);
563 tcg_temp_free_i32(carry_32
);
564 #if TARGET_LONG_BITS == 64
565 tcg_temp_free(carry
);
570 tcg_gen_mov_tl(cpu_cc_src
, src1
);
571 tcg_gen_mov_tl(cpu_cc_src2
, src2
);
572 tcg_gen_mov_tl(cpu_cc_dst
, dst
);
573 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUBX
);
574 dc
->cc_op
= CC_OP_SUBX
;
578 static inline void gen_op_mulscc(TCGv dst
, TCGv src1
, TCGv src2
)
580 TCGv r_temp
, zero
, t0
;
582 r_temp
= tcg_temp_new();
589 zero
= tcg_const_tl(0);
590 tcg_gen_andi_tl(cpu_cc_src
, src1
, 0xffffffff);
591 tcg_gen_andi_tl(r_temp
, cpu_y
, 0x1);
592 tcg_gen_andi_tl(cpu_cc_src2
, src2
, 0xffffffff);
593 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_cc_src2
, r_temp
, zero
,
598 // env->y = (b2 << 31) | (env->y >> 1);
599 tcg_gen_andi_tl(r_temp
, cpu_cc_src
, 0x1);
600 tcg_gen_shli_tl(r_temp
, r_temp
, 31);
601 tcg_gen_shri_tl(t0
, cpu_y
, 1);
602 tcg_gen_andi_tl(t0
, t0
, 0x7fffffff);
603 tcg_gen_or_tl(t0
, t0
, r_temp
);
604 tcg_gen_andi_tl(cpu_y
, t0
, 0xffffffff);
607 gen_mov_reg_N(t0
, cpu_psr
);
608 gen_mov_reg_V(r_temp
, cpu_psr
);
609 tcg_gen_xor_tl(t0
, t0
, r_temp
);
610 tcg_temp_free(r_temp
);
612 // T0 = (b1 << 31) | (T0 >> 1);
614 tcg_gen_shli_tl(t0
, t0
, 31);
615 tcg_gen_shri_tl(cpu_cc_src
, cpu_cc_src
, 1);
616 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
619 tcg_gen_add_tl(cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
);
621 tcg_gen_mov_tl(dst
, cpu_cc_dst
);
624 static inline void gen_op_multiply(TCGv dst
, TCGv src1
, TCGv src2
, int sign_ext
)
626 #if TARGET_LONG_BITS == 32
628 tcg_gen_muls2_tl(dst
, cpu_y
, src1
, src2
);
630 tcg_gen_mulu2_tl(dst
, cpu_y
, src1
, src2
);
633 TCGv t0
= tcg_temp_new_i64();
634 TCGv t1
= tcg_temp_new_i64();
637 tcg_gen_ext32s_i64(t0
, src1
);
638 tcg_gen_ext32s_i64(t1
, src2
);
640 tcg_gen_ext32u_i64(t0
, src1
);
641 tcg_gen_ext32u_i64(t1
, src2
);
644 tcg_gen_mul_i64(dst
, t0
, t1
);
648 tcg_gen_shri_i64(cpu_y
, dst
, 32);
652 static inline void gen_op_umul(TCGv dst
, TCGv src1
, TCGv src2
)
654 /* zero-extend truncated operands before multiplication */
655 gen_op_multiply(dst
, src1
, src2
, 0);
658 static inline void gen_op_smul(TCGv dst
, TCGv src1
, TCGv src2
)
660 /* sign-extend truncated operands before multiplication */
661 gen_op_multiply(dst
, src1
, src2
, 1);
665 static inline void gen_op_eval_ba(TCGv dst
)
667 tcg_gen_movi_tl(dst
, 1);
671 static inline void gen_op_eval_be(TCGv dst
, TCGv_i32 src
)
673 gen_mov_reg_Z(dst
, src
);
677 static inline void gen_op_eval_ble(TCGv dst
, TCGv_i32 src
)
679 TCGv t0
= tcg_temp_new();
680 gen_mov_reg_N(t0
, src
);
681 gen_mov_reg_V(dst
, src
);
682 tcg_gen_xor_tl(dst
, dst
, t0
);
683 gen_mov_reg_Z(t0
, src
);
684 tcg_gen_or_tl(dst
, dst
, t0
);
689 static inline void gen_op_eval_bl(TCGv dst
, TCGv_i32 src
)
691 TCGv t0
= tcg_temp_new();
692 gen_mov_reg_V(t0
, src
);
693 gen_mov_reg_N(dst
, src
);
694 tcg_gen_xor_tl(dst
, dst
, t0
);
699 static inline void gen_op_eval_bleu(TCGv dst
, TCGv_i32 src
)
701 TCGv t0
= tcg_temp_new();
702 gen_mov_reg_Z(t0
, src
);
703 gen_mov_reg_C(dst
, src
);
704 tcg_gen_or_tl(dst
, dst
, t0
);
709 static inline void gen_op_eval_bcs(TCGv dst
, TCGv_i32 src
)
711 gen_mov_reg_C(dst
, src
);
715 static inline void gen_op_eval_bvs(TCGv dst
, TCGv_i32 src
)
717 gen_mov_reg_V(dst
, src
);
721 static inline void gen_op_eval_bn(TCGv dst
)
723 tcg_gen_movi_tl(dst
, 0);
727 static inline void gen_op_eval_bneg(TCGv dst
, TCGv_i32 src
)
729 gen_mov_reg_N(dst
, src
);
733 static inline void gen_op_eval_bne(TCGv dst
, TCGv_i32 src
)
735 gen_mov_reg_Z(dst
, src
);
736 tcg_gen_xori_tl(dst
, dst
, 0x1);
740 static inline void gen_op_eval_bg(TCGv dst
, TCGv_i32 src
)
742 gen_op_eval_ble(dst
, src
);
743 tcg_gen_xori_tl(dst
, dst
, 0x1);
747 static inline void gen_op_eval_bge(TCGv dst
, TCGv_i32 src
)
749 gen_op_eval_bl(dst
, src
);
750 tcg_gen_xori_tl(dst
, dst
, 0x1);
754 static inline void gen_op_eval_bgu(TCGv dst
, TCGv_i32 src
)
756 gen_op_eval_bleu(dst
, src
);
757 tcg_gen_xori_tl(dst
, dst
, 0x1);
761 static inline void gen_op_eval_bcc(TCGv dst
, TCGv_i32 src
)
763 gen_mov_reg_C(dst
, src
);
764 tcg_gen_xori_tl(dst
, dst
, 0x1);
768 static inline void gen_op_eval_bpos(TCGv dst
, TCGv_i32 src
)
770 gen_mov_reg_N(dst
, src
);
771 tcg_gen_xori_tl(dst
, dst
, 0x1);
775 static inline void gen_op_eval_bvc(TCGv dst
, TCGv_i32 src
)
777 gen_mov_reg_V(dst
, src
);
778 tcg_gen_xori_tl(dst
, dst
, 0x1);
782 FPSR bit field FCC1 | FCC0:
788 static inline void gen_mov_reg_FCC0(TCGv reg
, TCGv src
,
789 unsigned int fcc_offset
)
791 tcg_gen_shri_tl(reg
, src
, FSR_FCC0_SHIFT
+ fcc_offset
);
792 tcg_gen_andi_tl(reg
, reg
, 0x1);
795 static inline void gen_mov_reg_FCC1(TCGv reg
, TCGv src
,
796 unsigned int fcc_offset
)
798 tcg_gen_shri_tl(reg
, src
, FSR_FCC1_SHIFT
+ fcc_offset
);
799 tcg_gen_andi_tl(reg
, reg
, 0x1);
803 static inline void gen_op_eval_fbne(TCGv dst
, TCGv src
,
804 unsigned int fcc_offset
)
806 TCGv t0
= tcg_temp_new();
807 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
808 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
809 tcg_gen_or_tl(dst
, dst
, t0
);
813 // 1 or 2: FCC0 ^ FCC1
814 static inline void gen_op_eval_fblg(TCGv dst
, TCGv src
,
815 unsigned int fcc_offset
)
817 TCGv t0
= tcg_temp_new();
818 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
819 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
820 tcg_gen_xor_tl(dst
, dst
, t0
);
825 static inline void gen_op_eval_fbul(TCGv dst
, TCGv src
,
826 unsigned int fcc_offset
)
828 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
832 static inline void gen_op_eval_fbl(TCGv dst
, TCGv src
,
833 unsigned int fcc_offset
)
835 TCGv t0
= tcg_temp_new();
836 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
837 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
838 tcg_gen_andc_tl(dst
, dst
, t0
);
843 static inline void gen_op_eval_fbug(TCGv dst
, TCGv src
,
844 unsigned int fcc_offset
)
846 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
850 static inline void gen_op_eval_fbg(TCGv dst
, TCGv src
,
851 unsigned int fcc_offset
)
853 TCGv t0
= tcg_temp_new();
854 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
855 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
856 tcg_gen_andc_tl(dst
, t0
, dst
);
861 static inline void gen_op_eval_fbu(TCGv dst
, TCGv src
,
862 unsigned int fcc_offset
)
864 TCGv t0
= tcg_temp_new();
865 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
866 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
867 tcg_gen_and_tl(dst
, dst
, t0
);
872 static inline void gen_op_eval_fbe(TCGv dst
, TCGv src
,
873 unsigned int fcc_offset
)
875 TCGv t0
= tcg_temp_new();
876 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
877 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
878 tcg_gen_or_tl(dst
, dst
, t0
);
879 tcg_gen_xori_tl(dst
, dst
, 0x1);
883 // 0 or 3: !(FCC0 ^ FCC1)
884 static inline void gen_op_eval_fbue(TCGv dst
, TCGv src
,
885 unsigned int fcc_offset
)
887 TCGv t0
= tcg_temp_new();
888 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
889 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
890 tcg_gen_xor_tl(dst
, dst
, t0
);
891 tcg_gen_xori_tl(dst
, dst
, 0x1);
896 static inline void gen_op_eval_fbge(TCGv dst
, TCGv src
,
897 unsigned int fcc_offset
)
899 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
900 tcg_gen_xori_tl(dst
, dst
, 0x1);
903 // !1: !(FCC0 & !FCC1)
904 static inline void gen_op_eval_fbuge(TCGv dst
, TCGv src
,
905 unsigned int fcc_offset
)
907 TCGv t0
= tcg_temp_new();
908 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
909 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
910 tcg_gen_andc_tl(dst
, dst
, t0
);
911 tcg_gen_xori_tl(dst
, dst
, 0x1);
916 static inline void gen_op_eval_fble(TCGv dst
, TCGv src
,
917 unsigned int fcc_offset
)
919 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
920 tcg_gen_xori_tl(dst
, dst
, 0x1);
923 // !2: !(!FCC0 & FCC1)
924 static inline void gen_op_eval_fbule(TCGv dst
, TCGv src
,
925 unsigned int fcc_offset
)
927 TCGv t0
= tcg_temp_new();
928 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
929 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
930 tcg_gen_andc_tl(dst
, t0
, dst
);
931 tcg_gen_xori_tl(dst
, dst
, 0x1);
935 // !3: !(FCC0 & FCC1)
936 static inline void gen_op_eval_fbo(TCGv dst
, TCGv src
,
937 unsigned int fcc_offset
)
939 TCGv t0
= tcg_temp_new();
940 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
941 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
942 tcg_gen_and_tl(dst
, dst
, t0
);
943 tcg_gen_xori_tl(dst
, dst
, 0x1);
947 static inline void gen_branch2(DisasContext
*dc
, target_ulong pc1
,
948 target_ulong pc2
, TCGv r_cond
)
950 TCGLabel
*l1
= gen_new_label();
952 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_cond
, 0, l1
);
954 gen_goto_tb(dc
, 0, pc1
, pc1
+ 4);
957 gen_goto_tb(dc
, 1, pc2
, pc2
+ 4);
960 static void gen_branch_a(DisasContext
*dc
, target_ulong pc1
)
962 TCGLabel
*l1
= gen_new_label();
963 target_ulong npc
= dc
->npc
;
965 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_cond
, 0, l1
);
967 gen_goto_tb(dc
, 0, npc
, pc1
);
970 gen_goto_tb(dc
, 1, npc
+ 4, npc
+ 8);
975 static void gen_branch_n(DisasContext
*dc
, target_ulong pc1
)
977 target_ulong npc
= dc
->npc
;
979 if (likely(npc
!= DYNAMIC_PC
)) {
981 dc
->jump_pc
[0] = pc1
;
982 dc
->jump_pc
[1] = npc
+ 4;
987 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
989 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
990 t
= tcg_const_tl(pc1
);
992 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_npc
, cpu_cond
, z
, t
, cpu_npc
);
1000 static inline void gen_generic_branch(DisasContext
*dc
)
1002 TCGv npc0
= tcg_const_tl(dc
->jump_pc
[0]);
1003 TCGv npc1
= tcg_const_tl(dc
->jump_pc
[1]);
1004 TCGv zero
= tcg_const_tl(0);
1006 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_npc
, cpu_cond
, zero
, npc0
, npc1
);
1008 tcg_temp_free(npc0
);
1009 tcg_temp_free(npc1
);
1010 tcg_temp_free(zero
);
1013 /* call this function before using the condition register as it may
1014 have been set for a jump */
1015 static inline void flush_cond(DisasContext
*dc
)
1017 if (dc
->npc
== JUMP_PC
) {
1018 gen_generic_branch(dc
);
1019 dc
->npc
= DYNAMIC_PC
;
1023 static inline void save_npc(DisasContext
*dc
)
1025 if (dc
->npc
== JUMP_PC
) {
1026 gen_generic_branch(dc
);
1027 dc
->npc
= DYNAMIC_PC
;
1028 } else if (dc
->npc
!= DYNAMIC_PC
) {
1029 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
1033 static inline void update_psr(DisasContext
*dc
)
1035 if (dc
->cc_op
!= CC_OP_FLAGS
) {
1036 dc
->cc_op
= CC_OP_FLAGS
;
1037 gen_helper_compute_psr(cpu_env
);
1041 static inline void save_state(DisasContext
*dc
)
1043 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1047 static inline void gen_mov_pc_npc(DisasContext
*dc
)
1049 if (dc
->npc
== JUMP_PC
) {
1050 gen_generic_branch(dc
);
1051 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1052 dc
->pc
= DYNAMIC_PC
;
1053 } else if (dc
->npc
== DYNAMIC_PC
) {
1054 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1055 dc
->pc
= DYNAMIC_PC
;
1061 static inline void gen_op_next_insn(void)
1063 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1064 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
1067 static void free_compare(DisasCompare
*cmp
)
1070 tcg_temp_free(cmp
->c1
);
1073 tcg_temp_free(cmp
->c2
);
1077 static void gen_compare(DisasCompare
*cmp
, bool xcc
, unsigned int cond
,
1080 static int subcc_cond
[16] = {
1096 -1, /* no overflow */
1099 static int logic_cond
[16] = {
1101 TCG_COND_EQ
, /* eq: Z */
1102 TCG_COND_LE
, /* le: Z | (N ^ V) -> Z | N */
1103 TCG_COND_LT
, /* lt: N ^ V -> N */
1104 TCG_COND_EQ
, /* leu: C | Z -> Z */
1105 TCG_COND_NEVER
, /* ltu: C -> 0 */
1106 TCG_COND_LT
, /* neg: N */
1107 TCG_COND_NEVER
, /* vs: V -> 0 */
1109 TCG_COND_NE
, /* ne: !Z */
1110 TCG_COND_GT
, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1111 TCG_COND_GE
, /* ge: !(N ^ V) -> !N */
1112 TCG_COND_NE
, /* gtu: !(C | Z) -> !Z */
1113 TCG_COND_ALWAYS
, /* geu: !C -> 1 */
1114 TCG_COND_GE
, /* pos: !N */
1115 TCG_COND_ALWAYS
, /* vc: !V -> 1 */
1121 #ifdef TARGET_SPARC64
1131 switch (dc
->cc_op
) {
1133 cmp
->cond
= logic_cond
[cond
];
1135 cmp
->is_bool
= false;
1137 cmp
->c2
= tcg_const_tl(0);
1138 #ifdef TARGET_SPARC64
1141 cmp
->c1
= tcg_temp_new();
1142 tcg_gen_ext32s_tl(cmp
->c1
, cpu_cc_dst
);
1147 cmp
->c1
= cpu_cc_dst
;
1154 cmp
->cond
= (cond
== 6 ? TCG_COND_LT
: TCG_COND_GE
);
1155 goto do_compare_dst_0
;
1157 case 7: /* overflow */
1158 case 15: /* !overflow */
1162 cmp
->cond
= subcc_cond
[cond
];
1163 cmp
->is_bool
= false;
1164 #ifdef TARGET_SPARC64
1166 /* Note that sign-extension works for unsigned compares as
1167 long as both operands are sign-extended. */
1168 cmp
->g1
= cmp
->g2
= false;
1169 cmp
->c1
= tcg_temp_new();
1170 cmp
->c2
= tcg_temp_new();
1171 tcg_gen_ext32s_tl(cmp
->c1
, cpu_cc_src
);
1172 tcg_gen_ext32s_tl(cmp
->c2
, cpu_cc_src2
);
1176 cmp
->g1
= cmp
->g2
= true;
1177 cmp
->c1
= cpu_cc_src
;
1178 cmp
->c2
= cpu_cc_src2
;
1185 gen_helper_compute_psr(cpu_env
);
1186 dc
->cc_op
= CC_OP_FLAGS
;
1190 /* We're going to generate a boolean result. */
1191 cmp
->cond
= TCG_COND_NE
;
1192 cmp
->is_bool
= true;
1193 cmp
->g1
= cmp
->g2
= false;
1194 cmp
->c1
= r_dst
= tcg_temp_new();
1195 cmp
->c2
= tcg_const_tl(0);
1199 gen_op_eval_bn(r_dst
);
1202 gen_op_eval_be(r_dst
, r_src
);
1205 gen_op_eval_ble(r_dst
, r_src
);
1208 gen_op_eval_bl(r_dst
, r_src
);
1211 gen_op_eval_bleu(r_dst
, r_src
);
1214 gen_op_eval_bcs(r_dst
, r_src
);
1217 gen_op_eval_bneg(r_dst
, r_src
);
1220 gen_op_eval_bvs(r_dst
, r_src
);
1223 gen_op_eval_ba(r_dst
);
1226 gen_op_eval_bne(r_dst
, r_src
);
1229 gen_op_eval_bg(r_dst
, r_src
);
1232 gen_op_eval_bge(r_dst
, r_src
);
1235 gen_op_eval_bgu(r_dst
, r_src
);
1238 gen_op_eval_bcc(r_dst
, r_src
);
1241 gen_op_eval_bpos(r_dst
, r_src
);
1244 gen_op_eval_bvc(r_dst
, r_src
);
1251 static void gen_fcompare(DisasCompare
*cmp
, unsigned int cc
, unsigned int cond
)
1253 unsigned int offset
;
1256 /* For now we still generate a straight boolean result. */
1257 cmp
->cond
= TCG_COND_NE
;
1258 cmp
->is_bool
= true;
1259 cmp
->g1
= cmp
->g2
= false;
1260 cmp
->c1
= r_dst
= tcg_temp_new();
1261 cmp
->c2
= tcg_const_tl(0);
1281 gen_op_eval_bn(r_dst
);
1284 gen_op_eval_fbne(r_dst
, cpu_fsr
, offset
);
1287 gen_op_eval_fblg(r_dst
, cpu_fsr
, offset
);
1290 gen_op_eval_fbul(r_dst
, cpu_fsr
, offset
);
1293 gen_op_eval_fbl(r_dst
, cpu_fsr
, offset
);
1296 gen_op_eval_fbug(r_dst
, cpu_fsr
, offset
);
1299 gen_op_eval_fbg(r_dst
, cpu_fsr
, offset
);
1302 gen_op_eval_fbu(r_dst
, cpu_fsr
, offset
);
1305 gen_op_eval_ba(r_dst
);
1308 gen_op_eval_fbe(r_dst
, cpu_fsr
, offset
);
1311 gen_op_eval_fbue(r_dst
, cpu_fsr
, offset
);
1314 gen_op_eval_fbge(r_dst
, cpu_fsr
, offset
);
1317 gen_op_eval_fbuge(r_dst
, cpu_fsr
, offset
);
1320 gen_op_eval_fble(r_dst
, cpu_fsr
, offset
);
1323 gen_op_eval_fbule(r_dst
, cpu_fsr
, offset
);
1326 gen_op_eval_fbo(r_dst
, cpu_fsr
, offset
);
1331 static void gen_cond(TCGv r_dst
, unsigned int cc
, unsigned int cond
,
1335 gen_compare(&cmp
, cc
, cond
, dc
);
1337 /* The interface is to return a boolean in r_dst. */
1339 tcg_gen_mov_tl(r_dst
, cmp
.c1
);
1341 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1347 static void gen_fcond(TCGv r_dst
, unsigned int cc
, unsigned int cond
)
1350 gen_fcompare(&cmp
, cc
, cond
);
1352 /* The interface is to return a boolean in r_dst. */
1354 tcg_gen_mov_tl(r_dst
, cmp
.c1
);
1356 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1362 #ifdef TARGET_SPARC64
1364 static const int gen_tcg_cond_reg
[8] = {
1375 static void gen_compare_reg(DisasCompare
*cmp
, int cond
, TCGv r_src
)
1377 cmp
->cond
= tcg_invert_cond(gen_tcg_cond_reg
[cond
]);
1378 cmp
->is_bool
= false;
1382 cmp
->c2
= tcg_const_tl(0);
1385 static inline void gen_cond_reg(TCGv r_dst
, int cond
, TCGv r_src
)
1388 gen_compare_reg(&cmp
, cond
, r_src
);
1390 /* The interface is to return a boolean in r_dst. */
1391 tcg_gen_setcond_tl(cmp
.cond
, r_dst
, cmp
.c1
, cmp
.c2
);
1397 static void do_branch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
)
1399 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1400 target_ulong target
= dc
->pc
+ offset
;
1402 #ifdef TARGET_SPARC64
1403 if (unlikely(AM_CHECK(dc
))) {
1404 target
&= 0xffffffffULL
;
1408 /* unconditional not taken */
1410 dc
->pc
= dc
->npc
+ 4;
1411 dc
->npc
= dc
->pc
+ 4;
1414 dc
->npc
= dc
->pc
+ 4;
1416 } else if (cond
== 0x8) {
1417 /* unconditional taken */
1420 dc
->npc
= dc
->pc
+ 4;
1424 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1428 gen_cond(cpu_cond
, cc
, cond
, dc
);
1430 gen_branch_a(dc
, target
);
1432 gen_branch_n(dc
, target
);
1437 static void do_fbranch(DisasContext
*dc
, int32_t offset
, uint32_t insn
, int cc
)
1439 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
1440 target_ulong target
= dc
->pc
+ offset
;
1442 #ifdef TARGET_SPARC64
1443 if (unlikely(AM_CHECK(dc
))) {
1444 target
&= 0xffffffffULL
;
1448 /* unconditional not taken */
1450 dc
->pc
= dc
->npc
+ 4;
1451 dc
->npc
= dc
->pc
+ 4;
1454 dc
->npc
= dc
->pc
+ 4;
1456 } else if (cond
== 0x8) {
1457 /* unconditional taken */
1460 dc
->npc
= dc
->pc
+ 4;
1464 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
1468 gen_fcond(cpu_cond
, cc
, cond
);
1470 gen_branch_a(dc
, target
);
1472 gen_branch_n(dc
, target
);
1477 #ifdef TARGET_SPARC64
1478 static void do_branch_reg(DisasContext
*dc
, int32_t offset
, uint32_t insn
,
1481 unsigned int cond
= GET_FIELD_SP(insn
, 25, 27), a
= (insn
& (1 << 29));
1482 target_ulong target
= dc
->pc
+ offset
;
1484 if (unlikely(AM_CHECK(dc
))) {
1485 target
&= 0xffffffffULL
;
1488 gen_cond_reg(cpu_cond
, cond
, r_reg
);
1490 gen_branch_a(dc
, target
);
1492 gen_branch_n(dc
, target
);
1496 static inline void gen_op_fcmps(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1500 gen_helper_fcmps(cpu_env
, r_rs1
, r_rs2
);
1503 gen_helper_fcmps_fcc1(cpu_env
, r_rs1
, r_rs2
);
1506 gen_helper_fcmps_fcc2(cpu_env
, r_rs1
, r_rs2
);
1509 gen_helper_fcmps_fcc3(cpu_env
, r_rs1
, r_rs2
);
1514 static inline void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1518 gen_helper_fcmpd(cpu_env
, r_rs1
, r_rs2
);
1521 gen_helper_fcmpd_fcc1(cpu_env
, r_rs1
, r_rs2
);
1524 gen_helper_fcmpd_fcc2(cpu_env
, r_rs1
, r_rs2
);
1527 gen_helper_fcmpd_fcc3(cpu_env
, r_rs1
, r_rs2
);
1532 static inline void gen_op_fcmpq(int fccno
)
1536 gen_helper_fcmpq(cpu_env
);
1539 gen_helper_fcmpq_fcc1(cpu_env
);
1542 gen_helper_fcmpq_fcc2(cpu_env
);
1545 gen_helper_fcmpq_fcc3(cpu_env
);
1550 static inline void gen_op_fcmpes(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1554 gen_helper_fcmpes(cpu_env
, r_rs1
, r_rs2
);
1557 gen_helper_fcmpes_fcc1(cpu_env
, r_rs1
, r_rs2
);
1560 gen_helper_fcmpes_fcc2(cpu_env
, r_rs1
, r_rs2
);
1563 gen_helper_fcmpes_fcc3(cpu_env
, r_rs1
, r_rs2
);
1568 static inline void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1572 gen_helper_fcmped(cpu_env
, r_rs1
, r_rs2
);
1575 gen_helper_fcmped_fcc1(cpu_env
, r_rs1
, r_rs2
);
1578 gen_helper_fcmped_fcc2(cpu_env
, r_rs1
, r_rs2
);
1581 gen_helper_fcmped_fcc3(cpu_env
, r_rs1
, r_rs2
);
1586 static inline void gen_op_fcmpeq(int fccno
)
1590 gen_helper_fcmpeq(cpu_env
);
1593 gen_helper_fcmpeq_fcc1(cpu_env
);
1596 gen_helper_fcmpeq_fcc2(cpu_env
);
1599 gen_helper_fcmpeq_fcc3(cpu_env
);
1606 static inline void gen_op_fcmps(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1608 gen_helper_fcmps(cpu_env
, r_rs1
, r_rs2
);
1611 static inline void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1613 gen_helper_fcmpd(cpu_env
, r_rs1
, r_rs2
);
1616 static inline void gen_op_fcmpq(int fccno
)
1618 gen_helper_fcmpq(cpu_env
);
1621 static inline void gen_op_fcmpes(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1623 gen_helper_fcmpes(cpu_env
, r_rs1
, r_rs2
);
1626 static inline void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1628 gen_helper_fcmped(cpu_env
, r_rs1
, r_rs2
);
1631 static inline void gen_op_fcmpeq(int fccno
)
1633 gen_helper_fcmpeq(cpu_env
);
1637 static inline void gen_op_fpexception_im(int fsr_flags
)
1641 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_NMASK
);
1642 tcg_gen_ori_tl(cpu_fsr
, cpu_fsr
, fsr_flags
);
1643 r_const
= tcg_const_i32(TT_FP_EXCP
);
1644 gen_helper_raise_exception(cpu_env
, r_const
);
1645 tcg_temp_free_i32(r_const
);
1648 static int gen_trap_ifnofpu(DisasContext
*dc
)
1650 #if !defined(CONFIG_USER_ONLY)
1651 if (!dc
->fpu_enabled
) {
1655 r_const
= tcg_const_i32(TT_NFPU_INSN
);
1656 gen_helper_raise_exception(cpu_env
, r_const
);
1657 tcg_temp_free_i32(r_const
);
1665 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1667 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_CEXC_NMASK
);
1670 static inline void gen_fop_FF(DisasContext
*dc
, int rd
, int rs
,
1671 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i32
))
1675 src
= gen_load_fpr_F(dc
, rs
);
1676 dst
= gen_dest_fpr_F(dc
);
1678 gen(dst
, cpu_env
, src
);
1680 gen_store_fpr_F(dc
, rd
, dst
);
1683 static inline void gen_ne_fop_FF(DisasContext
*dc
, int rd
, int rs
,
1684 void (*gen
)(TCGv_i32
, TCGv_i32
))
1688 src
= gen_load_fpr_F(dc
, rs
);
1689 dst
= gen_dest_fpr_F(dc
);
1693 gen_store_fpr_F(dc
, rd
, dst
);
1696 static inline void gen_fop_FFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1697 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
))
1699 TCGv_i32 dst
, src1
, src2
;
1701 src1
= gen_load_fpr_F(dc
, rs1
);
1702 src2
= gen_load_fpr_F(dc
, rs2
);
1703 dst
= gen_dest_fpr_F(dc
);
1705 gen(dst
, cpu_env
, src1
, src2
);
1707 gen_store_fpr_F(dc
, rd
, dst
);
1710 #ifdef TARGET_SPARC64
1711 static inline void gen_ne_fop_FFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1712 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
1714 TCGv_i32 dst
, src1
, src2
;
1716 src1
= gen_load_fpr_F(dc
, rs1
);
1717 src2
= gen_load_fpr_F(dc
, rs2
);
1718 dst
= gen_dest_fpr_F(dc
);
1720 gen(dst
, src1
, src2
);
1722 gen_store_fpr_F(dc
, rd
, dst
);
1726 static inline void gen_fop_DD(DisasContext
*dc
, int rd
, int rs
,
1727 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i64
))
1731 src
= gen_load_fpr_D(dc
, rs
);
1732 dst
= gen_dest_fpr_D(dc
, rd
);
1734 gen(dst
, cpu_env
, src
);
1736 gen_store_fpr_D(dc
, rd
, dst
);
1739 #ifdef TARGET_SPARC64
1740 static inline void gen_ne_fop_DD(DisasContext
*dc
, int rd
, int rs
,
1741 void (*gen
)(TCGv_i64
, TCGv_i64
))
1745 src
= gen_load_fpr_D(dc
, rs
);
1746 dst
= gen_dest_fpr_D(dc
, rd
);
1750 gen_store_fpr_D(dc
, rd
, dst
);
1754 static inline void gen_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1755 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
))
1757 TCGv_i64 dst
, src1
, src2
;
1759 src1
= gen_load_fpr_D(dc
, rs1
);
1760 src2
= gen_load_fpr_D(dc
, rs2
);
1761 dst
= gen_dest_fpr_D(dc
, rd
);
1763 gen(dst
, cpu_env
, src1
, src2
);
1765 gen_store_fpr_D(dc
, rd
, dst
);
1768 #ifdef TARGET_SPARC64
1769 static inline void gen_ne_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1770 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
))
1772 TCGv_i64 dst
, src1
, src2
;
1774 src1
= gen_load_fpr_D(dc
, rs1
);
1775 src2
= gen_load_fpr_D(dc
, rs2
);
1776 dst
= gen_dest_fpr_D(dc
, rd
);
1778 gen(dst
, src1
, src2
);
1780 gen_store_fpr_D(dc
, rd
, dst
);
1783 static inline void gen_gsr_fop_DDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1784 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
1786 TCGv_i64 dst
, src1
, src2
;
1788 src1
= gen_load_fpr_D(dc
, rs1
);
1789 src2
= gen_load_fpr_D(dc
, rs2
);
1790 dst
= gen_dest_fpr_D(dc
, rd
);
1792 gen(dst
, cpu_gsr
, src1
, src2
);
1794 gen_store_fpr_D(dc
, rd
, dst
);
1797 static inline void gen_ne_fop_DDDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1798 void (*gen
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
1800 TCGv_i64 dst
, src0
, src1
, src2
;
1802 src1
= gen_load_fpr_D(dc
, rs1
);
1803 src2
= gen_load_fpr_D(dc
, rs2
);
1804 src0
= gen_load_fpr_D(dc
, rd
);
1805 dst
= gen_dest_fpr_D(dc
, rd
);
1807 gen(dst
, src0
, src1
, src2
);
1809 gen_store_fpr_D(dc
, rd
, dst
);
1813 static inline void gen_fop_QQ(DisasContext
*dc
, int rd
, int rs
,
1814 void (*gen
)(TCGv_ptr
))
1816 gen_op_load_fpr_QT1(QFPREG(rs
));
1820 gen_op_store_QT0_fpr(QFPREG(rd
));
1821 gen_update_fprs_dirty(QFPREG(rd
));
1824 #ifdef TARGET_SPARC64
1825 static inline void gen_ne_fop_QQ(DisasContext
*dc
, int rd
, int rs
,
1826 void (*gen
)(TCGv_ptr
))
1828 gen_op_load_fpr_QT1(QFPREG(rs
));
1832 gen_op_store_QT0_fpr(QFPREG(rd
));
1833 gen_update_fprs_dirty(QFPREG(rd
));
1837 static inline void gen_fop_QQQ(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1838 void (*gen
)(TCGv_ptr
))
1840 gen_op_load_fpr_QT0(QFPREG(rs1
));
1841 gen_op_load_fpr_QT1(QFPREG(rs2
));
1845 gen_op_store_QT0_fpr(QFPREG(rd
));
1846 gen_update_fprs_dirty(QFPREG(rd
));
1849 static inline void gen_fop_DFF(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1850 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
, TCGv_i32
))
1853 TCGv_i32 src1
, src2
;
1855 src1
= gen_load_fpr_F(dc
, rs1
);
1856 src2
= gen_load_fpr_F(dc
, rs2
);
1857 dst
= gen_dest_fpr_D(dc
, rd
);
1859 gen(dst
, cpu_env
, src1
, src2
);
1861 gen_store_fpr_D(dc
, rd
, dst
);
1864 static inline void gen_fop_QDD(DisasContext
*dc
, int rd
, int rs1
, int rs2
,
1865 void (*gen
)(TCGv_ptr
, TCGv_i64
, TCGv_i64
))
1867 TCGv_i64 src1
, src2
;
1869 src1
= gen_load_fpr_D(dc
, rs1
);
1870 src2
= gen_load_fpr_D(dc
, rs2
);
1872 gen(cpu_env
, src1
, src2
);
1874 gen_op_store_QT0_fpr(QFPREG(rd
));
1875 gen_update_fprs_dirty(QFPREG(rd
));
1878 #ifdef TARGET_SPARC64
1879 static inline void gen_fop_DF(DisasContext
*dc
, int rd
, int rs
,
1880 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
))
1885 src
= gen_load_fpr_F(dc
, rs
);
1886 dst
= gen_dest_fpr_D(dc
, rd
);
1888 gen(dst
, cpu_env
, src
);
1890 gen_store_fpr_D(dc
, rd
, dst
);
1894 static inline void gen_ne_fop_DF(DisasContext
*dc
, int rd
, int rs
,
1895 void (*gen
)(TCGv_i64
, TCGv_ptr
, TCGv_i32
))
1900 src
= gen_load_fpr_F(dc
, rs
);
1901 dst
= gen_dest_fpr_D(dc
, rd
);
1903 gen(dst
, cpu_env
, src
);
1905 gen_store_fpr_D(dc
, rd
, dst
);
1908 static inline void gen_fop_FD(DisasContext
*dc
, int rd
, int rs
,
1909 void (*gen
)(TCGv_i32
, TCGv_ptr
, TCGv_i64
))
1914 src
= gen_load_fpr_D(dc
, rs
);
1915 dst
= gen_dest_fpr_F(dc
);
1917 gen(dst
, cpu_env
, src
);
1919 gen_store_fpr_F(dc
, rd
, dst
);
1922 static inline void gen_fop_FQ(DisasContext
*dc
, int rd
, int rs
,
1923 void (*gen
)(TCGv_i32
, TCGv_ptr
))
1927 gen_op_load_fpr_QT1(QFPREG(rs
));
1928 dst
= gen_dest_fpr_F(dc
);
1932 gen_store_fpr_F(dc
, rd
, dst
);
1935 static inline void gen_fop_DQ(DisasContext
*dc
, int rd
, int rs
,
1936 void (*gen
)(TCGv_i64
, TCGv_ptr
))
1940 gen_op_load_fpr_QT1(QFPREG(rs
));
1941 dst
= gen_dest_fpr_D(dc
, rd
);
1945 gen_store_fpr_D(dc
, rd
, dst
);
1948 static inline void gen_ne_fop_QF(DisasContext
*dc
, int rd
, int rs
,
1949 void (*gen
)(TCGv_ptr
, TCGv_i32
))
1953 src
= gen_load_fpr_F(dc
, rs
);
1957 gen_op_store_QT0_fpr(QFPREG(rd
));
1958 gen_update_fprs_dirty(QFPREG(rd
));
1961 static inline void gen_ne_fop_QD(DisasContext
*dc
, int rd
, int rs
,
1962 void (*gen
)(TCGv_ptr
, TCGv_i64
))
1966 src
= gen_load_fpr_D(dc
, rs
);
1970 gen_op_store_QT0_fpr(QFPREG(rd
));
1971 gen_update_fprs_dirty(QFPREG(rd
));
1975 #ifdef TARGET_SPARC64
1976 static inline TCGv_i32
gen_get_asi(int insn
, TCGv r_addr
)
1982 r_asi
= tcg_temp_new_i32();
1983 tcg_gen_mov_i32(r_asi
, cpu_asi
);
1985 asi
= GET_FIELD(insn
, 19, 26);
1986 r_asi
= tcg_const_i32(asi
);
1991 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
1994 TCGv_i32 r_asi
, r_size
, r_sign
;
1996 r_asi
= gen_get_asi(insn
, addr
);
1997 r_size
= tcg_const_i32(size
);
1998 r_sign
= tcg_const_i32(sign
);
1999 gen_helper_ld_asi(dst
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2000 tcg_temp_free_i32(r_sign
);
2001 tcg_temp_free_i32(r_size
);
2002 tcg_temp_free_i32(r_asi
);
2005 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
2007 TCGv_i32 r_asi
, r_size
;
2009 r_asi
= gen_get_asi(insn
, addr
);
2010 r_size
= tcg_const_i32(size
);
2011 gen_helper_st_asi(cpu_env
, addr
, src
, r_asi
, r_size
);
2012 tcg_temp_free_i32(r_size
);
2013 tcg_temp_free_i32(r_asi
);
2016 static inline void gen_ldf_asi(TCGv addr
, int insn
, int size
, int rd
)
2018 TCGv_i32 r_asi
, r_size
, r_rd
;
2020 r_asi
= gen_get_asi(insn
, addr
);
2021 r_size
= tcg_const_i32(size
);
2022 r_rd
= tcg_const_i32(rd
);
2023 gen_helper_ldf_asi(cpu_env
, addr
, r_asi
, r_size
, r_rd
);
2024 tcg_temp_free_i32(r_rd
);
2025 tcg_temp_free_i32(r_size
);
2026 tcg_temp_free_i32(r_asi
);
2029 static inline void gen_stf_asi(TCGv addr
, int insn
, int size
, int rd
)
2031 TCGv_i32 r_asi
, r_size
, r_rd
;
2033 r_asi
= gen_get_asi(insn
, addr
);
2034 r_size
= tcg_const_i32(size
);
2035 r_rd
= tcg_const_i32(rd
);
2036 gen_helper_stf_asi(cpu_env
, addr
, r_asi
, r_size
, r_rd
);
2037 tcg_temp_free_i32(r_rd
);
2038 tcg_temp_free_i32(r_size
);
2039 tcg_temp_free_i32(r_asi
);
2042 static inline void gen_swap_asi(TCGv dst
, TCGv src
, TCGv addr
, int insn
)
2044 TCGv_i32 r_asi
, r_size
, r_sign
;
2045 TCGv_i64 t64
= tcg_temp_new_i64();
2047 r_asi
= gen_get_asi(insn
, addr
);
2048 r_size
= tcg_const_i32(4);
2049 r_sign
= tcg_const_i32(0);
2050 gen_helper_ld_asi(t64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2051 tcg_temp_free_i32(r_sign
);
2052 gen_helper_st_asi(cpu_env
, addr
, src
, r_asi
, r_size
);
2053 tcg_temp_free_i32(r_size
);
2054 tcg_temp_free_i32(r_asi
);
2055 tcg_gen_trunc_i64_tl(dst
, t64
);
2056 tcg_temp_free_i64(t64
);
2059 static inline void gen_ldda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2062 TCGv_i32 r_asi
, r_rd
;
2064 r_asi
= gen_get_asi(insn
, addr
);
2065 r_rd
= tcg_const_i32(rd
);
2066 gen_helper_ldda_asi(cpu_env
, addr
, r_asi
, r_rd
);
2067 tcg_temp_free_i32(r_rd
);
2068 tcg_temp_free_i32(r_asi
);
2071 static inline void gen_stda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2074 TCGv_i32 r_asi
, r_size
;
2075 TCGv lo
= gen_load_gpr(dc
, rd
+ 1);
2076 TCGv_i64 t64
= tcg_temp_new_i64();
2078 tcg_gen_concat_tl_i64(t64
, lo
, hi
);
2079 r_asi
= gen_get_asi(insn
, addr
);
2080 r_size
= tcg_const_i32(8);
2081 gen_helper_st_asi(cpu_env
, addr
, t64
, r_asi
, r_size
);
2082 tcg_temp_free_i32(r_size
);
2083 tcg_temp_free_i32(r_asi
);
2084 tcg_temp_free_i64(t64
);
2087 static inline void gen_casx_asi(DisasContext
*dc
, TCGv addr
,
2088 TCGv val2
, int insn
, int rd
)
2090 TCGv val1
= gen_load_gpr(dc
, rd
);
2091 TCGv dst
= gen_dest_gpr(dc
, rd
);
2092 TCGv_i32 r_asi
= gen_get_asi(insn
, addr
);
2094 gen_helper_casx_asi(dst
, cpu_env
, addr
, val1
, val2
, r_asi
);
2095 tcg_temp_free_i32(r_asi
);
2096 gen_store_gpr(dc
, rd
, dst
);
2099 #elif !defined(CONFIG_USER_ONLY)
2101 static inline void gen_ld_asi(TCGv dst
, TCGv addr
, int insn
, int size
,
2104 TCGv_i32 r_asi
, r_size
, r_sign
;
2105 TCGv_i64 t64
= tcg_temp_new_i64();
2107 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2108 r_size
= tcg_const_i32(size
);
2109 r_sign
= tcg_const_i32(sign
);
2110 gen_helper_ld_asi(t64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2111 tcg_temp_free_i32(r_sign
);
2112 tcg_temp_free_i32(r_size
);
2113 tcg_temp_free_i32(r_asi
);
2114 tcg_gen_trunc_i64_tl(dst
, t64
);
2115 tcg_temp_free_i64(t64
);
2118 static inline void gen_st_asi(TCGv src
, TCGv addr
, int insn
, int size
)
2120 TCGv_i32 r_asi
, r_size
;
2121 TCGv_i64 t64
= tcg_temp_new_i64();
2123 tcg_gen_extu_tl_i64(t64
, src
);
2124 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2125 r_size
= tcg_const_i32(size
);
2126 gen_helper_st_asi(cpu_env
, addr
, t64
, r_asi
, r_size
);
2127 tcg_temp_free_i32(r_size
);
2128 tcg_temp_free_i32(r_asi
);
2129 tcg_temp_free_i64(t64
);
2132 static inline void gen_swap_asi(TCGv dst
, TCGv src
, TCGv addr
, int insn
)
2134 TCGv_i32 r_asi
, r_size
, r_sign
;
2135 TCGv_i64 r_val
, t64
;
2137 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2138 r_size
= tcg_const_i32(4);
2139 r_sign
= tcg_const_i32(0);
2140 t64
= tcg_temp_new_i64();
2141 gen_helper_ld_asi(t64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2142 tcg_temp_free(r_sign
);
2143 r_val
= tcg_temp_new_i64();
2144 tcg_gen_extu_tl_i64(r_val
, src
);
2145 gen_helper_st_asi(cpu_env
, addr
, r_val
, r_asi
, r_size
);
2146 tcg_temp_free_i64(r_val
);
2147 tcg_temp_free_i32(r_size
);
2148 tcg_temp_free_i32(r_asi
);
2149 tcg_gen_trunc_i64_tl(dst
, t64
);
2150 tcg_temp_free_i64(t64
);
2153 static inline void gen_ldda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2156 TCGv_i32 r_asi
, r_size
, r_sign
;
2160 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2161 r_size
= tcg_const_i32(8);
2162 r_sign
= tcg_const_i32(0);
2163 t64
= tcg_temp_new_i64();
2164 gen_helper_ld_asi(t64
, cpu_env
, addr
, r_asi
, r_size
, r_sign
);
2165 tcg_temp_free_i32(r_sign
);
2166 tcg_temp_free_i32(r_size
);
2167 tcg_temp_free_i32(r_asi
);
2169 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2170 whereby "rd + 1" elicits "error: array subscript is above array".
2171 Since we have already asserted that rd is even, the semantics
2173 t
= gen_dest_gpr(dc
, rd
| 1);
2174 tcg_gen_trunc_i64_tl(t
, t64
);
2175 gen_store_gpr(dc
, rd
| 1, t
);
2177 tcg_gen_shri_i64(t64
, t64
, 32);
2178 tcg_gen_trunc_i64_tl(hi
, t64
);
2179 tcg_temp_free_i64(t64
);
2180 gen_store_gpr(dc
, rd
, hi
);
2183 static inline void gen_stda_asi(DisasContext
*dc
, TCGv hi
, TCGv addr
,
2186 TCGv_i32 r_asi
, r_size
;
2187 TCGv lo
= gen_load_gpr(dc
, rd
+ 1);
2188 TCGv_i64 t64
= tcg_temp_new_i64();
2190 tcg_gen_concat_tl_i64(t64
, lo
, hi
);
2191 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2192 r_size
= tcg_const_i32(8);
2193 gen_helper_st_asi(cpu_env
, addr
, t64
, r_asi
, r_size
);
2194 tcg_temp_free_i32(r_size
);
2195 tcg_temp_free_i32(r_asi
);
2196 tcg_temp_free_i64(t64
);
2200 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2201 static inline void gen_cas_asi(DisasContext
*dc
, TCGv addr
,
2202 TCGv val2
, int insn
, int rd
)
2204 TCGv val1
= gen_load_gpr(dc
, rd
);
2205 TCGv dst
= gen_dest_gpr(dc
, rd
);
2206 #ifdef TARGET_SPARC64
2207 TCGv_i32 r_asi
= gen_get_asi(insn
, addr
);
2209 TCGv_i32 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2212 gen_helper_cas_asi(dst
, cpu_env
, addr
, val1
, val2
, r_asi
);
2213 tcg_temp_free_i32(r_asi
);
2214 gen_store_gpr(dc
, rd
, dst
);
2217 static inline void gen_ldstub_asi(TCGv dst
, TCGv addr
, int insn
)
2220 TCGv_i32 r_asi
, r_size
;
2222 gen_ld_asi(dst
, addr
, insn
, 1, 0);
2224 r_val
= tcg_const_i64(0xffULL
);
2225 r_asi
= tcg_const_i32(GET_FIELD(insn
, 19, 26));
2226 r_size
= tcg_const_i32(1);
2227 gen_helper_st_asi(cpu_env
, addr
, r_val
, r_asi
, r_size
);
2228 tcg_temp_free_i32(r_size
);
2229 tcg_temp_free_i32(r_asi
);
2230 tcg_temp_free_i64(r_val
);
2234 static TCGv
get_src1(DisasContext
*dc
, unsigned int insn
)
2236 unsigned int rs1
= GET_FIELD(insn
, 13, 17);
2237 return gen_load_gpr(dc
, rs1
);
2240 static TCGv
get_src2(DisasContext
*dc
, unsigned int insn
)
2242 if (IS_IMM
) { /* immediate */
2243 target_long simm
= GET_FIELDs(insn
, 19, 31);
2244 TCGv t
= get_temp_tl(dc
);
2245 tcg_gen_movi_tl(t
, simm
);
2247 } else { /* register */
2248 unsigned int rs2
= GET_FIELD(insn
, 27, 31);
2249 return gen_load_gpr(dc
, rs2
);
2253 #ifdef TARGET_SPARC64
2254 static void gen_fmovs(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2256 TCGv_i32 c32
, zero
, dst
, s1
, s2
;
2258 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2259 or fold the comparison down to 32 bits and use movcond_i32. Choose
2261 c32
= tcg_temp_new_i32();
2263 tcg_gen_extrl_i64_i32(c32
, cmp
->c1
);
2265 TCGv_i64 c64
= tcg_temp_new_i64();
2266 tcg_gen_setcond_i64(cmp
->cond
, c64
, cmp
->c1
, cmp
->c2
);
2267 tcg_gen_extrl_i64_i32(c32
, c64
);
2268 tcg_temp_free_i64(c64
);
2271 s1
= gen_load_fpr_F(dc
, rs
);
2272 s2
= gen_load_fpr_F(dc
, rd
);
2273 dst
= gen_dest_fpr_F(dc
);
2274 zero
= tcg_const_i32(0);
2276 tcg_gen_movcond_i32(TCG_COND_NE
, dst
, c32
, zero
, s1
, s2
);
2278 tcg_temp_free_i32(c32
);
2279 tcg_temp_free_i32(zero
);
2280 gen_store_fpr_F(dc
, rd
, dst
);
2283 static void gen_fmovd(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2285 TCGv_i64 dst
= gen_dest_fpr_D(dc
, rd
);
2286 tcg_gen_movcond_i64(cmp
->cond
, dst
, cmp
->c1
, cmp
->c2
,
2287 gen_load_fpr_D(dc
, rs
),
2288 gen_load_fpr_D(dc
, rd
));
2289 gen_store_fpr_D(dc
, rd
, dst
);
2292 static void gen_fmovq(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2294 int qd
= QFPREG(rd
);
2295 int qs
= QFPREG(rs
);
2297 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2], cmp
->c1
, cmp
->c2
,
2298 cpu_fpr
[qs
/ 2], cpu_fpr
[qd
/ 2]);
2299 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2 + 1], cmp
->c1
, cmp
->c2
,
2300 cpu_fpr
[qs
/ 2 + 1], cpu_fpr
[qd
/ 2 + 1]);
2302 gen_update_fprs_dirty(qd
);
2305 #ifndef CONFIG_USER_ONLY
2306 static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr
, TCGv_env cpu_env
)
2308 TCGv_i32 r_tl
= tcg_temp_new_i32();
2310 /* load env->tl into r_tl */
2311 tcg_gen_ld_i32(r_tl
, cpu_env
, offsetof(CPUSPARCState
, tl
));
2313 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2314 tcg_gen_andi_i32(r_tl
, r_tl
, MAXTL_MASK
);
2316 /* calculate offset to current trap state from env->ts, reuse r_tl */
2317 tcg_gen_muli_i32(r_tl
, r_tl
, sizeof (trap_state
));
2318 tcg_gen_addi_ptr(r_tsptr
, cpu_env
, offsetof(CPUSPARCState
, ts
));
2320 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2322 TCGv_ptr r_tl_tmp
= tcg_temp_new_ptr();
2323 tcg_gen_ext_i32_ptr(r_tl_tmp
, r_tl
);
2324 tcg_gen_add_ptr(r_tsptr
, r_tsptr
, r_tl_tmp
);
2325 tcg_temp_free_ptr(r_tl_tmp
);
2328 tcg_temp_free_i32(r_tl
);
2332 static void gen_edge(DisasContext
*dc
, TCGv dst
, TCGv s1
, TCGv s2
,
2333 int width
, bool cc
, bool left
)
2335 TCGv lo1
, lo2
, t1
, t2
;
2336 uint64_t amask
, tabl
, tabr
;
2337 int shift
, imask
, omask
;
2340 tcg_gen_mov_tl(cpu_cc_src
, s1
);
2341 tcg_gen_mov_tl(cpu_cc_src2
, s2
);
2342 tcg_gen_sub_tl(cpu_cc_dst
, s1
, s2
);
2343 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
2344 dc
->cc_op
= CC_OP_SUB
;
2347 /* Theory of operation: there are two tables, left and right (not to
2348 be confused with the left and right versions of the opcode). These
2349 are indexed by the low 3 bits of the inputs. To make things "easy",
2350 these tables are loaded into two constants, TABL and TABR below.
2351 The operation index = (input & imask) << shift calculates the index
2352 into the constant, while val = (table >> index) & omask calculates
2353 the value we're looking for. */
2360 tabl
= 0x80c0e0f0f8fcfeffULL
;
2361 tabr
= 0xff7f3f1f0f070301ULL
;
2363 tabl
= 0x0103070f1f3f7fffULL
;
2364 tabr
= 0xfffefcf8f0e0c080ULL
;
2384 tabl
= (2 << 2) | 3;
2385 tabr
= (3 << 2) | 1;
2387 tabl
= (1 << 2) | 3;
2388 tabr
= (3 << 2) | 2;
2395 lo1
= tcg_temp_new();
2396 lo2
= tcg_temp_new();
2397 tcg_gen_andi_tl(lo1
, s1
, imask
);
2398 tcg_gen_andi_tl(lo2
, s2
, imask
);
2399 tcg_gen_shli_tl(lo1
, lo1
, shift
);
2400 tcg_gen_shli_tl(lo2
, lo2
, shift
);
2402 t1
= tcg_const_tl(tabl
);
2403 t2
= tcg_const_tl(tabr
);
2404 tcg_gen_shr_tl(lo1
, t1
, lo1
);
2405 tcg_gen_shr_tl(lo2
, t2
, lo2
);
2406 tcg_gen_andi_tl(dst
, lo1
, omask
);
2407 tcg_gen_andi_tl(lo2
, lo2
, omask
);
2411 amask
&= 0xffffffffULL
;
2413 tcg_gen_andi_tl(s1
, s1
, amask
);
2414 tcg_gen_andi_tl(s2
, s2
, amask
);
2416 /* We want to compute
2417 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2418 We've already done dst = lo1, so this reduces to
2419 dst &= (s1 == s2 ? -1 : lo2)
2424 tcg_gen_setcond_tl(TCG_COND_EQ
, t1
, s1
, s2
);
2425 tcg_gen_neg_tl(t1
, t1
);
2426 tcg_gen_or_tl(lo2
, lo2
, t1
);
2427 tcg_gen_and_tl(dst
, dst
, lo2
);
2435 static void gen_alignaddr(TCGv dst
, TCGv s1
, TCGv s2
, bool left
)
2437 TCGv tmp
= tcg_temp_new();
2439 tcg_gen_add_tl(tmp
, s1
, s2
);
2440 tcg_gen_andi_tl(dst
, tmp
, -8);
2442 tcg_gen_neg_tl(tmp
, tmp
);
2444 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, tmp
, 0, 3);
2449 static void gen_faligndata(TCGv dst
, TCGv gsr
, TCGv s1
, TCGv s2
)
2453 t1
= tcg_temp_new();
2454 t2
= tcg_temp_new();
2455 shift
= tcg_temp_new();
2457 tcg_gen_andi_tl(shift
, gsr
, 7);
2458 tcg_gen_shli_tl(shift
, shift
, 3);
2459 tcg_gen_shl_tl(t1
, s1
, shift
);
2461 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2462 shift of (up to 63) followed by a constant shift of 1. */
2463 tcg_gen_xori_tl(shift
, shift
, 63);
2464 tcg_gen_shr_tl(t2
, s2
, shift
);
2465 tcg_gen_shri_tl(t2
, t2
, 1);
2467 tcg_gen_or_tl(dst
, t1
, t2
);
2471 tcg_temp_free(shift
);
2475 #define CHECK_IU_FEATURE(dc, FEATURE) \
2476 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2478 #define CHECK_FPU_FEATURE(dc, FEATURE) \
2479 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2482 /* before an instruction, dc->pc must be static */
2483 static void disas_sparc_insn(DisasContext
* dc
, unsigned int insn
)
2485 unsigned int opc
, rs1
, rs2
, rd
;
2486 TCGv cpu_src1
, cpu_src2
;
2487 TCGv_i32 cpu_src1_32
, cpu_src2_32
, cpu_dst_32
;
2488 TCGv_i64 cpu_src1_64
, cpu_src2_64
, cpu_dst_64
;
2491 opc
= GET_FIELD(insn
, 0, 1);
2492 rd
= GET_FIELD(insn
, 2, 6);
2495 case 0: /* branches/sethi */
2497 unsigned int xop
= GET_FIELD(insn
, 7, 9);
2500 #ifdef TARGET_SPARC64
2501 case 0x1: /* V9 BPcc */
2505 target
= GET_FIELD_SP(insn
, 0, 18);
2506 target
= sign_extend(target
, 19);
2508 cc
= GET_FIELD_SP(insn
, 20, 21);
2510 do_branch(dc
, target
, insn
, 0);
2512 do_branch(dc
, target
, insn
, 1);
2517 case 0x3: /* V9 BPr */
2519 target
= GET_FIELD_SP(insn
, 0, 13) |
2520 (GET_FIELD_SP(insn
, 20, 21) << 14);
2521 target
= sign_extend(target
, 16);
2523 cpu_src1
= get_src1(dc
, insn
);
2524 do_branch_reg(dc
, target
, insn
, cpu_src1
);
2527 case 0x5: /* V9 FBPcc */
2529 int cc
= GET_FIELD_SP(insn
, 20, 21);
2530 if (gen_trap_ifnofpu(dc
)) {
2533 target
= GET_FIELD_SP(insn
, 0, 18);
2534 target
= sign_extend(target
, 19);
2536 do_fbranch(dc
, target
, insn
, cc
);
2540 case 0x7: /* CBN+x */
2545 case 0x2: /* BN+x */
2547 target
= GET_FIELD(insn
, 10, 31);
2548 target
= sign_extend(target
, 22);
2550 do_branch(dc
, target
, insn
, 0);
2553 case 0x6: /* FBN+x */
2555 if (gen_trap_ifnofpu(dc
)) {
2558 target
= GET_FIELD(insn
, 10, 31);
2559 target
= sign_extend(target
, 22);
2561 do_fbranch(dc
, target
, insn
, 0);
2564 case 0x4: /* SETHI */
2565 /* Special-case %g0 because that's the canonical nop. */
2567 uint32_t value
= GET_FIELD(insn
, 10, 31);
2568 TCGv t
= gen_dest_gpr(dc
, rd
);
2569 tcg_gen_movi_tl(t
, value
<< 10);
2570 gen_store_gpr(dc
, rd
, t
);
2573 case 0x0: /* UNIMPL */
2582 target_long target
= GET_FIELDs(insn
, 2, 31) << 2;
2583 TCGv o7
= gen_dest_gpr(dc
, 15);
2585 tcg_gen_movi_tl(o7
, dc
->pc
);
2586 gen_store_gpr(dc
, 15, o7
);
2589 #ifdef TARGET_SPARC64
2590 if (unlikely(AM_CHECK(dc
))) {
2591 target
&= 0xffffffffULL
;
2597 case 2: /* FPU & Logical Operations */
2599 unsigned int xop
= GET_FIELD(insn
, 7, 12);
2600 TCGv cpu_dst
= get_temp_tl(dc
);
2603 if (xop
== 0x3a) { /* generate trap */
2604 int cond
= GET_FIELD(insn
, 3, 6);
2606 TCGLabel
*l1
= NULL
;
2617 /* Conditional trap. */
2619 #ifdef TARGET_SPARC64
2621 int cc
= GET_FIELD_SP(insn
, 11, 12);
2623 gen_compare(&cmp
, 0, cond
, dc
);
2624 } else if (cc
== 2) {
2625 gen_compare(&cmp
, 1, cond
, dc
);
2630 gen_compare(&cmp
, 0, cond
, dc
);
2632 l1
= gen_new_label();
2633 tcg_gen_brcond_tl(tcg_invert_cond(cmp
.cond
),
2634 cmp
.c1
, cmp
.c2
, l1
);
2638 mask
= ((dc
->def
->features
& CPU_FEATURE_HYPV
) && supervisor(dc
)
2639 ? UA2005_HTRAP_MASK
: V8_TRAP_MASK
);
2641 /* Don't use the normal temporaries, as they may well have
2642 gone out of scope with the branch above. While we're
2643 doing that we might as well pre-truncate to 32-bit. */
2644 trap
= tcg_temp_new_i32();
2646 rs1
= GET_FIELD_SP(insn
, 14, 18);
2648 rs2
= GET_FIELD_SP(insn
, 0, 6);
2650 tcg_gen_movi_i32(trap
, (rs2
& mask
) + TT_TRAP
);
2651 /* Signal that the trap value is fully constant. */
2654 TCGv t1
= gen_load_gpr(dc
, rs1
);
2655 tcg_gen_trunc_tl_i32(trap
, t1
);
2656 tcg_gen_addi_i32(trap
, trap
, rs2
);
2660 rs2
= GET_FIELD_SP(insn
, 0, 4);
2661 t1
= gen_load_gpr(dc
, rs1
);
2662 t2
= gen_load_gpr(dc
, rs2
);
2663 tcg_gen_add_tl(t1
, t1
, t2
);
2664 tcg_gen_trunc_tl_i32(trap
, t1
);
2667 tcg_gen_andi_i32(trap
, trap
, mask
);
2668 tcg_gen_addi_i32(trap
, trap
, TT_TRAP
);
2671 gen_helper_raise_exception(cpu_env
, trap
);
2672 tcg_temp_free_i32(trap
);
2675 /* An unconditional trap ends the TB. */
2679 /* A conditional trap falls through to the next insn. */
2683 } else if (xop
== 0x28) {
2684 rs1
= GET_FIELD(insn
, 13, 17);
2687 #ifndef TARGET_SPARC64
2688 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2689 manual, rdy on the microSPARC
2691 case 0x0f: /* stbar in the SPARCv8 manual,
2692 rdy on the microSPARC II */
2693 case 0x10 ... 0x1f: /* implementation-dependent in the
2694 SPARCv8 manual, rdy on the
2697 if (rs1
== 0x11 && dc
->def
->features
& CPU_FEATURE_ASR17
) {
2698 TCGv t
= gen_dest_gpr(dc
, rd
);
2699 /* Read Asr17 for a Leon3 monoprocessor */
2700 tcg_gen_movi_tl(t
, (1 << 8) | (dc
->def
->nwindows
- 1));
2701 gen_store_gpr(dc
, rd
, t
);
2705 gen_store_gpr(dc
, rd
, cpu_y
);
2707 #ifdef TARGET_SPARC64
2708 case 0x2: /* V9 rdccr */
2710 gen_helper_rdccr(cpu_dst
, cpu_env
);
2711 gen_store_gpr(dc
, rd
, cpu_dst
);
2713 case 0x3: /* V9 rdasi */
2714 tcg_gen_ext_i32_tl(cpu_dst
, cpu_asi
);
2715 gen_store_gpr(dc
, rd
, cpu_dst
);
2717 case 0x4: /* V9 rdtick */
2722 r_tickptr
= tcg_temp_new_ptr();
2723 r_const
= tcg_const_i32(dc
->mem_idx
);
2724 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2725 offsetof(CPUSPARCState
, tick
));
2726 gen_helper_tick_get_count(cpu_dst
, cpu_env
, r_tickptr
,
2728 tcg_temp_free_ptr(r_tickptr
);
2729 tcg_temp_free_i32(r_const
);
2730 gen_store_gpr(dc
, rd
, cpu_dst
);
2733 case 0x5: /* V9 rdpc */
2735 TCGv t
= gen_dest_gpr(dc
, rd
);
2736 if (unlikely(AM_CHECK(dc
))) {
2737 tcg_gen_movi_tl(t
, dc
->pc
& 0xffffffffULL
);
2739 tcg_gen_movi_tl(t
, dc
->pc
);
2741 gen_store_gpr(dc
, rd
, t
);
2744 case 0x6: /* V9 rdfprs */
2745 tcg_gen_ext_i32_tl(cpu_dst
, cpu_fprs
);
2746 gen_store_gpr(dc
, rd
, cpu_dst
);
2748 case 0xf: /* V9 membar */
2749 break; /* no effect */
2750 case 0x13: /* Graphics Status */
2751 if (gen_trap_ifnofpu(dc
)) {
2754 gen_store_gpr(dc
, rd
, cpu_gsr
);
2756 case 0x16: /* Softint */
2757 tcg_gen_ext_i32_tl(cpu_dst
, cpu_softint
);
2758 gen_store_gpr(dc
, rd
, cpu_dst
);
2760 case 0x17: /* Tick compare */
2761 gen_store_gpr(dc
, rd
, cpu_tick_cmpr
);
2763 case 0x18: /* System tick */
2768 r_tickptr
= tcg_temp_new_ptr();
2769 r_const
= tcg_const_i32(dc
->mem_idx
);
2770 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2771 offsetof(CPUSPARCState
, stick
));
2772 gen_helper_tick_get_count(cpu_dst
, cpu_env
, r_tickptr
,
2774 tcg_temp_free_ptr(r_tickptr
);
2775 tcg_temp_free_i32(r_const
);
2776 gen_store_gpr(dc
, rd
, cpu_dst
);
2779 case 0x19: /* System tick compare */
2780 gen_store_gpr(dc
, rd
, cpu_stick_cmpr
);
2782 case 0x10: /* Performance Control */
2783 case 0x11: /* Performance Instrumentation Counter */
2784 case 0x12: /* Dispatch Control */
2785 case 0x14: /* Softint set, WO */
2786 case 0x15: /* Softint clear, WO */
2791 #if !defined(CONFIG_USER_ONLY)
2792 } else if (xop
== 0x29) { /* rdpsr / UA2005 rdhpr */
2793 #ifndef TARGET_SPARC64
2794 if (!supervisor(dc
)) {
2798 gen_helper_rdpsr(cpu_dst
, cpu_env
);
2800 CHECK_IU_FEATURE(dc
, HYPV
);
2801 if (!hypervisor(dc
))
2803 rs1
= GET_FIELD(insn
, 13, 17);
2806 // gen_op_rdhpstate();
2809 // gen_op_rdhtstate();
2812 tcg_gen_mov_tl(cpu_dst
, cpu_hintp
);
2815 tcg_gen_mov_tl(cpu_dst
, cpu_htba
);
2818 tcg_gen_mov_tl(cpu_dst
, cpu_hver
);
2820 case 31: // hstick_cmpr
2821 tcg_gen_mov_tl(cpu_dst
, cpu_hstick_cmpr
);
2827 gen_store_gpr(dc
, rd
, cpu_dst
);
2829 } else if (xop
== 0x2a) { /* rdwim / V9 rdpr */
2830 if (!supervisor(dc
)) {
2833 cpu_tmp0
= get_temp_tl(dc
);
2834 #ifdef TARGET_SPARC64
2835 rs1
= GET_FIELD(insn
, 13, 17);
2841 r_tsptr
= tcg_temp_new_ptr();
2842 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2843 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2844 offsetof(trap_state
, tpc
));
2845 tcg_temp_free_ptr(r_tsptr
);
2852 r_tsptr
= tcg_temp_new_ptr();
2853 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2854 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2855 offsetof(trap_state
, tnpc
));
2856 tcg_temp_free_ptr(r_tsptr
);
2863 r_tsptr
= tcg_temp_new_ptr();
2864 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2865 tcg_gen_ld_tl(cpu_tmp0
, r_tsptr
,
2866 offsetof(trap_state
, tstate
));
2867 tcg_temp_free_ptr(r_tsptr
);
2872 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
2874 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
2875 tcg_gen_ld32s_tl(cpu_tmp0
, r_tsptr
,
2876 offsetof(trap_state
, tt
));
2877 tcg_temp_free_ptr(r_tsptr
);
2885 r_tickptr
= tcg_temp_new_ptr();
2886 r_const
= tcg_const_i32(dc
->mem_idx
);
2887 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
2888 offsetof(CPUSPARCState
, tick
));
2889 gen_helper_tick_get_count(cpu_tmp0
, cpu_env
,
2890 r_tickptr
, r_const
);
2891 tcg_temp_free_ptr(r_tickptr
);
2892 tcg_temp_free_i32(r_const
);
2896 tcg_gen_mov_tl(cpu_tmp0
, cpu_tbr
);
2899 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2900 offsetof(CPUSPARCState
, pstate
));
2903 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2904 offsetof(CPUSPARCState
, tl
));
2907 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2908 offsetof(CPUSPARCState
, psrpil
));
2911 gen_helper_rdcwp(cpu_tmp0
, cpu_env
);
2914 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2915 offsetof(CPUSPARCState
, cansave
));
2917 case 11: // canrestore
2918 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2919 offsetof(CPUSPARCState
, canrestore
));
2921 case 12: // cleanwin
2922 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2923 offsetof(CPUSPARCState
, cleanwin
));
2925 case 13: // otherwin
2926 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2927 offsetof(CPUSPARCState
, otherwin
));
2930 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2931 offsetof(CPUSPARCState
, wstate
));
2933 case 16: // UA2005 gl
2934 CHECK_IU_FEATURE(dc
, GL
);
2935 tcg_gen_ld32s_tl(cpu_tmp0
, cpu_env
,
2936 offsetof(CPUSPARCState
, gl
));
2938 case 26: // UA2005 strand status
2939 CHECK_IU_FEATURE(dc
, HYPV
);
2940 if (!hypervisor(dc
))
2942 tcg_gen_mov_tl(cpu_tmp0
, cpu_ssr
);
2945 tcg_gen_mov_tl(cpu_tmp0
, cpu_ver
);
2952 tcg_gen_ext_i32_tl(cpu_tmp0
, cpu_wim
);
2954 gen_store_gpr(dc
, rd
, cpu_tmp0
);
2956 } else if (xop
== 0x2b) { /* rdtbr / V9 flushw */
2957 #ifdef TARGET_SPARC64
2959 gen_helper_flushw(cpu_env
);
2961 if (!supervisor(dc
))
2963 gen_store_gpr(dc
, rd
, cpu_tbr
);
2967 } else if (xop
== 0x34) { /* FPU Operations */
2968 if (gen_trap_ifnofpu(dc
)) {
2971 gen_op_clear_ieee_excp_and_FTT();
2972 rs1
= GET_FIELD(insn
, 13, 17);
2973 rs2
= GET_FIELD(insn
, 27, 31);
2974 xop
= GET_FIELD(insn
, 18, 26);
2977 case 0x1: /* fmovs */
2978 cpu_src1_32
= gen_load_fpr_F(dc
, rs2
);
2979 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
2981 case 0x5: /* fnegs */
2982 gen_ne_fop_FF(dc
, rd
, rs2
, gen_helper_fnegs
);
2984 case 0x9: /* fabss */
2985 gen_ne_fop_FF(dc
, rd
, rs2
, gen_helper_fabss
);
2987 case 0x29: /* fsqrts */
2988 CHECK_FPU_FEATURE(dc
, FSQRT
);
2989 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fsqrts
);
2991 case 0x2a: /* fsqrtd */
2992 CHECK_FPU_FEATURE(dc
, FSQRT
);
2993 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fsqrtd
);
2995 case 0x2b: /* fsqrtq */
2996 CHECK_FPU_FEATURE(dc
, FLOAT128
);
2997 gen_fop_QQ(dc
, rd
, rs2
, gen_helper_fsqrtq
);
2999 case 0x41: /* fadds */
3000 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fadds
);
3002 case 0x42: /* faddd */
3003 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_faddd
);
3005 case 0x43: /* faddq */
3006 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3007 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_faddq
);
3009 case 0x45: /* fsubs */
3010 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fsubs
);
3012 case 0x46: /* fsubd */
3013 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fsubd
);
3015 case 0x47: /* fsubq */
3016 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3017 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fsubq
);
3019 case 0x49: /* fmuls */
3020 CHECK_FPU_FEATURE(dc
, FMUL
);
3021 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fmuls
);
3023 case 0x4a: /* fmuld */
3024 CHECK_FPU_FEATURE(dc
, FMUL
);
3025 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld
);
3027 case 0x4b: /* fmulq */
3028 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3029 CHECK_FPU_FEATURE(dc
, FMUL
);
3030 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fmulq
);
3032 case 0x4d: /* fdivs */
3033 gen_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fdivs
);
3035 case 0x4e: /* fdivd */
3036 gen_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fdivd
);
3038 case 0x4f: /* fdivq */
3039 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3040 gen_fop_QQQ(dc
, rd
, rs1
, rs2
, gen_helper_fdivq
);
3042 case 0x69: /* fsmuld */
3043 CHECK_FPU_FEATURE(dc
, FSMULD
);
3044 gen_fop_DFF(dc
, rd
, rs1
, rs2
, gen_helper_fsmuld
);
3046 case 0x6e: /* fdmulq */
3047 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3048 gen_fop_QDD(dc
, rd
, rs1
, rs2
, gen_helper_fdmulq
);
3050 case 0xc4: /* fitos */
3051 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fitos
);
3053 case 0xc6: /* fdtos */
3054 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fdtos
);
3056 case 0xc7: /* fqtos */
3057 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3058 gen_fop_FQ(dc
, rd
, rs2
, gen_helper_fqtos
);
3060 case 0xc8: /* fitod */
3061 gen_ne_fop_DF(dc
, rd
, rs2
, gen_helper_fitod
);
3063 case 0xc9: /* fstod */
3064 gen_ne_fop_DF(dc
, rd
, rs2
, gen_helper_fstod
);
3066 case 0xcb: /* fqtod */
3067 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3068 gen_fop_DQ(dc
, rd
, rs2
, gen_helper_fqtod
);
3070 case 0xcc: /* fitoq */
3071 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3072 gen_ne_fop_QF(dc
, rd
, rs2
, gen_helper_fitoq
);
3074 case 0xcd: /* fstoq */
3075 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3076 gen_ne_fop_QF(dc
, rd
, rs2
, gen_helper_fstoq
);
3078 case 0xce: /* fdtoq */
3079 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3080 gen_ne_fop_QD(dc
, rd
, rs2
, gen_helper_fdtoq
);
3082 case 0xd1: /* fstoi */
3083 gen_fop_FF(dc
, rd
, rs2
, gen_helper_fstoi
);
3085 case 0xd2: /* fdtoi */
3086 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fdtoi
);
3088 case 0xd3: /* fqtoi */
3089 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3090 gen_fop_FQ(dc
, rd
, rs2
, gen_helper_fqtoi
);
3092 #ifdef TARGET_SPARC64
3093 case 0x2: /* V9 fmovd */
3094 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
3095 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
3097 case 0x3: /* V9 fmovq */
3098 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3099 gen_move_Q(rd
, rs2
);
3101 case 0x6: /* V9 fnegd */
3102 gen_ne_fop_DD(dc
, rd
, rs2
, gen_helper_fnegd
);
3104 case 0x7: /* V9 fnegq */
3105 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3106 gen_ne_fop_QQ(dc
, rd
, rs2
, gen_helper_fnegq
);
3108 case 0xa: /* V9 fabsd */
3109 gen_ne_fop_DD(dc
, rd
, rs2
, gen_helper_fabsd
);
3111 case 0xb: /* V9 fabsq */
3112 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3113 gen_ne_fop_QQ(dc
, rd
, rs2
, gen_helper_fabsq
);
3115 case 0x81: /* V9 fstox */
3116 gen_fop_DF(dc
, rd
, rs2
, gen_helper_fstox
);
3118 case 0x82: /* V9 fdtox */
3119 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fdtox
);
3121 case 0x83: /* V9 fqtox */
3122 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3123 gen_fop_DQ(dc
, rd
, rs2
, gen_helper_fqtox
);
3125 case 0x84: /* V9 fxtos */
3126 gen_fop_FD(dc
, rd
, rs2
, gen_helper_fxtos
);
3128 case 0x88: /* V9 fxtod */
3129 gen_fop_DD(dc
, rd
, rs2
, gen_helper_fxtod
);
3131 case 0x8c: /* V9 fxtoq */
3132 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3133 gen_ne_fop_QD(dc
, rd
, rs2
, gen_helper_fxtoq
);
3139 } else if (xop
== 0x35) { /* FPU Operations */
3140 #ifdef TARGET_SPARC64
3143 if (gen_trap_ifnofpu(dc
)) {
3146 gen_op_clear_ieee_excp_and_FTT();
3147 rs1
= GET_FIELD(insn
, 13, 17);
3148 rs2
= GET_FIELD(insn
, 27, 31);
3149 xop
= GET_FIELD(insn
, 18, 26);
3152 #ifdef TARGET_SPARC64
3156 cond = GET_FIELD_SP(insn, 10, 12); \
3157 cpu_src1 = get_src1(dc, insn); \
3158 gen_compare_reg(&cmp, cond, cpu_src1); \
3159 gen_fmov##sz(dc, &cmp, rd, rs2); \
3160 free_compare(&cmp); \
3163 if ((xop
& 0x11f) == 0x005) { /* V9 fmovsr */
3166 } else if ((xop
& 0x11f) == 0x006) { // V9 fmovdr
3169 } else if ((xop
& 0x11f) == 0x007) { // V9 fmovqr
3170 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3177 #ifdef TARGET_SPARC64
3178 #define FMOVCC(fcc, sz) \
3181 cond = GET_FIELD_SP(insn, 14, 17); \
3182 gen_fcompare(&cmp, fcc, cond); \
3183 gen_fmov##sz(dc, &cmp, rd, rs2); \
3184 free_compare(&cmp); \
3187 case 0x001: /* V9 fmovscc %fcc0 */
3190 case 0x002: /* V9 fmovdcc %fcc0 */
3193 case 0x003: /* V9 fmovqcc %fcc0 */
3194 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3197 case 0x041: /* V9 fmovscc %fcc1 */
3200 case 0x042: /* V9 fmovdcc %fcc1 */
3203 case 0x043: /* V9 fmovqcc %fcc1 */
3204 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3207 case 0x081: /* V9 fmovscc %fcc2 */
3210 case 0x082: /* V9 fmovdcc %fcc2 */
3213 case 0x083: /* V9 fmovqcc %fcc2 */
3214 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3217 case 0x0c1: /* V9 fmovscc %fcc3 */
3220 case 0x0c2: /* V9 fmovdcc %fcc3 */
3223 case 0x0c3: /* V9 fmovqcc %fcc3 */
3224 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3228 #define FMOVCC(xcc, sz) \
3231 cond = GET_FIELD_SP(insn, 14, 17); \
3232 gen_compare(&cmp, xcc, cond, dc); \
3233 gen_fmov##sz(dc, &cmp, rd, rs2); \
3234 free_compare(&cmp); \
3237 case 0x101: /* V9 fmovscc %icc */
3240 case 0x102: /* V9 fmovdcc %icc */
3243 case 0x103: /* V9 fmovqcc %icc */
3244 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3247 case 0x181: /* V9 fmovscc %xcc */
3250 case 0x182: /* V9 fmovdcc %xcc */
3253 case 0x183: /* V9 fmovqcc %xcc */
3254 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3259 case 0x51: /* fcmps, V9 %fcc */
3260 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
3261 cpu_src2_32
= gen_load_fpr_F(dc
, rs2
);
3262 gen_op_fcmps(rd
& 3, cpu_src1_32
, cpu_src2_32
);
3264 case 0x52: /* fcmpd, V9 %fcc */
3265 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
3266 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
3267 gen_op_fcmpd(rd
& 3, cpu_src1_64
, cpu_src2_64
);
3269 case 0x53: /* fcmpq, V9 %fcc */
3270 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3271 gen_op_load_fpr_QT0(QFPREG(rs1
));
3272 gen_op_load_fpr_QT1(QFPREG(rs2
));
3273 gen_op_fcmpq(rd
& 3);
3275 case 0x55: /* fcmpes, V9 %fcc */
3276 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
3277 cpu_src2_32
= gen_load_fpr_F(dc
, rs2
);
3278 gen_op_fcmpes(rd
& 3, cpu_src1_32
, cpu_src2_32
);
3280 case 0x56: /* fcmped, V9 %fcc */
3281 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
3282 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
3283 gen_op_fcmped(rd
& 3, cpu_src1_64
, cpu_src2_64
);
3285 case 0x57: /* fcmpeq, V9 %fcc */
3286 CHECK_FPU_FEATURE(dc
, FLOAT128
);
3287 gen_op_load_fpr_QT0(QFPREG(rs1
));
3288 gen_op_load_fpr_QT1(QFPREG(rs2
));
3289 gen_op_fcmpeq(rd
& 3);
3294 } else if (xop
== 0x2) {
3295 TCGv dst
= gen_dest_gpr(dc
, rd
);
3296 rs1
= GET_FIELD(insn
, 13, 17);
3298 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
3299 if (IS_IMM
) { /* immediate */
3300 simm
= GET_FIELDs(insn
, 19, 31);
3301 tcg_gen_movi_tl(dst
, simm
);
3302 gen_store_gpr(dc
, rd
, dst
);
3303 } else { /* register */
3304 rs2
= GET_FIELD(insn
, 27, 31);
3306 tcg_gen_movi_tl(dst
, 0);
3307 gen_store_gpr(dc
, rd
, dst
);
3309 cpu_src2
= gen_load_gpr(dc
, rs2
);
3310 gen_store_gpr(dc
, rd
, cpu_src2
);
3314 cpu_src1
= get_src1(dc
, insn
);
3315 if (IS_IMM
) { /* immediate */
3316 simm
= GET_FIELDs(insn
, 19, 31);
3317 tcg_gen_ori_tl(dst
, cpu_src1
, simm
);
3318 gen_store_gpr(dc
, rd
, dst
);
3319 } else { /* register */
3320 rs2
= GET_FIELD(insn
, 27, 31);
3322 /* mov shortcut: or x, %g0, y -> mov x, y */
3323 gen_store_gpr(dc
, rd
, cpu_src1
);
3325 cpu_src2
= gen_load_gpr(dc
, rs2
);
3326 tcg_gen_or_tl(dst
, cpu_src1
, cpu_src2
);
3327 gen_store_gpr(dc
, rd
, dst
);
3331 #ifdef TARGET_SPARC64
3332 } else if (xop
== 0x25) { /* sll, V9 sllx */
3333 cpu_src1
= get_src1(dc
, insn
);
3334 if (IS_IMM
) { /* immediate */
3335 simm
= GET_FIELDs(insn
, 20, 31);
3336 if (insn
& (1 << 12)) {
3337 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3339 tcg_gen_shli_i64(cpu_dst
, cpu_src1
, simm
& 0x1f);
3341 } else { /* register */
3342 rs2
= GET_FIELD(insn
, 27, 31);
3343 cpu_src2
= gen_load_gpr(dc
, rs2
);
3344 cpu_tmp0
= get_temp_tl(dc
);
3345 if (insn
& (1 << 12)) {
3346 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3348 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3350 tcg_gen_shl_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3352 gen_store_gpr(dc
, rd
, cpu_dst
);
3353 } else if (xop
== 0x26) { /* srl, V9 srlx */
3354 cpu_src1
= get_src1(dc
, insn
);
3355 if (IS_IMM
) { /* immediate */
3356 simm
= GET_FIELDs(insn
, 20, 31);
3357 if (insn
& (1 << 12)) {
3358 tcg_gen_shri_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3360 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3361 tcg_gen_shri_i64(cpu_dst
, cpu_dst
, simm
& 0x1f);
3363 } else { /* register */
3364 rs2
= GET_FIELD(insn
, 27, 31);
3365 cpu_src2
= gen_load_gpr(dc
, rs2
);
3366 cpu_tmp0
= get_temp_tl(dc
);
3367 if (insn
& (1 << 12)) {
3368 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3369 tcg_gen_shr_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3371 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3372 tcg_gen_andi_i64(cpu_dst
, cpu_src1
, 0xffffffffULL
);
3373 tcg_gen_shr_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
3376 gen_store_gpr(dc
, rd
, cpu_dst
);
3377 } else if (xop
== 0x27) { /* sra, V9 srax */
3378 cpu_src1
= get_src1(dc
, insn
);
3379 if (IS_IMM
) { /* immediate */
3380 simm
= GET_FIELDs(insn
, 20, 31);
3381 if (insn
& (1 << 12)) {
3382 tcg_gen_sari_i64(cpu_dst
, cpu_src1
, simm
& 0x3f);
3384 tcg_gen_ext32s_i64(cpu_dst
, cpu_src1
);
3385 tcg_gen_sari_i64(cpu_dst
, cpu_dst
, simm
& 0x1f);
3387 } else { /* register */
3388 rs2
= GET_FIELD(insn
, 27, 31);
3389 cpu_src2
= gen_load_gpr(dc
, rs2
);
3390 cpu_tmp0
= get_temp_tl(dc
);
3391 if (insn
& (1 << 12)) {
3392 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x3f);
3393 tcg_gen_sar_i64(cpu_dst
, cpu_src1
, cpu_tmp0
);
3395 tcg_gen_andi_i64(cpu_tmp0
, cpu_src2
, 0x1f);
3396 tcg_gen_ext32s_i64(cpu_dst
, cpu_src1
);
3397 tcg_gen_sar_i64(cpu_dst
, cpu_dst
, cpu_tmp0
);
3400 gen_store_gpr(dc
, rd
, cpu_dst
);
3402 } else if (xop
< 0x36) {
3404 cpu_src1
= get_src1(dc
, insn
);
3405 cpu_src2
= get_src2(dc
, insn
);
3406 switch (xop
& ~0x10) {
3409 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3410 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3411 dc
->cc_op
= CC_OP_ADD
;
3413 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3417 tcg_gen_and_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3419 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3420 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3421 dc
->cc_op
= CC_OP_LOGIC
;
3425 tcg_gen_or_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3427 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3428 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3429 dc
->cc_op
= CC_OP_LOGIC
;
3433 tcg_gen_xor_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3435 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3436 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3437 dc
->cc_op
= CC_OP_LOGIC
;
3442 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3443 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SUB
);
3444 dc
->cc_op
= CC_OP_SUB
;
3446 tcg_gen_sub_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3449 case 0x5: /* andn */
3450 tcg_gen_andc_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3452 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3453 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3454 dc
->cc_op
= CC_OP_LOGIC
;
3458 tcg_gen_orc_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3460 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3461 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3462 dc
->cc_op
= CC_OP_LOGIC
;
3465 case 0x7: /* xorn */
3466 tcg_gen_eqv_tl(cpu_dst
, cpu_src1
, cpu_src2
);
3468 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3469 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3470 dc
->cc_op
= CC_OP_LOGIC
;
3473 case 0x8: /* addx, V9 addc */
3474 gen_op_addx_int(dc
, cpu_dst
, cpu_src1
, cpu_src2
,
3477 #ifdef TARGET_SPARC64
3478 case 0x9: /* V9 mulx */
3479 tcg_gen_mul_i64(cpu_dst
, cpu_src1
, cpu_src2
);
3482 case 0xa: /* umul */
3483 CHECK_IU_FEATURE(dc
, MUL
);
3484 gen_op_umul(cpu_dst
, cpu_src1
, cpu_src2
);
3486 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3487 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3488 dc
->cc_op
= CC_OP_LOGIC
;
3491 case 0xb: /* smul */
3492 CHECK_IU_FEATURE(dc
, MUL
);
3493 gen_op_smul(cpu_dst
, cpu_src1
, cpu_src2
);
3495 tcg_gen_mov_tl(cpu_cc_dst
, cpu_dst
);
3496 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_LOGIC
);
3497 dc
->cc_op
= CC_OP_LOGIC
;
3500 case 0xc: /* subx, V9 subc */
3501 gen_op_subx_int(dc
, cpu_dst
, cpu_src1
, cpu_src2
,
3504 #ifdef TARGET_SPARC64
3505 case 0xd: /* V9 udivx */
3506 gen_helper_udivx(cpu_dst
, cpu_env
, cpu_src1
, cpu_src2
);
3509 case 0xe: /* udiv */
3510 CHECK_IU_FEATURE(dc
, DIV
);
3512 gen_helper_udiv_cc(cpu_dst
, cpu_env
, cpu_src1
,
3514 dc
->cc_op
= CC_OP_DIV
;
3516 gen_helper_udiv(cpu_dst
, cpu_env
, cpu_src1
,
3520 case 0xf: /* sdiv */
3521 CHECK_IU_FEATURE(dc
, DIV
);
3523 gen_helper_sdiv_cc(cpu_dst
, cpu_env
, cpu_src1
,
3525 dc
->cc_op
= CC_OP_DIV
;
3527 gen_helper_sdiv(cpu_dst
, cpu_env
, cpu_src1
,
3534 gen_store_gpr(dc
, rd
, cpu_dst
);
3536 cpu_src1
= get_src1(dc
, insn
);
3537 cpu_src2
= get_src2(dc
, insn
);
3539 case 0x20: /* taddcc */
3540 gen_op_add_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3541 gen_store_gpr(dc
, rd
, cpu_dst
);
3542 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_TADD
);
3543 dc
->cc_op
= CC_OP_TADD
;
3545 case 0x21: /* tsubcc */
3546 gen_op_sub_cc(cpu_dst
, cpu_src1
, cpu_src2
);
3547 gen_store_gpr(dc
, rd
, cpu_dst
);
3548 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_TSUB
);
3549 dc
->cc_op
= CC_OP_TSUB
;
3551 case 0x22: /* taddcctv */
3552 gen_helper_taddcctv(cpu_dst
, cpu_env
,
3553 cpu_src1
, cpu_src2
);
3554 gen_store_gpr(dc
, rd
, cpu_dst
);
3555 dc
->cc_op
= CC_OP_TADDTV
;
3557 case 0x23: /* tsubcctv */
3558 gen_helper_tsubcctv(cpu_dst
, cpu_env
,
3559 cpu_src1
, cpu_src2
);
3560 gen_store_gpr(dc
, rd
, cpu_dst
);
3561 dc
->cc_op
= CC_OP_TSUBTV
;
3563 case 0x24: /* mulscc */
3565 gen_op_mulscc(cpu_dst
, cpu_src1
, cpu_src2
);
3566 gen_store_gpr(dc
, rd
, cpu_dst
);
3567 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_ADD
);
3568 dc
->cc_op
= CC_OP_ADD
;
3570 #ifndef TARGET_SPARC64
3571 case 0x25: /* sll */
3572 if (IS_IMM
) { /* immediate */
3573 simm
= GET_FIELDs(insn
, 20, 31);
3574 tcg_gen_shli_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3575 } else { /* register */
3576 cpu_tmp0
= get_temp_tl(dc
);
3577 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3578 tcg_gen_shl_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3580 gen_store_gpr(dc
, rd
, cpu_dst
);
3582 case 0x26: /* srl */
3583 if (IS_IMM
) { /* immediate */
3584 simm
= GET_FIELDs(insn
, 20, 31);
3585 tcg_gen_shri_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3586 } else { /* register */
3587 cpu_tmp0
= get_temp_tl(dc
);
3588 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3589 tcg_gen_shr_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3591 gen_store_gpr(dc
, rd
, cpu_dst
);
3593 case 0x27: /* sra */
3594 if (IS_IMM
) { /* immediate */
3595 simm
= GET_FIELDs(insn
, 20, 31);
3596 tcg_gen_sari_tl(cpu_dst
, cpu_src1
, simm
& 0x1f);
3597 } else { /* register */
3598 cpu_tmp0
= get_temp_tl(dc
);
3599 tcg_gen_andi_tl(cpu_tmp0
, cpu_src2
, 0x1f);
3600 tcg_gen_sar_tl(cpu_dst
, cpu_src1
, cpu_tmp0
);
3602 gen_store_gpr(dc
, rd
, cpu_dst
);
3607 cpu_tmp0
= get_temp_tl(dc
);
3610 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3611 tcg_gen_andi_tl(cpu_y
, cpu_tmp0
, 0xffffffff);
3613 #ifndef TARGET_SPARC64
3614 case 0x01 ... 0x0f: /* undefined in the
3618 case 0x10 ... 0x1f: /* implementation-dependent
3622 if ((rd
== 0x13) && (dc
->def
->features
&
3623 CPU_FEATURE_POWERDOWN
)) {
3624 /* LEON3 power-down */
3626 gen_helper_power_down(cpu_env
);
3630 case 0x2: /* V9 wrccr */
3631 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3632 gen_helper_wrccr(cpu_env
, cpu_tmp0
);
3633 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_FLAGS
);
3634 dc
->cc_op
= CC_OP_FLAGS
;
3636 case 0x3: /* V9 wrasi */
3637 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3638 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xff);
3639 tcg_gen_trunc_tl_i32(cpu_asi
, cpu_tmp0
);
3641 case 0x6: /* V9 wrfprs */
3642 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3643 tcg_gen_trunc_tl_i32(cpu_fprs
, cpu_tmp0
);
3649 case 0xf: /* V9 sir, nop if user */
3650 #if !defined(CONFIG_USER_ONLY)
3651 if (supervisor(dc
)) {
3656 case 0x13: /* Graphics Status */
3657 if (gen_trap_ifnofpu(dc
)) {
3660 tcg_gen_xor_tl(cpu_gsr
, cpu_src1
, cpu_src2
);
3662 case 0x14: /* Softint set */
3663 if (!supervisor(dc
))
3665 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3666 gen_helper_set_softint(cpu_env
, cpu_tmp0
);
3668 case 0x15: /* Softint clear */
3669 if (!supervisor(dc
))
3671 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3672 gen_helper_clear_softint(cpu_env
, cpu_tmp0
);
3674 case 0x16: /* Softint write */
3675 if (!supervisor(dc
))
3677 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3678 gen_helper_write_softint(cpu_env
, cpu_tmp0
);
3680 case 0x17: /* Tick compare */
3681 #if !defined(CONFIG_USER_ONLY)
3682 if (!supervisor(dc
))
3688 tcg_gen_xor_tl(cpu_tick_cmpr
, cpu_src1
,
3690 r_tickptr
= tcg_temp_new_ptr();
3691 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3692 offsetof(CPUSPARCState
, tick
));
3693 gen_helper_tick_set_limit(r_tickptr
,
3695 tcg_temp_free_ptr(r_tickptr
);
3698 case 0x18: /* System tick */
3699 #if !defined(CONFIG_USER_ONLY)
3700 if (!supervisor(dc
))
3706 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
,
3708 r_tickptr
= tcg_temp_new_ptr();
3709 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3710 offsetof(CPUSPARCState
, stick
));
3711 gen_helper_tick_set_count(r_tickptr
,
3713 tcg_temp_free_ptr(r_tickptr
);
3716 case 0x19: /* System tick compare */
3717 #if !defined(CONFIG_USER_ONLY)
3718 if (!supervisor(dc
))
3724 tcg_gen_xor_tl(cpu_stick_cmpr
, cpu_src1
,
3726 r_tickptr
= tcg_temp_new_ptr();
3727 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3728 offsetof(CPUSPARCState
, stick
));
3729 gen_helper_tick_set_limit(r_tickptr
,
3731 tcg_temp_free_ptr(r_tickptr
);
3735 case 0x10: /* Performance Control */
3736 case 0x11: /* Performance Instrumentation
3738 case 0x12: /* Dispatch Control */
3745 #if !defined(CONFIG_USER_ONLY)
3746 case 0x31: /* wrpsr, V9 saved, restored */
3748 if (!supervisor(dc
))
3750 #ifdef TARGET_SPARC64
3753 gen_helper_saved(cpu_env
);
3756 gen_helper_restored(cpu_env
);
3758 case 2: /* UA2005 allclean */
3759 case 3: /* UA2005 otherw */
3760 case 4: /* UA2005 normalw */
3761 case 5: /* UA2005 invalw */
3767 cpu_tmp0
= get_temp_tl(dc
);
3768 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3769 gen_helper_wrpsr(cpu_env
, cpu_tmp0
);
3770 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_FLAGS
);
3771 dc
->cc_op
= CC_OP_FLAGS
;
3779 case 0x32: /* wrwim, V9 wrpr */
3781 if (!supervisor(dc
))
3783 cpu_tmp0
= get_temp_tl(dc
);
3784 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3785 #ifdef TARGET_SPARC64
3791 r_tsptr
= tcg_temp_new_ptr();
3792 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3793 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3794 offsetof(trap_state
, tpc
));
3795 tcg_temp_free_ptr(r_tsptr
);
3802 r_tsptr
= tcg_temp_new_ptr();
3803 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3804 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3805 offsetof(trap_state
, tnpc
));
3806 tcg_temp_free_ptr(r_tsptr
);
3813 r_tsptr
= tcg_temp_new_ptr();
3814 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3815 tcg_gen_st_tl(cpu_tmp0
, r_tsptr
,
3816 offsetof(trap_state
,
3818 tcg_temp_free_ptr(r_tsptr
);
3825 r_tsptr
= tcg_temp_new_ptr();
3826 gen_load_trap_state_at_tl(r_tsptr
, cpu_env
);
3827 tcg_gen_st32_tl(cpu_tmp0
, r_tsptr
,
3828 offsetof(trap_state
, tt
));
3829 tcg_temp_free_ptr(r_tsptr
);
3836 r_tickptr
= tcg_temp_new_ptr();
3837 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3838 offsetof(CPUSPARCState
, tick
));
3839 gen_helper_tick_set_count(r_tickptr
,
3841 tcg_temp_free_ptr(r_tickptr
);
3845 tcg_gen_mov_tl(cpu_tbr
, cpu_tmp0
);
3849 gen_helper_wrpstate(cpu_env
, cpu_tmp0
);
3850 dc
->npc
= DYNAMIC_PC
;
3854 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3855 offsetof(CPUSPARCState
, tl
));
3856 dc
->npc
= DYNAMIC_PC
;
3859 gen_helper_wrpil(cpu_env
, cpu_tmp0
);
3862 gen_helper_wrcwp(cpu_env
, cpu_tmp0
);
3865 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3866 offsetof(CPUSPARCState
,
3869 case 11: // canrestore
3870 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3871 offsetof(CPUSPARCState
,
3874 case 12: // cleanwin
3875 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3876 offsetof(CPUSPARCState
,
3879 case 13: // otherwin
3880 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3881 offsetof(CPUSPARCState
,
3885 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3886 offsetof(CPUSPARCState
,
3889 case 16: // UA2005 gl
3890 CHECK_IU_FEATURE(dc
, GL
);
3891 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
,
3892 offsetof(CPUSPARCState
, gl
));
3894 case 26: // UA2005 strand status
3895 CHECK_IU_FEATURE(dc
, HYPV
);
3896 if (!hypervisor(dc
))
3898 tcg_gen_mov_tl(cpu_ssr
, cpu_tmp0
);
3904 tcg_gen_trunc_tl_i32(cpu_wim
, cpu_tmp0
);
3905 if (dc
->def
->nwindows
!= 32) {
3906 tcg_gen_andi_tl(cpu_wim
, cpu_wim
,
3907 (1 << dc
->def
->nwindows
) - 1);
3912 case 0x33: /* wrtbr, UA2005 wrhpr */
3914 #ifndef TARGET_SPARC64
3915 if (!supervisor(dc
))
3917 tcg_gen_xor_tl(cpu_tbr
, cpu_src1
, cpu_src2
);
3919 CHECK_IU_FEATURE(dc
, HYPV
);
3920 if (!hypervisor(dc
))
3922 cpu_tmp0
= get_temp_tl(dc
);
3923 tcg_gen_xor_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
3926 // XXX gen_op_wrhpstate();
3933 // XXX gen_op_wrhtstate();
3936 tcg_gen_mov_tl(cpu_hintp
, cpu_tmp0
);
3939 tcg_gen_mov_tl(cpu_htba
, cpu_tmp0
);
3941 case 31: // hstick_cmpr
3945 tcg_gen_mov_tl(cpu_hstick_cmpr
, cpu_tmp0
);
3946 r_tickptr
= tcg_temp_new_ptr();
3947 tcg_gen_ld_ptr(r_tickptr
, cpu_env
,
3948 offsetof(CPUSPARCState
, hstick
));
3949 gen_helper_tick_set_limit(r_tickptr
,
3951 tcg_temp_free_ptr(r_tickptr
);
3954 case 6: // hver readonly
3962 #ifdef TARGET_SPARC64
3963 case 0x2c: /* V9 movcc */
3965 int cc
= GET_FIELD_SP(insn
, 11, 12);
3966 int cond
= GET_FIELD_SP(insn
, 14, 17);
3970 if (insn
& (1 << 18)) {
3972 gen_compare(&cmp
, 0, cond
, dc
);
3973 } else if (cc
== 2) {
3974 gen_compare(&cmp
, 1, cond
, dc
);
3979 gen_fcompare(&cmp
, cc
, cond
);
3982 /* The get_src2 above loaded the normal 13-bit
3983 immediate field, not the 11-bit field we have
3984 in movcc. But it did handle the reg case. */
3986 simm
= GET_FIELD_SPs(insn
, 0, 10);
3987 tcg_gen_movi_tl(cpu_src2
, simm
);
3990 dst
= gen_load_gpr(dc
, rd
);
3991 tcg_gen_movcond_tl(cmp
.cond
, dst
,
3995 gen_store_gpr(dc
, rd
, dst
);
3998 case 0x2d: /* V9 sdivx */
3999 gen_helper_sdivx(cpu_dst
, cpu_env
, cpu_src1
, cpu_src2
);
4000 gen_store_gpr(dc
, rd
, cpu_dst
);
4002 case 0x2e: /* V9 popc */
4003 gen_helper_popc(cpu_dst
, cpu_src2
);
4004 gen_store_gpr(dc
, rd
, cpu_dst
);
4006 case 0x2f: /* V9 movr */
4008 int cond
= GET_FIELD_SP(insn
, 10, 12);
4012 gen_compare_reg(&cmp
, cond
, cpu_src1
);
4014 /* The get_src2 above loaded the normal 13-bit
4015 immediate field, not the 10-bit field we have
4016 in movr. But it did handle the reg case. */
4018 simm
= GET_FIELD_SPs(insn
, 0, 9);
4019 tcg_gen_movi_tl(cpu_src2
, simm
);
4022 dst
= gen_load_gpr(dc
, rd
);
4023 tcg_gen_movcond_tl(cmp
.cond
, dst
,
4027 gen_store_gpr(dc
, rd
, dst
);
4035 } else if (xop
== 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4036 #ifdef TARGET_SPARC64
4037 int opf
= GET_FIELD_SP(insn
, 5, 13);
4038 rs1
= GET_FIELD(insn
, 13, 17);
4039 rs2
= GET_FIELD(insn
, 27, 31);
4040 if (gen_trap_ifnofpu(dc
)) {
4045 case 0x000: /* VIS I edge8cc */
4046 CHECK_FPU_FEATURE(dc
, VIS1
);
4047 cpu_src1
= gen_load_gpr(dc
, rs1
);
4048 cpu_src2
= gen_load_gpr(dc
, rs2
);
4049 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 1, 0);
4050 gen_store_gpr(dc
, rd
, cpu_dst
);
4052 case 0x001: /* VIS II edge8n */
4053 CHECK_FPU_FEATURE(dc
, VIS2
);
4054 cpu_src1
= gen_load_gpr(dc
, rs1
);
4055 cpu_src2
= gen_load_gpr(dc
, rs2
);
4056 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 0, 0);
4057 gen_store_gpr(dc
, rd
, cpu_dst
);
4059 case 0x002: /* VIS I edge8lcc */
4060 CHECK_FPU_FEATURE(dc
, VIS1
);
4061 cpu_src1
= gen_load_gpr(dc
, rs1
);
4062 cpu_src2
= gen_load_gpr(dc
, rs2
);
4063 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 1, 1);
4064 gen_store_gpr(dc
, rd
, cpu_dst
);
4066 case 0x003: /* VIS II edge8ln */
4067 CHECK_FPU_FEATURE(dc
, VIS2
);
4068 cpu_src1
= gen_load_gpr(dc
, rs1
);
4069 cpu_src2
= gen_load_gpr(dc
, rs2
);
4070 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 8, 0, 1);
4071 gen_store_gpr(dc
, rd
, cpu_dst
);
4073 case 0x004: /* VIS I edge16cc */
4074 CHECK_FPU_FEATURE(dc
, VIS1
);
4075 cpu_src1
= gen_load_gpr(dc
, rs1
);
4076 cpu_src2
= gen_load_gpr(dc
, rs2
);
4077 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 1, 0);
4078 gen_store_gpr(dc
, rd
, cpu_dst
);
4080 case 0x005: /* VIS II edge16n */
4081 CHECK_FPU_FEATURE(dc
, VIS2
);
4082 cpu_src1
= gen_load_gpr(dc
, rs1
);
4083 cpu_src2
= gen_load_gpr(dc
, rs2
);
4084 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 0, 0);
4085 gen_store_gpr(dc
, rd
, cpu_dst
);
4087 case 0x006: /* VIS I edge16lcc */
4088 CHECK_FPU_FEATURE(dc
, VIS1
);
4089 cpu_src1
= gen_load_gpr(dc
, rs1
);
4090 cpu_src2
= gen_load_gpr(dc
, rs2
);
4091 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 1, 1);
4092 gen_store_gpr(dc
, rd
, cpu_dst
);
4094 case 0x007: /* VIS II edge16ln */
4095 CHECK_FPU_FEATURE(dc
, VIS2
);
4096 cpu_src1
= gen_load_gpr(dc
, rs1
);
4097 cpu_src2
= gen_load_gpr(dc
, rs2
);
4098 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 16, 0, 1);
4099 gen_store_gpr(dc
, rd
, cpu_dst
);
4101 case 0x008: /* VIS I edge32cc */
4102 CHECK_FPU_FEATURE(dc
, VIS1
);
4103 cpu_src1
= gen_load_gpr(dc
, rs1
);
4104 cpu_src2
= gen_load_gpr(dc
, rs2
);
4105 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 1, 0);
4106 gen_store_gpr(dc
, rd
, cpu_dst
);
4108 case 0x009: /* VIS II edge32n */
4109 CHECK_FPU_FEATURE(dc
, VIS2
);
4110 cpu_src1
= gen_load_gpr(dc
, rs1
);
4111 cpu_src2
= gen_load_gpr(dc
, rs2
);
4112 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 0, 0);
4113 gen_store_gpr(dc
, rd
, cpu_dst
);
4115 case 0x00a: /* VIS I edge32lcc */
4116 CHECK_FPU_FEATURE(dc
, VIS1
);
4117 cpu_src1
= gen_load_gpr(dc
, rs1
);
4118 cpu_src2
= gen_load_gpr(dc
, rs2
);
4119 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 1, 1);
4120 gen_store_gpr(dc
, rd
, cpu_dst
);
4122 case 0x00b: /* VIS II edge32ln */
4123 CHECK_FPU_FEATURE(dc
, VIS2
);
4124 cpu_src1
= gen_load_gpr(dc
, rs1
);
4125 cpu_src2
= gen_load_gpr(dc
, rs2
);
4126 gen_edge(dc
, cpu_dst
, cpu_src1
, cpu_src2
, 32, 0, 1);
4127 gen_store_gpr(dc
, rd
, cpu_dst
);
4129 case 0x010: /* VIS I array8 */
4130 CHECK_FPU_FEATURE(dc
, VIS1
);
4131 cpu_src1
= gen_load_gpr(dc
, rs1
);
4132 cpu_src2
= gen_load_gpr(dc
, rs2
);
4133 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4134 gen_store_gpr(dc
, rd
, cpu_dst
);
4136 case 0x012: /* VIS I array16 */
4137 CHECK_FPU_FEATURE(dc
, VIS1
);
4138 cpu_src1
= gen_load_gpr(dc
, rs1
);
4139 cpu_src2
= gen_load_gpr(dc
, rs2
);
4140 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4141 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 1);
4142 gen_store_gpr(dc
, rd
, cpu_dst
);
4144 case 0x014: /* VIS I array32 */
4145 CHECK_FPU_FEATURE(dc
, VIS1
);
4146 cpu_src1
= gen_load_gpr(dc
, rs1
);
4147 cpu_src2
= gen_load_gpr(dc
, rs2
);
4148 gen_helper_array8(cpu_dst
, cpu_src1
, cpu_src2
);
4149 tcg_gen_shli_i64(cpu_dst
, cpu_dst
, 2);
4150 gen_store_gpr(dc
, rd
, cpu_dst
);
4152 case 0x018: /* VIS I alignaddr */
4153 CHECK_FPU_FEATURE(dc
, VIS1
);
4154 cpu_src1
= gen_load_gpr(dc
, rs1
);
4155 cpu_src2
= gen_load_gpr(dc
, rs2
);
4156 gen_alignaddr(cpu_dst
, cpu_src1
, cpu_src2
, 0);
4157 gen_store_gpr(dc
, rd
, cpu_dst
);
4159 case 0x01a: /* VIS I alignaddrl */
4160 CHECK_FPU_FEATURE(dc
, VIS1
);
4161 cpu_src1
= gen_load_gpr(dc
, rs1
);
4162 cpu_src2
= gen_load_gpr(dc
, rs2
);
4163 gen_alignaddr(cpu_dst
, cpu_src1
, cpu_src2
, 1);
4164 gen_store_gpr(dc
, rd
, cpu_dst
);
4166 case 0x019: /* VIS II bmask */
4167 CHECK_FPU_FEATURE(dc
, VIS2
);
4168 cpu_src1
= gen_load_gpr(dc
, rs1
);
4169 cpu_src2
= gen_load_gpr(dc
, rs2
);
4170 tcg_gen_add_tl(cpu_dst
, cpu_src1
, cpu_src2
);
4171 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, cpu_dst
, 32, 32);
4172 gen_store_gpr(dc
, rd
, cpu_dst
);
4174 case 0x020: /* VIS I fcmple16 */
4175 CHECK_FPU_FEATURE(dc
, VIS1
);
4176 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4177 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4178 gen_helper_fcmple16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4179 gen_store_gpr(dc
, rd
, cpu_dst
);
4181 case 0x022: /* VIS I fcmpne16 */
4182 CHECK_FPU_FEATURE(dc
, VIS1
);
4183 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4184 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4185 gen_helper_fcmpne16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4186 gen_store_gpr(dc
, rd
, cpu_dst
);
4188 case 0x024: /* VIS I fcmple32 */
4189 CHECK_FPU_FEATURE(dc
, VIS1
);
4190 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4191 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4192 gen_helper_fcmple32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4193 gen_store_gpr(dc
, rd
, cpu_dst
);
4195 case 0x026: /* VIS I fcmpne32 */
4196 CHECK_FPU_FEATURE(dc
, VIS1
);
4197 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4198 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4199 gen_helper_fcmpne32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4200 gen_store_gpr(dc
, rd
, cpu_dst
);
4202 case 0x028: /* VIS I fcmpgt16 */
4203 CHECK_FPU_FEATURE(dc
, VIS1
);
4204 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4205 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4206 gen_helper_fcmpgt16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4207 gen_store_gpr(dc
, rd
, cpu_dst
);
4209 case 0x02a: /* VIS I fcmpeq16 */
4210 CHECK_FPU_FEATURE(dc
, VIS1
);
4211 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4212 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4213 gen_helper_fcmpeq16(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4214 gen_store_gpr(dc
, rd
, cpu_dst
);
4216 case 0x02c: /* VIS I fcmpgt32 */
4217 CHECK_FPU_FEATURE(dc
, VIS1
);
4218 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4219 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4220 gen_helper_fcmpgt32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4221 gen_store_gpr(dc
, rd
, cpu_dst
);
4223 case 0x02e: /* VIS I fcmpeq32 */
4224 CHECK_FPU_FEATURE(dc
, VIS1
);
4225 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4226 cpu_src2_64
= gen_load_fpr_D(dc
, rs2
);
4227 gen_helper_fcmpeq32(cpu_dst
, cpu_src1_64
, cpu_src2_64
);
4228 gen_store_gpr(dc
, rd
, cpu_dst
);
4230 case 0x031: /* VIS I fmul8x16 */
4231 CHECK_FPU_FEATURE(dc
, VIS1
);
4232 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16
);
4234 case 0x033: /* VIS I fmul8x16au */
4235 CHECK_FPU_FEATURE(dc
, VIS1
);
4236 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16au
);
4238 case 0x035: /* VIS I fmul8x16al */
4239 CHECK_FPU_FEATURE(dc
, VIS1
);
4240 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8x16al
);
4242 case 0x036: /* VIS I fmul8sux16 */
4243 CHECK_FPU_FEATURE(dc
, VIS1
);
4244 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8sux16
);
4246 case 0x037: /* VIS I fmul8ulx16 */
4247 CHECK_FPU_FEATURE(dc
, VIS1
);
4248 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmul8ulx16
);
4250 case 0x038: /* VIS I fmuld8sux16 */
4251 CHECK_FPU_FEATURE(dc
, VIS1
);
4252 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld8sux16
);
4254 case 0x039: /* VIS I fmuld8ulx16 */
4255 CHECK_FPU_FEATURE(dc
, VIS1
);
4256 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fmuld8ulx16
);
4258 case 0x03a: /* VIS I fpack32 */
4259 CHECK_FPU_FEATURE(dc
, VIS1
);
4260 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpack32
);
4262 case 0x03b: /* VIS I fpack16 */
4263 CHECK_FPU_FEATURE(dc
, VIS1
);
4264 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4265 cpu_dst_32
= gen_dest_fpr_F(dc
);
4266 gen_helper_fpack16(cpu_dst_32
, cpu_gsr
, cpu_src1_64
);
4267 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4269 case 0x03d: /* VIS I fpackfix */
4270 CHECK_FPU_FEATURE(dc
, VIS1
);
4271 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4272 cpu_dst_32
= gen_dest_fpr_F(dc
);
4273 gen_helper_fpackfix(cpu_dst_32
, cpu_gsr
, cpu_src1_64
);
4274 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4276 case 0x03e: /* VIS I pdist */
4277 CHECK_FPU_FEATURE(dc
, VIS1
);
4278 gen_ne_fop_DDDD(dc
, rd
, rs1
, rs2
, gen_helper_pdist
);
4280 case 0x048: /* VIS I faligndata */
4281 CHECK_FPU_FEATURE(dc
, VIS1
);
4282 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_faligndata
);
4284 case 0x04b: /* VIS I fpmerge */
4285 CHECK_FPU_FEATURE(dc
, VIS1
);
4286 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpmerge
);
4288 case 0x04c: /* VIS II bshuffle */
4289 CHECK_FPU_FEATURE(dc
, VIS2
);
4290 gen_gsr_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_bshuffle
);
4292 case 0x04d: /* VIS I fexpand */
4293 CHECK_FPU_FEATURE(dc
, VIS1
);
4294 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fexpand
);
4296 case 0x050: /* VIS I fpadd16 */
4297 CHECK_FPU_FEATURE(dc
, VIS1
);
4298 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpadd16
);
4300 case 0x051: /* VIS I fpadd16s */
4301 CHECK_FPU_FEATURE(dc
, VIS1
);
4302 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fpadd16s
);
4304 case 0x052: /* VIS I fpadd32 */
4305 CHECK_FPU_FEATURE(dc
, VIS1
);
4306 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpadd32
);
4308 case 0x053: /* VIS I fpadd32s */
4309 CHECK_FPU_FEATURE(dc
, VIS1
);
4310 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_add_i32
);
4312 case 0x054: /* VIS I fpsub16 */
4313 CHECK_FPU_FEATURE(dc
, VIS1
);
4314 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpsub16
);
4316 case 0x055: /* VIS I fpsub16s */
4317 CHECK_FPU_FEATURE(dc
, VIS1
);
4318 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, gen_helper_fpsub16s
);
4320 case 0x056: /* VIS I fpsub32 */
4321 CHECK_FPU_FEATURE(dc
, VIS1
);
4322 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, gen_helper_fpsub32
);
4324 case 0x057: /* VIS I fpsub32s */
4325 CHECK_FPU_FEATURE(dc
, VIS1
);
4326 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_sub_i32
);
4328 case 0x060: /* VIS I fzero */
4329 CHECK_FPU_FEATURE(dc
, VIS1
);
4330 cpu_dst_64
= gen_dest_fpr_D(dc
, rd
);
4331 tcg_gen_movi_i64(cpu_dst_64
, 0);
4332 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4334 case 0x061: /* VIS I fzeros */
4335 CHECK_FPU_FEATURE(dc
, VIS1
);
4336 cpu_dst_32
= gen_dest_fpr_F(dc
);
4337 tcg_gen_movi_i32(cpu_dst_32
, 0);
4338 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4340 case 0x062: /* VIS I fnor */
4341 CHECK_FPU_FEATURE(dc
, VIS1
);
4342 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_nor_i64
);
4344 case 0x063: /* VIS I fnors */
4345 CHECK_FPU_FEATURE(dc
, VIS1
);
4346 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_nor_i32
);
4348 case 0x064: /* VIS I fandnot2 */
4349 CHECK_FPU_FEATURE(dc
, VIS1
);
4350 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_andc_i64
);
4352 case 0x065: /* VIS I fandnot2s */
4353 CHECK_FPU_FEATURE(dc
, VIS1
);
4354 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_andc_i32
);
4356 case 0x066: /* VIS I fnot2 */
4357 CHECK_FPU_FEATURE(dc
, VIS1
);
4358 gen_ne_fop_DD(dc
, rd
, rs2
, tcg_gen_not_i64
);
4360 case 0x067: /* VIS I fnot2s */
4361 CHECK_FPU_FEATURE(dc
, VIS1
);
4362 gen_ne_fop_FF(dc
, rd
, rs2
, tcg_gen_not_i32
);
4364 case 0x068: /* VIS I fandnot1 */
4365 CHECK_FPU_FEATURE(dc
, VIS1
);
4366 gen_ne_fop_DDD(dc
, rd
, rs2
, rs1
, tcg_gen_andc_i64
);
4368 case 0x069: /* VIS I fandnot1s */
4369 CHECK_FPU_FEATURE(dc
, VIS1
);
4370 gen_ne_fop_FFF(dc
, rd
, rs2
, rs1
, tcg_gen_andc_i32
);
4372 case 0x06a: /* VIS I fnot1 */
4373 CHECK_FPU_FEATURE(dc
, VIS1
);
4374 gen_ne_fop_DD(dc
, rd
, rs1
, tcg_gen_not_i64
);
4376 case 0x06b: /* VIS I fnot1s */
4377 CHECK_FPU_FEATURE(dc
, VIS1
);
4378 gen_ne_fop_FF(dc
, rd
, rs1
, tcg_gen_not_i32
);
4380 case 0x06c: /* VIS I fxor */
4381 CHECK_FPU_FEATURE(dc
, VIS1
);
4382 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_xor_i64
);
4384 case 0x06d: /* VIS I fxors */
4385 CHECK_FPU_FEATURE(dc
, VIS1
);
4386 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_xor_i32
);
4388 case 0x06e: /* VIS I fnand */
4389 CHECK_FPU_FEATURE(dc
, VIS1
);
4390 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_nand_i64
);
4392 case 0x06f: /* VIS I fnands */
4393 CHECK_FPU_FEATURE(dc
, VIS1
);
4394 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_nand_i32
);
4396 case 0x070: /* VIS I fand */
4397 CHECK_FPU_FEATURE(dc
, VIS1
);
4398 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_and_i64
);
4400 case 0x071: /* VIS I fands */
4401 CHECK_FPU_FEATURE(dc
, VIS1
);
4402 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_and_i32
);
4404 case 0x072: /* VIS I fxnor */
4405 CHECK_FPU_FEATURE(dc
, VIS1
);
4406 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_eqv_i64
);
4408 case 0x073: /* VIS I fxnors */
4409 CHECK_FPU_FEATURE(dc
, VIS1
);
4410 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_eqv_i32
);
4412 case 0x074: /* VIS I fsrc1 */
4413 CHECK_FPU_FEATURE(dc
, VIS1
);
4414 cpu_src1_64
= gen_load_fpr_D(dc
, rs1
);
4415 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
4417 case 0x075: /* VIS I fsrc1s */
4418 CHECK_FPU_FEATURE(dc
, VIS1
);
4419 cpu_src1_32
= gen_load_fpr_F(dc
, rs1
);
4420 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
4422 case 0x076: /* VIS I fornot2 */
4423 CHECK_FPU_FEATURE(dc
, VIS1
);
4424 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_orc_i64
);
4426 case 0x077: /* VIS I fornot2s */
4427 CHECK_FPU_FEATURE(dc
, VIS1
);
4428 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_orc_i32
);
4430 case 0x078: /* VIS I fsrc2 */
4431 CHECK_FPU_FEATURE(dc
, VIS1
);
4432 cpu_src1_64
= gen_load_fpr_D(dc
, rs2
);
4433 gen_store_fpr_D(dc
, rd
, cpu_src1_64
);
4435 case 0x079: /* VIS I fsrc2s */
4436 CHECK_FPU_FEATURE(dc
, VIS1
);
4437 cpu_src1_32
= gen_load_fpr_F(dc
, rs2
);
4438 gen_store_fpr_F(dc
, rd
, cpu_src1_32
);
4440 case 0x07a: /* VIS I fornot1 */
4441 CHECK_FPU_FEATURE(dc
, VIS1
);
4442 gen_ne_fop_DDD(dc
, rd
, rs2
, rs1
, tcg_gen_orc_i64
);
4444 case 0x07b: /* VIS I fornot1s */
4445 CHECK_FPU_FEATURE(dc
, VIS1
);
4446 gen_ne_fop_FFF(dc
, rd
, rs2
, rs1
, tcg_gen_orc_i32
);
4448 case 0x07c: /* VIS I for */
4449 CHECK_FPU_FEATURE(dc
, VIS1
);
4450 gen_ne_fop_DDD(dc
, rd
, rs1
, rs2
, tcg_gen_or_i64
);
4452 case 0x07d: /* VIS I fors */
4453 CHECK_FPU_FEATURE(dc
, VIS1
);
4454 gen_ne_fop_FFF(dc
, rd
, rs1
, rs2
, tcg_gen_or_i32
);
4456 case 0x07e: /* VIS I fone */
4457 CHECK_FPU_FEATURE(dc
, VIS1
);
4458 cpu_dst_64
= gen_dest_fpr_D(dc
, rd
);
4459 tcg_gen_movi_i64(cpu_dst_64
, -1);
4460 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4462 case 0x07f: /* VIS I fones */
4463 CHECK_FPU_FEATURE(dc
, VIS1
);
4464 cpu_dst_32
= gen_dest_fpr_F(dc
);
4465 tcg_gen_movi_i32(cpu_dst_32
, -1);
4466 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4468 case 0x080: /* VIS I shutdown */
4469 case 0x081: /* VIS II siam */
4478 } else if (xop
== 0x37) { /* V8 CPop2, V9 impdep2 */
4479 #ifdef TARGET_SPARC64
4484 #ifdef TARGET_SPARC64
4485 } else if (xop
== 0x39) { /* V9 return */
4489 cpu_src1
= get_src1(dc
, insn
);
4490 cpu_tmp0
= get_temp_tl(dc
);
4491 if (IS_IMM
) { /* immediate */
4492 simm
= GET_FIELDs(insn
, 19, 31);
4493 tcg_gen_addi_tl(cpu_tmp0
, cpu_src1
, simm
);
4494 } else { /* register */
4495 rs2
= GET_FIELD(insn
, 27, 31);
4497 cpu_src2
= gen_load_gpr(dc
, rs2
);
4498 tcg_gen_add_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
4500 tcg_gen_mov_tl(cpu_tmp0
, cpu_src1
);
4503 gen_helper_restore(cpu_env
);
4505 r_const
= tcg_const_i32(3);
4506 gen_helper_check_align(cpu_env
, cpu_tmp0
, r_const
);
4507 tcg_temp_free_i32(r_const
);
4508 tcg_gen_mov_tl(cpu_npc
, cpu_tmp0
);
4509 dc
->npc
= DYNAMIC_PC
;
4513 cpu_src1
= get_src1(dc
, insn
);
4514 cpu_tmp0
= get_temp_tl(dc
);
4515 if (IS_IMM
) { /* immediate */
4516 simm
= GET_FIELDs(insn
, 19, 31);
4517 tcg_gen_addi_tl(cpu_tmp0
, cpu_src1
, simm
);
4518 } else { /* register */
4519 rs2
= GET_FIELD(insn
, 27, 31);
4521 cpu_src2
= gen_load_gpr(dc
, rs2
);
4522 tcg_gen_add_tl(cpu_tmp0
, cpu_src1
, cpu_src2
);
4524 tcg_gen_mov_tl(cpu_tmp0
, cpu_src1
);
4528 case 0x38: /* jmpl */
4533 t
= gen_dest_gpr(dc
, rd
);
4534 tcg_gen_movi_tl(t
, dc
->pc
);
4535 gen_store_gpr(dc
, rd
, t
);
4537 r_const
= tcg_const_i32(3);
4538 gen_helper_check_align(cpu_env
, cpu_tmp0
, r_const
);
4539 tcg_temp_free_i32(r_const
);
4540 gen_address_mask(dc
, cpu_tmp0
);
4541 tcg_gen_mov_tl(cpu_npc
, cpu_tmp0
);
4542 dc
->npc
= DYNAMIC_PC
;
4545 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4546 case 0x39: /* rett, V9 return */
4550 if (!supervisor(dc
))
4553 r_const
= tcg_const_i32(3);
4554 gen_helper_check_align(cpu_env
, cpu_tmp0
, r_const
);
4555 tcg_temp_free_i32(r_const
);
4556 tcg_gen_mov_tl(cpu_npc
, cpu_tmp0
);
4557 dc
->npc
= DYNAMIC_PC
;
4558 gen_helper_rett(cpu_env
);
4562 case 0x3b: /* flush */
4563 if (!((dc
)->def
->features
& CPU_FEATURE_FLUSH
))
4567 case 0x3c: /* save */
4569 gen_helper_save(cpu_env
);
4570 gen_store_gpr(dc
, rd
, cpu_tmp0
);
4572 case 0x3d: /* restore */
4574 gen_helper_restore(cpu_env
);
4575 gen_store_gpr(dc
, rd
, cpu_tmp0
);
4577 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4578 case 0x3e: /* V9 done/retry */
4582 if (!supervisor(dc
))
4584 dc
->npc
= DYNAMIC_PC
;
4585 dc
->pc
= DYNAMIC_PC
;
4586 gen_helper_done(cpu_env
);
4589 if (!supervisor(dc
))
4591 dc
->npc
= DYNAMIC_PC
;
4592 dc
->pc
= DYNAMIC_PC
;
4593 gen_helper_retry(cpu_env
);
4608 case 3: /* load/store instructions */
4610 unsigned int xop
= GET_FIELD(insn
, 7, 12);
4611 /* ??? gen_address_mask prevents us from using a source
4612 register directly. Always generate a temporary. */
4613 TCGv cpu_addr
= get_temp_tl(dc
);
4615 tcg_gen_mov_tl(cpu_addr
, get_src1(dc
, insn
));
4616 if (xop
== 0x3c || xop
== 0x3e) {
4617 /* V9 casa/casxa : no offset */
4618 } else if (IS_IMM
) { /* immediate */
4619 simm
= GET_FIELDs(insn
, 19, 31);
4621 tcg_gen_addi_tl(cpu_addr
, cpu_addr
, simm
);
4623 } else { /* register */
4624 rs2
= GET_FIELD(insn
, 27, 31);
4626 tcg_gen_add_tl(cpu_addr
, cpu_addr
, gen_load_gpr(dc
, rs2
));
4629 if (xop
< 4 || (xop
> 7 && xop
< 0x14 && xop
!= 0x0e) ||
4630 (xop
> 0x17 && xop
<= 0x1d ) ||
4631 (xop
> 0x2c && xop
<= 0x33) || xop
== 0x1f || xop
== 0x3d) {
4632 TCGv cpu_val
= gen_dest_gpr(dc
, rd
);
4635 case 0x0: /* ld, V9 lduw, load unsigned word */
4636 gen_address_mask(dc
, cpu_addr
);
4637 tcg_gen_qemu_ld32u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4639 case 0x1: /* ldub, load unsigned byte */
4640 gen_address_mask(dc
, cpu_addr
);
4641 tcg_gen_qemu_ld8u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4643 case 0x2: /* lduh, load unsigned halfword */
4644 gen_address_mask(dc
, cpu_addr
);
4645 tcg_gen_qemu_ld16u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4647 case 0x3: /* ldd, load double word */
4655 r_const
= tcg_const_i32(7);
4656 /* XXX remove alignment check */
4657 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
4658 tcg_temp_free_i32(r_const
);
4659 gen_address_mask(dc
, cpu_addr
);
4660 t64
= tcg_temp_new_i64();
4661 tcg_gen_qemu_ld64(t64
, cpu_addr
, dc
->mem_idx
);
4662 tcg_gen_trunc_i64_tl(cpu_val
, t64
);
4663 tcg_gen_ext32u_tl(cpu_val
, cpu_val
);
4664 gen_store_gpr(dc
, rd
+ 1, cpu_val
);
4665 tcg_gen_shri_i64(t64
, t64
, 32);
4666 tcg_gen_trunc_i64_tl(cpu_val
, t64
);
4667 tcg_temp_free_i64(t64
);
4668 tcg_gen_ext32u_tl(cpu_val
, cpu_val
);
4671 case 0x9: /* ldsb, load signed byte */
4672 gen_address_mask(dc
, cpu_addr
);
4673 tcg_gen_qemu_ld8s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4675 case 0xa: /* ldsh, load signed halfword */
4676 gen_address_mask(dc
, cpu_addr
);
4677 tcg_gen_qemu_ld16s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4679 case 0xd: /* ldstub -- XXX: should be atomically */
4683 gen_address_mask(dc
, cpu_addr
);
4684 tcg_gen_qemu_ld8u(cpu_val
, cpu_addr
, dc
->mem_idx
);
4685 r_const
= tcg_const_tl(0xff);
4686 tcg_gen_qemu_st8(r_const
, cpu_addr
, dc
->mem_idx
);
4687 tcg_temp_free(r_const
);
4691 /* swap, swap register with memory. Also atomically */
4693 TCGv t0
= get_temp_tl(dc
);
4694 CHECK_IU_FEATURE(dc
, SWAP
);
4695 cpu_src1
= gen_load_gpr(dc
, rd
);
4696 gen_address_mask(dc
, cpu_addr
);
4697 tcg_gen_qemu_ld32u(t0
, cpu_addr
, dc
->mem_idx
);
4698 tcg_gen_qemu_st32(cpu_src1
, cpu_addr
, dc
->mem_idx
);
4699 tcg_gen_mov_tl(cpu_val
, t0
);
4702 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4703 case 0x10: /* lda, V9 lduwa, load word alternate */
4704 #ifndef TARGET_SPARC64
4707 if (!supervisor(dc
))
4711 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 0);
4713 case 0x11: /* lduba, load unsigned byte alternate */
4714 #ifndef TARGET_SPARC64
4717 if (!supervisor(dc
))
4721 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 0);
4723 case 0x12: /* lduha, load unsigned halfword alternate */
4724 #ifndef TARGET_SPARC64
4727 if (!supervisor(dc
))
4731 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 0);
4733 case 0x13: /* ldda, load double word alternate */
4734 #ifndef TARGET_SPARC64
4737 if (!supervisor(dc
))
4743 gen_ldda_asi(dc
, cpu_val
, cpu_addr
, insn
, rd
);
4745 case 0x19: /* ldsba, load signed byte alternate */
4746 #ifndef TARGET_SPARC64
4749 if (!supervisor(dc
))
4753 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 1, 1);
4755 case 0x1a: /* ldsha, load signed halfword alternate */
4756 #ifndef TARGET_SPARC64
4759 if (!supervisor(dc
))
4763 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 2, 1);
4765 case 0x1d: /* ldstuba -- XXX: should be atomically */
4766 #ifndef TARGET_SPARC64
4769 if (!supervisor(dc
))
4773 gen_ldstub_asi(cpu_val
, cpu_addr
, insn
);
4775 case 0x1f: /* swapa, swap reg with alt. memory. Also
4777 CHECK_IU_FEATURE(dc
, SWAP
);
4778 #ifndef TARGET_SPARC64
4781 if (!supervisor(dc
))
4785 cpu_src1
= gen_load_gpr(dc
, rd
);
4786 gen_swap_asi(cpu_val
, cpu_src1
, cpu_addr
, insn
);
4789 #ifndef TARGET_SPARC64
4790 case 0x30: /* ldc */
4791 case 0x31: /* ldcsr */
4792 case 0x33: /* lddc */
4796 #ifdef TARGET_SPARC64
4797 case 0x08: /* V9 ldsw */
4798 gen_address_mask(dc
, cpu_addr
);
4799 tcg_gen_qemu_ld32s(cpu_val
, cpu_addr
, dc
->mem_idx
);
4801 case 0x0b: /* V9 ldx */
4802 gen_address_mask(dc
, cpu_addr
);
4803 tcg_gen_qemu_ld64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4805 case 0x18: /* V9 ldswa */
4807 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 4, 1);
4809 case 0x1b: /* V9 ldxa */
4811 gen_ld_asi(cpu_val
, cpu_addr
, insn
, 8, 0);
4813 case 0x2d: /* V9 prefetch, no effect */
4815 case 0x30: /* V9 ldfa */
4816 if (gen_trap_ifnofpu(dc
)) {
4820 gen_ldf_asi(cpu_addr
, insn
, 4, rd
);
4821 gen_update_fprs_dirty(rd
);
4823 case 0x33: /* V9 lddfa */
4824 if (gen_trap_ifnofpu(dc
)) {
4828 gen_ldf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
4829 gen_update_fprs_dirty(DFPREG(rd
));
4831 case 0x3d: /* V9 prefetcha, no effect */
4833 case 0x32: /* V9 ldqfa */
4834 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4835 if (gen_trap_ifnofpu(dc
)) {
4839 gen_ldf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
4840 gen_update_fprs_dirty(QFPREG(rd
));
4846 gen_store_gpr(dc
, rd
, cpu_val
);
4847 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4850 } else if (xop
>= 0x20 && xop
< 0x24) {
4853 if (gen_trap_ifnofpu(dc
)) {
4858 case 0x20: /* ldf, load fpreg */
4859 gen_address_mask(dc
, cpu_addr
);
4860 t0
= get_temp_tl(dc
);
4861 tcg_gen_qemu_ld32u(t0
, cpu_addr
, dc
->mem_idx
);
4862 cpu_dst_32
= gen_dest_fpr_F(dc
);
4863 tcg_gen_trunc_tl_i32(cpu_dst_32
, t0
);
4864 gen_store_fpr_F(dc
, rd
, cpu_dst_32
);
4866 case 0x21: /* ldfsr, V9 ldxfsr */
4867 #ifdef TARGET_SPARC64
4868 gen_address_mask(dc
, cpu_addr
);
4870 TCGv_i64 t64
= tcg_temp_new_i64();
4871 tcg_gen_qemu_ld64(t64
, cpu_addr
, dc
->mem_idx
);
4872 gen_helper_ldxfsr(cpu_env
, t64
);
4873 tcg_temp_free_i64(t64
);
4877 cpu_dst_32
= get_temp_i32(dc
);
4878 t0
= get_temp_tl(dc
);
4879 tcg_gen_qemu_ld32u(t0
, cpu_addr
, dc
->mem_idx
);
4880 tcg_gen_trunc_tl_i32(cpu_dst_32
, t0
);
4881 gen_helper_ldfsr(cpu_env
, cpu_dst_32
);
4883 case 0x22: /* ldqf, load quad fpreg */
4887 CHECK_FPU_FEATURE(dc
, FLOAT128
);
4888 r_const
= tcg_const_i32(dc
->mem_idx
);
4889 gen_address_mask(dc
, cpu_addr
);
4890 gen_helper_ldqf(cpu_env
, cpu_addr
, r_const
);
4891 tcg_temp_free_i32(r_const
);
4892 gen_op_store_QT0_fpr(QFPREG(rd
));
4893 gen_update_fprs_dirty(QFPREG(rd
));
4896 case 0x23: /* lddf, load double fpreg */
4897 gen_address_mask(dc
, cpu_addr
);
4898 cpu_dst_64
= gen_dest_fpr_D(dc
, rd
);
4899 tcg_gen_qemu_ld64(cpu_dst_64
, cpu_addr
, dc
->mem_idx
);
4900 gen_store_fpr_D(dc
, rd
, cpu_dst_64
);
4905 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18) ||
4906 xop
== 0xe || xop
== 0x1e) {
4907 TCGv cpu_val
= gen_load_gpr(dc
, rd
);
4910 case 0x4: /* st, store word */
4911 gen_address_mask(dc
, cpu_addr
);
4912 tcg_gen_qemu_st32(cpu_val
, cpu_addr
, dc
->mem_idx
);
4914 case 0x5: /* stb, store byte */
4915 gen_address_mask(dc
, cpu_addr
);
4916 tcg_gen_qemu_st8(cpu_val
, cpu_addr
, dc
->mem_idx
);
4918 case 0x6: /* sth, store halfword */
4919 gen_address_mask(dc
, cpu_addr
);
4920 tcg_gen_qemu_st16(cpu_val
, cpu_addr
, dc
->mem_idx
);
4922 case 0x7: /* std, store double word */
4931 gen_address_mask(dc
, cpu_addr
);
4932 r_const
= tcg_const_i32(7);
4933 /* XXX remove alignment check */
4934 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
4935 tcg_temp_free_i32(r_const
);
4936 lo
= gen_load_gpr(dc
, rd
+ 1);
4938 t64
= tcg_temp_new_i64();
4939 tcg_gen_concat_tl_i64(t64
, lo
, cpu_val
);
4940 tcg_gen_qemu_st64(t64
, cpu_addr
, dc
->mem_idx
);
4941 tcg_temp_free_i64(t64
);
4944 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4945 case 0x14: /* sta, V9 stwa, store word alternate */
4946 #ifndef TARGET_SPARC64
4949 if (!supervisor(dc
))
4953 gen_st_asi(cpu_val
, cpu_addr
, insn
, 4);
4954 dc
->npc
= DYNAMIC_PC
;
4956 case 0x15: /* stba, store byte alternate */
4957 #ifndef TARGET_SPARC64
4960 if (!supervisor(dc
))
4964 gen_st_asi(cpu_val
, cpu_addr
, insn
, 1);
4965 dc
->npc
= DYNAMIC_PC
;
4967 case 0x16: /* stha, store halfword alternate */
4968 #ifndef TARGET_SPARC64
4971 if (!supervisor(dc
))
4975 gen_st_asi(cpu_val
, cpu_addr
, insn
, 2);
4976 dc
->npc
= DYNAMIC_PC
;
4978 case 0x17: /* stda, store double word alternate */
4979 #ifndef TARGET_SPARC64
4982 if (!supervisor(dc
))
4989 gen_stda_asi(dc
, cpu_val
, cpu_addr
, insn
, rd
);
4993 #ifdef TARGET_SPARC64
4994 case 0x0e: /* V9 stx */
4995 gen_address_mask(dc
, cpu_addr
);
4996 tcg_gen_qemu_st64(cpu_val
, cpu_addr
, dc
->mem_idx
);
4998 case 0x1e: /* V9 stxa */
5000 gen_st_asi(cpu_val
, cpu_addr
, insn
, 8);
5001 dc
->npc
= DYNAMIC_PC
;
5007 } else if (xop
> 0x23 && xop
< 0x28) {
5008 if (gen_trap_ifnofpu(dc
)) {
5013 case 0x24: /* stf, store fpreg */
5015 TCGv t
= get_temp_tl(dc
);
5016 gen_address_mask(dc
, cpu_addr
);
5017 cpu_src1_32
= gen_load_fpr_F(dc
, rd
);
5018 tcg_gen_ext_i32_tl(t
, cpu_src1_32
);
5019 tcg_gen_qemu_st32(t
, cpu_addr
, dc
->mem_idx
);
5022 case 0x25: /* stfsr, V9 stxfsr */
5024 TCGv t
= get_temp_tl(dc
);
5026 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUSPARCState
, fsr
));
5027 #ifdef TARGET_SPARC64
5028 gen_address_mask(dc
, cpu_addr
);
5030 tcg_gen_qemu_st64(t
, cpu_addr
, dc
->mem_idx
);
5034 tcg_gen_qemu_st32(t
, cpu_addr
, dc
->mem_idx
);
5038 #ifdef TARGET_SPARC64
5039 /* V9 stqf, store quad fpreg */
5043 CHECK_FPU_FEATURE(dc
, FLOAT128
);
5044 gen_op_load_fpr_QT0(QFPREG(rd
));
5045 r_const
= tcg_const_i32(dc
->mem_idx
);
5046 gen_address_mask(dc
, cpu_addr
);
5047 gen_helper_stqf(cpu_env
, cpu_addr
, r_const
);
5048 tcg_temp_free_i32(r_const
);
5051 #else /* !TARGET_SPARC64 */
5052 /* stdfq, store floating point queue */
5053 #if defined(CONFIG_USER_ONLY)
5056 if (!supervisor(dc
))
5058 if (gen_trap_ifnofpu(dc
)) {
5064 case 0x27: /* stdf, store double fpreg */
5065 gen_address_mask(dc
, cpu_addr
);
5066 cpu_src1_64
= gen_load_fpr_D(dc
, rd
);
5067 tcg_gen_qemu_st64(cpu_src1_64
, cpu_addr
, dc
->mem_idx
);
5072 } else if (xop
> 0x33 && xop
< 0x3f) {
5075 #ifdef TARGET_SPARC64
5076 case 0x34: /* V9 stfa */
5077 if (gen_trap_ifnofpu(dc
)) {
5080 gen_stf_asi(cpu_addr
, insn
, 4, rd
);
5082 case 0x36: /* V9 stqfa */
5086 CHECK_FPU_FEATURE(dc
, FLOAT128
);
5087 if (gen_trap_ifnofpu(dc
)) {
5090 r_const
= tcg_const_i32(7);
5091 gen_helper_check_align(cpu_env
, cpu_addr
, r_const
);
5092 tcg_temp_free_i32(r_const
);
5093 gen_stf_asi(cpu_addr
, insn
, 16, QFPREG(rd
));
5096 case 0x37: /* V9 stdfa */
5097 if (gen_trap_ifnofpu(dc
)) {
5100 gen_stf_asi(cpu_addr
, insn
, 8, DFPREG(rd
));
5102 case 0x3e: /* V9 casxa */
5103 rs2
= GET_FIELD(insn
, 27, 31);
5104 cpu_src2
= gen_load_gpr(dc
, rs2
);
5105 gen_casx_asi(dc
, cpu_addr
, cpu_src2
, insn
, rd
);
5108 case 0x34: /* stc */
5109 case 0x35: /* stcsr */
5110 case 0x36: /* stdcq */
5111 case 0x37: /* stdc */
5114 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5115 case 0x3c: /* V9 or LEON3 casa */
5116 #ifndef TARGET_SPARC64
5117 CHECK_IU_FEATURE(dc
, CASA
);
5121 /* LEON3 allows CASA from user space with ASI 0xa */
5122 if ((GET_FIELD(insn
, 19, 26) != 0xa) && !supervisor(dc
)) {
5126 rs2
= GET_FIELD(insn
, 27, 31);
5127 cpu_src2
= gen_load_gpr(dc
, rs2
);
5128 gen_cas_asi(dc
, cpu_addr
, cpu_src2
, insn
, rd
);
5140 /* default case for non jump instructions */
5141 if (dc
->npc
== DYNAMIC_PC
) {
5142 dc
->pc
= DYNAMIC_PC
;
5144 } else if (dc
->npc
== JUMP_PC
) {
5145 /* we can do a static jump */
5146 gen_branch2(dc
, dc
->jump_pc
[0], dc
->jump_pc
[1], cpu_cond
);
5150 dc
->npc
= dc
->npc
+ 4;
5159 r_const
= tcg_const_i32(TT_ILL_INSN
);
5160 gen_helper_raise_exception(cpu_env
, r_const
);
5161 tcg_temp_free_i32(r_const
);
5170 r_const
= tcg_const_i32(TT_UNIMP_FLUSH
);
5171 gen_helper_raise_exception(cpu_env
, r_const
);
5172 tcg_temp_free_i32(r_const
);
5176 #if !defined(CONFIG_USER_ONLY)
5182 r_const
= tcg_const_i32(TT_PRIV_INSN
);
5183 gen_helper_raise_exception(cpu_env
, r_const
);
5184 tcg_temp_free_i32(r_const
);
5191 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP
);
5194 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
5197 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR
);
5201 #ifndef TARGET_SPARC64
5207 r_const
= tcg_const_i32(TT_NCP_INSN
);
5208 gen_helper_raise_exception(cpu_env
, r_const
);
5209 tcg_temp_free(r_const
);
5215 if (dc
->n_t32
!= 0) {
5217 for (i
= dc
->n_t32
- 1; i
>= 0; --i
) {
5218 tcg_temp_free_i32(dc
->t32
[i
]);
5222 if (dc
->n_ttl
!= 0) {
5224 for (i
= dc
->n_ttl
- 1; i
>= 0; --i
) {
5225 tcg_temp_free(dc
->ttl
[i
]);
5231 void gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
5233 SPARCCPU
*cpu
= sparc_env_get_cpu(env
);
5234 CPUState
*cs
= CPU(cpu
);
5235 target_ulong pc_start
, last_pc
;
5236 DisasContext dc1
, *dc
= &dc1
;
5241 memset(dc
, 0, sizeof(DisasContext
));
5246 dc
->npc
= (target_ulong
) tb
->cs_base
;
5247 dc
->cc_op
= CC_OP_DYNAMIC
;
5248 dc
->mem_idx
= cpu_mmu_index(env
, false);
5250 dc
->fpu_enabled
= tb_fpu_enabled(tb
->flags
);
5251 dc
->address_mask_32bit
= tb_am_enabled(tb
->flags
);
5252 dc
->singlestep
= (cs
->singlestep_enabled
|| singlestep
);
5255 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
5256 if (max_insns
== 0) {
5257 max_insns
= CF_COUNT_MASK
;
5259 if (max_insns
> TCG_MAX_INSNS
) {
5260 max_insns
= TCG_MAX_INSNS
;
5265 if (dc
->npc
& JUMP_PC
) {
5266 assert(dc
->jump_pc
[1] == dc
->pc
+ 4);
5267 tcg_gen_insn_start(dc
->pc
, dc
->jump_pc
[0] | JUMP_PC
);
5269 tcg_gen_insn_start(dc
->pc
, dc
->npc
);
5274 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
5275 if (dc
->pc
!= pc_start
) {
5278 gen_helper_debug(cpu_env
);
5284 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
5288 insn
= cpu_ldl_code(env
, dc
->pc
);
5290 disas_sparc_insn(dc
, insn
);
5294 /* if the next PC is different, we abort now */
5295 if (dc
->pc
!= (last_pc
+ 4))
5297 /* if we reach a page boundary, we stop generation so that the
5298 PC of a TT_TFAULT exception is always in the right page */
5299 if ((dc
->pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
5301 /* if single step mode, we generate only one instruction and
5302 generate an exception */
5303 if (dc
->singlestep
) {
5306 } while (!tcg_op_buf_full() &&
5307 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32) &&
5308 num_insns
< max_insns
);
5311 if (tb
->cflags
& CF_LAST_IO
) {
5315 if (dc
->pc
!= DYNAMIC_PC
&&
5316 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
5317 /* static PC and NPC: we can use direct chaining */
5318 gen_goto_tb(dc
, 0, dc
->pc
, dc
->npc
);
5320 if (dc
->pc
!= DYNAMIC_PC
) {
5321 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
5327 gen_tb_end(tb
, num_insns
);
5329 tb
->size
= last_pc
+ 4 - pc_start
;
5330 tb
->icount
= num_insns
;
5333 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
5334 && qemu_log_in_addr_range(pc_start
)) {
5335 qemu_log("--------------\n");
5336 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5337 log_target_disas(cs
, pc_start
, last_pc
+ 4 - pc_start
, 0);
5343 void gen_intermediate_code_init(CPUSPARCState
*env
)
5346 static const char gregnames
[32][4] = {
5347 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
5348 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5349 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5350 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
5352 static const char fregnames
[32][4] = {
5353 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5354 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5355 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5356 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5359 static const struct { TCGv_i32
*ptr
; int off
; const char *name
; } r32
[] = {
5360 #ifdef TARGET_SPARC64
5361 { &cpu_xcc
, offsetof(CPUSPARCState
, xcc
), "xcc" },
5362 { &cpu_asi
, offsetof(CPUSPARCState
, asi
), "asi" },
5363 { &cpu_fprs
, offsetof(CPUSPARCState
, fprs
), "fprs" },
5364 { &cpu_softint
, offsetof(CPUSPARCState
, softint
), "softint" },
5366 { &cpu_wim
, offsetof(CPUSPARCState
, wim
), "wim" },
5368 { &cpu_cc_op
, offsetof(CPUSPARCState
, cc_op
), "cc_op" },
5369 { &cpu_psr
, offsetof(CPUSPARCState
, psr
), "psr" },
5372 static const struct { TCGv
*ptr
; int off
; const char *name
; } rtl
[] = {
5373 #ifdef TARGET_SPARC64
5374 { &cpu_gsr
, offsetof(CPUSPARCState
, gsr
), "gsr" },
5375 { &cpu_tick_cmpr
, offsetof(CPUSPARCState
, tick_cmpr
), "tick_cmpr" },
5376 { &cpu_stick_cmpr
, offsetof(CPUSPARCState
, stick_cmpr
), "stick_cmpr" },
5377 { &cpu_hstick_cmpr
, offsetof(CPUSPARCState
, hstick_cmpr
),
5379 { &cpu_hintp
, offsetof(CPUSPARCState
, hintp
), "hintp" },
5380 { &cpu_htba
, offsetof(CPUSPARCState
, htba
), "htba" },
5381 { &cpu_hver
, offsetof(CPUSPARCState
, hver
), "hver" },
5382 { &cpu_ssr
, offsetof(CPUSPARCState
, ssr
), "ssr" },
5383 { &cpu_ver
, offsetof(CPUSPARCState
, version
), "ver" },
5385 { &cpu_cond
, offsetof(CPUSPARCState
, cond
), "cond" },
5386 { &cpu_cc_src
, offsetof(CPUSPARCState
, cc_src
), "cc_src" },
5387 { &cpu_cc_src2
, offsetof(CPUSPARCState
, cc_src2
), "cc_src2" },
5388 { &cpu_cc_dst
, offsetof(CPUSPARCState
, cc_dst
), "cc_dst" },
5389 { &cpu_fsr
, offsetof(CPUSPARCState
, fsr
), "fsr" },
5390 { &cpu_pc
, offsetof(CPUSPARCState
, pc
), "pc" },
5391 { &cpu_npc
, offsetof(CPUSPARCState
, npc
), "npc" },
5392 { &cpu_y
, offsetof(CPUSPARCState
, y
), "y" },
5393 #ifndef CONFIG_USER_ONLY
5394 { &cpu_tbr
, offsetof(CPUSPARCState
, tbr
), "tbr" },
5400 /* init various static tables */
5406 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
5407 tcg_ctx
.tcg_env
= cpu_env
;
5409 cpu_regwptr
= tcg_global_mem_new_ptr(cpu_env
,
5410 offsetof(CPUSPARCState
, regwptr
),
5413 for (i
= 0; i
< ARRAY_SIZE(r32
); ++i
) {
5414 *r32
[i
].ptr
= tcg_global_mem_new_i32(cpu_env
, r32
[i
].off
, r32
[i
].name
);
5417 for (i
= 0; i
< ARRAY_SIZE(rtl
); ++i
) {
5418 *rtl
[i
].ptr
= tcg_global_mem_new(cpu_env
, rtl
[i
].off
, rtl
[i
].name
);
5421 TCGV_UNUSED(cpu_regs
[0]);
5422 for (i
= 1; i
< 8; ++i
) {
5423 cpu_regs
[i
] = tcg_global_mem_new(cpu_env
,
5424 offsetof(CPUSPARCState
, gregs
[i
]),
5428 for (i
= 8; i
< 32; ++i
) {
5429 cpu_regs
[i
] = tcg_global_mem_new(cpu_regwptr
,
5430 (i
- 8) * sizeof(target_ulong
),
5434 for (i
= 0; i
< TARGET_DPREGS
; i
++) {
5435 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
5436 offsetof(CPUSPARCState
, fpr
[i
]),
5441 void restore_state_to_opc(CPUSPARCState
*env
, TranslationBlock
*tb
,
5444 target_ulong pc
= data
[0];
5445 target_ulong npc
= data
[1];
5448 if (npc
== DYNAMIC_PC
) {
5449 /* dynamic NPC: already stored */
5450 } else if (npc
& JUMP_PC
) {
5451 /* jump PC: use 'cond' and the jump targets of the translation */
5453 env
->npc
= npc
& ~3;