target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #if !defined (__CPU_PPC_H__)
  20 #define __CPU_PPC_H__
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 //#define PPC_EMULATE_32BITS_HYPV
  26
  27 #if defined (TARGET_PPC64)
  28 /* PowerPC 64 definitions */
  29 #define TARGET_LONG_BITS 64
  30 #define TARGET_PAGE_BITS 12
  31
  32 /* Note that the official physical address space bits is 62-M where M
  33    is implementation dependent.  I've not looked up M for the set of
  34    cpus we emulate at the system level.  */
  35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  36
  37 /* Note that the PPC environment architecture talks about 80 bit virtual
  38    addresses, with segmentation.  Obviously that's not all visible to a
  39    single process, which is all we're concerned with here.  */
  40 #ifdef TARGET_ABI32
  41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  42 #else
  43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  44 #endif
  45
  46 #define TARGET_PAGE_BITS_16M 24
  47
  48 #else /* defined (TARGET_PPC64) */
  49 /* PowerPC 32 definitions */
  50 #define TARGET_LONG_BITS 32
  51
  52 #if defined(TARGET_PPCEMB)
  53 /* Specific definitions for PowerPC embedded */
  54 /* BookE have 36 bits physical address space */
  55 #if defined(CONFIG_USER_ONLY)
  56 /* It looks like a lot of Linux programs assume page size
  57  * is 4kB long. This is evil, but we have to deal with it...
  58  */
  59 #define TARGET_PAGE_BITS 12
  60 #else /* defined(CONFIG_USER_ONLY) */
  61 /* Pages can be 1 kB small */
  62 #define TARGET_PAGE_BITS 10
  63 #endif /* defined(CONFIG_USER_ONLY) */
  64 #else /* defined(TARGET_PPCEMB) */
  65 /* "standard" PowerPC 32 definitions */
  66 #define TARGET_PAGE_BITS 12
  67 #endif /* defined(TARGET_PPCEMB) */
  68
  69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  71
  72 #endif /* defined (TARGET_PPC64) */
  73
  74 #define CPUArchState struct CPUPPCState
  75
  76 #include "exec/cpu-defs.h"
  77
  78 #include "fpu/softfloat.h"
  79
  80 #define TARGET_HAS_ICE 1
  81
  82 #if defined (TARGET_PPC64)
  83 #define ELF_MACHINE     EM_PPC64
  84 #else
  85 #define ELF_MACHINE     EM_PPC
  86 #endif
  87
  88 /*****************************************************************************/
  89 /* MMU model                                                                 */
  90 typedef enum powerpc_mmu_t powerpc_mmu_t;
  91 enum powerpc_mmu_t {
  92     POWERPC_MMU_UNKNOWN    = 0x00000000,
  93     /* Standard 32 bits PowerPC MMU                            */
  94     POWERPC_MMU_32B        = 0x00000001,
  95     /* PowerPC 6xx MMU with software TLB                       */
  96     POWERPC_MMU_SOFT_6xx   = 0x00000002,
  97     /* PowerPC 74xx MMU with software TLB                      */
  98     POWERPC_MMU_SOFT_74xx  = 0x00000003,
  99     /* PowerPC 4xx MMU with software TLB                       */
 100     POWERPC_MMU_SOFT_4xx   = 0x00000004,
 101     /* PowerPC 4xx MMU with software TLB and zones protections */
 102     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
 103     /* PowerPC MMU in real mode only                           */
 104     POWERPC_MMU_REAL       = 0x00000006,
 105     /* Freescale MPC8xx MMU model                              */
 106     POWERPC_MMU_MPC8xx     = 0x00000007,
 107     /* BookE MMU model                                         */
 108     POWERPC_MMU_BOOKE      = 0x00000008,
 109     /* BookE 2.06 MMU model                                    */
 110     POWERPC_MMU_BOOKE206   = 0x00000009,
 111     /* PowerPC 601 MMU model (specific BATs format)            */
 112     POWERPC_MMU_601        = 0x0000000A,
 113 #if defined(TARGET_PPC64)
 114 #define POWERPC_MMU_64       0x00010000
 115 #define POWERPC_MMU_1TSEG    0x00020000
 116 #define POWERPC_MMU_AMR      0x00040000
 117     /* 64 bits PowerPC MMU                                     */
 118     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
 119     /* Architecture 2.06 variant                               */
 120     POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
 121                              | POWERPC_MMU_AMR | 0x00000003,
 122     /* Architecture 2.06 "degraded" (no 1T segments)           */
 123     POWERPC_MMU_2_06a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
 124                              | 0x00000003,
 125     /* Architecture 2.06 "degraded" (no 1T segments or AMR)    */
 126     POWERPC_MMU_2_06d      = POWERPC_MMU_64 | 0x00000003,
 127 #endif /* defined(TARGET_PPC64) */
 128 };
 129
 130 /*****************************************************************************/
 131 /* Exception model                                                           */
 132 typedef enum powerpc_excp_t powerpc_excp_t;
 133 enum powerpc_excp_t {
 134     POWERPC_EXCP_UNKNOWN   = 0,
 135     /* Standard PowerPC exception model */
 136     POWERPC_EXCP_STD,
 137     /* PowerPC 40x exception model      */
 138     POWERPC_EXCP_40x,
 139     /* PowerPC 601 exception model      */
 140     POWERPC_EXCP_601,
 141     /* PowerPC 602 exception model      */
 142     POWERPC_EXCP_602,
 143     /* PowerPC 603 exception model      */
 144     POWERPC_EXCP_603,
 145     /* PowerPC 603e exception model     */
 146     POWERPC_EXCP_603E,
 147     /* PowerPC G2 exception model       */
 148     POWERPC_EXCP_G2,
 149     /* PowerPC 604 exception model      */
 150     POWERPC_EXCP_604,
 151     /* PowerPC 7x0 exception model      */
 152     POWERPC_EXCP_7x0,
 153     /* PowerPC 7x5 exception model      */
 154     POWERPC_EXCP_7x5,
 155     /* PowerPC 74xx exception model     */
 156     POWERPC_EXCP_74xx,
 157     /* BookE exception model            */
 158     POWERPC_EXCP_BOOKE,
 159 #if defined(TARGET_PPC64)
 160     /* PowerPC 970 exception model      */
 161     POWERPC_EXCP_970,
 162     /* POWER7 exception model           */
 163     POWERPC_EXCP_POWER7,
 164 #endif /* defined(TARGET_PPC64) */
 165 };
 166
 167 /*****************************************************************************/
 168 /* Exception vectors definitions                                             */
 169 enum {
 170     POWERPC_EXCP_NONE    = -1,
 171     /* The 64 first entries are used by the PowerPC embedded specification   */
 172     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 173     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 174     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 175     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 176     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 177     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 178     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 179     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 180     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 181     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 182     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 183     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 184     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 185     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 186     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 187     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 188     /* Vectors 16 to 31 are reserved                                         */
 189     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 190     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 191     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 192     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 193     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 194     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 195     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 196     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 197     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 198     /* Vectors 42 to 63 are reserved                                         */
 199     /* Exceptions defined in the PowerPC server specification                */
 200     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 201     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 202     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 203     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 204     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 205     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 206     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 207     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 208     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 209     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 210     /* 40x specific exceptions                                               */
 211     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 212     /* 601 specific exceptions                                               */
 213     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 214     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 215     /* 602 specific exceptions                                               */
 216     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 217     /* 602/603 specific exceptions                                           */
 218     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 219     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 220     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 221     /* Exceptions available on most PowerPC                                  */
 222     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 223     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 224     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 225     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 226     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 227     /* 7xx/74xx specific exceptions                                          */
 228     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 229     /* 74xx specific exceptions                                              */
 230     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 231     /* 970FX specific exceptions                                             */
 232     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 233     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 234     /* Freescale embedded cores specific exceptions                          */
 235     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 236     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 237     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 238     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 239     /* VSX Unavailable (Power ISA 2.06 and later)                            */
 240     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 241     /* EOL                                                                   */
 242     POWERPC_EXCP_NB       = 96,
 243     /* QEMU exceptions: used internally during code translation              */
 244     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 245     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 246     /* QEMU exceptions: special cases we want to stop translation            */
 247     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 248     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 249     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
 250 };
 251
 252 /* Exceptions error codes                                                    */
 253 enum {
 254     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 255     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 256     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 257     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 258     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 259     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 260     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 261     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 262     /* FP exceptions                                                         */
 263     POWERPC_EXCP_FP            = 0x10,
 264     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 265     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 266     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 267     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 268     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 269     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 270     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 271     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 272     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 273     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 274     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 275     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 276     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 277     /* Invalid instruction                                                   */
 278     POWERPC_EXCP_INVAL         = 0x20,
 279     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 280     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 281     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 282     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 283     /* Privileged instruction                                                */
 284     POWERPC_EXCP_PRIV          = 0x30,
 285     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 286     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 287     /* Trap                                                                  */
 288     POWERPC_EXCP_TRAP          = 0x40,
 289 };
 290
 291 /*****************************************************************************/
 292 /* Input pins model                                                          */
 293 typedef enum powerpc_input_t powerpc_input_t;
 294 enum powerpc_input_t {
 295     PPC_FLAGS_INPUT_UNKNOWN = 0,
 296     /* PowerPC 6xx bus                  */
 297     PPC_FLAGS_INPUT_6xx,
 298     /* BookE bus                        */
 299     PPC_FLAGS_INPUT_BookE,
 300     /* PowerPC 405 bus                  */
 301     PPC_FLAGS_INPUT_405,
 302     /* PowerPC 970 bus                  */
 303     PPC_FLAGS_INPUT_970,
 304     /* PowerPC POWER7 bus               */
 305     PPC_FLAGS_INPUT_POWER7,
 306     /* PowerPC 401 bus                  */
 307     PPC_FLAGS_INPUT_401,
 308     /* Freescale RCPU bus               */
 309     PPC_FLAGS_INPUT_RCPU,
 310 };
 311
 312 #define PPC_INPUT(env) (env->bus_model)
 313
 314 /*****************************************************************************/
 315 typedef struct opc_handler_t opc_handler_t;
 316
 317 /*****************************************************************************/
 318 /* Types used to describe some PowerPC registers */
 319 typedef struct CPUPPCState CPUPPCState;
 320 typedef struct ppc_tb_t ppc_tb_t;
 321 typedef struct ppc_spr_t ppc_spr_t;
 322 typedef struct ppc_dcr_t ppc_dcr_t;
 323 typedef union ppc_avr_t ppc_avr_t;
 324 typedef union ppc_tlb_t ppc_tlb_t;
 325
 326 /* SPR access micro-ops generations callbacks */
 327 struct ppc_spr_t {
 328     void (*uea_read)(void *opaque, int gpr_num, int spr_num);
 329     void (*uea_write)(void *opaque, int spr_num, int gpr_num);
 330 #if !defined(CONFIG_USER_ONLY)
 331     void (*oea_read)(void *opaque, int gpr_num, int spr_num);
 332     void (*oea_write)(void *opaque, int spr_num, int gpr_num);
 333     void (*hea_read)(void *opaque, int gpr_num, int spr_num);
 334     void (*hea_write)(void *opaque, int spr_num, int gpr_num);
 335 #endif
 336     const char *name;
 337 #ifdef CONFIG_KVM
 338     /* We (ab)use the fact that all the SPRs will have ids for the
 339      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 340      * don't sync this */
 341     uint64_t one_reg_id;
 342 #endif
 343 };
 344
 345 /* Altivec registers (128 bits) */
 346 union ppc_avr_t {
 347     float32 f[4];
 348     uint8_t u8[16];
 349     uint16_t u16[8];
 350     uint32_t u32[4];
 351     int8_t s8[16];
 352     int16_t s16[8];
 353     int32_t s32[4];
 354     uint64_t u64[2];
 355     int64_t s64[2];
 356 #ifdef CONFIG_INT128
 357     __uint128_t u128;
 358 #endif
 359 };
 360
 361 #if !defined(CONFIG_USER_ONLY)
 362 /* Software TLB cache */
 363 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 364 struct ppc6xx_tlb_t {
 365     target_ulong pte0;
 366     target_ulong pte1;
 367     target_ulong EPN;
 368 };
 369
 370 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 371 struct ppcemb_tlb_t {
 372     uint64_t RPN;
 373     target_ulong EPN;
 374     target_ulong PID;
 375     target_ulong size;
 376     uint32_t prot;
 377     uint32_t attr; /* Storage attributes */
 378 };
 379
 380 typedef struct ppcmas_tlb_t {
 381      uint32_t mas8;
 382      uint32_t mas1;
 383      uint64_t mas2;
 384      uint64_t mas7_3;
 385 } ppcmas_tlb_t;
 386
 387 union ppc_tlb_t {
 388     ppc6xx_tlb_t *tlb6;
 389     ppcemb_tlb_t *tlbe;
 390     ppcmas_tlb_t *tlbm;
 391 };
 392
 393 /* possible TLB variants */
 394 #define TLB_NONE               0
 395 #define TLB_6XX                1
 396 #define TLB_EMB                2
 397 #define TLB_MAS                3
 398 #endif
 399
 400 #define SDR_32_HTABORG         0xFFFF0000UL
 401 #define SDR_32_HTABMASK        0x000001FFUL
 402
 403 #if defined(TARGET_PPC64)
 404 #define SDR_64_HTABORG         0xFFFFFFFFFFFC0000ULL
 405 #define SDR_64_HTABSIZE        0x000000000000001FULL
 406 #endif /* defined(TARGET_PPC64 */
 407
 408 typedef struct ppc_slb_t ppc_slb_t;
 409 struct ppc_slb_t {
 410     uint64_t esid;
 411     uint64_t vsid;
 412 };
 413
 414 #define MAX_SLB_ENTRIES         64
 415 #define SEGMENT_SHIFT_256M      28
 416 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 417
 418 #define SEGMENT_SHIFT_1T        40
 419 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 420
 421
 422 /*****************************************************************************/
 423 /* Machine state register bits definition                                    */
 424 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 425 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 426 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 427 #define MSR_SHV  60 /* hypervisor state                               hflags */
 428 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 429 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 430 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 431 #define MSR_GS   28 /* guest state for BookE                                 */
 432 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 433 #define MSR_VR   25 /* altivec available                            x hflags */
 434 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 435 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 436 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 437 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 438 #define MSR_KEY  19 /* key bit on 603e                                       */
 439 #define MSR_POW  18 /* Power management                                      */
 440 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 441 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 442 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 443 #define MSR_EE   15 /* External interrupt enable                             */
 444 #define MSR_PR   14 /* Problem state                                  hflags */
 445 #define MSR_FP   13 /* Floating point available                       hflags */
 446 #define MSR_ME   12 /* Machine check interrupt enable                        */
 447 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 448 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 449 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 450 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 451 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 452 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 453 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 454 #define MSR_AL   7  /* AL bit on POWER                                       */
 455 #define MSR_EP   6  /* Exception prefix on 601                               */
 456 #define MSR_IR   5  /* Instruction relocate                                  */
 457 #define MSR_DR   4  /* Data relocate                                         */
 458 #define MSR_PE   3  /* Protection enable on 403                              */
 459 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 460 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 461 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 462 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 463
 464 #define LPCR_ILE (1 << (63-38))
 465
 466 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 467 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 468 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 469 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 470 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 471 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 472 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 473 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 474 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 475 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 476 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 477 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 478 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 479 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 480 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 481 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 482 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 483 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 484 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 485 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 486 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 487 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 488 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 489 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 490 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 491 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 492 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 493 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 494 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 495 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 496 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 497 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 498 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 499 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 500 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 501 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 502 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 503 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 504 /* Hypervisor bit is more specific */
 505 #if defined(TARGET_PPC64)
 506 #define MSR_HVB (1ULL << MSR_SHV)
 507 #define msr_hv  msr_shv
 508 #else
 509 #if defined(PPC_EMULATE_32BITS_HYPV)
 510 #define MSR_HVB (1ULL << MSR_THV)
 511 #define msr_hv  msr_thv
 512 #else
 513 #define MSR_HVB (0ULL)
 514 #define msr_hv  (0)
 515 #endif
 516 #endif
 517
 518 /* Exception state register bits definition                                  */
 519 #define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */
 520 #define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */
 521 #define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */
 522 #define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */
 523 #define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */
 524 #define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */
 525 #define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */
 526 #define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */
 527 #define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */
 528 #define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */
 529 #define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */
 530 #define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */
 531 #define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */
 532 #define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */
 533 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
 534 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
 535
 536 enum {
 537     POWERPC_FLAG_NONE     = 0x00000000,
 538     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 539     POWERPC_FLAG_SPE      = 0x00000001,
 540     POWERPC_FLAG_VRE      = 0x00000002,
 541     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 542     POWERPC_FLAG_TGPR     = 0x00000004,
 543     POWERPC_FLAG_CE       = 0x00000008,
 544     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 545     POWERPC_FLAG_SE       = 0x00000010,
 546     POWERPC_FLAG_DWE      = 0x00000020,
 547     POWERPC_FLAG_UBLE     = 0x00000040,
 548     /* Flag for MSR bit 9 signification (BE/DE)                              */
 549     POWERPC_FLAG_BE       = 0x00000080,
 550     POWERPC_FLAG_DE       = 0x00000100,
 551     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 552     POWERPC_FLAG_PX       = 0x00000200,
 553     POWERPC_FLAG_PMM      = 0x00000400,
 554     /* Flag for special features                                             */
 555     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 556     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 557     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 558     /* Has CFAR                                                              */
 559     POWERPC_FLAG_CFAR     = 0x00040000,
 560     /* Has VSX                                                               */
 561     POWERPC_FLAG_VSX      = 0x00080000,
 562 };
 563
 564 /*****************************************************************************/
 565 /* Floating point status and control register                                */
 566 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 567 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 568 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 569 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 570 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 571 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 572 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 573 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 574 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 575 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 576 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 577 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 578 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 579 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 580 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 581 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 582 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 583 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 584 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 585 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 586 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 587 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 588 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 589 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 590 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 591 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 592 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 593 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 594 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 595 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 596 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 597 #define FPSCR_RN1    1
 598 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 599 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 600 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 601 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 602 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 603 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 604 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 605 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 606 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 607 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 608 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 609 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 610 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 611 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 612 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 613 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 614 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 615 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 616 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 617 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 618 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 619 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 620 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 621 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 622 /* Invalid operation exception summary */
 623 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 624                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 625                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 626                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 627                                   (1 << FPSCR_VXCVI)))
 628 /* exception summary */
 629 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 630 /* enabled exception summary */
 631 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 632                    0x1F)
 633
 634 /*****************************************************************************/
 635 /* Vector status and control register */
 636 #define VSCR_NJ         16 /* Vector non-java */
 637 #define VSCR_SAT        0 /* Vector saturation */
 638 #define vscr_nj         (((env->vscr) >> VSCR_NJ)       & 0x1)
 639 #define vscr_sat        (((env->vscr) >> VSCR_SAT)      & 0x1)
 640
 641 /*****************************************************************************/
 642 /* BookE e500 MMU registers */
 643
 644 #define MAS0_NV_SHIFT      0
 645 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 646
 647 #define MAS0_WQ_SHIFT      12
 648 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 649 /* Write TLB entry regardless of reservation */
 650 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 651 /* Write TLB entry only already in use */
 652 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 653 /* Clear TLB entry */
 654 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 655
 656 #define MAS0_HES_SHIFT     14
 657 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 658
 659 #define MAS0_ESEL_SHIFT    16
 660 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 661
 662 #define MAS0_TLBSEL_SHIFT  28
 663 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 664 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 665 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 666 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 667 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 668
 669 #define MAS0_ATSEL_SHIFT   31
 670 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 671 #define MAS0_ATSEL_TLB     0
 672 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 673
 674 #define MAS1_TSIZE_SHIFT   7
 675 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 676
 677 #define MAS1_TS_SHIFT      12
 678 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 679
 680 #define MAS1_IND_SHIFT     13
 681 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 682
 683 #define MAS1_TID_SHIFT     16
 684 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 685
 686 #define MAS1_IPROT_SHIFT   30
 687 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 688
 689 #define MAS1_VALID_SHIFT   31
 690 #define MAS1_VALID         0x80000000
 691
 692 #define MAS2_EPN_SHIFT     12
 693 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 694
 695 #define MAS2_ACM_SHIFT     6
 696 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 697
 698 #define MAS2_VLE_SHIFT     5
 699 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 700
 701 #define MAS2_W_SHIFT       4
 702 #define MAS2_W             (1 << MAS2_W_SHIFT)
 703
 704 #define MAS2_I_SHIFT       3
 705 #define MAS2_I             (1 << MAS2_I_SHIFT)
 706
 707 #define MAS2_M_SHIFT       2
 708 #define MAS2_M             (1 << MAS2_M_SHIFT)
 709
 710 #define MAS2_G_SHIFT       1
 711 #define MAS2_G             (1 << MAS2_G_SHIFT)
 712
 713 #define MAS2_E_SHIFT       0
 714 #define MAS2_E             (1 << MAS2_E_SHIFT)
 715
 716 #define MAS3_RPN_SHIFT     12
 717 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 718
 719 #define MAS3_U0                 0x00000200
 720 #define MAS3_U1                 0x00000100
 721 #define MAS3_U2                 0x00000080
 722 #define MAS3_U3                 0x00000040
 723 #define MAS3_UX                 0x00000020
 724 #define MAS3_SX                 0x00000010
 725 #define MAS3_UW                 0x00000008
 726 #define MAS3_SW                 0x00000004
 727 #define MAS3_UR                 0x00000002
 728 #define MAS3_SR                 0x00000001
 729 #define MAS3_SPSIZE_SHIFT       1
 730 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 731
 732 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 733 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 734 #define MAS4_TIDSELD_MASK       0x00030000
 735 #define MAS4_TIDSELD_PID0       0x00000000
 736 #define MAS4_TIDSELD_PID1       0x00010000
 737 #define MAS4_TIDSELD_PID2       0x00020000
 738 #define MAS4_TIDSELD_PIDZ       0x00030000
 739 #define MAS4_INDD               0x00008000      /* Default IND */
 740 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 741 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 742 #define MAS4_ACMD               0x00000040
 743 #define MAS4_VLED               0x00000020
 744 #define MAS4_WD                 0x00000010
 745 #define MAS4_ID                 0x00000008
 746 #define MAS4_MD                 0x00000004
 747 #define MAS4_GD                 0x00000002
 748 #define MAS4_ED                 0x00000001
 749 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 750 #define MAS4_WIMGED_SHIFT       0
 751
 752 #define MAS5_SGS                0x80000000
 753 #define MAS5_SLPID_MASK         0x00000fff
 754
 755 #define MAS6_SPID0              0x3fff0000
 756 #define MAS6_SPID1              0x00007ffe
 757 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 758 #define MAS6_SAS                0x00000001
 759 #define MAS6_SPID               MAS6_SPID0
 760 #define MAS6_SIND               0x00000002      /* Indirect page */
 761 #define MAS6_SIND_SHIFT         1
 762 #define MAS6_SPID_MASK          0x3fff0000
 763 #define MAS6_SPID_SHIFT         16
 764 #define MAS6_ISIZE_MASK         0x00000f80
 765 #define MAS6_ISIZE_SHIFT        7
 766
 767 #define MAS7_RPN                0xffffffff
 768
 769 #define MAS8_TGS                0x80000000
 770 #define MAS8_VF                 0x40000000
 771 #define MAS8_TLBPID             0x00000fff
 772
 773 /* Bit definitions for MMUCFG */
 774 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 775 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 776 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 777 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 778 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 779 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 780 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 781 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 782 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 783
 784 /* Bit definitions for MMUCSR0 */
 785 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 786 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 787 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 788 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 789 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 790                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 791 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 792 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 793 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 794 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 795
 796 /* TLBnCFG encoding */
 797 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 798 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 799 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 800 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 801 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 802 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 803 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 804 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 805 #define TLBnCFG_MINSIZE_SHIFT   20
 806 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 807 #define TLBnCFG_MAXSIZE_SHIFT   16
 808 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 809 #define TLBnCFG_ASSOC_SHIFT     24
 810
 811 /* TLBnPS encoding */
 812 #define TLBnPS_4K               0x00000004
 813 #define TLBnPS_8K               0x00000008
 814 #define TLBnPS_16K              0x00000010
 815 #define TLBnPS_32K              0x00000020
 816 #define TLBnPS_64K              0x00000040
 817 #define TLBnPS_128K             0x00000080
 818 #define TLBnPS_256K             0x00000100
 819 #define TLBnPS_512K             0x00000200
 820 #define TLBnPS_1M               0x00000400
 821 #define TLBnPS_2M               0x00000800
 822 #define TLBnPS_4M               0x00001000
 823 #define TLBnPS_8M               0x00002000
 824 #define TLBnPS_16M              0x00004000
 825 #define TLBnPS_32M              0x00008000
 826 #define TLBnPS_64M              0x00010000
 827 #define TLBnPS_128M             0x00020000
 828 #define TLBnPS_256M             0x00040000
 829 #define TLBnPS_512M             0x00080000
 830 #define TLBnPS_1G               0x00100000
 831 #define TLBnPS_2G               0x00200000
 832 #define TLBnPS_4G               0x00400000
 833 #define TLBnPS_8G               0x00800000
 834 #define TLBnPS_16G              0x01000000
 835 #define TLBnPS_32G              0x02000000
 836 #define TLBnPS_64G              0x04000000
 837 #define TLBnPS_128G             0x08000000
 838 #define TLBnPS_256G             0x10000000
 839
 840 /* tlbilx action encoding */
 841 #define TLBILX_T_ALL                    0
 842 #define TLBILX_T_TID                    1
 843 #define TLBILX_T_FULLMATCH              3
 844 #define TLBILX_T_CLASS0                 4
 845 #define TLBILX_T_CLASS1                 5
 846 #define TLBILX_T_CLASS2                 6
 847 #define TLBILX_T_CLASS3                 7
 848
 849 /* BookE 2.06 helper defines */
 850
 851 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 852 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 853 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 854 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 855
 856 /* number of possible TLBs */
 857 #define BOOKE206_MAX_TLBN      4
 858
 859 /*****************************************************************************/
 860 /* Embedded.Processor Control */
 861
 862 #define DBELL_TYPE_SHIFT               27
 863 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 864 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 865 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 866 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 867 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 868 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 869
 870 #define DBELL_BRDCAST                  (1 << 26)
 871 #define DBELL_LPIDTAG_SHIFT            14
 872 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 873 #define DBELL_PIRTAG_MASK              0x3fff
 874
 875 /*****************************************************************************/
 876 /* Segment page size information, used by recent hash MMUs
 877  * The format of this structure mirrors kvm_ppc_smmu_info
 878  */
 879
 880 #define PPC_PAGE_SIZES_MAX_SZ   8
 881
 882 struct ppc_one_page_size {
 883     uint32_t page_shift;  /* Page shift (or 0) */
 884     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
 885 };
 886
 887 struct ppc_one_seg_page_size {
 888     uint32_t page_shift;  /* Base page shift of segment (or 0) */
 889     uint32_t slb_enc;     /* SLB encoding for BookS */
 890     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
 891 };
 892
 893 struct ppc_segment_page_sizes {
 894     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
 895 };
 896
 897
 898 /*****************************************************************************/
 899 /* The whole PowerPC CPU context */
 900 #define NB_MMU_MODES 3
 901
 902 #define PPC_CPU_OPCODES_LEN 0x40
 903
 904 struct CPUPPCState {
 905     /* First are the most commonly used resources
 906      * during translated code execution
 907      */
 908     /* general purpose registers */
 909     target_ulong gpr[32];
 910 #if !defined(TARGET_PPC64)
 911     /* Storage for GPR MSB, used by the SPE extension */
 912     target_ulong gprh[32];
 913 #endif
 914     /* LR */
 915     target_ulong lr;
 916     /* CTR */
 917     target_ulong ctr;
 918     /* condition register */
 919     uint32_t crf[8];
 920 #if defined(TARGET_PPC64)
 921     /* CFAR */
 922     target_ulong cfar;
 923 #endif
 924     /* XER (with SO, OV, CA split out) */
 925     target_ulong xer;
 926     target_ulong so;
 927     target_ulong ov;
 928     target_ulong ca;
 929     /* Reservation address */
 930     target_ulong reserve_addr;
 931     /* Reservation value */
 932     target_ulong reserve_val;
 933     target_ulong reserve_val2;
 934     /* Reservation store address */
 935     target_ulong reserve_ea;
 936     /* Reserved store source register and size */
 937     target_ulong reserve_info;
 938
 939     /* Those ones are used in supervisor mode only */
 940     /* machine state register */
 941     target_ulong msr;
 942     /* temporary general purpose registers */
 943     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
 944
 945     /* Floating point execution context */
 946     float_status fp_status;
 947     /* floating point registers */
 948     float64 fpr[32];
 949     /* floating point status and control register */
 950     target_ulong fpscr;
 951
 952     /* Next instruction pointer */
 953     target_ulong nip;
 954
 955     int access_type; /* when a memory exception occurs, the access
 956                         type is stored here */
 957
 958     CPU_COMMON
 959
 960     /* MMU context - only relevant for full system emulation */
 961 #if !defined(CONFIG_USER_ONLY)
 962 #if defined(TARGET_PPC64)
 963     /* PowerPC 64 SLB area */
 964     ppc_slb_t slb[MAX_SLB_ENTRIES];
 965     int32_t slb_nr;
 966 #endif
 967     /* segment registers */
 968     hwaddr htab_base;
 969     /* mask used to normalize hash value to PTEG index */
 970     hwaddr htab_mask;
 971     target_ulong sr[32];
 972     /* externally stored hash table */
 973     uint8_t *external_htab;
 974     /* BATs */
 975     uint32_t nb_BATs;
 976     target_ulong DBAT[2][8];
 977     target_ulong IBAT[2][8];
 978     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
 979     int32_t nb_tlb;      /* Total number of TLB                              */
 980     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 981     int nb_ways;     /* Number of ways in the TLB set                        */
 982     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
 983     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
 984     int nb_pids;     /* Number of available PID registers                    */
 985     int tlb_type;    /* Type of TLB we're dealing with                       */
 986     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
 987     /* 403 dedicated access protection registers */
 988     target_ulong pb[4];
 989     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
 990     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
 991 #endif
 992
 993     /* Other registers */
 994     /* Special purpose registers */
 995     target_ulong spr[1024];
 996     ppc_spr_t spr_cb[1024];
 997     /* Altivec registers */
 998     ppc_avr_t avr[32];
 999     uint32_t vscr;
1000     /* VSX registers */
1001     uint64_t vsr[32];
1002     /* SPE registers */
1003     uint64_t spe_acc;
1004     uint32_t spe_fscr;
1005     /* SPE and Altivec can share a status since they will never be used
1006      * simultaneously */
1007     float_status vec_status;
1008
1009     /* Internal devices resources */
1010     /* Time base and decrementer */
1011     ppc_tb_t *tb_env;
1012     /* Device control registers */
1013     ppc_dcr_t *dcr_env;
1014
1015     int dcache_line_size;
1016     int icache_line_size;
1017
1018     /* Those resources are used during exception processing */
1019     /* CPU model definition */
1020     target_ulong msr_mask;
1021     powerpc_mmu_t mmu_model;
1022     powerpc_excp_t excp_model;
1023     powerpc_input_t bus_model;
1024     int bfd_mach;
1025     uint32_t flags;
1026     uint64_t insns_flags;
1027     uint64_t insns_flags2;
1028 #if defined(TARGET_PPC64)
1029     struct ppc_segment_page_sizes sps;
1030 #endif
1031
1032 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1033     uint64_t vpa_addr;
1034     uint64_t slb_shadow_addr, slb_shadow_size;
1035     uint64_t dtl_addr, dtl_size;
1036 #endif /* TARGET_PPC64 */
1037
1038     int error_code;
1039     uint32_t pending_interrupts;
1040 #if !defined(CONFIG_USER_ONLY)
1041     /* This is the IRQ controller, which is implementation dependent
1042      * and only relevant when emulating a complete machine.
1043      */
1044     uint32_t irq_input_state;
1045     void **irq_inputs;
1046     /* Exception vectors */
1047     target_ulong excp_vectors[POWERPC_EXCP_NB];
1048     target_ulong excp_prefix;
1049     target_ulong ivor_mask;
1050     target_ulong ivpr_mask;
1051     target_ulong hreset_vector;
1052     hwaddr mpic_iack;
1053     /* true when the external proxy facility mode is enabled */
1054     bool mpic_proxy;
1055 #endif
1056
1057     /* Those resources are used only during code translation */
1058     /* opcode handlers */
1059     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1060
1061     /* Those resources are used only in QEMU core */
1062     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1063     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1064     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
1065
1066     /* Power management */
1067     int (*check_pow)(CPUPPCState *env);
1068
1069 #if !defined(CONFIG_USER_ONLY)
1070     void *load_info;    /* Holds boot loading state.  */
1071 #endif
1072
1073     /* booke timers */
1074
1075     /* Specifies bit locations of the Time Base used to signal a fixed timer
1076      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1077      *
1078      * 0 selects the least significant bit.
1079      * 63 selects the most significant bit.
1080      */
1081     uint8_t fit_period[4];
1082     uint8_t wdt_period[4];
1083 };
1084
1085 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1086 do {                                            \
1087     env->fit_period[0] = (a_);                  \
1088     env->fit_period[1] = (b_);                  \
1089     env->fit_period[2] = (c_);                  \
1090     env->fit_period[3] = (d_);                  \
1091  } while (0)
1092
1093 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1094 do {                                            \
1095     env->wdt_period[0] = (a_);                  \
1096     env->wdt_period[1] = (b_);                  \
1097     env->wdt_period[2] = (c_);                  \
1098     env->wdt_period[3] = (d_);                  \
1099  } while (0)
1100
1101 #include "cpu-qom.h"
1102
1103 /*****************************************************************************/
1104 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1105 void ppc_translate_init(void);
1106 int cpu_ppc_exec (CPUPPCState *s);
1107 /* you can call this signal handler from your SIGBUS and SIGSEGV
1108    signal handlers to inform the virtual CPU of exceptions. non zero
1109    is returned if the signal was handled by the virtual CPU.  */
1110 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1111                             void *puc);
1112 void ppc_hw_interrupt (CPUPPCState *env);
1113 #if defined(CONFIG_USER_ONLY)
1114 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1115                              int mmu_idx);
1116 #endif
1117
1118 #if !defined(CONFIG_USER_ONLY)
1119 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1120 #endif /* !defined(CONFIG_USER_ONLY) */
1121 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1122
1123 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1124
1125 /* Time-base and decrementer management */
1126 #ifndef NO_CPU_IO_DEFS
1127 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1128 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1129 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1130 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1131 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1132 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1133 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1134 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1135 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1136 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1137 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1138 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1139 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1140 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1141 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1142 #if !defined(CONFIG_USER_ONLY)
1143 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1144 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1145 target_ulong load_40x_pit (CPUPPCState *env);
1146 void store_40x_pit (CPUPPCState *env, target_ulong val);
1147 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1148 void store_40x_sler (CPUPPCState *env, uint32_t val);
1149 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1150 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1151 void ppc_tlb_invalidate_all (CPUPPCState *env);
1152 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1153 #endif
1154 #endif
1155
1156 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1157
1158 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1159 {
1160     uint64_t gprv;
1161
1162     gprv = env->gpr[gprn];
1163 #if !defined(TARGET_PPC64)
1164     if (env->flags & POWERPC_FLAG_SPE) {
1165         /* If the CPU implements the SPE extension, we have to get the
1166          * high bits of the GPR from the gprh storage area
1167          */
1168         gprv &= 0xFFFFFFFFULL;
1169         gprv |= (uint64_t)env->gprh[gprn] << 32;
1170     }
1171 #endif
1172
1173     return gprv;
1174 }
1175
1176 /* Device control registers */
1177 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1178 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1179
1180 static inline CPUPPCState *cpu_init(const char *cpu_model)
1181 {
1182     PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1183     if (cpu == NULL) {
1184         return NULL;
1185     }
1186     return &cpu->env;
1187 }
1188
1189 #define cpu_exec cpu_ppc_exec
1190 #define cpu_gen_code cpu_ppc_gen_code
1191 #define cpu_signal_handler cpu_ppc_signal_handler
1192 #define cpu_list ppc_cpu_list
1193
1194 /* MMU modes definitions */
1195 #define MMU_MODE0_SUFFIX _user
1196 #define MMU_MODE1_SUFFIX _kernel
1197 #define MMU_MODE2_SUFFIX _hypv
1198 #define MMU_USER_IDX 0
1199 static inline int cpu_mmu_index (CPUPPCState *env)
1200 {
1201     return env->mmu_idx;
1202 }
1203
1204 #include "exec/cpu-all.h"
1205
1206 /*****************************************************************************/
1207 /* CRF definitions */
1208 #define CRF_LT        3
1209 #define CRF_GT        2
1210 #define CRF_EQ        1
1211 #define CRF_SO        0
1212 #define CRF_CH        (1 << CRF_LT)
1213 #define CRF_CL        (1 << CRF_GT)
1214 #define CRF_CH_OR_CL  (1 << CRF_EQ)
1215 #define CRF_CH_AND_CL (1 << CRF_SO)
1216
1217 /* XER definitions */
1218 #define XER_SO  31
1219 #define XER_OV  30
1220 #define XER_CA  29
1221 #define XER_CMP  8
1222 #define XER_BC   0
1223 #define xer_so  (env->so)
1224 #define xer_ov  (env->ov)
1225 #define xer_ca  (env->ca)
1226 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1227 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1228
1229 /* SPR definitions */
1230 #define SPR_MQ                (0x000)
1231 #define SPR_XER               (0x001)
1232 #define SPR_601_VRTCU         (0x004)
1233 #define SPR_601_VRTCL         (0x005)
1234 #define SPR_601_UDECR         (0x006)
1235 #define SPR_LR                (0x008)
1236 #define SPR_CTR               (0x009)
1237 #define SPR_UAMR              (0x00C)
1238 #define SPR_DSCR              (0x011)
1239 #define SPR_DSISR             (0x012)
1240 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1241 #define SPR_601_RTCU          (0x014)
1242 #define SPR_601_RTCL          (0x015)
1243 #define SPR_DECR              (0x016)
1244 #define SPR_SDR1              (0x019)
1245 #define SPR_SRR0              (0x01A)
1246 #define SPR_SRR1              (0x01B)
1247 #define SPR_CFAR              (0x01C)
1248 #define SPR_AMR               (0x01D)
1249 #define SPR_BOOKE_PID         (0x030)
1250 #define SPR_BOOKE_DECAR       (0x036)
1251 #define SPR_BOOKE_CSRR0       (0x03A)
1252 #define SPR_BOOKE_CSRR1       (0x03B)
1253 #define SPR_BOOKE_DEAR        (0x03D)
1254 #define SPR_BOOKE_ESR         (0x03E)
1255 #define SPR_BOOKE_IVPR        (0x03F)
1256 #define SPR_MPC_EIE           (0x050)
1257 #define SPR_MPC_EID           (0x051)
1258 #define SPR_MPC_NRI           (0x052)
1259 #define SPR_UCTRL             (0x088)
1260 #define SPR_MPC_CMPA          (0x090)
1261 #define SPR_MPC_CMPB          (0x091)
1262 #define SPR_MPC_CMPC          (0x092)
1263 #define SPR_MPC_CMPD          (0x093)
1264 #define SPR_MPC_ECR           (0x094)
1265 #define SPR_MPC_DER           (0x095)
1266 #define SPR_MPC_COUNTA        (0x096)
1267 #define SPR_MPC_COUNTB        (0x097)
1268 #define SPR_CTRL              (0x098)
1269 #define SPR_MPC_CMPE          (0x098)
1270 #define SPR_MPC_CMPF          (0x099)
1271 #define SPR_MPC_CMPG          (0x09A)
1272 #define SPR_MPC_CMPH          (0x09B)
1273 #define SPR_MPC_LCTRL1        (0x09C)
1274 #define SPR_MPC_LCTRL2        (0x09D)
1275 #define SPR_UAMOR             (0x09D)
1276 #define SPR_MPC_ICTRL         (0x09E)
1277 #define SPR_MPC_BAR           (0x09F)
1278 #define SPR_VRSAVE            (0x100)
1279 #define SPR_USPRG0            (0x100)
1280 #define SPR_USPRG1            (0x101)
1281 #define SPR_USPRG2            (0x102)
1282 #define SPR_USPRG3            (0x103)
1283 #define SPR_USPRG4            (0x104)
1284 #define SPR_USPRG5            (0x105)
1285 #define SPR_USPRG6            (0x106)
1286 #define SPR_USPRG7            (0x107)
1287 #define SPR_VTBL              (0x10C)
1288 #define SPR_VTBU              (0x10D)
1289 #define SPR_SPRG0             (0x110)
1290 #define SPR_SPRG1             (0x111)
1291 #define SPR_SPRG2             (0x112)
1292 #define SPR_SPRG3             (0x113)
1293 #define SPR_SPRG4             (0x114)
1294 #define SPR_SCOMC             (0x114)
1295 #define SPR_SPRG5             (0x115)
1296 #define SPR_SCOMD             (0x115)
1297 #define SPR_SPRG6             (0x116)
1298 #define SPR_SPRG7             (0x117)
1299 #define SPR_ASR               (0x118)
1300 #define SPR_EAR               (0x11A)
1301 #define SPR_TBL               (0x11C)
1302 #define SPR_TBU               (0x11D)
1303 #define SPR_TBU40             (0x11E)
1304 #define SPR_SVR               (0x11E)
1305 #define SPR_BOOKE_PIR         (0x11E)
1306 #define SPR_PVR               (0x11F)
1307 #define SPR_HSPRG0            (0x130)
1308 #define SPR_BOOKE_DBSR        (0x130)
1309 #define SPR_HSPRG1            (0x131)
1310 #define SPR_HDSISR            (0x132)
1311 #define SPR_HDAR              (0x133)
1312 #define SPR_BOOKE_EPCR        (0x133)
1313 #define SPR_SPURR             (0x134)
1314 #define SPR_BOOKE_DBCR0       (0x134)
1315 #define SPR_IBCR              (0x135)
1316 #define SPR_PURR              (0x135)
1317 #define SPR_BOOKE_DBCR1       (0x135)
1318 #define SPR_DBCR              (0x136)
1319 #define SPR_HDEC              (0x136)
1320 #define SPR_BOOKE_DBCR2       (0x136)
1321 #define SPR_HIOR              (0x137)
1322 #define SPR_MBAR              (0x137)
1323 #define SPR_RMOR              (0x138)
1324 #define SPR_BOOKE_IAC1        (0x138)
1325 #define SPR_HRMOR             (0x139)
1326 #define SPR_BOOKE_IAC2        (0x139)
1327 #define SPR_HSRR0             (0x13A)
1328 #define SPR_BOOKE_IAC3        (0x13A)
1329 #define SPR_HSRR1             (0x13B)
1330 #define SPR_BOOKE_IAC4        (0x13B)
1331 #define SPR_BOOKE_DAC1        (0x13C)
1332 #define SPR_LPIDR             (0x13D)
1333 #define SPR_DABR2             (0x13D)
1334 #define SPR_BOOKE_DAC2        (0x13D)
1335 #define SPR_BOOKE_DVC1        (0x13E)
1336 #define SPR_LPCR              (0x13E)
1337 #define SPR_BOOKE_DVC2        (0x13F)
1338 #define SPR_BOOKE_TSR         (0x150)
1339 #define SPR_BOOKE_TCR         (0x154)
1340 #define SPR_BOOKE_TLB0PS      (0x158)
1341 #define SPR_BOOKE_TLB1PS      (0x159)
1342 #define SPR_BOOKE_TLB2PS      (0x15A)
1343 #define SPR_BOOKE_TLB3PS      (0x15B)
1344 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1345 #define SPR_BOOKE_IVOR0       (0x190)
1346 #define SPR_BOOKE_IVOR1       (0x191)
1347 #define SPR_BOOKE_IVOR2       (0x192)
1348 #define SPR_BOOKE_IVOR3       (0x193)
1349 #define SPR_BOOKE_IVOR4       (0x194)
1350 #define SPR_BOOKE_IVOR5       (0x195)
1351 #define SPR_BOOKE_IVOR6       (0x196)
1352 #define SPR_BOOKE_IVOR7       (0x197)
1353 #define SPR_BOOKE_IVOR8       (0x198)
1354 #define SPR_BOOKE_IVOR9       (0x199)
1355 #define SPR_BOOKE_IVOR10      (0x19A)
1356 #define SPR_BOOKE_IVOR11      (0x19B)
1357 #define SPR_BOOKE_IVOR12      (0x19C)
1358 #define SPR_BOOKE_IVOR13      (0x19D)
1359 #define SPR_BOOKE_IVOR14      (0x19E)
1360 #define SPR_BOOKE_IVOR15      (0x19F)
1361 #define SPR_BOOKE_IVOR38      (0x1B0)
1362 #define SPR_BOOKE_IVOR39      (0x1B1)
1363 #define SPR_BOOKE_IVOR40      (0x1B2)
1364 #define SPR_BOOKE_IVOR41      (0x1B3)
1365 #define SPR_BOOKE_IVOR42      (0x1B4)
1366 #define SPR_BOOKE_SPEFSCR     (0x200)
1367 #define SPR_Exxx_BBEAR        (0x201)
1368 #define SPR_Exxx_BBTAR        (0x202)
1369 #define SPR_Exxx_L1CFG0       (0x203)
1370 #define SPR_Exxx_NPIDR        (0x205)
1371 #define SPR_ATBL              (0x20E)
1372 #define SPR_ATBU              (0x20F)
1373 #define SPR_IBAT0U            (0x210)
1374 #define SPR_BOOKE_IVOR32      (0x210)
1375 #define SPR_RCPU_MI_GRA       (0x210)
1376 #define SPR_IBAT0L            (0x211)
1377 #define SPR_BOOKE_IVOR33      (0x211)
1378 #define SPR_IBAT1U            (0x212)
1379 #define SPR_BOOKE_IVOR34      (0x212)
1380 #define SPR_IBAT1L            (0x213)
1381 #define SPR_BOOKE_IVOR35      (0x213)
1382 #define SPR_IBAT2U            (0x214)
1383 #define SPR_BOOKE_IVOR36      (0x214)
1384 #define SPR_IBAT2L            (0x215)
1385 #define SPR_BOOKE_IVOR37      (0x215)
1386 #define SPR_IBAT3U            (0x216)
1387 #define SPR_IBAT3L            (0x217)
1388 #define SPR_DBAT0U            (0x218)
1389 #define SPR_RCPU_L2U_GRA      (0x218)
1390 #define SPR_DBAT0L            (0x219)
1391 #define SPR_DBAT1U            (0x21A)
1392 #define SPR_DBAT1L            (0x21B)
1393 #define SPR_DBAT2U            (0x21C)
1394 #define SPR_DBAT2L            (0x21D)
1395 #define SPR_DBAT3U            (0x21E)
1396 #define SPR_DBAT3L            (0x21F)
1397 #define SPR_IBAT4U            (0x230)
1398 #define SPR_RPCU_BBCMCR       (0x230)
1399 #define SPR_MPC_IC_CST        (0x230)
1400 #define SPR_Exxx_CTXCR        (0x230)
1401 #define SPR_IBAT4L            (0x231)
1402 #define SPR_MPC_IC_ADR        (0x231)
1403 #define SPR_Exxx_DBCR3        (0x231)
1404 #define SPR_IBAT5U            (0x232)
1405 #define SPR_MPC_IC_DAT        (0x232)
1406 #define SPR_Exxx_DBCNT        (0x232)
1407 #define SPR_IBAT5L            (0x233)
1408 #define SPR_IBAT6U            (0x234)
1409 #define SPR_IBAT6L            (0x235)
1410 #define SPR_IBAT7U            (0x236)
1411 #define SPR_IBAT7L            (0x237)
1412 #define SPR_DBAT4U            (0x238)
1413 #define SPR_RCPU_L2U_MCR      (0x238)
1414 #define SPR_MPC_DC_CST        (0x238)
1415 #define SPR_Exxx_ALTCTXCR     (0x238)
1416 #define SPR_DBAT4L            (0x239)
1417 #define SPR_MPC_DC_ADR        (0x239)
1418 #define SPR_DBAT5U            (0x23A)
1419 #define SPR_BOOKE_MCSRR0      (0x23A)
1420 #define SPR_MPC_DC_DAT        (0x23A)
1421 #define SPR_DBAT5L            (0x23B)
1422 #define SPR_BOOKE_MCSRR1      (0x23B)
1423 #define SPR_DBAT6U            (0x23C)
1424 #define SPR_BOOKE_MCSR        (0x23C)
1425 #define SPR_DBAT6L            (0x23D)
1426 #define SPR_Exxx_MCAR         (0x23D)
1427 #define SPR_DBAT7U            (0x23E)
1428 #define SPR_BOOKE_DSRR0       (0x23E)
1429 #define SPR_DBAT7L            (0x23F)
1430 #define SPR_BOOKE_DSRR1       (0x23F)
1431 #define SPR_BOOKE_SPRG8       (0x25C)
1432 #define SPR_BOOKE_SPRG9       (0x25D)
1433 #define SPR_BOOKE_MAS0        (0x270)
1434 #define SPR_BOOKE_MAS1        (0x271)
1435 #define SPR_BOOKE_MAS2        (0x272)
1436 #define SPR_BOOKE_MAS3        (0x273)
1437 #define SPR_BOOKE_MAS4        (0x274)
1438 #define SPR_BOOKE_MAS5        (0x275)
1439 #define SPR_BOOKE_MAS6        (0x276)
1440 #define SPR_BOOKE_PID1        (0x279)
1441 #define SPR_BOOKE_PID2        (0x27A)
1442 #define SPR_MPC_DPDR          (0x280)
1443 #define SPR_MPC_IMMR          (0x288)
1444 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1445 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1446 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1447 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1448 #define SPR_BOOKE_EPR         (0x2BE)
1449 #define SPR_PERF0             (0x300)
1450 #define SPR_RCPU_MI_RBA0      (0x300)
1451 #define SPR_MPC_MI_CTR        (0x300)
1452 #define SPR_PERF1             (0x301)
1453 #define SPR_RCPU_MI_RBA1      (0x301)
1454 #define SPR_PERF2             (0x302)
1455 #define SPR_RCPU_MI_RBA2      (0x302)
1456 #define SPR_MPC_MI_AP         (0x302)
1457 #define SPR_MMCRA             (0x302)
1458 #define SPR_PERF3             (0x303)
1459 #define SPR_RCPU_MI_RBA3      (0x303)
1460 #define SPR_MPC_MI_EPN        (0x303)
1461 #define SPR_PERF4             (0x304)
1462 #define SPR_PERF5             (0x305)
1463 #define SPR_MPC_MI_TWC        (0x305)
1464 #define SPR_PERF6             (0x306)
1465 #define SPR_MPC_MI_RPN        (0x306)
1466 #define SPR_PERF7             (0x307)
1467 #define SPR_PERF8             (0x308)
1468 #define SPR_RCPU_L2U_RBA0     (0x308)
1469 #define SPR_MPC_MD_CTR        (0x308)
1470 #define SPR_PERF9             (0x309)
1471 #define SPR_RCPU_L2U_RBA1     (0x309)
1472 #define SPR_MPC_MD_CASID      (0x309)
1473 #define SPR_PERFA             (0x30A)
1474 #define SPR_RCPU_L2U_RBA2     (0x30A)
1475 #define SPR_MPC_MD_AP         (0x30A)
1476 #define SPR_PERFB             (0x30B)
1477 #define SPR_RCPU_L2U_RBA3     (0x30B)
1478 #define SPR_MPC_MD_EPN        (0x30B)
1479 #define SPR_PERFC             (0x30C)
1480 #define SPR_MPC_MD_TWB        (0x30C)
1481 #define SPR_PERFD             (0x30D)
1482 #define SPR_MPC_MD_TWC        (0x30D)
1483 #define SPR_PERFE             (0x30E)
1484 #define SPR_MPC_MD_RPN        (0x30E)
1485 #define SPR_PERFF             (0x30F)
1486 #define SPR_MPC_MD_TW         (0x30F)
1487 #define SPR_UPERF0            (0x310)
1488 #define SPR_UPERF1            (0x311)
1489 #define SPR_UPERF2            (0x312)
1490 #define SPR_UPERF3            (0x313)
1491 #define SPR_UPERF4            (0x314)
1492 #define SPR_UPERF5            (0x315)
1493 #define SPR_UPERF6            (0x316)
1494 #define SPR_UPERF7            (0x317)
1495 #define SPR_UPERF8            (0x318)
1496 #define SPR_UPERF9            (0x319)
1497 #define SPR_UPERFA            (0x31A)
1498 #define SPR_UPERFB            (0x31B)
1499 #define SPR_UPERFC            (0x31C)
1500 #define SPR_UPERFD            (0x31D)
1501 #define SPR_UPERFE            (0x31E)
1502 #define SPR_UPERFF            (0x31F)
1503 #define SPR_RCPU_MI_RA0       (0x320)
1504 #define SPR_MPC_MI_DBCAM      (0x320)
1505 #define SPR_RCPU_MI_RA1       (0x321)
1506 #define SPR_MPC_MI_DBRAM0     (0x321)
1507 #define SPR_RCPU_MI_RA2       (0x322)
1508 #define SPR_MPC_MI_DBRAM1     (0x322)
1509 #define SPR_RCPU_MI_RA3       (0x323)
1510 #define SPR_RCPU_L2U_RA0      (0x328)
1511 #define SPR_MPC_MD_DBCAM      (0x328)
1512 #define SPR_RCPU_L2U_RA1      (0x329)
1513 #define SPR_MPC_MD_DBRAM0     (0x329)
1514 #define SPR_RCPU_L2U_RA2      (0x32A)
1515 #define SPR_MPC_MD_DBRAM1     (0x32A)
1516 #define SPR_RCPU_L2U_RA3      (0x32B)
1517 #define SPR_TAR               (0x32F)
1518 #define SPR_440_INV0          (0x370)
1519 #define SPR_440_INV1          (0x371)
1520 #define SPR_440_INV2          (0x372)
1521 #define SPR_440_INV3          (0x373)
1522 #define SPR_440_ITV0          (0x374)
1523 #define SPR_440_ITV1          (0x375)
1524 #define SPR_440_ITV2          (0x376)
1525 #define SPR_440_ITV3          (0x377)
1526 #define SPR_440_CCR1          (0x378)
1527 #define SPR_DCRIPR            (0x37B)
1528 #define SPR_PPR               (0x380)
1529 #define SPR_750_GQR0          (0x390)
1530 #define SPR_440_DNV0          (0x390)
1531 #define SPR_750_GQR1          (0x391)
1532 #define SPR_440_DNV1          (0x391)
1533 #define SPR_750_GQR2          (0x392)
1534 #define SPR_440_DNV2          (0x392)
1535 #define SPR_750_GQR3          (0x393)
1536 #define SPR_440_DNV3          (0x393)
1537 #define SPR_750_GQR4          (0x394)
1538 #define SPR_440_DTV0          (0x394)
1539 #define SPR_750_GQR5          (0x395)
1540 #define SPR_440_DTV1          (0x395)
1541 #define SPR_750_GQR6          (0x396)
1542 #define SPR_440_DTV2          (0x396)
1543 #define SPR_750_GQR7          (0x397)
1544 #define SPR_440_DTV3          (0x397)
1545 #define SPR_750_THRM4         (0x398)
1546 #define SPR_750CL_HID2        (0x398)
1547 #define SPR_440_DVLIM         (0x398)
1548 #define SPR_750_WPAR          (0x399)
1549 #define SPR_440_IVLIM         (0x399)
1550 #define SPR_750_DMAU          (0x39A)
1551 #define SPR_750_DMAL          (0x39B)
1552 #define SPR_440_RSTCFG        (0x39B)
1553 #define SPR_BOOKE_DCDBTRL     (0x39C)
1554 #define SPR_BOOKE_DCDBTRH     (0x39D)
1555 #define SPR_BOOKE_ICDBTRL     (0x39E)
1556 #define SPR_BOOKE_ICDBTRH     (0x39F)
1557 #define SPR_UMMCR2            (0x3A0)
1558 #define SPR_UPMC5             (0x3A1)
1559 #define SPR_UPMC6             (0x3A2)
1560 #define SPR_UBAMR             (0x3A7)
1561 #define SPR_UMMCR0            (0x3A8)
1562 #define SPR_UPMC1             (0x3A9)
1563 #define SPR_UPMC2             (0x3AA)
1564 #define SPR_USIAR             (0x3AB)
1565 #define SPR_UMMCR1            (0x3AC)
1566 #define SPR_UPMC3             (0x3AD)
1567 #define SPR_UPMC4             (0x3AE)
1568 #define SPR_USDA              (0x3AF)
1569 #define SPR_40x_ZPR           (0x3B0)
1570 #define SPR_BOOKE_MAS7        (0x3B0)
1571 #define SPR_MMCR2             (0x3B0)
1572 #define SPR_PMC5              (0x3B1)
1573 #define SPR_40x_PID           (0x3B1)
1574 #define SPR_PMC6              (0x3B2)
1575 #define SPR_440_MMUCR         (0x3B2)
1576 #define SPR_4xx_CCR0          (0x3B3)
1577 #define SPR_BOOKE_EPLC        (0x3B3)
1578 #define SPR_405_IAC3          (0x3B4)
1579 #define SPR_BOOKE_EPSC        (0x3B4)
1580 #define SPR_405_IAC4          (0x3B5)
1581 #define SPR_405_DVC1          (0x3B6)
1582 #define SPR_405_DVC2          (0x3B7)
1583 #define SPR_BAMR              (0x3B7)
1584 #define SPR_MMCR0             (0x3B8)
1585 #define SPR_PMC1              (0x3B9)
1586 #define SPR_40x_SGR           (0x3B9)
1587 #define SPR_PMC2              (0x3BA)
1588 #define SPR_40x_DCWR          (0x3BA)
1589 #define SPR_SIAR              (0x3BB)
1590 #define SPR_405_SLER          (0x3BB)
1591 #define SPR_MMCR1             (0x3BC)
1592 #define SPR_405_SU0R          (0x3BC)
1593 #define SPR_401_SKR           (0x3BC)
1594 #define SPR_PMC3              (0x3BD)
1595 #define SPR_405_DBCR1         (0x3BD)
1596 #define SPR_PMC4              (0x3BE)
1597 #define SPR_SDA               (0x3BF)
1598 #define SPR_403_VTBL          (0x3CC)
1599 #define SPR_403_VTBU          (0x3CD)
1600 #define SPR_DMISS             (0x3D0)
1601 #define SPR_DCMP              (0x3D1)
1602 #define SPR_HASH1             (0x3D2)
1603 #define SPR_HASH2             (0x3D3)
1604 #define SPR_BOOKE_ICDBDR      (0x3D3)
1605 #define SPR_TLBMISS           (0x3D4)
1606 #define SPR_IMISS             (0x3D4)
1607 #define SPR_40x_ESR           (0x3D4)
1608 #define SPR_PTEHI             (0x3D5)
1609 #define SPR_ICMP              (0x3D5)
1610 #define SPR_40x_DEAR          (0x3D5)
1611 #define SPR_PTELO             (0x3D6)
1612 #define SPR_RPA               (0x3D6)
1613 #define SPR_40x_EVPR          (0x3D6)
1614 #define SPR_L3PM              (0x3D7)
1615 #define SPR_403_CDBCR         (0x3D7)
1616 #define SPR_L3ITCR0           (0x3D8)
1617 #define SPR_TCR               (0x3D8)
1618 #define SPR_40x_TSR           (0x3D8)
1619 #define SPR_IBR               (0x3DA)
1620 #define SPR_40x_TCR           (0x3DA)
1621 #define SPR_ESASRR            (0x3DB)
1622 #define SPR_40x_PIT           (0x3DB)
1623 #define SPR_403_TBL           (0x3DC)
1624 #define SPR_403_TBU           (0x3DD)
1625 #define SPR_SEBR              (0x3DE)
1626 #define SPR_40x_SRR2          (0x3DE)
1627 #define SPR_SER               (0x3DF)
1628 #define SPR_40x_SRR3          (0x3DF)
1629 #define SPR_L3OHCR            (0x3E8)
1630 #define SPR_L3ITCR1           (0x3E9)
1631 #define SPR_L3ITCR2           (0x3EA)
1632 #define SPR_L3ITCR3           (0x3EB)
1633 #define SPR_HID0              (0x3F0)
1634 #define SPR_40x_DBSR          (0x3F0)
1635 #define SPR_HID1              (0x3F1)
1636 #define SPR_IABR              (0x3F2)
1637 #define SPR_40x_DBCR0         (0x3F2)
1638 #define SPR_601_HID2          (0x3F2)
1639 #define SPR_Exxx_L1CSR0       (0x3F2)
1640 #define SPR_ICTRL             (0x3F3)
1641 #define SPR_HID2              (0x3F3)
1642 #define SPR_750CL_HID4        (0x3F3)
1643 #define SPR_Exxx_L1CSR1       (0x3F3)
1644 #define SPR_440_DBDR          (0x3F3)
1645 #define SPR_LDSTDB            (0x3F4)
1646 #define SPR_750_TDCL          (0x3F4)
1647 #define SPR_40x_IAC1          (0x3F4)
1648 #define SPR_MMUCSR0           (0x3F4)
1649 #define SPR_DABR              (0x3F5)
1650 #define DABR_MASK (~(target_ulong)0x7)
1651 #define SPR_Exxx_BUCSR        (0x3F5)
1652 #define SPR_40x_IAC2          (0x3F5)
1653 #define SPR_601_HID5          (0x3F5)
1654 #define SPR_40x_DAC1          (0x3F6)
1655 #define SPR_MSSCR0            (0x3F6)
1656 #define SPR_970_HID5          (0x3F6)
1657 #define SPR_MSSSR0            (0x3F7)
1658 #define SPR_MSSCR1            (0x3F7)
1659 #define SPR_DABRX             (0x3F7)
1660 #define SPR_40x_DAC2          (0x3F7)
1661 #define SPR_MMUCFG            (0x3F7)
1662 #define SPR_LDSTCR            (0x3F8)
1663 #define SPR_L2PMCR            (0x3F8)
1664 #define SPR_750FX_HID2        (0x3F8)
1665 #define SPR_Exxx_L1FINV0      (0x3F8)
1666 #define SPR_L2CR              (0x3F9)
1667 #define SPR_L3CR              (0x3FA)
1668 #define SPR_750_TDCH          (0x3FA)
1669 #define SPR_IABR2             (0x3FA)
1670 #define SPR_40x_DCCR          (0x3FA)
1671 #define SPR_ICTC              (0x3FB)
1672 #define SPR_40x_ICCR          (0x3FB)
1673 #define SPR_THRM1             (0x3FC)
1674 #define SPR_403_PBL1          (0x3FC)
1675 #define SPR_SP                (0x3FD)
1676 #define SPR_THRM2             (0x3FD)
1677 #define SPR_403_PBU1          (0x3FD)
1678 #define SPR_604_HID13         (0x3FD)
1679 #define SPR_LT                (0x3FE)
1680 #define SPR_THRM3             (0x3FE)
1681 #define SPR_RCPU_FPECR        (0x3FE)
1682 #define SPR_403_PBL2          (0x3FE)
1683 #define SPR_PIR               (0x3FF)
1684 #define SPR_403_PBU2          (0x3FF)
1685 #define SPR_601_HID15         (0x3FF)
1686 #define SPR_604_HID15         (0x3FF)
1687 #define SPR_E500_SVR          (0x3FF)
1688
1689 /* Disable MAS Interrupt Updates for Hypervisor */
1690 #define EPCR_DMIUH            (1 << 22)
1691 /* Disable Guest TLB Management Instructions */
1692 #define EPCR_DGTMI            (1 << 23)
1693 /* Guest Interrupt Computation Mode */
1694 #define EPCR_GICM             (1 << 24)
1695 /* Interrupt Computation Mode */
1696 #define EPCR_ICM              (1 << 25)
1697 /* Disable Embedded Hypervisor Debug */
1698 #define EPCR_DUVD             (1 << 26)
1699 /* Instruction Storage Interrupt Directed to Guest State */
1700 #define EPCR_ISIGS            (1 << 27)
1701 /* Data Storage Interrupt Directed to Guest State */
1702 #define EPCR_DSIGS            (1 << 28)
1703 /* Instruction TLB Error Interrupt Directed to Guest State */
1704 #define EPCR_ITLBGS           (1 << 29)
1705 /* Data TLB Error Interrupt Directed to Guest State */
1706 #define EPCR_DTLBGS           (1 << 30)
1707 /* External Input Interrupt Directed to Guest State */
1708 #define EPCR_EXTGS            (1 << 31)
1709
1710 /*****************************************************************************/
1711 /* PowerPC Instructions types definitions                                    */
1712 enum {
1713     PPC_NONE           = 0x0000000000000000ULL,
1714     /* PowerPC base instructions set                                         */
1715     PPC_INSNS_BASE     = 0x0000000000000001ULL,
1716     /*   integer operations instructions                                     */
1717 #define PPC_INTEGER PPC_INSNS_BASE
1718     /*   flow control instructions                                           */
1719 #define PPC_FLOW    PPC_INSNS_BASE
1720     /*   virtual memory instructions                                         */
1721 #define PPC_MEM     PPC_INSNS_BASE
1722     /*   ld/st with reservation instructions                                 */
1723 #define PPC_RES     PPC_INSNS_BASE
1724     /*   spr/msr access instructions                                         */
1725 #define PPC_MISC    PPC_INSNS_BASE
1726     /* Deprecated instruction sets                                           */
1727     /*   Original POWER instruction set                                      */
1728     PPC_POWER          = 0x0000000000000002ULL,
1729     /*   POWER2 instruction set extension                                    */
1730     PPC_POWER2         = 0x0000000000000004ULL,
1731     /*   Power RTC support                                                   */
1732     PPC_POWER_RTC      = 0x0000000000000008ULL,
1733     /*   Power-to-PowerPC bridge (601)                                       */
1734     PPC_POWER_BR       = 0x0000000000000010ULL,
1735     /* 64 bits PowerPC instruction set                                       */
1736     PPC_64B            = 0x0000000000000020ULL,
1737     /*   New 64 bits extensions (PowerPC 2.0x)                               */
1738     PPC_64BX           = 0x0000000000000040ULL,
1739     /*   64 bits hypervisor extensions                                       */
1740     PPC_64H            = 0x0000000000000080ULL,
1741     /*   New wait instruction (PowerPC 2.0x)                                 */
1742     PPC_WAIT           = 0x0000000000000100ULL,
1743     /*   Time base mftb instruction                                          */
1744     PPC_MFTB           = 0x0000000000000200ULL,
1745
1746     /* Fixed-point unit extensions                                           */
1747     /*   PowerPC 602 specific                                                */
1748     PPC_602_SPEC       = 0x0000000000000400ULL,
1749     /*   isel instruction                                                    */
1750     PPC_ISEL           = 0x0000000000000800ULL,
1751     /*   popcntb instruction                                                 */
1752     PPC_POPCNTB        = 0x0000000000001000ULL,
1753     /*   string load / store                                                 */
1754     PPC_STRING         = 0x0000000000002000ULL,
1755
1756     /* Floating-point unit extensions                                        */
1757     /*   Optional floating point instructions                                */
1758     PPC_FLOAT          = 0x0000000000010000ULL,
1759     /* New floating-point extensions (PowerPC 2.0x)                          */
1760     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
1761     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
1762     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
1763     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
1764     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1765     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
1766     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
1767
1768     /* Vector/SIMD extensions                                                */
1769     /*   Altivec support                                                     */
1770     PPC_ALTIVEC        = 0x0000000001000000ULL,
1771     /*   PowerPC 2.03 SPE extension                                          */
1772     PPC_SPE            = 0x0000000002000000ULL,
1773     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
1774     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
1775     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
1776     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
1777
1778     /* Optional memory control instructions                                  */
1779     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
1780     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
1781     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
1782     /*   sync instruction                                                    */
1783     PPC_MEM_SYNC       = 0x0000000080000000ULL,
1784     /*   eieio instruction                                                   */
1785     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
1786
1787     /* Cache control instructions                                            */
1788     PPC_CACHE          = 0x0000000200000000ULL,
1789     /*   icbi instruction                                                    */
1790     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
1791     /*   dcbz instruction                                                    */
1792     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
1793     /*   dcba instruction                                                    */
1794     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
1795     /*   Freescale cache locking instructions                                */
1796     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
1797
1798     /* MMU related extensions                                                */
1799     /*   external control instructions                                       */
1800     PPC_EXTERN         = 0x0000010000000000ULL,
1801     /*   segment register access instructions                                */
1802     PPC_SEGMENT        = 0x0000020000000000ULL,
1803     /*   PowerPC 6xx TLB management instructions                             */
1804     PPC_6xx_TLB        = 0x0000040000000000ULL,
1805     /* PowerPC 74xx TLB management instructions                              */
1806     PPC_74xx_TLB       = 0x0000080000000000ULL,
1807     /*   PowerPC 40x TLB management instructions                             */
1808     PPC_40x_TLB        = 0x0000100000000000ULL,
1809     /*   segment register access instructions for PowerPC 64 "bridge"        */
1810     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
1811     /*   SLB management                                                      */
1812     PPC_SLBI           = 0x0000400000000000ULL,
1813
1814     /* Embedded PowerPC dedicated instructions                               */
1815     PPC_WRTEE          = 0x0001000000000000ULL,
1816     /* PowerPC 40x exception model                                           */
1817     PPC_40x_EXCP       = 0x0002000000000000ULL,
1818     /* PowerPC 405 Mac instructions                                          */
1819     PPC_405_MAC        = 0x0004000000000000ULL,
1820     /* PowerPC 440 specific instructions                                     */
1821     PPC_440_SPEC       = 0x0008000000000000ULL,
1822     /* BookE (embedded) PowerPC specification                                */
1823     PPC_BOOKE          = 0x0010000000000000ULL,
1824     /* mfapidi instruction                                                   */
1825     PPC_MFAPIDI        = 0x0020000000000000ULL,
1826     /* tlbiva instruction                                                    */
1827     PPC_TLBIVA         = 0x0040000000000000ULL,
1828     /* tlbivax instruction                                                   */
1829     PPC_TLBIVAX        = 0x0080000000000000ULL,
1830     /* PowerPC 4xx dedicated instructions                                    */
1831     PPC_4xx_COMMON     = 0x0100000000000000ULL,
1832     /* PowerPC 40x ibct instructions                                         */
1833     PPC_40x_ICBT       = 0x0200000000000000ULL,
1834     /* rfmci is not implemented in all BookE PowerPC                         */
1835     PPC_RFMCI          = 0x0400000000000000ULL,
1836     /* rfdi instruction                                                      */
1837     PPC_RFDI           = 0x0800000000000000ULL,
1838     /* DCR accesses                                                          */
1839     PPC_DCR            = 0x1000000000000000ULL,
1840     /* DCR extended accesse                                                  */
1841     PPC_DCRX           = 0x2000000000000000ULL,
1842     /* user-mode DCR access, implemented in PowerPC 460                      */
1843     PPC_DCRUX          = 0x4000000000000000ULL,
1844     /* popcntw and popcntd instructions                                      */
1845     PPC_POPCNTWD       = 0x8000000000000000ULL,
1846
1847 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1848                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1849                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1850                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1851                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1852                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1853                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1854                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1855                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1856                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1857                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1858                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1859                         | PPC_CACHE | PPC_CACHE_ICBI \
1860                         | PPC_CACHE_DCBZ \
1861                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1862                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1863                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1864                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1865                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1866                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1867                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1868                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1869                         | PPC_POPCNTWD)
1870
1871     /* extended type values */
1872
1873     /* BookE 2.06 PowerPC specification                                      */
1874     PPC2_BOOKE206      = 0x0000000000000001ULL,
1875     /* VSX (extensions to Altivec / VMX)                                     */
1876     PPC2_VSX           = 0x0000000000000002ULL,
1877     /* Decimal Floating Point (DFP)                                          */
1878     PPC2_DFP           = 0x0000000000000004ULL,
1879     /* Embedded.Processor Control                                            */
1880     PPC2_PRCNTL        = 0x0000000000000008ULL,
1881     /* Byte-reversed, indexed, double-word load and store                    */
1882     PPC2_DBRX          = 0x0000000000000010ULL,
1883     /* Book I 2.05 PowerPC specification                                     */
1884     PPC2_ISA205        = 0x0000000000000020ULL,
1885     /* VSX additions in ISA 2.07                                             */
1886     PPC2_VSX207        = 0x0000000000000040ULL,
1887     /* ISA 2.06B bpermd                                                      */
1888     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
1889     /* ISA 2.06B divide extended variants                                    */
1890     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
1891     /* ISA 2.06B larx/stcx. instructions                                     */
1892     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1893     /* ISA 2.06B floating point integer conversion                           */
1894     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
1895     /* ISA 2.06B floating point test instructions                            */
1896     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
1897     /* ISA 2.07 bctar instruction                                            */
1898     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
1899     /* ISA 2.07 load/store quadword                                          */
1900     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
1901     /* ISA 2.07 Altivec                                                      */
1902     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
1903
1904 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
1905                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1906                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
1907                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
1908                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
1909                         PPC2_ALTIVEC_207)
1910 };
1911
1912 /*****************************************************************************/
1913 /* Memory access type :
1914  * may be needed for precise access rights control and precise exceptions.
1915  */
1916 enum {
1917     /* 1 bit to define user level / supervisor access */
1918     ACCESS_USER  = 0x00,
1919     ACCESS_SUPER = 0x01,
1920     /* Type of instruction that generated the access */
1921     ACCESS_CODE  = 0x10, /* Code fetch access                */
1922     ACCESS_INT   = 0x20, /* Integer load/store access        */
1923     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1924     ACCESS_RES   = 0x40, /* load/store with reservation      */
1925     ACCESS_EXT   = 0x50, /* external access                  */
1926     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1927 };
1928
1929 /* Hardware interruption sources:
1930  * all those exception can be raised simulteaneously
1931  */
1932 /* Input pins definitions */
1933 enum {
1934     /* 6xx bus input pins */
1935     PPC6xx_INPUT_HRESET     = 0,
1936     PPC6xx_INPUT_SRESET     = 1,
1937     PPC6xx_INPUT_CKSTP_IN   = 2,
1938     PPC6xx_INPUT_MCP        = 3,
1939     PPC6xx_INPUT_SMI        = 4,
1940     PPC6xx_INPUT_INT        = 5,
1941     PPC6xx_INPUT_TBEN       = 6,
1942     PPC6xx_INPUT_WAKEUP     = 7,
1943     PPC6xx_INPUT_NB,
1944 };
1945
1946 enum {
1947     /* Embedded PowerPC input pins */
1948     PPCBookE_INPUT_HRESET     = 0,
1949     PPCBookE_INPUT_SRESET     = 1,
1950     PPCBookE_INPUT_CKSTP_IN   = 2,
1951     PPCBookE_INPUT_MCP        = 3,
1952     PPCBookE_INPUT_SMI        = 4,
1953     PPCBookE_INPUT_INT        = 5,
1954     PPCBookE_INPUT_CINT       = 6,
1955     PPCBookE_INPUT_NB,
1956 };
1957
1958 enum {
1959     /* PowerPC E500 input pins */
1960     PPCE500_INPUT_RESET_CORE = 0,
1961     PPCE500_INPUT_MCK        = 1,
1962     PPCE500_INPUT_CINT       = 3,
1963     PPCE500_INPUT_INT        = 4,
1964     PPCE500_INPUT_DEBUG      = 6,
1965     PPCE500_INPUT_NB,
1966 };
1967
1968 enum {
1969     /* PowerPC 40x input pins */
1970     PPC40x_INPUT_RESET_CORE = 0,
1971     PPC40x_INPUT_RESET_CHIP = 1,
1972     PPC40x_INPUT_RESET_SYS  = 2,
1973     PPC40x_INPUT_CINT       = 3,
1974     PPC40x_INPUT_INT        = 4,
1975     PPC40x_INPUT_HALT       = 5,
1976     PPC40x_INPUT_DEBUG      = 6,
1977     PPC40x_INPUT_NB,
1978 };
1979
1980 enum {
1981     /* RCPU input pins */
1982     PPCRCPU_INPUT_PORESET   = 0,
1983     PPCRCPU_INPUT_HRESET    = 1,
1984     PPCRCPU_INPUT_SRESET    = 2,
1985     PPCRCPU_INPUT_IRQ0      = 3,
1986     PPCRCPU_INPUT_IRQ1      = 4,
1987     PPCRCPU_INPUT_IRQ2      = 5,
1988     PPCRCPU_INPUT_IRQ3      = 6,
1989     PPCRCPU_INPUT_IRQ4      = 7,
1990     PPCRCPU_INPUT_IRQ5      = 8,
1991     PPCRCPU_INPUT_IRQ6      = 9,
1992     PPCRCPU_INPUT_IRQ7      = 10,
1993     PPCRCPU_INPUT_NB,
1994 };
1995
1996 #if defined(TARGET_PPC64)
1997 enum {
1998     /* PowerPC 970 input pins */
1999     PPC970_INPUT_HRESET     = 0,
2000     PPC970_INPUT_SRESET     = 1,
2001     PPC970_INPUT_CKSTP      = 2,
2002     PPC970_INPUT_TBEN       = 3,
2003     PPC970_INPUT_MCP        = 4,
2004     PPC970_INPUT_INT        = 5,
2005     PPC970_INPUT_THINT      = 6,
2006     PPC970_INPUT_NB,
2007 };
2008
2009 enum {
2010     /* POWER7 input pins */
2011     POWER7_INPUT_INT        = 0,
2012     /* POWER7 probably has other inputs, but we don't care about them
2013      * for any existing machine.  We can wire these up when we need
2014      * them */
2015     POWER7_INPUT_NB,
2016 };
2017 #endif
2018
2019 /* Hardware exceptions definitions */
2020 enum {
2021     /* External hardware exception sources */
2022     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2023     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2024     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2025     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2026     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2027     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2028     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2029     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2030     /* Internal hardware exception sources */
2031     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2032     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2033     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2034     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2035     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2036     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2037     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2038     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2039 };
2040
2041 /* CPU should be reset next, restart from scratch afterwards */
2042 #define CPU_INTERRUPT_RESET       CPU_INTERRUPT_TGT_INT_0
2043
2044 /*****************************************************************************/
2045
2046 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2047 {
2048     return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2049 }
2050
2051 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2052 {
2053     env->so = (xer >> XER_SO) & 1;
2054     env->ov = (xer >> XER_OV) & 1;
2055     env->ca = (xer >> XER_CA) & 1;
2056     env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2057 }
2058
2059 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2060                                         target_ulong *cs_base, int *flags)
2061 {
2062     *pc = env->nip;
2063     *cs_base = 0;
2064     *flags = env->hflags;
2065 }
2066
2067 #if !defined(CONFIG_USER_ONLY)
2068 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2069 {
2070     uintptr_t tlbml = (uintptr_t)tlbm;
2071     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2072
2073     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2074 }
2075
2076 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2077 {
2078     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2079     int r = tlbncfg & TLBnCFG_N_ENTRY;
2080     return r;
2081 }
2082
2083 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2084 {
2085     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2086     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2087     return r;
2088 }
2089
2090 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2091 {
2092     int id = booke206_tlbm_id(env, tlbm);
2093     int end = 0;
2094     int i;
2095
2096     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2097         end += booke206_tlb_size(env, i);
2098         if (id < end) {
2099             return i;
2100         }
2101     }
2102
2103     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2104     return 0;
2105 }
2106
2107 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2108 {
2109     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2110     int tlbid = booke206_tlbm_id(env, tlb);
2111     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2112 }
2113
2114 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2115                                               target_ulong ea, int way)
2116 {
2117     int r;
2118     uint32_t ways = booke206_tlb_ways(env, tlbn);
2119     int ways_bits = ffs(ways) - 1;
2120     int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2121     int i;
2122
2123     way &= ways - 1;
2124     ea >>= MAS2_EPN_SHIFT;
2125     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2126     r = (ea << ways_bits) | way;
2127
2128     if (r >= booke206_tlb_size(env, tlbn)) {
2129         return NULL;
2130     }
2131
2132     /* bump up to tlbn index */
2133     for (i = 0; i < tlbn; i++) {
2134         r += booke206_tlb_size(env, i);
2135     }
2136
2137     return &env->tlb.tlbm[r];
2138 }
2139
2140 /* returns bitmap of supported page sizes for a given TLB */
2141 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2142 {
2143     bool mav2 = false;
2144     uint32_t ret = 0;
2145
2146     if (mav2) {
2147         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2148     } else {
2149         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2150         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2151         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2152         int i;
2153         for (i = min; i <= max; i++) {
2154             ret |= (1 << (i << 1));
2155         }
2156     }
2157
2158     return ret;
2159 }
2160
2161 #endif
2162
2163 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2164 {
2165     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2166         return msr & (1ULL << MSR_CM);
2167     }
2168
2169     return msr & (1ULL << MSR_SF);
2170 }
2171
2172 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2173
2174 #include "exec/exec-all.h"
2175
2176 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2177
2178 /**
2179  * ppc_get_vcpu_dt_id:
2180  * @cs: a PowerPCCPU struct.
2181  *
2182  * Returns a device-tree ID for a CPU.
2183  */
2184 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2185
2186 /**
2187  * ppc_get_vcpu_by_dt_id:
2188  * @cpu_dt_id: a device tree id
2189  *
2190  * Searches for a CPU by @cpu_dt_id.
2191  *
2192  * Returns: a PowerPCCPU struct
2193  */
2194 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2195
2196 #endif /* !defined (__CPU_PPC_H__) */