4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
121 case ARMMMUIdx_SE20_2
:
122 case ARMMMUIdx_SE20_2_PAN
:
123 useridx
= ARMMMUIdx_SE20_0
;
126 g_assert_not_reached();
129 return arm_to_core_mmu_idx(useridx
);
132 static void reset_btype(DisasContext
*s
)
135 TCGv_i32 zero
= tcg_const_i32(0);
136 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
137 tcg_temp_free_i32(zero
);
142 static void set_btype(DisasContext
*s
, int val
)
146 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
147 tcg_debug_assert(val
>= 1 && val
<= 3);
149 tcg_val
= tcg_const_i32(val
);
150 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
151 tcg_temp_free_i32(tcg_val
);
155 void gen_a64_set_pc_im(uint64_t val
)
157 tcg_gen_movi_i64(cpu_pc
, val
);
161 * Handle Top Byte Ignore (TBI) bits.
163 * If address tagging is enabled via the TCR TBI bits:
164 * + for EL2 and EL3 there is only one TBI bit, and if it is set
165 * then the address is zero-extended, clearing bits [63:56]
166 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
167 * and TBI1 controls addressses with bit 55 == 1.
168 * If the appropriate TBI bit is set for the address then
169 * the address is sign-extended from bit 55 into bits [63:56]
171 * Here We have concatenated TBI{1,0} into tbi.
173 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
174 TCGv_i64 src
, int tbi
)
177 /* Load unmodified address */
178 tcg_gen_mov_i64(dst
, src
);
179 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
180 /* Force tag byte to all zero */
181 tcg_gen_extract_i64(dst
, src
, 0, 56);
183 /* Sign-extend from bit 55. */
184 tcg_gen_sextract_i64(dst
, src
, 0, 56);
187 TCGv_i64 tcg_zero
= tcg_const_i64(0);
190 * The two TBI bits differ.
191 * If tbi0, then !tbi1: only use the extension if positive.
192 * if !tbi0, then tbi1: only use the extension if negative.
194 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
195 dst
, dst
, tcg_zero
, dst
, src
);
196 tcg_temp_free_i64(tcg_zero
);
201 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
204 * If address tagging is enabled for instructions via the TCR TBI bits,
205 * then loading an address into the PC will clear out any tag.
207 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
211 * Handle MTE and/or TBI.
213 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
214 * for the tag to be present in the FAR_ELx register. But for user-only
215 * mode we do not have a TLB with which to implement this, so we must
216 * remove the top byte now.
218 * Always return a fresh temporary that we can increment independently
219 * of the write-back address.
222 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
224 TCGv_i64 clean
= new_tmp_a64(s
);
225 #ifdef CONFIG_USER_ONLY
226 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
228 tcg_gen_mov_i64(clean
, addr
);
233 /* Insert a zero tag into src, with the result at dst. */
234 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
236 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
239 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
240 MMUAccessType acc
, int log2_size
)
242 TCGv_i32 t_acc
= tcg_const_i32(acc
);
243 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
244 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
246 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
247 tcg_temp_free_i32(t_acc
);
248 tcg_temp_free_i32(t_idx
);
249 tcg_temp_free_i32(t_size
);
253 * For MTE, check a single logical or atomic access. This probes a single
254 * address, the exact one specified. The size and alignment of the access
255 * is not relevant to MTE, per se, but watchpoints do require the size,
256 * and we want to recognize those before making any other changes to state.
258 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
259 bool is_write
, bool tag_checked
,
260 int log2_size
, bool is_unpriv
,
263 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
268 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
269 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
270 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
271 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
272 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_size
);
273 tcg_desc
= tcg_const_i32(desc
);
275 ret
= new_tmp_a64(s
);
276 gen_helper_mte_check1(ret
, cpu_env
, tcg_desc
, addr
);
277 tcg_temp_free_i32(tcg_desc
);
281 return clean_data_tbi(s
, addr
);
284 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
285 bool tag_checked
, int log2_size
)
287 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
288 false, get_mem_index(s
));
292 * For MTE, check multiple logical sequential accesses.
294 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
295 bool tag_checked
, int log2_esize
, int total_size
)
297 if (tag_checked
&& s
->mte_active
[0] && total_size
!= (1 << log2_esize
)) {
302 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
303 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
304 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
305 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
306 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_esize
);
307 desc
= FIELD_DP32(desc
, MTEDESC
, TSIZE
, total_size
);
308 tcg_desc
= tcg_const_i32(desc
);
310 ret
= new_tmp_a64(s
);
311 gen_helper_mte_checkN(ret
, cpu_env
, tcg_desc
, addr
);
312 tcg_temp_free_i32(tcg_desc
);
316 return gen_mte_check1(s
, addr
, is_write
, tag_checked
, log2_esize
);
319 typedef struct DisasCompare64
{
324 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
328 arm_test_cc(&c32
, cc
);
330 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
331 * properly. The NE/EQ comparisons are also fine with this choice. */
332 c64
->cond
= c32
.cond
;
333 c64
->value
= tcg_temp_new_i64();
334 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
339 static void a64_free_cc(DisasCompare64
*c64
)
341 tcg_temp_free_i64(c64
->value
);
344 static void gen_exception_internal(int excp
)
346 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
348 assert(excp_is_internal(excp
));
349 gen_helper_exception_internal(cpu_env
, tcg_excp
);
350 tcg_temp_free_i32(tcg_excp
);
353 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
355 gen_a64_set_pc_im(pc
);
356 gen_exception_internal(excp
);
357 s
->base
.is_jmp
= DISAS_NORETURN
;
360 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
361 uint32_t syndrome
, uint32_t target_el
)
363 gen_a64_set_pc_im(pc
);
364 gen_exception(excp
, syndrome
, target_el
);
365 s
->base
.is_jmp
= DISAS_NORETURN
;
368 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
372 gen_a64_set_pc_im(s
->pc_curr
);
373 tcg_syn
= tcg_const_i32(syndrome
);
374 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
375 tcg_temp_free_i32(tcg_syn
);
376 s
->base
.is_jmp
= DISAS_NORETURN
;
379 static void gen_step_complete_exception(DisasContext
*s
)
381 /* We just completed step of an insn. Move from Active-not-pending
382 * to Active-pending, and then also take the swstep exception.
383 * This corresponds to making the (IMPDEF) choice to prioritize
384 * swstep exceptions over asynchronous exceptions taken to an exception
385 * level where debug is disabled. This choice has the advantage that
386 * we do not need to maintain internal state corresponding to the
387 * ISV/EX syndrome bits between completion of the step and generation
388 * of the exception, and our syndrome information is always correct.
391 gen_swstep_exception(s
, 1, s
->is_ldex
);
392 s
->base
.is_jmp
= DISAS_NORETURN
;
395 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
397 /* No direct tb linking with singlestep (either QEMU's or the ARM
398 * debug architecture kind) or deterministic io
400 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
401 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
405 #ifndef CONFIG_USER_ONLY
406 /* Only link tbs from inside the same guest page */
407 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
415 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
417 const TranslationBlock
*tb
;
420 if (use_goto_tb(s
, n
, dest
)) {
422 gen_a64_set_pc_im(dest
);
423 tcg_gen_exit_tb(tb
, n
);
424 s
->base
.is_jmp
= DISAS_NORETURN
;
426 gen_a64_set_pc_im(dest
);
428 gen_step_complete_exception(s
);
429 } else if (s
->base
.singlestep_enabled
) {
430 gen_exception_internal(EXCP_DEBUG
);
432 tcg_gen_lookup_and_goto_ptr();
433 s
->base
.is_jmp
= DISAS_NORETURN
;
438 void unallocated_encoding(DisasContext
*s
)
440 /* Unallocated and reserved encodings are uncategorized */
441 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
442 default_exception_el(s
));
445 static void init_tmp_a64_array(DisasContext
*s
)
447 #ifdef CONFIG_DEBUG_TCG
448 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
450 s
->tmp_a64_count
= 0;
453 static void free_tmp_a64(DisasContext
*s
)
456 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
457 tcg_temp_free_i64(s
->tmp_a64
[i
]);
459 init_tmp_a64_array(s
);
462 TCGv_i64
new_tmp_a64(DisasContext
*s
)
464 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
465 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
468 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
470 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
471 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
474 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
476 TCGv_i64 t
= new_tmp_a64(s
);
477 tcg_gen_movi_i64(t
, 0);
482 * Register access functions
484 * These functions are used for directly accessing a register in where
485 * changes to the final register value are likely to be made. If you
486 * need to use a register for temporary calculation (e.g. index type
487 * operations) use the read_* form.
489 * B1.2.1 Register mappings
491 * In instruction register encoding 31 can refer to ZR (zero register) or
492 * the SP (stack pointer) depending on context. In QEMU's case we map SP
493 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
494 * This is the point of the _sp forms.
496 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
499 return new_tmp_a64_zero(s
);
505 /* register access for when 31 == SP */
506 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
511 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
512 * representing the register contents. This TCGv is an auto-freed
513 * temporary so it need not be explicitly freed, and may be modified.
515 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
517 TCGv_i64 v
= new_tmp_a64(s
);
520 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
522 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
525 tcg_gen_movi_i64(v
, 0);
530 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
532 TCGv_i64 v
= new_tmp_a64(s
);
534 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
536 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
541 /* Return the offset into CPUARMState of a slice (from
542 * the least significant end) of FP register Qn (ie
544 * (Note that this is not the same mapping as for A32; see cpu.h)
546 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
548 return vec_reg_offset(s
, regno
, 0, size
);
551 /* Offset of the high half of the 128 bit vector Qn */
552 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
554 return vec_reg_offset(s
, regno
, 1, MO_64
);
557 /* Convenience accessors for reading and writing single and double
558 * FP registers. Writing clears the upper parts of the associated
559 * 128 bit vector register, as required by the architecture.
560 * Note that unlike the GP register accessors, the values returned
561 * by the read functions must be manually freed.
563 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
565 TCGv_i64 v
= tcg_temp_new_i64();
567 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
571 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
573 TCGv_i32 v
= tcg_temp_new_i32();
575 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
579 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
581 TCGv_i32 v
= tcg_temp_new_i32();
583 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
587 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
588 * If SVE is not enabled, then there are only 128 bits in the vector.
590 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
592 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
593 unsigned vsz
= vec_full_reg_size(s
);
595 /* Nop move, with side effect of clearing the tail. */
596 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
599 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
601 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
603 tcg_gen_st_i64(v
, cpu_env
, ofs
);
604 clear_vec_high(s
, false, reg
);
607 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
609 TCGv_i64 tmp
= tcg_temp_new_i64();
611 tcg_gen_extu_i32_i64(tmp
, v
);
612 write_fp_dreg(s
, reg
, tmp
);
613 tcg_temp_free_i64(tmp
);
616 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
617 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
618 GVecGen2Fn
*gvec_fn
, int vece
)
620 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
621 is_q
? 16 : 8, vec_full_reg_size(s
));
624 /* Expand a 2-operand + immediate AdvSIMD vector operation using
625 * an expander function.
627 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
628 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
630 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
631 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
634 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
635 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
636 GVecGen3Fn
*gvec_fn
, int vece
)
638 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
639 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
642 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
643 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
644 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
646 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
647 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
648 is_q
? 16 : 8, vec_full_reg_size(s
));
651 /* Expand a 2-operand operation using an out-of-line helper. */
652 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
653 int rn
, int data
, gen_helper_gvec_2
*fn
)
655 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
656 vec_full_reg_offset(s
, rn
),
657 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
660 /* Expand a 3-operand operation using an out-of-line helper. */
661 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
662 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
664 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
665 vec_full_reg_offset(s
, rn
),
666 vec_full_reg_offset(s
, rm
),
667 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
670 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
671 * an out-of-line helper.
673 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
674 int rm
, bool is_fp16
, int data
,
675 gen_helper_gvec_3_ptr
*fn
)
677 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
678 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
679 vec_full_reg_offset(s
, rn
),
680 vec_full_reg_offset(s
, rm
), fpst
,
681 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
682 tcg_temp_free_ptr(fpst
);
685 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
686 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
687 int rm
, gen_helper_gvec_3_ptr
*fn
)
689 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
691 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
692 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
693 vec_full_reg_offset(s
, rn
),
694 vec_full_reg_offset(s
, rm
), qc_ptr
,
695 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
696 tcg_temp_free_ptr(qc_ptr
);
699 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
700 * than the 32 bit equivalent.
702 static inline void gen_set_NZ64(TCGv_i64 result
)
704 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
705 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
708 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
709 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
712 gen_set_NZ64(result
);
714 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
715 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
717 tcg_gen_movi_i32(cpu_CF
, 0);
718 tcg_gen_movi_i32(cpu_VF
, 0);
721 /* dest = T0 + T1; compute C, N, V and Z flags */
722 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
725 TCGv_i64 result
, flag
, tmp
;
726 result
= tcg_temp_new_i64();
727 flag
= tcg_temp_new_i64();
728 tmp
= tcg_temp_new_i64();
730 tcg_gen_movi_i64(tmp
, 0);
731 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
733 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
735 gen_set_NZ64(result
);
737 tcg_gen_xor_i64(flag
, result
, t0
);
738 tcg_gen_xor_i64(tmp
, t0
, t1
);
739 tcg_gen_andc_i64(flag
, flag
, tmp
);
740 tcg_temp_free_i64(tmp
);
741 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
743 tcg_gen_mov_i64(dest
, result
);
744 tcg_temp_free_i64(result
);
745 tcg_temp_free_i64(flag
);
747 /* 32 bit arithmetic */
748 TCGv_i32 t0_32
= tcg_temp_new_i32();
749 TCGv_i32 t1_32
= tcg_temp_new_i32();
750 TCGv_i32 tmp
= tcg_temp_new_i32();
752 tcg_gen_movi_i32(tmp
, 0);
753 tcg_gen_extrl_i64_i32(t0_32
, t0
);
754 tcg_gen_extrl_i64_i32(t1_32
, t1
);
755 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
756 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
757 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
758 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
759 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
760 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
762 tcg_temp_free_i32(tmp
);
763 tcg_temp_free_i32(t0_32
);
764 tcg_temp_free_i32(t1_32
);
768 /* dest = T0 - T1; compute C, N, V and Z flags */
769 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
772 /* 64 bit arithmetic */
773 TCGv_i64 result
, flag
, tmp
;
775 result
= tcg_temp_new_i64();
776 flag
= tcg_temp_new_i64();
777 tcg_gen_sub_i64(result
, t0
, t1
);
779 gen_set_NZ64(result
);
781 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
782 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
784 tcg_gen_xor_i64(flag
, result
, t0
);
785 tmp
= tcg_temp_new_i64();
786 tcg_gen_xor_i64(tmp
, t0
, t1
);
787 tcg_gen_and_i64(flag
, flag
, tmp
);
788 tcg_temp_free_i64(tmp
);
789 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
790 tcg_gen_mov_i64(dest
, result
);
791 tcg_temp_free_i64(flag
);
792 tcg_temp_free_i64(result
);
794 /* 32 bit arithmetic */
795 TCGv_i32 t0_32
= tcg_temp_new_i32();
796 TCGv_i32 t1_32
= tcg_temp_new_i32();
799 tcg_gen_extrl_i64_i32(t0_32
, t0
);
800 tcg_gen_extrl_i64_i32(t1_32
, t1
);
801 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
802 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
803 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
804 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
805 tmp
= tcg_temp_new_i32();
806 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
807 tcg_temp_free_i32(t0_32
);
808 tcg_temp_free_i32(t1_32
);
809 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
810 tcg_temp_free_i32(tmp
);
811 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
815 /* dest = T0 + T1 + CF; do not compute flags. */
816 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
818 TCGv_i64 flag
= tcg_temp_new_i64();
819 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
820 tcg_gen_add_i64(dest
, t0
, t1
);
821 tcg_gen_add_i64(dest
, dest
, flag
);
822 tcg_temp_free_i64(flag
);
825 tcg_gen_ext32u_i64(dest
, dest
);
829 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
830 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
833 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
834 result
= tcg_temp_new_i64();
835 cf_64
= tcg_temp_new_i64();
836 vf_64
= tcg_temp_new_i64();
837 tmp
= tcg_const_i64(0);
839 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
840 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
841 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
842 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
843 gen_set_NZ64(result
);
845 tcg_gen_xor_i64(vf_64
, result
, t0
);
846 tcg_gen_xor_i64(tmp
, t0
, t1
);
847 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
848 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
850 tcg_gen_mov_i64(dest
, result
);
852 tcg_temp_free_i64(tmp
);
853 tcg_temp_free_i64(vf_64
);
854 tcg_temp_free_i64(cf_64
);
855 tcg_temp_free_i64(result
);
857 TCGv_i32 t0_32
, t1_32
, tmp
;
858 t0_32
= tcg_temp_new_i32();
859 t1_32
= tcg_temp_new_i32();
860 tmp
= tcg_const_i32(0);
862 tcg_gen_extrl_i64_i32(t0_32
, t0
);
863 tcg_gen_extrl_i64_i32(t1_32
, t1
);
864 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
865 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
867 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
868 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
869 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
870 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
871 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
873 tcg_temp_free_i32(tmp
);
874 tcg_temp_free_i32(t1_32
);
875 tcg_temp_free_i32(t0_32
);
880 * Load/Store generators
884 * Store from GPR register to memory.
886 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
887 TCGv_i64 tcg_addr
, int size
, int memidx
,
889 unsigned int iss_srt
,
890 bool iss_sf
, bool iss_ar
)
893 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
898 syn
= syn_data_abort_with_iss(0,
904 0, 0, 0, 0, 0, false);
905 disas_set_insn_syndrome(s
, syn
);
909 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
910 TCGv_i64 tcg_addr
, int size
,
912 unsigned int iss_srt
,
913 bool iss_sf
, bool iss_ar
)
915 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
916 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
920 * Load from memory to GPR register
922 static void do_gpr_ld_memidx(DisasContext
*s
,
923 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
924 int size
, bool is_signed
,
925 bool extend
, int memidx
,
926 bool iss_valid
, unsigned int iss_srt
,
927 bool iss_sf
, bool iss_ar
)
929 MemOp memop
= s
->be_data
+ size
;
937 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
939 if (extend
&& is_signed
) {
941 tcg_gen_ext32u_i64(dest
, dest
);
947 syn
= syn_data_abort_with_iss(0,
953 0, 0, 0, 0, 0, false);
954 disas_set_insn_syndrome(s
, syn
);
958 static void do_gpr_ld(DisasContext
*s
,
959 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
960 int size
, bool is_signed
, bool extend
,
961 bool iss_valid
, unsigned int iss_srt
,
962 bool iss_sf
, bool iss_ar
)
964 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
966 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
970 * Store from FP register to memory
972 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
974 /* This writes the bottom N bits of a 128 bit wide vector to memory */
975 TCGv_i64 tmp
= tcg_temp_new_i64();
976 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
978 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
981 bool be
= s
->be_data
== MO_BE
;
982 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
984 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
985 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
987 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
988 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
990 tcg_temp_free_i64(tcg_hiaddr
);
993 tcg_temp_free_i64(tmp
);
997 * Load from memory to FP register
999 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1001 /* This always zero-extends and writes to a full 128 bit wide vector */
1002 TCGv_i64 tmplo
= tcg_temp_new_i64();
1003 TCGv_i64 tmphi
= NULL
;
1006 MemOp memop
= s
->be_data
+ size
;
1007 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1009 bool be
= s
->be_data
== MO_BE
;
1010 TCGv_i64 tcg_hiaddr
;
1012 tmphi
= tcg_temp_new_i64();
1013 tcg_hiaddr
= tcg_temp_new_i64();
1015 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1016 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1018 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1020 tcg_temp_free_i64(tcg_hiaddr
);
1023 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1024 tcg_temp_free_i64(tmplo
);
1027 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1028 tcg_temp_free_i64(tmphi
);
1030 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1034 * Vector load/store helpers.
1036 * The principal difference between this and a FP load is that we don't
1037 * zero extend as we are filling a partial chunk of the vector register.
1038 * These functions don't support 128 bit loads/stores, which would be
1039 * normal load/store operations.
1041 * The _i32 versions are useful when operating on 32 bit quantities
1042 * (eg for floating point single or using Neon helper functions).
1045 /* Get value of an element within a vector register */
1046 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1047 int element
, MemOp memop
)
1049 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1052 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1055 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1058 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1061 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1064 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1067 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1071 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1074 g_assert_not_reached();
1078 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1079 int element
, MemOp memop
)
1081 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1084 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1087 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1090 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1093 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1097 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1100 g_assert_not_reached();
1104 /* Set value of an element within a vector register */
1105 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1106 int element
, MemOp memop
)
1108 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1111 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1114 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1117 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1120 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1123 g_assert_not_reached();
1127 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1128 int destidx
, int element
, MemOp memop
)
1130 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1133 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1136 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1139 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1142 g_assert_not_reached();
1146 /* Store from vector register to memory */
1147 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1148 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1150 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1152 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1153 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1155 tcg_temp_free_i64(tcg_tmp
);
1158 /* Load from memory to vector register */
1159 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1160 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1162 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1164 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1165 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1167 tcg_temp_free_i64(tcg_tmp
);
1170 /* Check that FP/Neon access is enabled. If it is, return
1171 * true. If not, emit code to generate an appropriate exception,
1172 * and return false; the caller should not emit any code for
1173 * the instruction. Note that this check must happen after all
1174 * unallocated-encoding checks (otherwise the syndrome information
1175 * for the resulting exception will be incorrect).
1177 static bool fp_access_check(DisasContext
*s
)
1179 if (s
->fp_excp_el
) {
1180 assert(!s
->fp_access_checked
);
1181 s
->fp_access_checked
= true;
1183 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1184 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1187 s
->fp_access_checked
= true;
1191 /* Check that SVE access is enabled. If it is, return true.
1192 * If not, emit code to generate an appropriate exception and return false.
1194 bool sve_access_check(DisasContext
*s
)
1196 if (s
->sve_excp_el
) {
1197 assert(!s
->sve_access_checked
);
1198 s
->sve_access_checked
= true;
1200 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1201 syn_sve_access_trap(), s
->sve_excp_el
);
1204 s
->sve_access_checked
= true;
1205 return fp_access_check(s
);
1209 * This utility function is for doing register extension with an
1210 * optional shift. You will likely want to pass a temporary for the
1211 * destination register. See DecodeRegExtend() in the ARM ARM.
1213 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1214 int option
, unsigned int shift
)
1216 int extsize
= extract32(option
, 0, 2);
1217 bool is_signed
= extract32(option
, 2, 1);
1222 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1225 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1228 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1231 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1237 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1240 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1243 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1246 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1252 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1256 static inline void gen_check_sp_alignment(DisasContext
*s
)
1258 /* The AArch64 architecture mandates that (if enabled via PSTATE
1259 * or SCTLR bits) there is a check that SP is 16-aligned on every
1260 * SP-relative load or store (with an exception generated if it is not).
1261 * In line with general QEMU practice regarding misaligned accesses,
1262 * we omit these checks for the sake of guest program performance.
1263 * This function is provided as a hook so we can more easily add these
1264 * checks in future (possibly as a "favour catching guest program bugs
1265 * over speed" user selectable option).
1270 * This provides a simple table based table lookup decoder. It is
1271 * intended to be used when the relevant bits for decode are too
1272 * awkwardly placed and switch/if based logic would be confusing and
1273 * deeply nested. Since it's a linear search through the table, tables
1274 * should be kept small.
1276 * It returns the first handler where insn & mask == pattern, or
1277 * NULL if there is no match.
1278 * The table is terminated by an empty mask (i.e. 0)
1280 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1283 const AArch64DecodeTable
*tptr
= table
;
1285 while (tptr
->mask
) {
1286 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1287 return tptr
->disas_fn
;
1295 * The instruction disassembly implemented here matches
1296 * the instruction encoding classifications in chapter C4
1297 * of the ARM Architecture Reference Manual (DDI0487B_a);
1298 * classification names and decode diagrams here should generally
1299 * match up with those in the manual.
1302 /* Unconditional branch (immediate)
1304 * +----+-----------+-------------------------------------+
1305 * | op | 0 0 1 0 1 | imm26 |
1306 * +----+-----------+-------------------------------------+
1308 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1310 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1312 if (insn
& (1U << 31)) {
1313 /* BL Branch with link */
1314 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1317 /* B Branch / BL Branch with link */
1319 gen_goto_tb(s
, 0, addr
);
1322 /* Compare and branch (immediate)
1323 * 31 30 25 24 23 5 4 0
1324 * +----+-------------+----+---------------------+--------+
1325 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1326 * +----+-------------+----+---------------------+--------+
1328 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1330 unsigned int sf
, op
, rt
;
1332 TCGLabel
*label_match
;
1335 sf
= extract32(insn
, 31, 1);
1336 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1337 rt
= extract32(insn
, 0, 5);
1338 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1340 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1341 label_match
= gen_new_label();
1344 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1345 tcg_cmp
, 0, label_match
);
1347 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1348 gen_set_label(label_match
);
1349 gen_goto_tb(s
, 1, addr
);
1352 /* Test and branch (immediate)
1353 * 31 30 25 24 23 19 18 5 4 0
1354 * +----+-------------+----+-------+-------------+------+
1355 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1356 * +----+-------------+----+-------+-------------+------+
1358 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1360 unsigned int bit_pos
, op
, rt
;
1362 TCGLabel
*label_match
;
1365 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1366 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1367 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1368 rt
= extract32(insn
, 0, 5);
1370 tcg_cmp
= tcg_temp_new_i64();
1371 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1372 label_match
= gen_new_label();
1375 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1376 tcg_cmp
, 0, label_match
);
1377 tcg_temp_free_i64(tcg_cmp
);
1378 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1379 gen_set_label(label_match
);
1380 gen_goto_tb(s
, 1, addr
);
1383 /* Conditional branch (immediate)
1384 * 31 25 24 23 5 4 3 0
1385 * +---------------+----+---------------------+----+------+
1386 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1387 * +---------------+----+---------------------+----+------+
1389 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1394 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1395 unallocated_encoding(s
);
1398 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1399 cond
= extract32(insn
, 0, 4);
1403 /* genuinely conditional branches */
1404 TCGLabel
*label_match
= gen_new_label();
1405 arm_gen_test_cc(cond
, label_match
);
1406 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1407 gen_set_label(label_match
);
1408 gen_goto_tb(s
, 1, addr
);
1410 /* 0xe and 0xf are both "always" conditions */
1411 gen_goto_tb(s
, 0, addr
);
1415 /* HINT instruction group, including various allocated HINTs */
1416 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1417 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1419 unsigned int selector
= crm
<< 3 | op2
;
1422 unallocated_encoding(s
);
1427 case 0b00000: /* NOP */
1429 case 0b00011: /* WFI */
1430 s
->base
.is_jmp
= DISAS_WFI
;
1432 case 0b00001: /* YIELD */
1433 /* When running in MTTCG we don't generate jumps to the yield and
1434 * WFE helpers as it won't affect the scheduling of other vCPUs.
1435 * If we wanted to more completely model WFE/SEV so we don't busy
1436 * spin unnecessarily we would need to do something more involved.
1438 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1439 s
->base
.is_jmp
= DISAS_YIELD
;
1442 case 0b00010: /* WFE */
1443 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1444 s
->base
.is_jmp
= DISAS_WFE
;
1447 case 0b00100: /* SEV */
1448 case 0b00101: /* SEVL */
1449 /* we treat all as NOP at least for now */
1451 case 0b00111: /* XPACLRI */
1452 if (s
->pauth_active
) {
1453 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1456 case 0b01000: /* PACIA1716 */
1457 if (s
->pauth_active
) {
1458 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1461 case 0b01010: /* PACIB1716 */
1462 if (s
->pauth_active
) {
1463 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1466 case 0b01100: /* AUTIA1716 */
1467 if (s
->pauth_active
) {
1468 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1471 case 0b01110: /* AUTIB1716 */
1472 if (s
->pauth_active
) {
1473 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1476 case 0b11000: /* PACIAZ */
1477 if (s
->pauth_active
) {
1478 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1479 new_tmp_a64_zero(s
));
1482 case 0b11001: /* PACIASP */
1483 if (s
->pauth_active
) {
1484 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1487 case 0b11010: /* PACIBZ */
1488 if (s
->pauth_active
) {
1489 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1490 new_tmp_a64_zero(s
));
1493 case 0b11011: /* PACIBSP */
1494 if (s
->pauth_active
) {
1495 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1498 case 0b11100: /* AUTIAZ */
1499 if (s
->pauth_active
) {
1500 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1501 new_tmp_a64_zero(s
));
1504 case 0b11101: /* AUTIASP */
1505 if (s
->pauth_active
) {
1506 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1509 case 0b11110: /* AUTIBZ */
1510 if (s
->pauth_active
) {
1511 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1512 new_tmp_a64_zero(s
));
1515 case 0b11111: /* AUTIBSP */
1516 if (s
->pauth_active
) {
1517 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1521 /* default specified as NOP equivalent */
1526 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1528 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1531 /* CLREX, DSB, DMB, ISB */
1532 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1533 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1538 unallocated_encoding(s
);
1549 case 1: /* MBReqTypes_Reads */
1550 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1552 case 2: /* MBReqTypes_Writes */
1553 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1555 default: /* MBReqTypes_All */
1556 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1562 /* We need to break the TB after this insn to execute
1563 * a self-modified code correctly and also to take
1564 * any pending interrupts immediately.
1567 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1571 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1572 goto do_unallocated
;
1575 * TODO: There is no speculation barrier opcode for TCG;
1576 * MB and end the TB instead.
1578 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1579 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1584 unallocated_encoding(s
);
1589 static void gen_xaflag(void)
1591 TCGv_i32 z
= tcg_temp_new_i32();
1593 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1602 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1603 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1606 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1607 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1609 /* (!C & Z) << 31 -> -(Z & ~C) */
1610 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1611 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1614 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1616 tcg_temp_free_i32(z
);
1619 static void gen_axflag(void)
1621 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1622 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1624 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1625 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1627 tcg_gen_movi_i32(cpu_NF
, 0);
1628 tcg_gen_movi_i32(cpu_VF
, 0);
1631 /* MSR (immediate) - move immediate to processor state field */
1632 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1633 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1636 int op
= op1
<< 3 | op2
;
1638 /* End the TB by default, chaining is ok. */
1639 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1642 case 0x00: /* CFINV */
1643 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1644 goto do_unallocated
;
1646 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1647 s
->base
.is_jmp
= DISAS_NEXT
;
1650 case 0x01: /* XAFlag */
1651 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1652 goto do_unallocated
;
1655 s
->base
.is_jmp
= DISAS_NEXT
;
1658 case 0x02: /* AXFlag */
1659 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1660 goto do_unallocated
;
1663 s
->base
.is_jmp
= DISAS_NEXT
;
1666 case 0x03: /* UAO */
1667 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1668 goto do_unallocated
;
1671 set_pstate_bits(PSTATE_UAO
);
1673 clear_pstate_bits(PSTATE_UAO
);
1675 t1
= tcg_const_i32(s
->current_el
);
1676 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1677 tcg_temp_free_i32(t1
);
1680 case 0x04: /* PAN */
1681 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1682 goto do_unallocated
;
1685 set_pstate_bits(PSTATE_PAN
);
1687 clear_pstate_bits(PSTATE_PAN
);
1689 t1
= tcg_const_i32(s
->current_el
);
1690 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1691 tcg_temp_free_i32(t1
);
1694 case 0x05: /* SPSel */
1695 if (s
->current_el
== 0) {
1696 goto do_unallocated
;
1698 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1699 gen_helper_msr_i_spsel(cpu_env
, t1
);
1700 tcg_temp_free_i32(t1
);
1703 case 0x1e: /* DAIFSet */
1704 t1
= tcg_const_i32(crm
);
1705 gen_helper_msr_i_daifset(cpu_env
, t1
);
1706 tcg_temp_free_i32(t1
);
1709 case 0x1f: /* DAIFClear */
1710 t1
= tcg_const_i32(crm
);
1711 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1712 tcg_temp_free_i32(t1
);
1713 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1714 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1717 case 0x1c: /* TCO */
1718 if (dc_isar_feature(aa64_mte
, s
)) {
1719 /* Full MTE is enabled -- set the TCO bit as directed. */
1721 set_pstate_bits(PSTATE_TCO
);
1723 clear_pstate_bits(PSTATE_TCO
);
1725 t1
= tcg_const_i32(s
->current_el
);
1726 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1727 tcg_temp_free_i32(t1
);
1728 /* Many factors, including TCO, go into MTE_ACTIVE. */
1729 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1730 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1731 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1732 s
->base
.is_jmp
= DISAS_NEXT
;
1734 goto do_unallocated
;
1740 unallocated_encoding(s
);
1745 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1747 TCGv_i32 tmp
= tcg_temp_new_i32();
1748 TCGv_i32 nzcv
= tcg_temp_new_i32();
1750 /* build bit 31, N */
1751 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1752 /* build bit 30, Z */
1753 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1754 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1755 /* build bit 29, C */
1756 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1757 /* build bit 28, V */
1758 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1759 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1760 /* generate result */
1761 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1763 tcg_temp_free_i32(nzcv
);
1764 tcg_temp_free_i32(tmp
);
1767 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1769 TCGv_i32 nzcv
= tcg_temp_new_i32();
1771 /* take NZCV from R[t] */
1772 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1775 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1777 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1778 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1780 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1781 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1783 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1784 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1785 tcg_temp_free_i32(nzcv
);
1788 /* MRS - move from system register
1789 * MSR (register) - move to system register
1792 * These are all essentially the same insn in 'read' and 'write'
1793 * versions, with varying op0 fields.
1795 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1796 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1797 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1799 const ARMCPRegInfo
*ri
;
1802 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1803 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1804 crn
, crm
, op0
, op1
, op2
));
1807 /* Unknown register; this might be a guest error or a QEMU
1808 * unimplemented feature.
1810 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1811 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1812 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1813 unallocated_encoding(s
);
1817 /* Check access permissions */
1818 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1819 unallocated_encoding(s
);
1824 /* Emit code to perform further access permissions checks at
1825 * runtime; this may result in an exception.
1828 TCGv_i32 tcg_syn
, tcg_isread
;
1831 gen_a64_set_pc_im(s
->pc_curr
);
1832 tmpptr
= tcg_const_ptr(ri
);
1833 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1834 tcg_syn
= tcg_const_i32(syndrome
);
1835 tcg_isread
= tcg_const_i32(isread
);
1836 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1837 tcg_temp_free_ptr(tmpptr
);
1838 tcg_temp_free_i32(tcg_syn
);
1839 tcg_temp_free_i32(tcg_isread
);
1840 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1842 * The readfn or writefn might raise an exception;
1843 * synchronize the CPU state in case it does.
1845 gen_a64_set_pc_im(s
->pc_curr
);
1848 /* Handle special cases first */
1849 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1853 tcg_rt
= cpu_reg(s
, rt
);
1855 gen_get_nzcv(tcg_rt
);
1857 gen_set_nzcv(tcg_rt
);
1860 case ARM_CP_CURRENTEL
:
1861 /* Reads as current EL value from pstate, which is
1862 * guaranteed to be constant by the tb flags.
1864 tcg_rt
= cpu_reg(s
, rt
);
1865 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1868 /* Writes clear the aligned block of memory which rt points into. */
1869 if (s
->mte_active
[0]) {
1873 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1874 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1875 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1876 t_desc
= tcg_const_i32(desc
);
1878 tcg_rt
= new_tmp_a64(s
);
1879 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1880 tcg_temp_free_i32(t_desc
);
1882 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1884 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1888 TCGv_i64 clean_addr
, tag
;
1891 * DC_GVA, like DC_ZVA, requires that we supply the original
1892 * pointer for an invalid page. Probe that address first.
1894 tcg_rt
= cpu_reg(s
, rt
);
1895 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1896 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1899 /* Extract the tag from the register to match STZGM. */
1900 tag
= tcg_temp_new_i64();
1901 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1902 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1903 tcg_temp_free_i64(tag
);
1907 case ARM_CP_DC_GZVA
:
1909 TCGv_i64 clean_addr
, tag
;
1911 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1912 tcg_rt
= cpu_reg(s
, rt
);
1913 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1914 gen_helper_dc_zva(cpu_env
, clean_addr
);
1917 /* Extract the tag from the register to match STZGM. */
1918 tag
= tcg_temp_new_i64();
1919 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1920 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1921 tcg_temp_free_i64(tag
);
1928 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1930 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1934 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1938 tcg_rt
= cpu_reg(s
, rt
);
1941 if (ri
->type
& ARM_CP_CONST
) {
1942 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1943 } else if (ri
->readfn
) {
1945 tmpptr
= tcg_const_ptr(ri
);
1946 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1947 tcg_temp_free_ptr(tmpptr
);
1949 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1952 if (ri
->type
& ARM_CP_CONST
) {
1953 /* If not forbidden by access permissions, treat as WI */
1955 } else if (ri
->writefn
) {
1957 tmpptr
= tcg_const_ptr(ri
);
1958 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1959 tcg_temp_free_ptr(tmpptr
);
1961 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1965 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1966 /* I/O operations must end the TB here (whether read or write) */
1967 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1969 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1971 * A write to any coprocessor regiser that ends a TB
1972 * must rebuild the hflags for the next TB.
1974 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1975 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1976 tcg_temp_free_i32(tcg_el
);
1978 * We default to ending the TB on a coprocessor register write,
1979 * but allow this to be suppressed by the register definition
1980 * (usually only necessary to work around guest bugs).
1982 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1987 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1988 * +---------------------+---+-----+-----+-------+-------+-----+------+
1989 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1990 * +---------------------+---+-----+-----+-------+-------+-----+------+
1992 static void disas_system(DisasContext
*s
, uint32_t insn
)
1994 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1995 l
= extract32(insn
, 21, 1);
1996 op0
= extract32(insn
, 19, 2);
1997 op1
= extract32(insn
, 16, 3);
1998 crn
= extract32(insn
, 12, 4);
1999 crm
= extract32(insn
, 8, 4);
2000 op2
= extract32(insn
, 5, 3);
2001 rt
= extract32(insn
, 0, 5);
2004 if (l
|| rt
!= 31) {
2005 unallocated_encoding(s
);
2009 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2010 handle_hint(s
, insn
, op1
, op2
, crm
);
2012 case 3: /* CLREX, DSB, DMB, ISB */
2013 handle_sync(s
, insn
, op1
, op2
, crm
);
2015 case 4: /* MSR (immediate) */
2016 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2019 unallocated_encoding(s
);
2024 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2027 /* Exception generation
2029 * 31 24 23 21 20 5 4 2 1 0
2030 * +-----------------+-----+------------------------+-----+----+
2031 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2032 * +-----------------------+------------------------+----------+
2034 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2036 int opc
= extract32(insn
, 21, 3);
2037 int op2_ll
= extract32(insn
, 0, 5);
2038 int imm16
= extract32(insn
, 5, 16);
2043 /* For SVC, HVC and SMC we advance the single-step state
2044 * machine before taking the exception. This is architecturally
2045 * mandated, to ensure that single-stepping a system call
2046 * instruction works properly.
2051 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2052 syn_aa64_svc(imm16
), default_exception_el(s
));
2055 if (s
->current_el
== 0) {
2056 unallocated_encoding(s
);
2059 /* The pre HVC helper handles cases when HVC gets trapped
2060 * as an undefined insn by runtime configuration.
2062 gen_a64_set_pc_im(s
->pc_curr
);
2063 gen_helper_pre_hvc(cpu_env
);
2065 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2066 syn_aa64_hvc(imm16
), 2);
2069 if (s
->current_el
== 0) {
2070 unallocated_encoding(s
);
2073 gen_a64_set_pc_im(s
->pc_curr
);
2074 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2075 gen_helper_pre_smc(cpu_env
, tmp
);
2076 tcg_temp_free_i32(tmp
);
2078 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2079 syn_aa64_smc(imm16
), 3);
2082 unallocated_encoding(s
);
2088 unallocated_encoding(s
);
2092 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2096 unallocated_encoding(s
);
2099 /* HLT. This has two purposes.
2100 * Architecturally, it is an external halting debug instruction.
2101 * Since QEMU doesn't implement external debug, we treat this as
2102 * it is required for halting debug disabled: it will UNDEF.
2103 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2105 if (semihosting_enabled() && imm16
== 0xf000) {
2106 #ifndef CONFIG_USER_ONLY
2107 /* In system mode, don't allow userspace access to semihosting,
2108 * to provide some semblance of security (and for consistency
2109 * with our 32-bit semihosting).
2111 if (s
->current_el
== 0) {
2112 unsupported_encoding(s
, insn
);
2116 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2118 unsupported_encoding(s
, insn
);
2122 if (op2_ll
< 1 || op2_ll
> 3) {
2123 unallocated_encoding(s
);
2126 /* DCPS1, DCPS2, DCPS3 */
2127 unsupported_encoding(s
, insn
);
2130 unallocated_encoding(s
);
2135 /* Unconditional branch (register)
2136 * 31 25 24 21 20 16 15 10 9 5 4 0
2137 * +---------------+-------+-------+-------+------+-------+
2138 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2139 * +---------------+-------+-------+-------+------+-------+
2141 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2143 unsigned int opc
, op2
, op3
, rn
, op4
;
2144 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2148 opc
= extract32(insn
, 21, 4);
2149 op2
= extract32(insn
, 16, 5);
2150 op3
= extract32(insn
, 10, 6);
2151 rn
= extract32(insn
, 5, 5);
2152 op4
= extract32(insn
, 0, 5);
2155 goto do_unallocated
;
2167 goto do_unallocated
;
2169 dst
= cpu_reg(s
, rn
);
2174 if (!dc_isar_feature(aa64_pauth
, s
)) {
2175 goto do_unallocated
;
2179 if (rn
!= 0x1f || op4
!= 0x1f) {
2180 goto do_unallocated
;
2183 modifier
= cpu_X
[31];
2185 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2187 goto do_unallocated
;
2189 modifier
= new_tmp_a64_zero(s
);
2191 if (s
->pauth_active
) {
2192 dst
= new_tmp_a64(s
);
2194 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2196 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2199 dst
= cpu_reg(s
, rn
);
2204 goto do_unallocated
;
2206 gen_a64_set_pc(s
, dst
);
2207 /* BLR also needs to load return address */
2209 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2215 if (!dc_isar_feature(aa64_pauth
, s
)) {
2216 goto do_unallocated
;
2218 if ((op3
& ~1) != 2) {
2219 goto do_unallocated
;
2221 btype_mod
= opc
& 1;
2222 if (s
->pauth_active
) {
2223 dst
= new_tmp_a64(s
);
2224 modifier
= cpu_reg_sp(s
, op4
);
2226 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2228 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2231 dst
= cpu_reg(s
, rn
);
2233 gen_a64_set_pc(s
, dst
);
2234 /* BLRAA also needs to load return address */
2236 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2241 if (s
->current_el
== 0) {
2242 goto do_unallocated
;
2247 goto do_unallocated
;
2249 dst
= tcg_temp_new_i64();
2250 tcg_gen_ld_i64(dst
, cpu_env
,
2251 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2254 case 2: /* ERETAA */
2255 case 3: /* ERETAB */
2256 if (!dc_isar_feature(aa64_pauth
, s
)) {
2257 goto do_unallocated
;
2259 if (rn
!= 0x1f || op4
!= 0x1f) {
2260 goto do_unallocated
;
2262 dst
= tcg_temp_new_i64();
2263 tcg_gen_ld_i64(dst
, cpu_env
,
2264 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2265 if (s
->pauth_active
) {
2266 modifier
= cpu_X
[31];
2268 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2270 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2276 goto do_unallocated
;
2278 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2282 gen_helper_exception_return(cpu_env
, dst
);
2283 tcg_temp_free_i64(dst
);
2284 /* Must exit loop to check un-masked IRQs */
2285 s
->base
.is_jmp
= DISAS_EXIT
;
2289 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2290 goto do_unallocated
;
2292 unsupported_encoding(s
, insn
);
2298 unallocated_encoding(s
);
2302 switch (btype_mod
) {
2304 if (dc_isar_feature(aa64_bti
, s
)) {
2305 /* BR to {x16,x17} or !guard -> 1, else 3. */
2306 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2311 if (dc_isar_feature(aa64_bti
, s
)) {
2312 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2317 default: /* RET or none of the above. */
2318 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2322 s
->base
.is_jmp
= DISAS_JUMP
;
2325 /* Branches, exception generating and system instructions */
2326 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2328 switch (extract32(insn
, 25, 7)) {
2329 case 0x0a: case 0x0b:
2330 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2331 disas_uncond_b_imm(s
, insn
);
2333 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2334 disas_comp_b_imm(s
, insn
);
2336 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2337 disas_test_b_imm(s
, insn
);
2339 case 0x2a: /* Conditional branch (immediate) */
2340 disas_cond_b_imm(s
, insn
);
2342 case 0x6a: /* Exception generation / System */
2343 if (insn
& (1 << 24)) {
2344 if (extract32(insn
, 22, 2) == 0) {
2345 disas_system(s
, insn
);
2347 unallocated_encoding(s
);
2353 case 0x6b: /* Unconditional branch (register) */
2354 disas_uncond_b_reg(s
, insn
);
2357 unallocated_encoding(s
);
2363 * Load/Store exclusive instructions are implemented by remembering
2364 * the value/address loaded, and seeing if these are the same
2365 * when the store is performed. This is not actually the architecturally
2366 * mandated semantics, but it works for typical guest code sequences
2367 * and avoids having to monitor regular stores.
2369 * The store exclusive uses the atomic cmpxchg primitives to avoid
2370 * races in multi-threaded linux-user and when MTTCG softmmu is
2373 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2374 TCGv_i64 addr
, int size
, bool is_pair
)
2376 int idx
= get_mem_index(s
);
2377 MemOp memop
= s
->be_data
;
2379 g_assert(size
<= 3);
2381 g_assert(size
>= 2);
2383 /* The pair must be single-copy atomic for the doubleword. */
2384 memop
|= MO_64
| MO_ALIGN
;
2385 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2386 if (s
->be_data
== MO_LE
) {
2387 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2388 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2390 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2391 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2394 /* The pair must be single-copy atomic for *each* doubleword, not
2395 the entire quadword, however it must be quadword aligned. */
2397 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2398 memop
| MO_ALIGN_16
);
2400 TCGv_i64 addr2
= tcg_temp_new_i64();
2401 tcg_gen_addi_i64(addr2
, addr
, 8);
2402 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2403 tcg_temp_free_i64(addr2
);
2405 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2406 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2409 memop
|= size
| MO_ALIGN
;
2410 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2411 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2413 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2416 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2417 TCGv_i64 addr
, int size
, int is_pair
)
2419 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2420 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2423 * [addr + datasize] = {Rt2};
2429 * env->exclusive_addr = -1;
2431 TCGLabel
*fail_label
= gen_new_label();
2432 TCGLabel
*done_label
= gen_new_label();
2435 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2437 tmp
= tcg_temp_new_i64();
2440 if (s
->be_data
== MO_LE
) {
2441 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2443 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2445 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2446 cpu_exclusive_val
, tmp
,
2448 MO_64
| MO_ALIGN
| s
->be_data
);
2449 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2450 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2451 if (!HAVE_CMPXCHG128
) {
2452 gen_helper_exit_atomic(cpu_env
);
2453 s
->base
.is_jmp
= DISAS_NORETURN
;
2454 } else if (s
->be_data
== MO_LE
) {
2455 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2460 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2465 } else if (s
->be_data
== MO_LE
) {
2466 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2467 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2469 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2470 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2473 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2474 cpu_reg(s
, rt
), get_mem_index(s
),
2475 size
| MO_ALIGN
| s
->be_data
);
2476 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2478 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2479 tcg_temp_free_i64(tmp
);
2480 tcg_gen_br(done_label
);
2482 gen_set_label(fail_label
);
2483 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2484 gen_set_label(done_label
);
2485 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2488 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2491 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2492 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2493 int memidx
= get_mem_index(s
);
2494 TCGv_i64 clean_addr
;
2497 gen_check_sp_alignment(s
);
2499 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2500 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2501 size
| MO_ALIGN
| s
->be_data
);
2504 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2507 TCGv_i64 s1
= cpu_reg(s
, rs
);
2508 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2509 TCGv_i64 t1
= cpu_reg(s
, rt
);
2510 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2511 TCGv_i64 clean_addr
;
2512 int memidx
= get_mem_index(s
);
2515 gen_check_sp_alignment(s
);
2518 /* This is a single atomic access, despite the "pair". */
2519 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2522 TCGv_i64 cmp
= tcg_temp_new_i64();
2523 TCGv_i64 val
= tcg_temp_new_i64();
2525 if (s
->be_data
== MO_LE
) {
2526 tcg_gen_concat32_i64(val
, t1
, t2
);
2527 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2529 tcg_gen_concat32_i64(val
, t2
, t1
);
2530 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2533 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2534 MO_64
| MO_ALIGN
| s
->be_data
);
2535 tcg_temp_free_i64(val
);
2537 if (s
->be_data
== MO_LE
) {
2538 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2540 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2542 tcg_temp_free_i64(cmp
);
2543 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2544 if (HAVE_CMPXCHG128
) {
2545 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2546 if (s
->be_data
== MO_LE
) {
2547 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2548 clean_addr
, t1
, t2
);
2550 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2551 clean_addr
, t1
, t2
);
2553 tcg_temp_free_i32(tcg_rs
);
2555 gen_helper_exit_atomic(cpu_env
);
2556 s
->base
.is_jmp
= DISAS_NORETURN
;
2559 TCGv_i64 d1
= tcg_temp_new_i64();
2560 TCGv_i64 d2
= tcg_temp_new_i64();
2561 TCGv_i64 a2
= tcg_temp_new_i64();
2562 TCGv_i64 c1
= tcg_temp_new_i64();
2563 TCGv_i64 c2
= tcg_temp_new_i64();
2564 TCGv_i64 zero
= tcg_const_i64(0);
2566 /* Load the two words, in memory order. */
2567 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2568 MO_64
| MO_ALIGN_16
| s
->be_data
);
2569 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2570 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2572 /* Compare the two words, also in memory order. */
2573 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2574 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2575 tcg_gen_and_i64(c2
, c2
, c1
);
2577 /* If compare equal, write back new data, else write back old data. */
2578 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2579 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2580 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2581 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2582 tcg_temp_free_i64(a2
);
2583 tcg_temp_free_i64(c1
);
2584 tcg_temp_free_i64(c2
);
2585 tcg_temp_free_i64(zero
);
2587 /* Write back the data from memory to Rs. */
2588 tcg_gen_mov_i64(s1
, d1
);
2589 tcg_gen_mov_i64(s2
, d2
);
2590 tcg_temp_free_i64(d1
);
2591 tcg_temp_free_i64(d2
);
2595 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2596 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2598 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2600 int opc0
= extract32(opc
, 0, 1);
2604 regsize
= opc0
? 32 : 64;
2606 regsize
= size
== 3 ? 64 : 32;
2608 return regsize
== 64;
2611 /* Load/store exclusive
2613 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2614 * +-----+-------------+----+---+----+------+----+-------+------+------+
2615 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2616 * +-----+-------------+----+---+----+------+----+-------+------+------+
2618 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2619 * L: 0 -> store, 1 -> load
2620 * o2: 0 -> exclusive, 1 -> not
2621 * o1: 0 -> single register, 1 -> register pair
2622 * o0: 1 -> load-acquire/store-release, 0 -> not
2624 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2626 int rt
= extract32(insn
, 0, 5);
2627 int rn
= extract32(insn
, 5, 5);
2628 int rt2
= extract32(insn
, 10, 5);
2629 int rs
= extract32(insn
, 16, 5);
2630 int is_lasr
= extract32(insn
, 15, 1);
2631 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2632 int size
= extract32(insn
, 30, 2);
2633 TCGv_i64 clean_addr
;
2635 switch (o2_L_o1_o0
) {
2636 case 0x0: /* STXR */
2637 case 0x1: /* STLXR */
2639 gen_check_sp_alignment(s
);
2642 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2644 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2645 true, rn
!= 31, size
);
2646 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2649 case 0x4: /* LDXR */
2650 case 0x5: /* LDAXR */
2652 gen_check_sp_alignment(s
);
2654 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2655 false, rn
!= 31, size
);
2657 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2659 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2663 case 0x8: /* STLLR */
2664 if (!dc_isar_feature(aa64_lor
, s
)) {
2667 /* StoreLORelease is the same as Store-Release for QEMU. */
2669 case 0x9: /* STLR */
2670 /* Generate ISS for non-exclusive accesses including LASR. */
2672 gen_check_sp_alignment(s
);
2674 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2675 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2676 true, rn
!= 31, size
);
2677 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2678 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2681 case 0xc: /* LDLAR */
2682 if (!dc_isar_feature(aa64_lor
, s
)) {
2685 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2687 case 0xd: /* LDAR */
2688 /* Generate ISS for non-exclusive accesses including LASR. */
2690 gen_check_sp_alignment(s
);
2692 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2693 false, rn
!= 31, size
);
2694 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2695 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2696 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2699 case 0x2: case 0x3: /* CASP / STXP */
2700 if (size
& 2) { /* STXP / STLXP */
2702 gen_check_sp_alignment(s
);
2705 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2707 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2708 true, rn
!= 31, size
);
2709 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2713 && ((rt
| rs
) & 1) == 0
2714 && dc_isar_feature(aa64_atomics
, s
)) {
2716 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2721 case 0x6: case 0x7: /* CASPA / LDXP */
2722 if (size
& 2) { /* LDXP / LDAXP */
2724 gen_check_sp_alignment(s
);
2726 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2727 false, rn
!= 31, size
);
2729 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2731 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2736 && ((rt
| rs
) & 1) == 0
2737 && dc_isar_feature(aa64_atomics
, s
)) {
2738 /* CASPA / CASPAL */
2739 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2745 case 0xb: /* CASL */
2746 case 0xe: /* CASA */
2747 case 0xf: /* CASAL */
2748 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2749 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2754 unallocated_encoding(s
);
2758 * Load register (literal)
2760 * 31 30 29 27 26 25 24 23 5 4 0
2761 * +-----+-------+---+-----+-------------------+-------+
2762 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2763 * +-----+-------+---+-----+-------------------+-------+
2765 * V: 1 -> vector (simd/fp)
2766 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2767 * 10-> 32 bit signed, 11 -> prefetch
2768 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2770 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2772 int rt
= extract32(insn
, 0, 5);
2773 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2774 bool is_vector
= extract32(insn
, 26, 1);
2775 int opc
= extract32(insn
, 30, 2);
2776 bool is_signed
= false;
2778 TCGv_i64 tcg_rt
, clean_addr
;
2782 unallocated_encoding(s
);
2786 if (!fp_access_check(s
)) {
2791 /* PRFM (literal) : prefetch */
2794 size
= 2 + extract32(opc
, 0, 1);
2795 is_signed
= extract32(opc
, 1, 1);
2798 tcg_rt
= cpu_reg(s
, rt
);
2800 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2802 do_fp_ld(s
, rt
, clean_addr
, size
);
2804 /* Only unsigned 32bit loads target 32bit registers. */
2805 bool iss_sf
= opc
!= 0;
2807 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2808 true, rt
, iss_sf
, false);
2810 tcg_temp_free_i64(clean_addr
);
2814 * LDNP (Load Pair - non-temporal hint)
2815 * LDP (Load Pair - non vector)
2816 * LDPSW (Load Pair Signed Word - non vector)
2817 * STNP (Store Pair - non-temporal hint)
2818 * STP (Store Pair - non vector)
2819 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2820 * LDP (Load Pair of SIMD&FP)
2821 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2822 * STP (Store Pair of SIMD&FP)
2824 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2825 * +-----+-------+---+---+-------+---+-----------------------------+
2826 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2827 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2829 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2831 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2832 * V: 0 -> GPR, 1 -> Vector
2833 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2834 * 10 -> signed offset, 11 -> pre-index
2835 * L: 0 -> Store 1 -> Load
2837 * Rt, Rt2 = GPR or SIMD registers to be stored
2838 * Rn = general purpose register containing address
2839 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2841 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2843 int rt
= extract32(insn
, 0, 5);
2844 int rn
= extract32(insn
, 5, 5);
2845 int rt2
= extract32(insn
, 10, 5);
2846 uint64_t offset
= sextract64(insn
, 15, 7);
2847 int index
= extract32(insn
, 23, 2);
2848 bool is_vector
= extract32(insn
, 26, 1);
2849 bool is_load
= extract32(insn
, 22, 1);
2850 int opc
= extract32(insn
, 30, 2);
2852 bool is_signed
= false;
2853 bool postindex
= false;
2855 bool set_tag
= false;
2857 TCGv_i64 clean_addr
, dirty_addr
;
2862 unallocated_encoding(s
);
2868 } else if (opc
== 1 && !is_load
) {
2870 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2871 unallocated_encoding(s
);
2877 size
= 2 + extract32(opc
, 1, 1);
2878 is_signed
= extract32(opc
, 0, 1);
2879 if (!is_load
&& is_signed
) {
2880 unallocated_encoding(s
);
2886 case 1: /* post-index */
2891 /* signed offset with "non-temporal" hint. Since we don't emulate
2892 * caches we don't care about hints to the cache system about
2893 * data access patterns, and handle this identically to plain
2897 /* There is no non-temporal-hint version of LDPSW */
2898 unallocated_encoding(s
);
2903 case 2: /* signed offset, rn not updated */
2906 case 3: /* pre-index */
2912 if (is_vector
&& !fp_access_check(s
)) {
2916 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2919 gen_check_sp_alignment(s
);
2922 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2924 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2930 * TODO: We could rely on the stores below, at least for
2931 * system mode, if we arrange to add MO_ALIGN_16.
2933 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2934 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2935 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2937 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2941 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2942 (wback
|| rn
!= 31) && !set_tag
,
2947 do_fp_ld(s
, rt
, clean_addr
, size
);
2949 do_fp_st(s
, rt
, clean_addr
, size
);
2951 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2953 do_fp_ld(s
, rt2
, clean_addr
, size
);
2955 do_fp_st(s
, rt2
, clean_addr
, size
);
2958 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2959 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2962 TCGv_i64 tmp
= tcg_temp_new_i64();
2964 /* Do not modify tcg_rt before recognizing any exception
2965 * from the second load.
2967 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2968 false, 0, false, false);
2969 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2970 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2971 false, 0, false, false);
2973 tcg_gen_mov_i64(tcg_rt
, tmp
);
2974 tcg_temp_free_i64(tmp
);
2976 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2977 false, 0, false, false);
2978 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2979 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2980 false, 0, false, false);
2986 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2988 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2993 * Load/store (immediate post-indexed)
2994 * Load/store (immediate pre-indexed)
2995 * Load/store (unscaled immediate)
2997 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2998 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2999 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3000 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3002 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3004 * V = 0 -> non-vector
3005 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3006 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3008 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3014 int rn
= extract32(insn
, 5, 5);
3015 int imm9
= sextract32(insn
, 12, 9);
3016 int idx
= extract32(insn
, 10, 2);
3017 bool is_signed
= false;
3018 bool is_store
= false;
3019 bool is_extended
= false;
3020 bool is_unpriv
= (idx
== 2);
3021 bool iss_valid
= !is_vector
;
3026 TCGv_i64 clean_addr
, dirty_addr
;
3029 size
|= (opc
& 2) << 1;
3030 if (size
> 4 || is_unpriv
) {
3031 unallocated_encoding(s
);
3034 is_store
= ((opc
& 1) == 0);
3035 if (!fp_access_check(s
)) {
3039 if (size
== 3 && opc
== 2) {
3040 /* PRFM - prefetch */
3042 unallocated_encoding(s
);
3047 if (opc
== 3 && size
> 1) {
3048 unallocated_encoding(s
);
3051 is_store
= (opc
== 0);
3052 is_signed
= extract32(opc
, 1, 1);
3053 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3071 g_assert_not_reached();
3075 gen_check_sp_alignment(s
);
3078 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3080 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3083 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3084 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3085 writeback
|| rn
!= 31,
3086 size
, is_unpriv
, memidx
);
3090 do_fp_st(s
, rt
, clean_addr
, size
);
3092 do_fp_ld(s
, rt
, clean_addr
, size
);
3095 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3096 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3099 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3100 iss_valid
, rt
, iss_sf
, false);
3102 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
3103 is_signed
, is_extended
, memidx
,
3104 iss_valid
, rt
, iss_sf
, false);
3109 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3111 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3113 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3118 * Load/store (register offset)
3120 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3121 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3122 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3123 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3126 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3127 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3129 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3130 * opc<0>: 0 -> store, 1 -> load
3131 * V: 1 -> vector/simd
3132 * opt: extend encoding (see DecodeRegExtend)
3133 * S: if S=1 then scale (essentially index by sizeof(size))
3134 * Rt: register to transfer into/out of
3135 * Rn: address register or SP for base
3136 * Rm: offset register or ZR for offset
3138 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3144 int rn
= extract32(insn
, 5, 5);
3145 int shift
= extract32(insn
, 12, 1);
3146 int rm
= extract32(insn
, 16, 5);
3147 int opt
= extract32(insn
, 13, 3);
3148 bool is_signed
= false;
3149 bool is_store
= false;
3150 bool is_extended
= false;
3152 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3154 if (extract32(opt
, 1, 1) == 0) {
3155 unallocated_encoding(s
);
3160 size
|= (opc
& 2) << 1;
3162 unallocated_encoding(s
);
3165 is_store
= !extract32(opc
, 0, 1);
3166 if (!fp_access_check(s
)) {
3170 if (size
== 3 && opc
== 2) {
3171 /* PRFM - prefetch */
3174 if (opc
== 3 && size
> 1) {
3175 unallocated_encoding(s
);
3178 is_store
= (opc
== 0);
3179 is_signed
= extract32(opc
, 1, 1);
3180 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3184 gen_check_sp_alignment(s
);
3186 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3188 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3189 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3191 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3192 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3196 do_fp_st(s
, rt
, clean_addr
, size
);
3198 do_fp_ld(s
, rt
, clean_addr
, size
);
3201 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3202 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3204 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3205 true, rt
, iss_sf
, false);
3207 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3208 is_signed
, is_extended
,
3209 true, rt
, iss_sf
, false);
3215 * Load/store (unsigned immediate)
3217 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3218 * +----+-------+---+-----+-----+------------+-------+------+
3219 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3220 * +----+-------+---+-----+-----+------------+-------+------+
3223 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3224 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3226 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3227 * opc<0>: 0 -> store, 1 -> load
3228 * Rn: base address register (inc SP)
3229 * Rt: target register
3231 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3237 int rn
= extract32(insn
, 5, 5);
3238 unsigned int imm12
= extract32(insn
, 10, 12);
3239 unsigned int offset
;
3241 TCGv_i64 clean_addr
, dirty_addr
;
3244 bool is_signed
= false;
3245 bool is_extended
= false;
3248 size
|= (opc
& 2) << 1;
3250 unallocated_encoding(s
);
3253 is_store
= !extract32(opc
, 0, 1);
3254 if (!fp_access_check(s
)) {
3258 if (size
== 3 && opc
== 2) {
3259 /* PRFM - prefetch */
3262 if (opc
== 3 && size
> 1) {
3263 unallocated_encoding(s
);
3266 is_store
= (opc
== 0);
3267 is_signed
= extract32(opc
, 1, 1);
3268 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3272 gen_check_sp_alignment(s
);
3274 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3275 offset
= imm12
<< size
;
3276 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3277 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3281 do_fp_st(s
, rt
, clean_addr
, size
);
3283 do_fp_ld(s
, rt
, clean_addr
, size
);
3286 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3287 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3289 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3290 true, rt
, iss_sf
, false);
3292 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3293 true, rt
, iss_sf
, false);
3298 /* Atomic memory operations
3300 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3301 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3302 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3303 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3305 * Rt: the result register
3306 * Rn: base address or SP
3307 * Rs: the source register for the operation
3308 * V: vector flag (always 0 as of v8.3)
3312 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3313 int size
, int rt
, bool is_vector
)
3315 int rs
= extract32(insn
, 16, 5);
3316 int rn
= extract32(insn
, 5, 5);
3317 int o3_opc
= extract32(insn
, 12, 4);
3318 bool r
= extract32(insn
, 22, 1);
3319 bool a
= extract32(insn
, 23, 1);
3320 TCGv_i64 tcg_rs
, clean_addr
;
3321 AtomicThreeOpFn
*fn
= NULL
;
3323 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3324 unallocated_encoding(s
);
3328 case 000: /* LDADD */
3329 fn
= tcg_gen_atomic_fetch_add_i64
;
3331 case 001: /* LDCLR */
3332 fn
= tcg_gen_atomic_fetch_and_i64
;
3334 case 002: /* LDEOR */
3335 fn
= tcg_gen_atomic_fetch_xor_i64
;
3337 case 003: /* LDSET */
3338 fn
= tcg_gen_atomic_fetch_or_i64
;
3340 case 004: /* LDSMAX */
3341 fn
= tcg_gen_atomic_fetch_smax_i64
;
3343 case 005: /* LDSMIN */
3344 fn
= tcg_gen_atomic_fetch_smin_i64
;
3346 case 006: /* LDUMAX */
3347 fn
= tcg_gen_atomic_fetch_umax_i64
;
3349 case 007: /* LDUMIN */
3350 fn
= tcg_gen_atomic_fetch_umin_i64
;
3353 fn
= tcg_gen_atomic_xchg_i64
;
3355 case 014: /* LDAPR, LDAPRH, LDAPRB */
3356 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3357 rs
!= 31 || a
!= 1 || r
!= 0) {
3358 unallocated_encoding(s
);
3363 unallocated_encoding(s
);
3368 gen_check_sp_alignment(s
);
3370 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3372 if (o3_opc
== 014) {
3374 * LDAPR* are a special case because they are a simple load, not a
3375 * fetch-and-do-something op.
3376 * The architectural consistency requirements here are weaker than
3377 * full load-acquire (we only need "load-acquire processor consistent"),
3378 * but we choose to implement them as full LDAQ.
3380 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3381 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3382 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3386 tcg_rs
= read_cpu_reg(s
, rs
, true);
3388 if (o3_opc
== 1) { /* LDCLR */
3389 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3392 /* The tcg atomic primitives are all full barriers. Therefore we
3393 * can ignore the Acquire and Release bits of this instruction.
3395 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3396 s
->be_data
| size
| MO_ALIGN
);
3400 * PAC memory operations
3402 * 31 30 27 26 24 22 21 12 11 10 5 0
3403 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3404 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3405 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3407 * Rt: the result register
3408 * Rn: base address or SP
3409 * V: vector flag (always 0 as of v8.3)
3410 * M: clear for key DA, set for key DB
3411 * W: pre-indexing flag
3414 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3415 int size
, int rt
, bool is_vector
)
3417 int rn
= extract32(insn
, 5, 5);
3418 bool is_wback
= extract32(insn
, 11, 1);
3419 bool use_key_a
= !extract32(insn
, 23, 1);
3421 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3423 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3424 unallocated_encoding(s
);
3429 gen_check_sp_alignment(s
);
3431 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3433 if (s
->pauth_active
) {
3435 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3436 new_tmp_a64_zero(s
));
3438 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3439 new_tmp_a64_zero(s
));
3443 /* Form the 10-bit signed, scaled offset. */
3444 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3445 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3446 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3448 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3449 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3450 is_wback
|| rn
!= 31, size
);
3452 tcg_rt
= cpu_reg(s
, rt
);
3453 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3454 /* extend */ false, /* iss_valid */ !is_wback
,
3455 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3458 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3463 * LDAPR/STLR (unscaled immediate)
3465 * 31 30 24 22 21 12 10 5 0
3466 * +------+-------------+-----+---+--------+-----+----+-----+
3467 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3468 * +------+-------------+-----+---+--------+-----+----+-----+
3470 * Rt: source or destination register
3472 * imm9: unscaled immediate offset
3473 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3474 * size: size of load/store
3476 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3478 int rt
= extract32(insn
, 0, 5);
3479 int rn
= extract32(insn
, 5, 5);
3480 int offset
= sextract32(insn
, 12, 9);
3481 int opc
= extract32(insn
, 22, 2);
3482 int size
= extract32(insn
, 30, 2);
3483 TCGv_i64 clean_addr
, dirty_addr
;
3484 bool is_store
= false;
3485 bool is_signed
= false;
3486 bool extend
= false;
3489 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3490 unallocated_encoding(s
);
3495 case 0: /* STLURB */
3498 case 1: /* LDAPUR* */
3500 case 2: /* LDAPURS* 64-bit variant */
3502 unallocated_encoding(s
);
3507 case 3: /* LDAPURS* 32-bit variant */
3509 unallocated_encoding(s
);
3513 extend
= true; /* zero-extend 32->64 after signed load */
3516 g_assert_not_reached();
3519 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3522 gen_check_sp_alignment(s
);
3525 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3526 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3527 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3530 /* Store-Release semantics */
3531 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3532 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3535 * Load-AcquirePC semantics; we implement as the slightly more
3536 * restrictive Load-Acquire.
3538 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3539 true, rt
, iss_sf
, true);
3540 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3544 /* Load/store register (all forms) */
3545 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3547 int rt
= extract32(insn
, 0, 5);
3548 int opc
= extract32(insn
, 22, 2);
3549 bool is_vector
= extract32(insn
, 26, 1);
3550 int size
= extract32(insn
, 30, 2);
3552 switch (extract32(insn
, 24, 2)) {
3554 if (extract32(insn
, 21, 1) == 0) {
3555 /* Load/store register (unscaled immediate)
3556 * Load/store immediate pre/post-indexed
3557 * Load/store register unprivileged
3559 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3562 switch (extract32(insn
, 10, 2)) {
3564 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3567 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3570 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3575 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3578 unallocated_encoding(s
);
3581 /* AdvSIMD load/store multiple structures
3583 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3584 * +---+---+---------------+---+-------------+--------+------+------+------+
3585 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3586 * +---+---+---------------+---+-------------+--------+------+------+------+
3588 * AdvSIMD load/store multiple structures (post-indexed)
3590 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3591 * +---+---+---------------+---+---+---------+--------+------+------+------+
3592 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3593 * +---+---+---------------+---+---+---------+--------+------+------+------+
3595 * Rt: first (or only) SIMD&FP register to be transferred
3596 * Rn: base address or SP
3597 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3599 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3601 int rt
= extract32(insn
, 0, 5);
3602 int rn
= extract32(insn
, 5, 5);
3603 int rm
= extract32(insn
, 16, 5);
3604 int size
= extract32(insn
, 10, 2);
3605 int opcode
= extract32(insn
, 12, 4);
3606 bool is_store
= !extract32(insn
, 22, 1);
3607 bool is_postidx
= extract32(insn
, 23, 1);
3608 bool is_q
= extract32(insn
, 30, 1);
3609 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3610 MemOp endian
= s
->be_data
;
3612 int total
; /* total bytes */
3613 int elements
; /* elements per vector */
3614 int rpt
; /* num iterations */
3615 int selem
; /* structure elements */
3618 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3619 unallocated_encoding(s
);
3623 if (!is_postidx
&& rm
!= 0) {
3624 unallocated_encoding(s
);
3628 /* From the shared decode logic */
3659 unallocated_encoding(s
);
3663 if (size
== 3 && !is_q
&& selem
!= 1) {
3665 unallocated_encoding(s
);
3669 if (!fp_access_check(s
)) {
3674 gen_check_sp_alignment(s
);
3677 /* For our purposes, bytes are always little-endian. */
3682 total
= rpt
* selem
* (is_q
? 16 : 8);
3683 tcg_rn
= cpu_reg_sp(s
, rn
);
3686 * Issue the MTE check vs the logical repeat count, before we
3687 * promote consecutive little-endian elements below.
3689 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3693 * Consecutive little-endian elements from a single register
3694 * can be promoted to a larger little-endian operation.
3696 if (selem
== 1 && endian
== MO_LE
) {
3699 elements
= (is_q
? 16 : 8) >> size
;
3701 tcg_ebytes
= tcg_const_i64(1 << size
);
3702 for (r
= 0; r
< rpt
; r
++) {
3704 for (e
= 0; e
< elements
; e
++) {
3706 for (xs
= 0; xs
< selem
; xs
++) {
3707 int tt
= (rt
+ r
+ xs
) % 32;
3709 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3711 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3713 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3717 tcg_temp_free_i64(tcg_ebytes
);
3720 /* For non-quad operations, setting a slice of the low
3721 * 64 bits of the register clears the high 64 bits (in
3722 * the ARM ARM pseudocode this is implicit in the fact
3723 * that 'rval' is a 64 bit wide variable).
3724 * For quad operations, we might still need to zero the
3727 for (r
= 0; r
< rpt
* selem
; r
++) {
3728 int tt
= (rt
+ r
) % 32;
3729 clear_vec_high(s
, is_q
, tt
);
3735 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3737 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3742 /* AdvSIMD load/store single structure
3744 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3745 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3746 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3747 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3749 * AdvSIMD load/store single structure (post-indexed)
3751 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3752 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3753 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3754 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3756 * Rt: first (or only) SIMD&FP register to be transferred
3757 * Rn: base address or SP
3758 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3759 * index = encoded in Q:S:size dependent on size
3761 * lane_size = encoded in R, opc
3762 * transfer width = encoded in opc, S, size
3764 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3766 int rt
= extract32(insn
, 0, 5);
3767 int rn
= extract32(insn
, 5, 5);
3768 int rm
= extract32(insn
, 16, 5);
3769 int size
= extract32(insn
, 10, 2);
3770 int S
= extract32(insn
, 12, 1);
3771 int opc
= extract32(insn
, 13, 3);
3772 int R
= extract32(insn
, 21, 1);
3773 int is_load
= extract32(insn
, 22, 1);
3774 int is_postidx
= extract32(insn
, 23, 1);
3775 int is_q
= extract32(insn
, 30, 1);
3777 int scale
= extract32(opc
, 1, 2);
3778 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3779 bool replicate
= false;
3780 int index
= is_q
<< 3 | S
<< 2 | size
;
3782 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3784 if (extract32(insn
, 31, 1)) {
3785 unallocated_encoding(s
);
3788 if (!is_postidx
&& rm
!= 0) {
3789 unallocated_encoding(s
);
3795 if (!is_load
|| S
) {
3796 unallocated_encoding(s
);
3805 if (extract32(size
, 0, 1)) {
3806 unallocated_encoding(s
);
3812 if (extract32(size
, 1, 1)) {
3813 unallocated_encoding(s
);
3816 if (!extract32(size
, 0, 1)) {
3820 unallocated_encoding(s
);
3828 g_assert_not_reached();
3831 if (!fp_access_check(s
)) {
3836 gen_check_sp_alignment(s
);
3839 total
= selem
<< scale
;
3840 tcg_rn
= cpu_reg_sp(s
, rn
);
3842 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3845 tcg_ebytes
= tcg_const_i64(1 << scale
);
3846 for (xs
= 0; xs
< selem
; xs
++) {
3848 /* Load and replicate to all elements */
3849 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3851 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3852 get_mem_index(s
), s
->be_data
+ scale
);
3853 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3854 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3856 tcg_temp_free_i64(tcg_tmp
);
3858 /* Load/store one element per register */
3860 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3862 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3865 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3868 tcg_temp_free_i64(tcg_ebytes
);
3872 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3874 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3880 * Load/Store memory tags
3882 * 31 30 29 24 22 21 12 10 5 0
3883 * +-----+-------------+-----+---+------+-----+------+------+
3884 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3885 * +-----+-------------+-----+---+------+-----+------+------+
3887 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3889 int rt
= extract32(insn
, 0, 5);
3890 int rn
= extract32(insn
, 5, 5);
3891 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3892 int op2
= extract32(insn
, 10, 2);
3893 int op1
= extract32(insn
, 22, 2);
3894 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3896 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3898 /* We checked insn bits [29:24,21] in the caller. */
3899 if (extract32(insn
, 30, 2) != 3) {
3900 goto do_unallocated
;
3904 * @index is a tri-state variable which has 3 states:
3905 * < 0 : post-index, writeback
3906 * = 0 : signed offset
3907 * > 0 : pre-index, writeback
3916 if (s
->current_el
== 0 || offset
!= 0) {
3917 goto do_unallocated
;
3919 is_mult
= is_zero
= true;
3939 if (s
->current_el
== 0 || offset
!= 0) {
3940 goto do_unallocated
;
3948 is_pair
= is_zero
= true;
3952 if (s
->current_el
== 0 || offset
!= 0) {
3953 goto do_unallocated
;
3955 is_mult
= is_load
= true;
3961 unallocated_encoding(s
);
3966 ? !dc_isar_feature(aa64_mte
, s
)
3967 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
3968 goto do_unallocated
;
3972 gen_check_sp_alignment(s
);
3975 addr
= read_cpu_reg_sp(s
, rn
, true);
3977 /* pre-index or signed offset */
3978 tcg_gen_addi_i64(addr
, addr
, offset
);
3982 tcg_rt
= cpu_reg(s
, rt
);
3985 int size
= 4 << s
->dcz_blocksize
;
3988 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
3991 * The non-tags portion of STZGM is mostly like DC_ZVA,
3992 * except the alignment happens before the access.
3994 clean_addr
= clean_data_tbi(s
, addr
);
3995 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
3996 gen_helper_dc_zva(cpu_env
, clean_addr
);
3997 } else if (s
->ata
) {
3999 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4001 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4004 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4005 int size
= 4 << GMID_EL1_BS
;
4007 clean_addr
= clean_data_tbi(s
, addr
);
4008 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4009 gen_probe_access(s
, clean_addr
, acc
, size
);
4012 /* The result tags are zeros. */
4013 tcg_gen_movi_i64(tcg_rt
, 0);
4020 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4021 tcg_rt
= cpu_reg(s
, rt
);
4023 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4025 clean_addr
= clean_data_tbi(s
, addr
);
4026 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4027 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4030 tcg_rt
= cpu_reg_sp(s
, rt
);
4033 * For STG and ST2G, we need to check alignment and probe memory.
4034 * TODO: For STZG and STZ2G, we could rely on the stores below,
4035 * at least for system mode; user-only won't enforce alignment.
4038 gen_helper_st2g_stub(cpu_env
, addr
);
4040 gen_helper_stg_stub(cpu_env
, addr
);
4042 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4044 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4046 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4050 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4052 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4058 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4059 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4060 int mem_index
= get_mem_index(s
);
4061 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4063 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4064 MO_Q
| MO_ALIGN_16
);
4065 for (i
= 8; i
< n
; i
+= 8) {
4066 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4067 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4069 tcg_temp_free_i64(tcg_zero
);
4073 /* pre-index or post-index */
4076 tcg_gen_addi_i64(addr
, addr
, offset
);
4078 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4082 /* Loads and stores */
4083 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4085 switch (extract32(insn
, 24, 6)) {
4086 case 0x08: /* Load/store exclusive */
4087 disas_ldst_excl(s
, insn
);
4089 case 0x18: case 0x1c: /* Load register (literal) */
4090 disas_ld_lit(s
, insn
);
4092 case 0x28: case 0x29:
4093 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4094 disas_ldst_pair(s
, insn
);
4096 case 0x38: case 0x39:
4097 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4098 disas_ldst_reg(s
, insn
);
4100 case 0x0c: /* AdvSIMD load/store multiple structures */
4101 disas_ldst_multiple_struct(s
, insn
);
4103 case 0x0d: /* AdvSIMD load/store single structure */
4104 disas_ldst_single_struct(s
, insn
);
4107 if (extract32(insn
, 21, 1) != 0) {
4108 disas_ldst_tag(s
, insn
);
4109 } else if (extract32(insn
, 10, 2) == 0) {
4110 disas_ldst_ldapr_stlr(s
, insn
);
4112 unallocated_encoding(s
);
4116 unallocated_encoding(s
);
4121 /* PC-rel. addressing
4122 * 31 30 29 28 24 23 5 4 0
4123 * +----+-------+-----------+-------------------+------+
4124 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4125 * +----+-------+-----------+-------------------+------+
4127 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4129 unsigned int page
, rd
;
4133 page
= extract32(insn
, 31, 1);
4134 /* SignExtend(immhi:immlo) -> offset */
4135 offset
= sextract64(insn
, 5, 19);
4136 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4137 rd
= extract32(insn
, 0, 5);
4141 /* ADRP (page based) */
4146 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4150 * Add/subtract (immediate)
4152 * 31 30 29 28 23 22 21 10 9 5 4 0
4153 * +--+--+--+-------------+--+-------------+-----+-----+
4154 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4155 * +--+--+--+-------------+--+-------------+-----+-----+
4157 * sf: 0 -> 32bit, 1 -> 64bit
4158 * op: 0 -> add , 1 -> sub
4160 * sh: 1 -> LSL imm by 12
4162 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4164 int rd
= extract32(insn
, 0, 5);
4165 int rn
= extract32(insn
, 5, 5);
4166 uint64_t imm
= extract32(insn
, 10, 12);
4167 bool shift
= extract32(insn
, 22, 1);
4168 bool setflags
= extract32(insn
, 29, 1);
4169 bool sub_op
= extract32(insn
, 30, 1);
4170 bool is_64bit
= extract32(insn
, 31, 1);
4172 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4173 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4174 TCGv_i64 tcg_result
;
4180 tcg_result
= tcg_temp_new_i64();
4183 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4185 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4188 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4190 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4192 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4194 tcg_temp_free_i64(tcg_imm
);
4198 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4200 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4203 tcg_temp_free_i64(tcg_result
);
4207 * Add/subtract (immediate, with tags)
4209 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4210 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4211 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4212 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4214 * op: 0 -> add, 1 -> sub
4216 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4218 int rd
= extract32(insn
, 0, 5);
4219 int rn
= extract32(insn
, 5, 5);
4220 int uimm4
= extract32(insn
, 10, 4);
4221 int uimm6
= extract32(insn
, 16, 6);
4222 bool sub_op
= extract32(insn
, 30, 1);
4223 TCGv_i64 tcg_rn
, tcg_rd
;
4226 /* Test all of sf=1, S=0, o2=0, o3=0. */
4227 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4228 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4229 unallocated_encoding(s
);
4233 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4238 tcg_rn
= cpu_reg_sp(s
, rn
);
4239 tcg_rd
= cpu_reg_sp(s
, rd
);
4242 TCGv_i32 offset
= tcg_const_i32(imm
);
4243 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4245 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4246 tcg_temp_free_i32(tag_offset
);
4247 tcg_temp_free_i32(offset
);
4249 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4250 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4254 /* The input should be a value in the bottom e bits (with higher
4255 * bits zero); returns that value replicated into every element
4256 * of size e in a 64 bit integer.
4258 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4268 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4269 static inline uint64_t bitmask64(unsigned int length
)
4271 assert(length
> 0 && length
<= 64);
4272 return ~0ULL >> (64 - length
);
4275 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4276 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4277 * value (ie should cause a guest UNDEF exception), and true if they are
4278 * valid, in which case the decoded bit pattern is written to result.
4280 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4281 unsigned int imms
, unsigned int immr
)
4284 unsigned e
, levels
, s
, r
;
4287 assert(immn
< 2 && imms
< 64 && immr
< 64);
4289 /* The bit patterns we create here are 64 bit patterns which
4290 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4291 * 64 bits each. Each element contains the same value: a run
4292 * of between 1 and e-1 non-zero bits, rotated within the
4293 * element by between 0 and e-1 bits.
4295 * The element size and run length are encoded into immn (1 bit)
4296 * and imms (6 bits) as follows:
4297 * 64 bit elements: immn = 1, imms = <length of run - 1>
4298 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4299 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4300 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4301 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4302 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4303 * Notice that immn = 0, imms = 11111x is the only combination
4304 * not covered by one of the above options; this is reserved.
4305 * Further, <length of run - 1> all-ones is a reserved pattern.
4307 * In all cases the rotation is by immr % e (and immr is 6 bits).
4310 /* First determine the element size */
4311 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4313 /* This is the immn == 0, imms == 0x11111x case */
4323 /* <length of run - 1> mustn't be all-ones. */
4327 /* Create the value of one element: s+1 set bits rotated
4328 * by r within the element (which is e bits wide)...
4330 mask
= bitmask64(s
+ 1);
4332 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4333 mask
&= bitmask64(e
);
4335 /* ...then replicate the element over the whole 64 bit value */
4336 mask
= bitfield_replicate(mask
, e
);
4341 /* Logical (immediate)
4342 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4343 * +----+-----+-------------+---+------+------+------+------+
4344 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4345 * +----+-----+-------------+---+------+------+------+------+
4347 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4349 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4350 TCGv_i64 tcg_rd
, tcg_rn
;
4352 bool is_and
= false;
4354 sf
= extract32(insn
, 31, 1);
4355 opc
= extract32(insn
, 29, 2);
4356 is_n
= extract32(insn
, 22, 1);
4357 immr
= extract32(insn
, 16, 6);
4358 imms
= extract32(insn
, 10, 6);
4359 rn
= extract32(insn
, 5, 5);
4360 rd
= extract32(insn
, 0, 5);
4363 unallocated_encoding(s
);
4367 if (opc
== 0x3) { /* ANDS */
4368 tcg_rd
= cpu_reg(s
, rd
);
4370 tcg_rd
= cpu_reg_sp(s
, rd
);
4372 tcg_rn
= cpu_reg(s
, rn
);
4374 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4375 /* some immediate field values are reserved */
4376 unallocated_encoding(s
);
4381 wmask
&= 0xffffffff;
4385 case 0x3: /* ANDS */
4387 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4391 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4394 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4397 assert(FALSE
); /* must handle all above */
4401 if (!sf
&& !is_and
) {
4402 /* zero extend final result; we know we can skip this for AND
4403 * since the immediate had the high 32 bits clear.
4405 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4408 if (opc
== 3) { /* ANDS */
4409 gen_logic_CC(sf
, tcg_rd
);
4414 * Move wide (immediate)
4416 * 31 30 29 28 23 22 21 20 5 4 0
4417 * +--+-----+-------------+-----+----------------+------+
4418 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4419 * +--+-----+-------------+-----+----------------+------+
4421 * sf: 0 -> 32 bit, 1 -> 64 bit
4422 * opc: 00 -> N, 10 -> Z, 11 -> K
4423 * hw: shift/16 (0,16, and sf only 32, 48)
4425 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4427 int rd
= extract32(insn
, 0, 5);
4428 uint64_t imm
= extract32(insn
, 5, 16);
4429 int sf
= extract32(insn
, 31, 1);
4430 int opc
= extract32(insn
, 29, 2);
4431 int pos
= extract32(insn
, 21, 2) << 4;
4432 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4435 if (!sf
&& (pos
>= 32)) {
4436 unallocated_encoding(s
);
4450 tcg_gen_movi_i64(tcg_rd
, imm
);
4453 tcg_imm
= tcg_const_i64(imm
);
4454 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4455 tcg_temp_free_i64(tcg_imm
);
4457 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4461 unallocated_encoding(s
);
4467 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4468 * +----+-----+-------------+---+------+------+------+------+
4469 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4470 * +----+-----+-------------+---+------+------+------+------+
4472 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4474 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4475 TCGv_i64 tcg_rd
, tcg_tmp
;
4477 sf
= extract32(insn
, 31, 1);
4478 opc
= extract32(insn
, 29, 2);
4479 n
= extract32(insn
, 22, 1);
4480 ri
= extract32(insn
, 16, 6);
4481 si
= extract32(insn
, 10, 6);
4482 rn
= extract32(insn
, 5, 5);
4483 rd
= extract32(insn
, 0, 5);
4484 bitsize
= sf
? 64 : 32;
4486 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4487 unallocated_encoding(s
);
4491 tcg_rd
= cpu_reg(s
, rd
);
4493 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4494 to be smaller than bitsize, we'll never reference data outside the
4495 low 32-bits anyway. */
4496 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4498 /* Recognize simple(r) extractions. */
4500 /* Wd<s-r:0> = Wn<s:r> */
4501 len
= (si
- ri
) + 1;
4502 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4503 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4505 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4506 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4509 /* opc == 1, BFXIL fall through to deposit */
4510 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4513 /* Handle the ri > si case with a deposit
4514 * Wd<32+s-r,32-r> = Wn<s:0>
4517 pos
= (bitsize
- ri
) & (bitsize
- 1);
4520 if (opc
== 0 && len
< ri
) {
4521 /* SBFM: sign extend the destination field from len to fill
4522 the balance of the word. Let the deposit below insert all
4523 of those sign bits. */
4524 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4528 if (opc
== 1) { /* BFM, BFXIL */
4529 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4531 /* SBFM or UBFM: We start with zero, and we haven't modified
4532 any bits outside bitsize, therefore the zero-extension
4533 below is unneeded. */
4534 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4539 if (!sf
) { /* zero extend final result */
4540 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4545 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4546 * +----+------+-------------+---+----+------+--------+------+------+
4547 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4548 * +----+------+-------------+---+----+------+--------+------+------+
4550 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4552 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4554 sf
= extract32(insn
, 31, 1);
4555 n
= extract32(insn
, 22, 1);
4556 rm
= extract32(insn
, 16, 5);
4557 imm
= extract32(insn
, 10, 6);
4558 rn
= extract32(insn
, 5, 5);
4559 rd
= extract32(insn
, 0, 5);
4560 op21
= extract32(insn
, 29, 2);
4561 op0
= extract32(insn
, 21, 1);
4562 bitsize
= sf
? 64 : 32;
4564 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4565 unallocated_encoding(s
);
4567 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4569 tcg_rd
= cpu_reg(s
, rd
);
4571 if (unlikely(imm
== 0)) {
4572 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4573 * so an extract from bit 0 is a special case.
4576 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4578 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4581 tcg_rm
= cpu_reg(s
, rm
);
4582 tcg_rn
= cpu_reg(s
, rn
);
4585 /* Specialization to ROR happens in EXTRACT2. */
4586 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4588 TCGv_i32 t0
= tcg_temp_new_i32();
4590 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4592 tcg_gen_rotri_i32(t0
, t0
, imm
);
4594 TCGv_i32 t1
= tcg_temp_new_i32();
4595 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4596 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4597 tcg_temp_free_i32(t1
);
4599 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4600 tcg_temp_free_i32(t0
);
4606 /* Data processing - immediate */
4607 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4609 switch (extract32(insn
, 23, 6)) {
4610 case 0x20: case 0x21: /* PC-rel. addressing */
4611 disas_pc_rel_adr(s
, insn
);
4613 case 0x22: /* Add/subtract (immediate) */
4614 disas_add_sub_imm(s
, insn
);
4616 case 0x23: /* Add/subtract (immediate, with tags) */
4617 disas_add_sub_imm_with_tags(s
, insn
);
4619 case 0x24: /* Logical (immediate) */
4620 disas_logic_imm(s
, insn
);
4622 case 0x25: /* Move wide (immediate) */
4623 disas_movw_imm(s
, insn
);
4625 case 0x26: /* Bitfield */
4626 disas_bitfield(s
, insn
);
4628 case 0x27: /* Extract */
4629 disas_extract(s
, insn
);
4632 unallocated_encoding(s
);
4637 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4638 * Note that it is the caller's responsibility to ensure that the
4639 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4640 * mandated semantics for out of range shifts.
4642 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4643 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4645 switch (shift_type
) {
4646 case A64_SHIFT_TYPE_LSL
:
4647 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4649 case A64_SHIFT_TYPE_LSR
:
4650 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4652 case A64_SHIFT_TYPE_ASR
:
4654 tcg_gen_ext32s_i64(dst
, src
);
4656 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4658 case A64_SHIFT_TYPE_ROR
:
4660 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4663 t0
= tcg_temp_new_i32();
4664 t1
= tcg_temp_new_i32();
4665 tcg_gen_extrl_i64_i32(t0
, src
);
4666 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4667 tcg_gen_rotr_i32(t0
, t0
, t1
);
4668 tcg_gen_extu_i32_i64(dst
, t0
);
4669 tcg_temp_free_i32(t0
);
4670 tcg_temp_free_i32(t1
);
4674 assert(FALSE
); /* all shift types should be handled */
4678 if (!sf
) { /* zero extend final result */
4679 tcg_gen_ext32u_i64(dst
, dst
);
4683 /* Shift a TCGv src by immediate, put result in dst.
4684 * The shift amount must be in range (this should always be true as the
4685 * relevant instructions will UNDEF on bad shift immediates).
4687 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4688 enum a64_shift_type shift_type
, unsigned int shift_i
)
4690 assert(shift_i
< (sf
? 64 : 32));
4693 tcg_gen_mov_i64(dst
, src
);
4695 TCGv_i64 shift_const
;
4697 shift_const
= tcg_const_i64(shift_i
);
4698 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4699 tcg_temp_free_i64(shift_const
);
4703 /* Logical (shifted register)
4704 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4705 * +----+-----+-----------+-------+---+------+--------+------+------+
4706 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4707 * +----+-----+-----------+-------+---+------+--------+------+------+
4709 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4711 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4712 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4714 sf
= extract32(insn
, 31, 1);
4715 opc
= extract32(insn
, 29, 2);
4716 shift_type
= extract32(insn
, 22, 2);
4717 invert
= extract32(insn
, 21, 1);
4718 rm
= extract32(insn
, 16, 5);
4719 shift_amount
= extract32(insn
, 10, 6);
4720 rn
= extract32(insn
, 5, 5);
4721 rd
= extract32(insn
, 0, 5);
4723 if (!sf
&& (shift_amount
& (1 << 5))) {
4724 unallocated_encoding(s
);
4728 tcg_rd
= cpu_reg(s
, rd
);
4730 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4731 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4732 * register-register MOV and MVN, so it is worth special casing.
4734 tcg_rm
= cpu_reg(s
, rm
);
4736 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4738 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4742 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4744 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4750 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4753 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4756 tcg_rn
= cpu_reg(s
, rn
);
4758 switch (opc
| (invert
<< 2)) {
4761 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4764 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4767 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4771 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4774 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4777 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4785 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4789 gen_logic_CC(sf
, tcg_rd
);
4794 * Add/subtract (extended register)
4796 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4797 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4798 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4799 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4801 * sf: 0 -> 32bit, 1 -> 64bit
4802 * op: 0 -> add , 1 -> sub
4805 * option: extension type (see DecodeRegExtend)
4806 * imm3: optional shift to Rm
4808 * Rd = Rn + LSL(extend(Rm), amount)
4810 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4812 int rd
= extract32(insn
, 0, 5);
4813 int rn
= extract32(insn
, 5, 5);
4814 int imm3
= extract32(insn
, 10, 3);
4815 int option
= extract32(insn
, 13, 3);
4816 int rm
= extract32(insn
, 16, 5);
4817 int opt
= extract32(insn
, 22, 2);
4818 bool setflags
= extract32(insn
, 29, 1);
4819 bool sub_op
= extract32(insn
, 30, 1);
4820 bool sf
= extract32(insn
, 31, 1);
4822 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4824 TCGv_i64 tcg_result
;
4826 if (imm3
> 4 || opt
!= 0) {
4827 unallocated_encoding(s
);
4831 /* non-flag setting ops may use SP */
4833 tcg_rd
= cpu_reg_sp(s
, rd
);
4835 tcg_rd
= cpu_reg(s
, rd
);
4837 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4839 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4840 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4842 tcg_result
= tcg_temp_new_i64();
4846 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4848 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4852 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4854 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4859 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4861 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4864 tcg_temp_free_i64(tcg_result
);
4868 * Add/subtract (shifted register)
4870 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4871 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4872 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4873 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4875 * sf: 0 -> 32bit, 1 -> 64bit
4876 * op: 0 -> add , 1 -> sub
4878 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4879 * imm6: Shift amount to apply to Rm before the add/sub
4881 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4883 int rd
= extract32(insn
, 0, 5);
4884 int rn
= extract32(insn
, 5, 5);
4885 int imm6
= extract32(insn
, 10, 6);
4886 int rm
= extract32(insn
, 16, 5);
4887 int shift_type
= extract32(insn
, 22, 2);
4888 bool setflags
= extract32(insn
, 29, 1);
4889 bool sub_op
= extract32(insn
, 30, 1);
4890 bool sf
= extract32(insn
, 31, 1);
4892 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4893 TCGv_i64 tcg_rn
, tcg_rm
;
4894 TCGv_i64 tcg_result
;
4896 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4897 unallocated_encoding(s
);
4901 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4902 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4904 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4906 tcg_result
= tcg_temp_new_i64();
4910 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4912 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4916 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4918 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4923 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4925 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4928 tcg_temp_free_i64(tcg_result
);
4931 /* Data-processing (3 source)
4933 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4934 * +--+------+-----------+------+------+----+------+------+------+
4935 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4936 * +--+------+-----------+------+------+----+------+------+------+
4938 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4940 int rd
= extract32(insn
, 0, 5);
4941 int rn
= extract32(insn
, 5, 5);
4942 int ra
= extract32(insn
, 10, 5);
4943 int rm
= extract32(insn
, 16, 5);
4944 int op_id
= (extract32(insn
, 29, 3) << 4) |
4945 (extract32(insn
, 21, 3) << 1) |
4946 extract32(insn
, 15, 1);
4947 bool sf
= extract32(insn
, 31, 1);
4948 bool is_sub
= extract32(op_id
, 0, 1);
4949 bool is_high
= extract32(op_id
, 2, 1);
4950 bool is_signed
= false;
4955 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4957 case 0x42: /* SMADDL */
4958 case 0x43: /* SMSUBL */
4959 case 0x44: /* SMULH */
4962 case 0x0: /* MADD (32bit) */
4963 case 0x1: /* MSUB (32bit) */
4964 case 0x40: /* MADD (64bit) */
4965 case 0x41: /* MSUB (64bit) */
4966 case 0x4a: /* UMADDL */
4967 case 0x4b: /* UMSUBL */
4968 case 0x4c: /* UMULH */
4971 unallocated_encoding(s
);
4976 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4977 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4978 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4979 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4982 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4984 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4987 tcg_temp_free_i64(low_bits
);
4991 tcg_op1
= tcg_temp_new_i64();
4992 tcg_op2
= tcg_temp_new_i64();
4993 tcg_tmp
= tcg_temp_new_i64();
4996 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4997 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5000 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5001 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5003 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5004 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5008 if (ra
== 31 && !is_sub
) {
5009 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5010 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5012 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5014 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5016 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5021 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5024 tcg_temp_free_i64(tcg_op1
);
5025 tcg_temp_free_i64(tcg_op2
);
5026 tcg_temp_free_i64(tcg_tmp
);
5029 /* Add/subtract (with carry)
5030 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5031 * +--+--+--+------------------------+------+-------------+------+-----+
5032 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5033 * +--+--+--+------------------------+------+-------------+------+-----+
5036 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5038 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5039 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5041 sf
= extract32(insn
, 31, 1);
5042 op
= extract32(insn
, 30, 1);
5043 setflags
= extract32(insn
, 29, 1);
5044 rm
= extract32(insn
, 16, 5);
5045 rn
= extract32(insn
, 5, 5);
5046 rd
= extract32(insn
, 0, 5);
5048 tcg_rd
= cpu_reg(s
, rd
);
5049 tcg_rn
= cpu_reg(s
, rn
);
5052 tcg_y
= new_tmp_a64(s
);
5053 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5055 tcg_y
= cpu_reg(s
, rm
);
5059 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5061 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5066 * Rotate right into flags
5067 * 31 30 29 21 15 10 5 4 0
5068 * +--+--+--+-----------------+--------+-----------+------+--+------+
5069 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5070 * +--+--+--+-----------------+--------+-----------+------+--+------+
5072 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5074 int mask
= extract32(insn
, 0, 4);
5075 int o2
= extract32(insn
, 4, 1);
5076 int rn
= extract32(insn
, 5, 5);
5077 int imm6
= extract32(insn
, 15, 6);
5078 int sf_op_s
= extract32(insn
, 29, 3);
5082 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5083 unallocated_encoding(s
);
5087 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5088 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5090 nzcv
= tcg_temp_new_i32();
5091 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5093 if (mask
& 8) { /* N */
5094 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5096 if (mask
& 4) { /* Z */
5097 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5098 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5100 if (mask
& 2) { /* C */
5101 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5103 if (mask
& 1) { /* V */
5104 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5107 tcg_temp_free_i32(nzcv
);
5111 * Evaluate into flags
5112 * 31 30 29 21 15 14 10 5 4 0
5113 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5114 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5115 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5117 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5119 int o3_mask
= extract32(insn
, 0, 5);
5120 int rn
= extract32(insn
, 5, 5);
5121 int o2
= extract32(insn
, 15, 6);
5122 int sz
= extract32(insn
, 14, 1);
5123 int sf_op_s
= extract32(insn
, 29, 3);
5127 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5128 !dc_isar_feature(aa64_condm_4
, s
)) {
5129 unallocated_encoding(s
);
5132 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5134 tmp
= tcg_temp_new_i32();
5135 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5136 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5137 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5138 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5139 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5140 tcg_temp_free_i32(tmp
);
5143 /* Conditional compare (immediate / register)
5144 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5145 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5146 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5147 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5150 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5152 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5153 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5154 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5157 if (!extract32(insn
, 29, 1)) {
5158 unallocated_encoding(s
);
5161 if (insn
& (1 << 10 | 1 << 4)) {
5162 unallocated_encoding(s
);
5165 sf
= extract32(insn
, 31, 1);
5166 op
= extract32(insn
, 30, 1);
5167 is_imm
= extract32(insn
, 11, 1);
5168 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5169 cond
= extract32(insn
, 12, 4);
5170 rn
= extract32(insn
, 5, 5);
5171 nzcv
= extract32(insn
, 0, 4);
5173 /* Set T0 = !COND. */
5174 tcg_t0
= tcg_temp_new_i32();
5175 arm_test_cc(&c
, cond
);
5176 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5179 /* Load the arguments for the new comparison. */
5181 tcg_y
= new_tmp_a64(s
);
5182 tcg_gen_movi_i64(tcg_y
, y
);
5184 tcg_y
= cpu_reg(s
, y
);
5186 tcg_rn
= cpu_reg(s
, rn
);
5188 /* Set the flags for the new comparison. */
5189 tcg_tmp
= tcg_temp_new_i64();
5191 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5193 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5195 tcg_temp_free_i64(tcg_tmp
);
5197 /* If COND was false, force the flags to #nzcv. Compute two masks
5198 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5199 * For tcg hosts that support ANDC, we can make do with just T1.
5200 * In either case, allow the tcg optimizer to delete any unused mask.
5202 tcg_t1
= tcg_temp_new_i32();
5203 tcg_t2
= tcg_temp_new_i32();
5204 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5205 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5207 if (nzcv
& 8) { /* N */
5208 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5210 if (TCG_TARGET_HAS_andc_i32
) {
5211 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5213 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5216 if (nzcv
& 4) { /* Z */
5217 if (TCG_TARGET_HAS_andc_i32
) {
5218 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5220 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5223 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5225 if (nzcv
& 2) { /* C */
5226 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5228 if (TCG_TARGET_HAS_andc_i32
) {
5229 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5231 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5234 if (nzcv
& 1) { /* V */
5235 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5237 if (TCG_TARGET_HAS_andc_i32
) {
5238 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5240 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5243 tcg_temp_free_i32(tcg_t0
);
5244 tcg_temp_free_i32(tcg_t1
);
5245 tcg_temp_free_i32(tcg_t2
);
5248 /* Conditional select
5249 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5250 * +----+----+---+-----------------+------+------+-----+------+------+
5251 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5252 * +----+----+---+-----------------+------+------+-----+------+------+
5254 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5256 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5257 TCGv_i64 tcg_rd
, zero
;
5260 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5261 /* S == 1 or op2<1> == 1 */
5262 unallocated_encoding(s
);
5265 sf
= extract32(insn
, 31, 1);
5266 else_inv
= extract32(insn
, 30, 1);
5267 rm
= extract32(insn
, 16, 5);
5268 cond
= extract32(insn
, 12, 4);
5269 else_inc
= extract32(insn
, 10, 1);
5270 rn
= extract32(insn
, 5, 5);
5271 rd
= extract32(insn
, 0, 5);
5273 tcg_rd
= cpu_reg(s
, rd
);
5275 a64_test_cc(&c
, cond
);
5276 zero
= tcg_const_i64(0);
5278 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5280 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5282 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5285 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5286 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5287 if (else_inv
&& else_inc
) {
5288 tcg_gen_neg_i64(t_false
, t_false
);
5289 } else if (else_inv
) {
5290 tcg_gen_not_i64(t_false
, t_false
);
5291 } else if (else_inc
) {
5292 tcg_gen_addi_i64(t_false
, t_false
, 1);
5294 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5297 tcg_temp_free_i64(zero
);
5301 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5305 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5306 unsigned int rn
, unsigned int rd
)
5308 TCGv_i64 tcg_rd
, tcg_rn
;
5309 tcg_rd
= cpu_reg(s
, rd
);
5310 tcg_rn
= cpu_reg(s
, rn
);
5313 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5315 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5316 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5317 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5318 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5319 tcg_temp_free_i32(tcg_tmp32
);
5323 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5324 unsigned int rn
, unsigned int rd
)
5326 TCGv_i64 tcg_rd
, tcg_rn
;
5327 tcg_rd
= cpu_reg(s
, rd
);
5328 tcg_rn
= cpu_reg(s
, rn
);
5331 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5333 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5334 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5335 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5336 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5337 tcg_temp_free_i32(tcg_tmp32
);
5341 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5342 unsigned int rn
, unsigned int rd
)
5344 TCGv_i64 tcg_rd
, tcg_rn
;
5345 tcg_rd
= cpu_reg(s
, rd
);
5346 tcg_rn
= cpu_reg(s
, rn
);
5349 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5351 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5352 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5353 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5354 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5355 tcg_temp_free_i32(tcg_tmp32
);
5359 /* REV with sf==1, opcode==3 ("REV64") */
5360 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5361 unsigned int rn
, unsigned int rd
)
5364 unallocated_encoding(s
);
5367 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5370 /* REV with sf==0, opcode==2
5371 * REV32 (sf==1, opcode==2)
5373 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5374 unsigned int rn
, unsigned int rd
)
5376 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5379 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5380 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5382 /* bswap32_i64 requires zero high word */
5383 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
5384 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
5385 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
5386 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
5387 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5389 tcg_temp_free_i64(tcg_tmp
);
5391 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
5392 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5396 /* REV16 (opcode==1) */
5397 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5398 unsigned int rn
, unsigned int rd
)
5400 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5401 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5402 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5403 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5405 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5406 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5407 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5408 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5409 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5411 tcg_temp_free_i64(mask
);
5412 tcg_temp_free_i64(tcg_tmp
);
5415 /* Data-processing (1 source)
5416 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5417 * +----+---+---+-----------------+---------+--------+------+------+
5418 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5419 * +----+---+---+-----------------+---------+--------+------+------+
5421 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5423 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5426 if (extract32(insn
, 29, 1)) {
5427 unallocated_encoding(s
);
5431 sf
= extract32(insn
, 31, 1);
5432 opcode
= extract32(insn
, 10, 6);
5433 opcode2
= extract32(insn
, 16, 5);
5434 rn
= extract32(insn
, 5, 5);
5435 rd
= extract32(insn
, 0, 5);
5437 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5439 switch (MAP(sf
, opcode2
, opcode
)) {
5440 case MAP(0, 0x00, 0x00): /* RBIT */
5441 case MAP(1, 0x00, 0x00):
5442 handle_rbit(s
, sf
, rn
, rd
);
5444 case MAP(0, 0x00, 0x01): /* REV16 */
5445 case MAP(1, 0x00, 0x01):
5446 handle_rev16(s
, sf
, rn
, rd
);
5448 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5449 case MAP(1, 0x00, 0x02):
5450 handle_rev32(s
, sf
, rn
, rd
);
5452 case MAP(1, 0x00, 0x03): /* REV64 */
5453 handle_rev64(s
, sf
, rn
, rd
);
5455 case MAP(0, 0x00, 0x04): /* CLZ */
5456 case MAP(1, 0x00, 0x04):
5457 handle_clz(s
, sf
, rn
, rd
);
5459 case MAP(0, 0x00, 0x05): /* CLS */
5460 case MAP(1, 0x00, 0x05):
5461 handle_cls(s
, sf
, rn
, rd
);
5463 case MAP(1, 0x01, 0x00): /* PACIA */
5464 if (s
->pauth_active
) {
5465 tcg_rd
= cpu_reg(s
, rd
);
5466 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5467 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5468 goto do_unallocated
;
5471 case MAP(1, 0x01, 0x01): /* PACIB */
5472 if (s
->pauth_active
) {
5473 tcg_rd
= cpu_reg(s
, rd
);
5474 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5475 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5476 goto do_unallocated
;
5479 case MAP(1, 0x01, 0x02): /* PACDA */
5480 if (s
->pauth_active
) {
5481 tcg_rd
= cpu_reg(s
, rd
);
5482 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5483 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5484 goto do_unallocated
;
5487 case MAP(1, 0x01, 0x03): /* PACDB */
5488 if (s
->pauth_active
) {
5489 tcg_rd
= cpu_reg(s
, rd
);
5490 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5491 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5492 goto do_unallocated
;
5495 case MAP(1, 0x01, 0x04): /* AUTIA */
5496 if (s
->pauth_active
) {
5497 tcg_rd
= cpu_reg(s
, rd
);
5498 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5499 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5500 goto do_unallocated
;
5503 case MAP(1, 0x01, 0x05): /* AUTIB */
5504 if (s
->pauth_active
) {
5505 tcg_rd
= cpu_reg(s
, rd
);
5506 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5507 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5508 goto do_unallocated
;
5511 case MAP(1, 0x01, 0x06): /* AUTDA */
5512 if (s
->pauth_active
) {
5513 tcg_rd
= cpu_reg(s
, rd
);
5514 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5515 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5516 goto do_unallocated
;
5519 case MAP(1, 0x01, 0x07): /* AUTDB */
5520 if (s
->pauth_active
) {
5521 tcg_rd
= cpu_reg(s
, rd
);
5522 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5523 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5524 goto do_unallocated
;
5527 case MAP(1, 0x01, 0x08): /* PACIZA */
5528 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5529 goto do_unallocated
;
5530 } else if (s
->pauth_active
) {
5531 tcg_rd
= cpu_reg(s
, rd
);
5532 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5535 case MAP(1, 0x01, 0x09): /* PACIZB */
5536 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5537 goto do_unallocated
;
5538 } else if (s
->pauth_active
) {
5539 tcg_rd
= cpu_reg(s
, rd
);
5540 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5543 case MAP(1, 0x01, 0x0a): /* PACDZA */
5544 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5545 goto do_unallocated
;
5546 } else if (s
->pauth_active
) {
5547 tcg_rd
= cpu_reg(s
, rd
);
5548 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5551 case MAP(1, 0x01, 0x0b): /* PACDZB */
5552 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5553 goto do_unallocated
;
5554 } else if (s
->pauth_active
) {
5555 tcg_rd
= cpu_reg(s
, rd
);
5556 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5559 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5560 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5561 goto do_unallocated
;
5562 } else if (s
->pauth_active
) {
5563 tcg_rd
= cpu_reg(s
, rd
);
5564 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5567 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5568 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5569 goto do_unallocated
;
5570 } else if (s
->pauth_active
) {
5571 tcg_rd
= cpu_reg(s
, rd
);
5572 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5575 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5576 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5577 goto do_unallocated
;
5578 } else if (s
->pauth_active
) {
5579 tcg_rd
= cpu_reg(s
, rd
);
5580 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5583 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5584 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5585 goto do_unallocated
;
5586 } else if (s
->pauth_active
) {
5587 tcg_rd
= cpu_reg(s
, rd
);
5588 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5591 case MAP(1, 0x01, 0x10): /* XPACI */
5592 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5593 goto do_unallocated
;
5594 } else if (s
->pauth_active
) {
5595 tcg_rd
= cpu_reg(s
, rd
);
5596 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5599 case MAP(1, 0x01, 0x11): /* XPACD */
5600 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5601 goto do_unallocated
;
5602 } else if (s
->pauth_active
) {
5603 tcg_rd
= cpu_reg(s
, rd
);
5604 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5609 unallocated_encoding(s
);
5616 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5617 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5619 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5620 tcg_rd
= cpu_reg(s
, rd
);
5622 if (!sf
&& is_signed
) {
5623 tcg_n
= new_tmp_a64(s
);
5624 tcg_m
= new_tmp_a64(s
);
5625 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5626 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5628 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5629 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5633 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5635 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5638 if (!sf
) { /* zero extend final result */
5639 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5643 /* LSLV, LSRV, ASRV, RORV */
5644 static void handle_shift_reg(DisasContext
*s
,
5645 enum a64_shift_type shift_type
, unsigned int sf
,
5646 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5648 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5649 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5650 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5652 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5653 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5654 tcg_temp_free_i64(tcg_shift
);
5657 /* CRC32[BHWX], CRC32C[BHWX] */
5658 static void handle_crc32(DisasContext
*s
,
5659 unsigned int sf
, unsigned int sz
, bool crc32c
,
5660 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5662 TCGv_i64 tcg_acc
, tcg_val
;
5665 if (!dc_isar_feature(aa64_crc32
, s
)
5666 || (sf
== 1 && sz
!= 3)
5667 || (sf
== 0 && sz
== 3)) {
5668 unallocated_encoding(s
);
5673 tcg_val
= cpu_reg(s
, rm
);
5687 g_assert_not_reached();
5689 tcg_val
= new_tmp_a64(s
);
5690 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5693 tcg_acc
= cpu_reg(s
, rn
);
5694 tcg_bytes
= tcg_const_i32(1 << sz
);
5697 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5699 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5702 tcg_temp_free_i32(tcg_bytes
);
5705 /* Data-processing (2 source)
5706 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5707 * +----+---+---+-----------------+------+--------+------+------+
5708 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5709 * +----+---+---+-----------------+------+--------+------+------+
5711 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5713 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5714 sf
= extract32(insn
, 31, 1);
5715 setflag
= extract32(insn
, 29, 1);
5716 rm
= extract32(insn
, 16, 5);
5717 opcode
= extract32(insn
, 10, 6);
5718 rn
= extract32(insn
, 5, 5);
5719 rd
= extract32(insn
, 0, 5);
5721 if (setflag
&& opcode
!= 0) {
5722 unallocated_encoding(s
);
5727 case 0: /* SUBP(S) */
5728 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5729 goto do_unallocated
;
5731 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5733 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5734 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5735 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5736 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5737 tcg_d
= cpu_reg(s
, rd
);
5740 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5742 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5747 handle_div(s
, false, sf
, rm
, rn
, rd
);
5750 handle_div(s
, true, sf
, rm
, rn
, rd
);
5753 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5754 goto do_unallocated
;
5757 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5758 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5760 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5765 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5766 goto do_unallocated
;
5768 TCGv_i64 t1
= tcg_const_i64(1);
5769 TCGv_i64 t2
= tcg_temp_new_i64();
5771 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5772 tcg_gen_shl_i64(t1
, t1
, t2
);
5773 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5775 tcg_temp_free_i64(t1
);
5776 tcg_temp_free_i64(t2
);
5780 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5783 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5786 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5789 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5791 case 12: /* PACGA */
5792 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5793 goto do_unallocated
;
5795 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5796 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5805 case 23: /* CRC32 */
5807 int sz
= extract32(opcode
, 0, 2);
5808 bool crc32c
= extract32(opcode
, 2, 1);
5809 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5814 unallocated_encoding(s
);
5820 * Data processing - register
5821 * 31 30 29 28 25 21 20 16 10 0
5822 * +--+---+--+---+-------+-----+-------+-------+---------+
5823 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5824 * +--+---+--+---+-------+-----+-------+-------+---------+
5826 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5828 int op0
= extract32(insn
, 30, 1);
5829 int op1
= extract32(insn
, 28, 1);
5830 int op2
= extract32(insn
, 21, 4);
5831 int op3
= extract32(insn
, 10, 6);
5836 /* Add/sub (extended register) */
5837 disas_add_sub_ext_reg(s
, insn
);
5839 /* Add/sub (shifted register) */
5840 disas_add_sub_reg(s
, insn
);
5843 /* Logical (shifted register) */
5844 disas_logic_reg(s
, insn
);
5852 case 0x00: /* Add/subtract (with carry) */
5853 disas_adc_sbc(s
, insn
);
5856 case 0x01: /* Rotate right into flags */
5858 disas_rotate_right_into_flags(s
, insn
);
5861 case 0x02: /* Evaluate into flags */
5865 disas_evaluate_into_flags(s
, insn
);
5869 goto do_unallocated
;
5873 case 0x2: /* Conditional compare */
5874 disas_cc(s
, insn
); /* both imm and reg forms */
5877 case 0x4: /* Conditional select */
5878 disas_cond_select(s
, insn
);
5881 case 0x6: /* Data-processing */
5882 if (op0
) { /* (1 source) */
5883 disas_data_proc_1src(s
, insn
);
5884 } else { /* (2 source) */
5885 disas_data_proc_2src(s
, insn
);
5888 case 0x8 ... 0xf: /* (3 source) */
5889 disas_data_proc_3src(s
, insn
);
5894 unallocated_encoding(s
);
5899 static void handle_fp_compare(DisasContext
*s
, int size
,
5900 unsigned int rn
, unsigned int rm
,
5901 bool cmp_with_zero
, bool signal_all_nans
)
5903 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5904 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5906 if (size
== MO_64
) {
5907 TCGv_i64 tcg_vn
, tcg_vm
;
5909 tcg_vn
= read_fp_dreg(s
, rn
);
5910 if (cmp_with_zero
) {
5911 tcg_vm
= tcg_const_i64(0);
5913 tcg_vm
= read_fp_dreg(s
, rm
);
5915 if (signal_all_nans
) {
5916 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5918 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5920 tcg_temp_free_i64(tcg_vn
);
5921 tcg_temp_free_i64(tcg_vm
);
5923 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5924 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5926 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5927 if (cmp_with_zero
) {
5928 tcg_gen_movi_i32(tcg_vm
, 0);
5930 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5935 if (signal_all_nans
) {
5936 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5938 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5942 if (signal_all_nans
) {
5943 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5945 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5949 g_assert_not_reached();
5952 tcg_temp_free_i32(tcg_vn
);
5953 tcg_temp_free_i32(tcg_vm
);
5956 tcg_temp_free_ptr(fpst
);
5958 gen_set_nzcv(tcg_flags
);
5960 tcg_temp_free_i64(tcg_flags
);
5963 /* Floating point compare
5964 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5965 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5966 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5967 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5969 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5971 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5974 mos
= extract32(insn
, 29, 3);
5975 type
= extract32(insn
, 22, 2);
5976 rm
= extract32(insn
, 16, 5);
5977 op
= extract32(insn
, 14, 2);
5978 rn
= extract32(insn
, 5, 5);
5979 opc
= extract32(insn
, 3, 2);
5980 op2r
= extract32(insn
, 0, 3);
5982 if (mos
|| op
|| op2r
) {
5983 unallocated_encoding(s
);
5996 if (dc_isar_feature(aa64_fp16
, s
)) {
6001 unallocated_encoding(s
);
6005 if (!fp_access_check(s
)) {
6009 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6012 /* Floating point conditional compare
6013 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6014 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6015 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6016 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6018 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6020 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6022 TCGLabel
*label_continue
= NULL
;
6025 mos
= extract32(insn
, 29, 3);
6026 type
= extract32(insn
, 22, 2);
6027 rm
= extract32(insn
, 16, 5);
6028 cond
= extract32(insn
, 12, 4);
6029 rn
= extract32(insn
, 5, 5);
6030 op
= extract32(insn
, 4, 1);
6031 nzcv
= extract32(insn
, 0, 4);
6034 unallocated_encoding(s
);
6047 if (dc_isar_feature(aa64_fp16
, s
)) {
6052 unallocated_encoding(s
);
6056 if (!fp_access_check(s
)) {
6060 if (cond
< 0x0e) { /* not always */
6061 TCGLabel
*label_match
= gen_new_label();
6062 label_continue
= gen_new_label();
6063 arm_gen_test_cc(cond
, label_match
);
6065 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6066 gen_set_nzcv(tcg_flags
);
6067 tcg_temp_free_i64(tcg_flags
);
6068 tcg_gen_br(label_continue
);
6069 gen_set_label(label_match
);
6072 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6075 gen_set_label(label_continue
);
6079 /* Floating point conditional select
6080 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6081 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6082 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6083 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6085 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6087 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6088 TCGv_i64 t_true
, t_false
, t_zero
;
6092 mos
= extract32(insn
, 29, 3);
6093 type
= extract32(insn
, 22, 2);
6094 rm
= extract32(insn
, 16, 5);
6095 cond
= extract32(insn
, 12, 4);
6096 rn
= extract32(insn
, 5, 5);
6097 rd
= extract32(insn
, 0, 5);
6100 unallocated_encoding(s
);
6113 if (dc_isar_feature(aa64_fp16
, s
)) {
6118 unallocated_encoding(s
);
6122 if (!fp_access_check(s
)) {
6126 /* Zero extend sreg & hreg inputs to 64 bits now. */
6127 t_true
= tcg_temp_new_i64();
6128 t_false
= tcg_temp_new_i64();
6129 read_vec_element(s
, t_true
, rn
, 0, sz
);
6130 read_vec_element(s
, t_false
, rm
, 0, sz
);
6132 a64_test_cc(&c
, cond
);
6133 t_zero
= tcg_const_i64(0);
6134 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6135 tcg_temp_free_i64(t_zero
);
6136 tcg_temp_free_i64(t_false
);
6139 /* Note that sregs & hregs write back zeros to the high bits,
6140 and we've already done the zero-extension. */
6141 write_fp_dreg(s
, rd
, t_true
);
6142 tcg_temp_free_i64(t_true
);
6145 /* Floating-point data-processing (1 source) - half precision */
6146 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6148 TCGv_ptr fpst
= NULL
;
6149 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6150 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6153 case 0x0: /* FMOV */
6154 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6156 case 0x1: /* FABS */
6157 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6159 case 0x2: /* FNEG */
6160 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6162 case 0x3: /* FSQRT */
6163 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6164 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6166 case 0x8: /* FRINTN */
6167 case 0x9: /* FRINTP */
6168 case 0xa: /* FRINTM */
6169 case 0xb: /* FRINTZ */
6170 case 0xc: /* FRINTA */
6172 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6173 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6175 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6176 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6178 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6179 tcg_temp_free_i32(tcg_rmode
);
6182 case 0xe: /* FRINTX */
6183 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6184 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6186 case 0xf: /* FRINTI */
6187 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6188 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6194 write_fp_sreg(s
, rd
, tcg_res
);
6197 tcg_temp_free_ptr(fpst
);
6199 tcg_temp_free_i32(tcg_op
);
6200 tcg_temp_free_i32(tcg_res
);
6203 /* Floating-point data-processing (1 source) - single precision */
6204 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6206 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6207 TCGv_i32 tcg_op
, tcg_res
;
6211 tcg_op
= read_fp_sreg(s
, rn
);
6212 tcg_res
= tcg_temp_new_i32();
6215 case 0x0: /* FMOV */
6216 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6218 case 0x1: /* FABS */
6219 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6221 case 0x2: /* FNEG */
6222 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6224 case 0x3: /* FSQRT */
6225 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6227 case 0x8: /* FRINTN */
6228 case 0x9: /* FRINTP */
6229 case 0xa: /* FRINTM */
6230 case 0xb: /* FRINTZ */
6231 case 0xc: /* FRINTA */
6232 rmode
= arm_rmode_to_sf(opcode
& 7);
6233 gen_fpst
= gen_helper_rints
;
6235 case 0xe: /* FRINTX */
6236 gen_fpst
= gen_helper_rints_exact
;
6238 case 0xf: /* FRINTI */
6239 gen_fpst
= gen_helper_rints
;
6241 case 0x10: /* FRINT32Z */
6242 rmode
= float_round_to_zero
;
6243 gen_fpst
= gen_helper_frint32_s
;
6245 case 0x11: /* FRINT32X */
6246 gen_fpst
= gen_helper_frint32_s
;
6248 case 0x12: /* FRINT64Z */
6249 rmode
= float_round_to_zero
;
6250 gen_fpst
= gen_helper_frint64_s
;
6252 case 0x13: /* FRINT64X */
6253 gen_fpst
= gen_helper_frint64_s
;
6256 g_assert_not_reached();
6259 fpst
= fpstatus_ptr(FPST_FPCR
);
6261 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6262 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6263 gen_fpst(tcg_res
, tcg_op
, fpst
);
6264 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6265 tcg_temp_free_i32(tcg_rmode
);
6267 gen_fpst(tcg_res
, tcg_op
, fpst
);
6269 tcg_temp_free_ptr(fpst
);
6272 write_fp_sreg(s
, rd
, tcg_res
);
6273 tcg_temp_free_i32(tcg_op
);
6274 tcg_temp_free_i32(tcg_res
);
6277 /* Floating-point data-processing (1 source) - double precision */
6278 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6280 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6281 TCGv_i64 tcg_op
, tcg_res
;
6286 case 0x0: /* FMOV */
6287 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6291 tcg_op
= read_fp_dreg(s
, rn
);
6292 tcg_res
= tcg_temp_new_i64();
6295 case 0x1: /* FABS */
6296 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6298 case 0x2: /* FNEG */
6299 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6301 case 0x3: /* FSQRT */
6302 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6304 case 0x8: /* FRINTN */
6305 case 0x9: /* FRINTP */
6306 case 0xa: /* FRINTM */
6307 case 0xb: /* FRINTZ */
6308 case 0xc: /* FRINTA */
6309 rmode
= arm_rmode_to_sf(opcode
& 7);
6310 gen_fpst
= gen_helper_rintd
;
6312 case 0xe: /* FRINTX */
6313 gen_fpst
= gen_helper_rintd_exact
;
6315 case 0xf: /* FRINTI */
6316 gen_fpst
= gen_helper_rintd
;
6318 case 0x10: /* FRINT32Z */
6319 rmode
= float_round_to_zero
;
6320 gen_fpst
= gen_helper_frint32_d
;
6322 case 0x11: /* FRINT32X */
6323 gen_fpst
= gen_helper_frint32_d
;
6325 case 0x12: /* FRINT64Z */
6326 rmode
= float_round_to_zero
;
6327 gen_fpst
= gen_helper_frint64_d
;
6329 case 0x13: /* FRINT64X */
6330 gen_fpst
= gen_helper_frint64_d
;
6333 g_assert_not_reached();
6336 fpst
= fpstatus_ptr(FPST_FPCR
);
6338 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6339 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6340 gen_fpst(tcg_res
, tcg_op
, fpst
);
6341 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6342 tcg_temp_free_i32(tcg_rmode
);
6344 gen_fpst(tcg_res
, tcg_op
, fpst
);
6346 tcg_temp_free_ptr(fpst
);
6349 write_fp_dreg(s
, rd
, tcg_res
);
6350 tcg_temp_free_i64(tcg_op
);
6351 tcg_temp_free_i64(tcg_res
);
6354 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6355 int rd
, int rn
, int dtype
, int ntype
)
6360 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6362 /* Single to double */
6363 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6364 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6365 write_fp_dreg(s
, rd
, tcg_rd
);
6366 tcg_temp_free_i64(tcg_rd
);
6368 /* Single to half */
6369 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6370 TCGv_i32 ahp
= get_ahp_flag();
6371 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6373 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6374 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6375 write_fp_sreg(s
, rd
, tcg_rd
);
6376 tcg_temp_free_i32(tcg_rd
);
6377 tcg_temp_free_i32(ahp
);
6378 tcg_temp_free_ptr(fpst
);
6380 tcg_temp_free_i32(tcg_rn
);
6385 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6386 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6388 /* Double to single */
6389 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6391 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6392 TCGv_i32 ahp
= get_ahp_flag();
6393 /* Double to half */
6394 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6395 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6396 tcg_temp_free_ptr(fpst
);
6397 tcg_temp_free_i32(ahp
);
6399 write_fp_sreg(s
, rd
, tcg_rd
);
6400 tcg_temp_free_i32(tcg_rd
);
6401 tcg_temp_free_i64(tcg_rn
);
6406 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6407 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6408 TCGv_i32 tcg_ahp
= get_ahp_flag();
6409 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6411 /* Half to single */
6412 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6413 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6414 write_fp_sreg(s
, rd
, tcg_rd
);
6415 tcg_temp_free_i32(tcg_rd
);
6417 /* Half to double */
6418 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6419 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6420 write_fp_dreg(s
, rd
, tcg_rd
);
6421 tcg_temp_free_i64(tcg_rd
);
6423 tcg_temp_free_i32(tcg_rn
);
6424 tcg_temp_free_ptr(tcg_fpst
);
6425 tcg_temp_free_i32(tcg_ahp
);
6433 /* Floating point data-processing (1 source)
6434 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6435 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6436 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6437 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6439 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6441 int mos
= extract32(insn
, 29, 3);
6442 int type
= extract32(insn
, 22, 2);
6443 int opcode
= extract32(insn
, 15, 6);
6444 int rn
= extract32(insn
, 5, 5);
6445 int rd
= extract32(insn
, 0, 5);
6448 unallocated_encoding(s
);
6453 case 0x4: case 0x5: case 0x7:
6455 /* FCVT between half, single and double precision */
6456 int dtype
= extract32(opcode
, 0, 2);
6457 if (type
== 2 || dtype
== type
) {
6458 unallocated_encoding(s
);
6461 if (!fp_access_check(s
)) {
6465 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6469 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6470 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6471 unallocated_encoding(s
);
6478 /* 32-to-32 and 64-to-64 ops */
6481 if (!fp_access_check(s
)) {
6484 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6487 if (!fp_access_check(s
)) {
6490 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6493 if (!dc_isar_feature(aa64_fp16
, s
)) {
6494 unallocated_encoding(s
);
6498 if (!fp_access_check(s
)) {
6501 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6504 unallocated_encoding(s
);
6509 unallocated_encoding(s
);
6514 /* Floating-point data-processing (2 source) - single precision */
6515 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6516 int rd
, int rn
, int rm
)
6523 tcg_res
= tcg_temp_new_i32();
6524 fpst
= fpstatus_ptr(FPST_FPCR
);
6525 tcg_op1
= read_fp_sreg(s
, rn
);
6526 tcg_op2
= read_fp_sreg(s
, rm
);
6529 case 0x0: /* FMUL */
6530 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6532 case 0x1: /* FDIV */
6533 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6535 case 0x2: /* FADD */
6536 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6538 case 0x3: /* FSUB */
6539 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6541 case 0x4: /* FMAX */
6542 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6544 case 0x5: /* FMIN */
6545 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6547 case 0x6: /* FMAXNM */
6548 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6550 case 0x7: /* FMINNM */
6551 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6553 case 0x8: /* FNMUL */
6554 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6555 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6559 write_fp_sreg(s
, rd
, tcg_res
);
6561 tcg_temp_free_ptr(fpst
);
6562 tcg_temp_free_i32(tcg_op1
);
6563 tcg_temp_free_i32(tcg_op2
);
6564 tcg_temp_free_i32(tcg_res
);
6567 /* Floating-point data-processing (2 source) - double precision */
6568 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6569 int rd
, int rn
, int rm
)
6576 tcg_res
= tcg_temp_new_i64();
6577 fpst
= fpstatus_ptr(FPST_FPCR
);
6578 tcg_op1
= read_fp_dreg(s
, rn
);
6579 tcg_op2
= read_fp_dreg(s
, rm
);
6582 case 0x0: /* FMUL */
6583 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6585 case 0x1: /* FDIV */
6586 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6588 case 0x2: /* FADD */
6589 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6591 case 0x3: /* FSUB */
6592 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6594 case 0x4: /* FMAX */
6595 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6597 case 0x5: /* FMIN */
6598 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6600 case 0x6: /* FMAXNM */
6601 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6603 case 0x7: /* FMINNM */
6604 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6606 case 0x8: /* FNMUL */
6607 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6608 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6612 write_fp_dreg(s
, rd
, tcg_res
);
6614 tcg_temp_free_ptr(fpst
);
6615 tcg_temp_free_i64(tcg_op1
);
6616 tcg_temp_free_i64(tcg_op2
);
6617 tcg_temp_free_i64(tcg_res
);
6620 /* Floating-point data-processing (2 source) - half precision */
6621 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6622 int rd
, int rn
, int rm
)
6629 tcg_res
= tcg_temp_new_i32();
6630 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6631 tcg_op1
= read_fp_hreg(s
, rn
);
6632 tcg_op2
= read_fp_hreg(s
, rm
);
6635 case 0x0: /* FMUL */
6636 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6638 case 0x1: /* FDIV */
6639 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6641 case 0x2: /* FADD */
6642 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6644 case 0x3: /* FSUB */
6645 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6647 case 0x4: /* FMAX */
6648 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6650 case 0x5: /* FMIN */
6651 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6653 case 0x6: /* FMAXNM */
6654 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6656 case 0x7: /* FMINNM */
6657 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6659 case 0x8: /* FNMUL */
6660 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6661 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6664 g_assert_not_reached();
6667 write_fp_sreg(s
, rd
, tcg_res
);
6669 tcg_temp_free_ptr(fpst
);
6670 tcg_temp_free_i32(tcg_op1
);
6671 tcg_temp_free_i32(tcg_op2
);
6672 tcg_temp_free_i32(tcg_res
);
6675 /* Floating point data-processing (2 source)
6676 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6677 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6678 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6679 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6681 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6683 int mos
= extract32(insn
, 29, 3);
6684 int type
= extract32(insn
, 22, 2);
6685 int rd
= extract32(insn
, 0, 5);
6686 int rn
= extract32(insn
, 5, 5);
6687 int rm
= extract32(insn
, 16, 5);
6688 int opcode
= extract32(insn
, 12, 4);
6690 if (opcode
> 8 || mos
) {
6691 unallocated_encoding(s
);
6697 if (!fp_access_check(s
)) {
6700 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6703 if (!fp_access_check(s
)) {
6706 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6709 if (!dc_isar_feature(aa64_fp16
, s
)) {
6710 unallocated_encoding(s
);
6713 if (!fp_access_check(s
)) {
6716 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6719 unallocated_encoding(s
);
6723 /* Floating-point data-processing (3 source) - single precision */
6724 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6725 int rd
, int rn
, int rm
, int ra
)
6727 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6728 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6729 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6731 tcg_op1
= read_fp_sreg(s
, rn
);
6732 tcg_op2
= read_fp_sreg(s
, rm
);
6733 tcg_op3
= read_fp_sreg(s
, ra
);
6735 /* These are fused multiply-add, and must be done as one
6736 * floating point operation with no rounding between the
6737 * multiplication and addition steps.
6738 * NB that doing the negations here as separate steps is
6739 * correct : an input NaN should come out with its sign bit
6740 * flipped if it is a negated-input.
6743 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6747 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6750 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6752 write_fp_sreg(s
, rd
, tcg_res
);
6754 tcg_temp_free_ptr(fpst
);
6755 tcg_temp_free_i32(tcg_op1
);
6756 tcg_temp_free_i32(tcg_op2
);
6757 tcg_temp_free_i32(tcg_op3
);
6758 tcg_temp_free_i32(tcg_res
);
6761 /* Floating-point data-processing (3 source) - double precision */
6762 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6763 int rd
, int rn
, int rm
, int ra
)
6765 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6766 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6767 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6769 tcg_op1
= read_fp_dreg(s
, rn
);
6770 tcg_op2
= read_fp_dreg(s
, rm
);
6771 tcg_op3
= read_fp_dreg(s
, ra
);
6773 /* These are fused multiply-add, and must be done as one
6774 * floating point operation with no rounding between the
6775 * multiplication and addition steps.
6776 * NB that doing the negations here as separate steps is
6777 * correct : an input NaN should come out with its sign bit
6778 * flipped if it is a negated-input.
6781 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6785 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6788 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6790 write_fp_dreg(s
, rd
, tcg_res
);
6792 tcg_temp_free_ptr(fpst
);
6793 tcg_temp_free_i64(tcg_op1
);
6794 tcg_temp_free_i64(tcg_op2
);
6795 tcg_temp_free_i64(tcg_op3
);
6796 tcg_temp_free_i64(tcg_res
);
6799 /* Floating-point data-processing (3 source) - half precision */
6800 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6801 int rd
, int rn
, int rm
, int ra
)
6803 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6804 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6805 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6807 tcg_op1
= read_fp_hreg(s
, rn
);
6808 tcg_op2
= read_fp_hreg(s
, rm
);
6809 tcg_op3
= read_fp_hreg(s
, ra
);
6811 /* These are fused multiply-add, and must be done as one
6812 * floating point operation with no rounding between the
6813 * multiplication and addition steps.
6814 * NB that doing the negations here as separate steps is
6815 * correct : an input NaN should come out with its sign bit
6816 * flipped if it is a negated-input.
6819 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6823 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6826 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6828 write_fp_sreg(s
, rd
, tcg_res
);
6830 tcg_temp_free_ptr(fpst
);
6831 tcg_temp_free_i32(tcg_op1
);
6832 tcg_temp_free_i32(tcg_op2
);
6833 tcg_temp_free_i32(tcg_op3
);
6834 tcg_temp_free_i32(tcg_res
);
6837 /* Floating point data-processing (3 source)
6838 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6839 * +---+---+---+-----------+------+----+------+----+------+------+------+
6840 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6841 * +---+---+---+-----------+------+----+------+----+------+------+------+
6843 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6845 int mos
= extract32(insn
, 29, 3);
6846 int type
= extract32(insn
, 22, 2);
6847 int rd
= extract32(insn
, 0, 5);
6848 int rn
= extract32(insn
, 5, 5);
6849 int ra
= extract32(insn
, 10, 5);
6850 int rm
= extract32(insn
, 16, 5);
6851 bool o0
= extract32(insn
, 15, 1);
6852 bool o1
= extract32(insn
, 21, 1);
6855 unallocated_encoding(s
);
6861 if (!fp_access_check(s
)) {
6864 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6867 if (!fp_access_check(s
)) {
6870 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6873 if (!dc_isar_feature(aa64_fp16
, s
)) {
6874 unallocated_encoding(s
);
6877 if (!fp_access_check(s
)) {
6880 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6883 unallocated_encoding(s
);
6887 /* Floating point immediate
6888 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6889 * +---+---+---+-----------+------+---+------------+-------+------+------+
6890 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6891 * +---+---+---+-----------+------+---+------------+-------+------+------+
6893 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6895 int rd
= extract32(insn
, 0, 5);
6896 int imm5
= extract32(insn
, 5, 5);
6897 int imm8
= extract32(insn
, 13, 8);
6898 int type
= extract32(insn
, 22, 2);
6899 int mos
= extract32(insn
, 29, 3);
6905 unallocated_encoding(s
);
6918 if (dc_isar_feature(aa64_fp16
, s
)) {
6923 unallocated_encoding(s
);
6927 if (!fp_access_check(s
)) {
6931 imm
= vfp_expand_imm(sz
, imm8
);
6933 tcg_res
= tcg_const_i64(imm
);
6934 write_fp_dreg(s
, rd
, tcg_res
);
6935 tcg_temp_free_i64(tcg_res
);
6938 /* Handle floating point <=> fixed point conversions. Note that we can
6939 * also deal with fp <=> integer conversions as a special case (scale == 64)
6940 * OPTME: consider handling that special case specially or at least skipping
6941 * the call to scalbn in the helpers for zero shifts.
6943 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6944 bool itof
, int rmode
, int scale
, int sf
, int type
)
6946 bool is_signed
= !(opcode
& 1);
6947 TCGv_ptr tcg_fpstatus
;
6948 TCGv_i32 tcg_shift
, tcg_single
;
6949 TCGv_i64 tcg_double
;
6951 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
6953 tcg_shift
= tcg_const_i32(64 - scale
);
6956 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6958 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6961 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6963 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6966 tcg_int
= tcg_extend
;
6970 case 1: /* float64 */
6971 tcg_double
= tcg_temp_new_i64();
6973 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6974 tcg_shift
, tcg_fpstatus
);
6976 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6977 tcg_shift
, tcg_fpstatus
);
6979 write_fp_dreg(s
, rd
, tcg_double
);
6980 tcg_temp_free_i64(tcg_double
);
6983 case 0: /* float32 */
6984 tcg_single
= tcg_temp_new_i32();
6986 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6987 tcg_shift
, tcg_fpstatus
);
6989 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6990 tcg_shift
, tcg_fpstatus
);
6992 write_fp_sreg(s
, rd
, tcg_single
);
6993 tcg_temp_free_i32(tcg_single
);
6996 case 3: /* float16 */
6997 tcg_single
= tcg_temp_new_i32();
6999 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7000 tcg_shift
, tcg_fpstatus
);
7002 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7003 tcg_shift
, tcg_fpstatus
);
7005 write_fp_sreg(s
, rd
, tcg_single
);
7006 tcg_temp_free_i32(tcg_single
);
7010 g_assert_not_reached();
7013 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7016 if (extract32(opcode
, 2, 1)) {
7017 /* There are too many rounding modes to all fit into rmode,
7018 * so FCVTA[US] is a special case.
7020 rmode
= FPROUNDING_TIEAWAY
;
7023 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7025 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7028 case 1: /* float64 */
7029 tcg_double
= read_fp_dreg(s
, rn
);
7032 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7033 tcg_shift
, tcg_fpstatus
);
7035 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7036 tcg_shift
, tcg_fpstatus
);
7040 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7041 tcg_shift
, tcg_fpstatus
);
7043 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7044 tcg_shift
, tcg_fpstatus
);
7048 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7050 tcg_temp_free_i64(tcg_double
);
7053 case 0: /* float32 */
7054 tcg_single
= read_fp_sreg(s
, rn
);
7057 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7058 tcg_shift
, tcg_fpstatus
);
7060 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7061 tcg_shift
, tcg_fpstatus
);
7064 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7066 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7067 tcg_shift
, tcg_fpstatus
);
7069 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7070 tcg_shift
, tcg_fpstatus
);
7072 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7073 tcg_temp_free_i32(tcg_dest
);
7075 tcg_temp_free_i32(tcg_single
);
7078 case 3: /* float16 */
7079 tcg_single
= read_fp_sreg(s
, rn
);
7082 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7083 tcg_shift
, tcg_fpstatus
);
7085 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7086 tcg_shift
, tcg_fpstatus
);
7089 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7091 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7092 tcg_shift
, tcg_fpstatus
);
7094 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7095 tcg_shift
, tcg_fpstatus
);
7097 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7098 tcg_temp_free_i32(tcg_dest
);
7100 tcg_temp_free_i32(tcg_single
);
7104 g_assert_not_reached();
7107 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7108 tcg_temp_free_i32(tcg_rmode
);
7111 tcg_temp_free_ptr(tcg_fpstatus
);
7112 tcg_temp_free_i32(tcg_shift
);
7115 /* Floating point <-> fixed point conversions
7116 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7117 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7118 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7119 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7121 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7123 int rd
= extract32(insn
, 0, 5);
7124 int rn
= extract32(insn
, 5, 5);
7125 int scale
= extract32(insn
, 10, 6);
7126 int opcode
= extract32(insn
, 16, 3);
7127 int rmode
= extract32(insn
, 19, 2);
7128 int type
= extract32(insn
, 22, 2);
7129 bool sbit
= extract32(insn
, 29, 1);
7130 bool sf
= extract32(insn
, 31, 1);
7133 if (sbit
|| (!sf
&& scale
< 32)) {
7134 unallocated_encoding(s
);
7139 case 0: /* float32 */
7140 case 1: /* float64 */
7142 case 3: /* float16 */
7143 if (dc_isar_feature(aa64_fp16
, s
)) {
7148 unallocated_encoding(s
);
7152 switch ((rmode
<< 3) | opcode
) {
7153 case 0x2: /* SCVTF */
7154 case 0x3: /* UCVTF */
7157 case 0x18: /* FCVTZS */
7158 case 0x19: /* FCVTZU */
7162 unallocated_encoding(s
);
7166 if (!fp_access_check(s
)) {
7170 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7173 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7175 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7176 * without conversion.
7180 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7186 tmp
= tcg_temp_new_i64();
7187 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7188 write_fp_dreg(s
, rd
, tmp
);
7189 tcg_temp_free_i64(tmp
);
7193 write_fp_dreg(s
, rd
, tcg_rn
);
7196 /* 64 bit to top half. */
7197 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7198 clear_vec_high(s
, true, rd
);
7202 tmp
= tcg_temp_new_i64();
7203 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7204 write_fp_dreg(s
, rd
, tmp
);
7205 tcg_temp_free_i64(tmp
);
7208 g_assert_not_reached();
7211 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7216 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7220 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7223 /* 64 bits from top half */
7224 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7228 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7231 g_assert_not_reached();
7236 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7238 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7239 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7241 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7243 tcg_temp_free_ptr(fpstatus
);
7245 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7246 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7247 tcg_gen_movi_i32(cpu_CF
, 0);
7248 tcg_gen_movi_i32(cpu_NF
, 0);
7249 tcg_gen_movi_i32(cpu_VF
, 0);
7251 tcg_temp_free_i64(t
);
7254 /* Floating point <-> integer conversions
7255 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7256 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7257 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7258 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7260 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7262 int rd
= extract32(insn
, 0, 5);
7263 int rn
= extract32(insn
, 5, 5);
7264 int opcode
= extract32(insn
, 16, 3);
7265 int rmode
= extract32(insn
, 19, 2);
7266 int type
= extract32(insn
, 22, 2);
7267 bool sbit
= extract32(insn
, 29, 1);
7268 bool sf
= extract32(insn
, 31, 1);
7272 goto do_unallocated
;
7280 case 4: /* FCVTAS */
7281 case 5: /* FCVTAU */
7283 goto do_unallocated
;
7286 case 0: /* FCVT[NPMZ]S */
7287 case 1: /* FCVT[NPMZ]U */
7289 case 0: /* float32 */
7290 case 1: /* float64 */
7292 case 3: /* float16 */
7293 if (!dc_isar_feature(aa64_fp16
, s
)) {
7294 goto do_unallocated
;
7298 goto do_unallocated
;
7300 if (!fp_access_check(s
)) {
7303 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7307 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7308 case 0b01100110: /* FMOV half <-> 32-bit int */
7310 case 0b11100110: /* FMOV half <-> 64-bit int */
7312 if (!dc_isar_feature(aa64_fp16
, s
)) {
7313 goto do_unallocated
;
7316 case 0b00000110: /* FMOV 32-bit */
7318 case 0b10100110: /* FMOV 64-bit */
7320 case 0b11001110: /* FMOV top half of 128-bit */
7322 if (!fp_access_check(s
)) {
7326 handle_fmov(s
, rd
, rn
, type
, itof
);
7329 case 0b00111110: /* FJCVTZS */
7330 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7331 goto do_unallocated
;
7332 } else if (fp_access_check(s
)) {
7333 handle_fjcvtzs(s
, rd
, rn
);
7339 unallocated_encoding(s
);
7346 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7347 * 31 30 29 28 25 24 0
7348 * +---+---+---+---------+-----------------------------+
7349 * | | 0 | | 1 1 1 1 | |
7350 * +---+---+---+---------+-----------------------------+
7352 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7354 if (extract32(insn
, 24, 1)) {
7355 /* Floating point data-processing (3 source) */
7356 disas_fp_3src(s
, insn
);
7357 } else if (extract32(insn
, 21, 1) == 0) {
7358 /* Floating point to fixed point conversions */
7359 disas_fp_fixed_conv(s
, insn
);
7361 switch (extract32(insn
, 10, 2)) {
7363 /* Floating point conditional compare */
7364 disas_fp_ccomp(s
, insn
);
7367 /* Floating point data-processing (2 source) */
7368 disas_fp_2src(s
, insn
);
7371 /* Floating point conditional select */
7372 disas_fp_csel(s
, insn
);
7375 switch (ctz32(extract32(insn
, 12, 4))) {
7376 case 0: /* [15:12] == xxx1 */
7377 /* Floating point immediate */
7378 disas_fp_imm(s
, insn
);
7380 case 1: /* [15:12] == xx10 */
7381 /* Floating point compare */
7382 disas_fp_compare(s
, insn
);
7384 case 2: /* [15:12] == x100 */
7385 /* Floating point data-processing (1 source) */
7386 disas_fp_1src(s
, insn
);
7388 case 3: /* [15:12] == 1000 */
7389 unallocated_encoding(s
);
7391 default: /* [15:12] == 0000 */
7392 /* Floating point <-> integer conversions */
7393 disas_fp_int_conv(s
, insn
);
7401 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7404 /* Extract 64 bits from the middle of two concatenated 64 bit
7405 * vector register slices left:right. The extracted bits start
7406 * at 'pos' bits into the right (least significant) side.
7407 * We return the result in tcg_right, and guarantee not to
7410 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7411 assert(pos
> 0 && pos
< 64);
7413 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7414 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7415 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7417 tcg_temp_free_i64(tcg_tmp
);
7421 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7422 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7423 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7424 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7426 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7428 int is_q
= extract32(insn
, 30, 1);
7429 int op2
= extract32(insn
, 22, 2);
7430 int imm4
= extract32(insn
, 11, 4);
7431 int rm
= extract32(insn
, 16, 5);
7432 int rn
= extract32(insn
, 5, 5);
7433 int rd
= extract32(insn
, 0, 5);
7434 int pos
= imm4
<< 3;
7435 TCGv_i64 tcg_resl
, tcg_resh
;
7437 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7438 unallocated_encoding(s
);
7442 if (!fp_access_check(s
)) {
7446 tcg_resh
= tcg_temp_new_i64();
7447 tcg_resl
= tcg_temp_new_i64();
7449 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7450 * either extracting 128 bits from a 128:128 concatenation, or
7451 * extracting 64 bits from a 64:64 concatenation.
7454 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7456 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7457 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7465 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7466 EltPosns
*elt
= eltposns
;
7473 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7475 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7478 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7479 tcg_hh
= tcg_temp_new_i64();
7480 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7481 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7482 tcg_temp_free_i64(tcg_hh
);
7486 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7487 tcg_temp_free_i64(tcg_resl
);
7489 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7491 tcg_temp_free_i64(tcg_resh
);
7492 clear_vec_high(s
, is_q
, rd
);
7496 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7497 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7498 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7499 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7501 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7503 int op2
= extract32(insn
, 22, 2);
7504 int is_q
= extract32(insn
, 30, 1);
7505 int rm
= extract32(insn
, 16, 5);
7506 int rn
= extract32(insn
, 5, 5);
7507 int rd
= extract32(insn
, 0, 5);
7508 int is_tblx
= extract32(insn
, 12, 1);
7509 int len
= extract32(insn
, 13, 2);
7510 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7511 TCGv_i32 tcg_regno
, tcg_numregs
;
7514 unallocated_encoding(s
);
7518 if (!fp_access_check(s
)) {
7522 /* This does a table lookup: for every byte element in the input
7523 * we index into a table formed from up to four vector registers,
7524 * and then the output is the result of the lookups. Our helper
7525 * function does the lookup operation for a single 64 bit part of
7528 tcg_resl
= tcg_temp_new_i64();
7532 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7534 tcg_gen_movi_i64(tcg_resl
, 0);
7538 tcg_resh
= tcg_temp_new_i64();
7540 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7542 tcg_gen_movi_i64(tcg_resh
, 0);
7546 tcg_idx
= tcg_temp_new_i64();
7547 tcg_regno
= tcg_const_i32(rn
);
7548 tcg_numregs
= tcg_const_i32(len
+ 1);
7549 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7550 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7551 tcg_regno
, tcg_numregs
);
7553 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7554 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7555 tcg_regno
, tcg_numregs
);
7557 tcg_temp_free_i64(tcg_idx
);
7558 tcg_temp_free_i32(tcg_regno
);
7559 tcg_temp_free_i32(tcg_numregs
);
7561 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7562 tcg_temp_free_i64(tcg_resl
);
7565 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7566 tcg_temp_free_i64(tcg_resh
);
7568 clear_vec_high(s
, is_q
, rd
);
7572 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7573 * +---+---+-------------+------+---+------+---+------------------+------+
7574 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7575 * +---+---+-------------+------+---+------+---+------------------+------+
7577 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7579 int rd
= extract32(insn
, 0, 5);
7580 int rn
= extract32(insn
, 5, 5);
7581 int rm
= extract32(insn
, 16, 5);
7582 int size
= extract32(insn
, 22, 2);
7583 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7584 * bit 2 indicates 1 vs 2 variant of the insn.
7586 int opcode
= extract32(insn
, 12, 2);
7587 bool part
= extract32(insn
, 14, 1);
7588 bool is_q
= extract32(insn
, 30, 1);
7589 int esize
= 8 << size
;
7591 int datasize
= is_q
? 128 : 64;
7592 int elements
= datasize
/ esize
;
7593 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7595 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7596 unallocated_encoding(s
);
7600 if (!fp_access_check(s
)) {
7604 tcg_resl
= tcg_const_i64(0);
7605 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7606 tcg_res
= tcg_temp_new_i64();
7608 for (i
= 0; i
< elements
; i
++) {
7610 case 1: /* UZP1/2 */
7612 int midpoint
= elements
/ 2;
7614 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7616 read_vec_element(s
, tcg_res
, rm
,
7617 2 * (i
- midpoint
) + part
, size
);
7621 case 2: /* TRN1/2 */
7623 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7625 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7628 case 3: /* ZIP1/2 */
7630 int base
= part
* elements
/ 2;
7632 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7634 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7639 g_assert_not_reached();
7644 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7645 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7647 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7648 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7652 tcg_temp_free_i64(tcg_res
);
7654 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7655 tcg_temp_free_i64(tcg_resl
);
7658 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7659 tcg_temp_free_i64(tcg_resh
);
7661 clear_vec_high(s
, is_q
, rd
);
7665 * do_reduction_op helper
7667 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7668 * important for correct NaN propagation that we do these
7669 * operations in exactly the order specified by the pseudocode.
7671 * This is a recursive function, TCG temps should be freed by the
7672 * calling function once it is done with the values.
7674 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7675 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7677 if (esize
== size
) {
7679 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7682 /* We should have one register left here */
7683 assert(ctpop8(vmap
) == 1);
7684 element
= ctz32(vmap
);
7685 assert(element
< 8);
7687 tcg_elem
= tcg_temp_new_i32();
7688 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7691 int bits
= size
/ 2;
7692 int shift
= ctpop8(vmap
) / 2;
7693 int vmap_lo
= (vmap
>> shift
) & vmap
;
7694 int vmap_hi
= (vmap
& ~vmap_lo
);
7695 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7697 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7698 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7699 tcg_res
= tcg_temp_new_i32();
7702 case 0x0c: /* fmaxnmv half-precision */
7703 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7705 case 0x0f: /* fmaxv half-precision */
7706 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7708 case 0x1c: /* fminnmv half-precision */
7709 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7711 case 0x1f: /* fminv half-precision */
7712 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7714 case 0x2c: /* fmaxnmv */
7715 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7717 case 0x2f: /* fmaxv */
7718 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7720 case 0x3c: /* fminnmv */
7721 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7723 case 0x3f: /* fminv */
7724 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7727 g_assert_not_reached();
7730 tcg_temp_free_i32(tcg_hi
);
7731 tcg_temp_free_i32(tcg_lo
);
7736 /* AdvSIMD across lanes
7737 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7738 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7739 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7740 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7742 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7744 int rd
= extract32(insn
, 0, 5);
7745 int rn
= extract32(insn
, 5, 5);
7746 int size
= extract32(insn
, 22, 2);
7747 int opcode
= extract32(insn
, 12, 5);
7748 bool is_q
= extract32(insn
, 30, 1);
7749 bool is_u
= extract32(insn
, 29, 1);
7751 bool is_min
= false;
7755 TCGv_i64 tcg_res
, tcg_elt
;
7758 case 0x1b: /* ADDV */
7760 unallocated_encoding(s
);
7764 case 0x3: /* SADDLV, UADDLV */
7765 case 0xa: /* SMAXV, UMAXV */
7766 case 0x1a: /* SMINV, UMINV */
7767 if (size
== 3 || (size
== 2 && !is_q
)) {
7768 unallocated_encoding(s
);
7772 case 0xc: /* FMAXNMV, FMINNMV */
7773 case 0xf: /* FMAXV, FMINV */
7774 /* Bit 1 of size field encodes min vs max and the actual size
7775 * depends on the encoding of the U bit. If not set (and FP16
7776 * enabled) then we do half-precision float instead of single
7779 is_min
= extract32(size
, 1, 1);
7781 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7783 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7784 unallocated_encoding(s
);
7791 unallocated_encoding(s
);
7795 if (!fp_access_check(s
)) {
7800 elements
= (is_q
? 128 : 64) / esize
;
7802 tcg_res
= tcg_temp_new_i64();
7803 tcg_elt
= tcg_temp_new_i64();
7805 /* These instructions operate across all lanes of a vector
7806 * to produce a single result. We can guarantee that a 64
7807 * bit intermediate is sufficient:
7808 * + for [US]ADDLV the maximum element size is 32 bits, and
7809 * the result type is 64 bits
7810 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7811 * same as the element size, which is 32 bits at most
7812 * For the integer operations we can choose to work at 64
7813 * or 32 bits and truncate at the end; for simplicity
7814 * we use 64 bits always. The floating point
7815 * ops do require 32 bit intermediates, though.
7818 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7820 for (i
= 1; i
< elements
; i
++) {
7821 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7824 case 0x03: /* SADDLV / UADDLV */
7825 case 0x1b: /* ADDV */
7826 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7828 case 0x0a: /* SMAXV / UMAXV */
7830 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7832 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7835 case 0x1a: /* SMINV / UMINV */
7837 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7839 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7843 g_assert_not_reached();
7848 /* Floating point vector reduction ops which work across 32
7849 * bit (single) or 16 bit (half-precision) intermediates.
7850 * Note that correct NaN propagation requires that we do these
7851 * operations in exactly the order specified by the pseudocode.
7853 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7854 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7855 int vmap
= (1 << elements
) - 1;
7856 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7857 (is_q
? 128 : 64), vmap
, fpst
);
7858 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7859 tcg_temp_free_i32(tcg_res32
);
7860 tcg_temp_free_ptr(fpst
);
7863 tcg_temp_free_i64(tcg_elt
);
7865 /* Now truncate the result to the width required for the final output */
7866 if (opcode
== 0x03) {
7867 /* SADDLV, UADDLV: result is 2*esize */
7873 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7876 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7879 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7884 g_assert_not_reached();
7887 write_fp_dreg(s
, rd
, tcg_res
);
7888 tcg_temp_free_i64(tcg_res
);
7891 /* DUP (Element, Vector)
7893 * 31 30 29 21 20 16 15 10 9 5 4 0
7894 * +---+---+-------------------+--------+-------------+------+------+
7895 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7896 * +---+---+-------------------+--------+-------------+------+------+
7898 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7900 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7903 int size
= ctz32(imm5
);
7906 if (size
> 3 || (size
== 3 && !is_q
)) {
7907 unallocated_encoding(s
);
7911 if (!fp_access_check(s
)) {
7915 index
= imm5
>> (size
+ 1);
7916 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7917 vec_reg_offset(s
, rn
, index
, size
),
7918 is_q
? 16 : 8, vec_full_reg_size(s
));
7921 /* DUP (element, scalar)
7922 * 31 21 20 16 15 10 9 5 4 0
7923 * +-----------------------+--------+-------------+------+------+
7924 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7925 * +-----------------------+--------+-------------+------+------+
7927 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7930 int size
= ctz32(imm5
);
7935 unallocated_encoding(s
);
7939 if (!fp_access_check(s
)) {
7943 index
= imm5
>> (size
+ 1);
7945 /* This instruction just extracts the specified element and
7946 * zero-extends it into the bottom of the destination register.
7948 tmp
= tcg_temp_new_i64();
7949 read_vec_element(s
, tmp
, rn
, index
, size
);
7950 write_fp_dreg(s
, rd
, tmp
);
7951 tcg_temp_free_i64(tmp
);
7956 * 31 30 29 21 20 16 15 10 9 5 4 0
7957 * +---+---+-------------------+--------+-------------+------+------+
7958 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7959 * +---+---+-------------------+--------+-------------+------+------+
7961 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7963 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7966 int size
= ctz32(imm5
);
7967 uint32_t dofs
, oprsz
, maxsz
;
7969 if (size
> 3 || ((size
== 3) && !is_q
)) {
7970 unallocated_encoding(s
);
7974 if (!fp_access_check(s
)) {
7978 dofs
= vec_full_reg_offset(s
, rd
);
7979 oprsz
= is_q
? 16 : 8;
7980 maxsz
= vec_full_reg_size(s
);
7982 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7987 * 31 21 20 16 15 14 11 10 9 5 4 0
7988 * +-----------------------+--------+------------+---+------+------+
7989 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7990 * +-----------------------+--------+------------+---+------+------+
7992 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7993 * index: encoded in imm5<4:size+1>
7995 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7998 int size
= ctz32(imm5
);
7999 int src_index
, dst_index
;
8003 unallocated_encoding(s
);
8007 if (!fp_access_check(s
)) {
8011 dst_index
= extract32(imm5
, 1+size
, 5);
8012 src_index
= extract32(imm4
, size
, 4);
8014 tmp
= tcg_temp_new_i64();
8016 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8017 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8019 tcg_temp_free_i64(tmp
);
8021 /* INS is considered a 128-bit write for SVE. */
8022 clear_vec_high(s
, true, rd
);
8028 * 31 21 20 16 15 10 9 5 4 0
8029 * +-----------------------+--------+-------------+------+------+
8030 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8031 * +-----------------------+--------+-------------+------+------+
8033 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8034 * index: encoded in imm5<4:size+1>
8036 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8038 int size
= ctz32(imm5
);
8042 unallocated_encoding(s
);
8046 if (!fp_access_check(s
)) {
8050 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8051 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8053 /* INS is considered a 128-bit write for SVE. */
8054 clear_vec_high(s
, true, rd
);
8061 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8062 * +---+---+-------------------+--------+-------------+------+------+
8063 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8064 * +---+---+-------------------+--------+-------------+------+------+
8066 * U: unsigned when set
8067 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8069 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8070 int rn
, int rd
, int imm5
)
8072 int size
= ctz32(imm5
);
8076 /* Check for UnallocatedEncodings */
8078 if (size
> 2 || (size
== 2 && !is_q
)) {
8079 unallocated_encoding(s
);
8084 || (size
< 3 && is_q
)
8085 || (size
== 3 && !is_q
)) {
8086 unallocated_encoding(s
);
8091 if (!fp_access_check(s
)) {
8095 element
= extract32(imm5
, 1+size
, 4);
8097 tcg_rd
= cpu_reg(s
, rd
);
8098 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8099 if (is_signed
&& !is_q
) {
8100 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8105 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8106 * +---+---+----+-----------------+------+---+------+---+------+------+
8107 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8108 * +---+---+----+-----------------+------+---+------+---+------+------+
8110 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8112 int rd
= extract32(insn
, 0, 5);
8113 int rn
= extract32(insn
, 5, 5);
8114 int imm4
= extract32(insn
, 11, 4);
8115 int op
= extract32(insn
, 29, 1);
8116 int is_q
= extract32(insn
, 30, 1);
8117 int imm5
= extract32(insn
, 16, 5);
8122 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8124 unallocated_encoding(s
);
8129 /* DUP (element - vector) */
8130 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8134 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8139 handle_simd_insg(s
, rd
, rn
, imm5
);
8141 unallocated_encoding(s
);
8146 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8147 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8150 unallocated_encoding(s
);
8156 /* AdvSIMD modified immediate
8157 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8158 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8159 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8160 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8162 * There are a number of operations that can be carried out here:
8163 * MOVI - move (shifted) imm into register
8164 * MVNI - move inverted (shifted) imm into register
8165 * ORR - bitwise OR of (shifted) imm with register
8166 * BIC - bitwise clear of (shifted) imm with register
8167 * With ARMv8.2 we also have:
8168 * FMOV half-precision
8170 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8172 int rd
= extract32(insn
, 0, 5);
8173 int cmode
= extract32(insn
, 12, 4);
8174 int cmode_3_1
= extract32(cmode
, 1, 3);
8175 int cmode_0
= extract32(cmode
, 0, 1);
8176 int o2
= extract32(insn
, 11, 1);
8177 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8178 bool is_neg
= extract32(insn
, 29, 1);
8179 bool is_q
= extract32(insn
, 30, 1);
8182 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8183 /* Check for FMOV (vector, immediate) - half-precision */
8184 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8185 unallocated_encoding(s
);
8190 if (!fp_access_check(s
)) {
8194 /* See AdvSIMDExpandImm() in ARM ARM */
8195 switch (cmode_3_1
) {
8196 case 0: /* Replicate(Zeros(24):imm8, 2) */
8197 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
8198 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
8199 case 3: /* Replicate(imm8:Zeros(24), 2) */
8201 int shift
= cmode_3_1
* 8;
8202 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
8205 case 4: /* Replicate(Zeros(8):imm8, 4) */
8206 case 5: /* Replicate(imm8:Zeros(8), 4) */
8208 int shift
= (cmode_3_1
& 0x1) * 8;
8209 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
8214 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
8215 imm
= (abcdefgh
<< 16) | 0xffff;
8217 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
8218 imm
= (abcdefgh
<< 8) | 0xff;
8220 imm
= bitfield_replicate(imm
, 32);
8223 if (!cmode_0
&& !is_neg
) {
8224 imm
= bitfield_replicate(abcdefgh
, 8);
8225 } else if (!cmode_0
&& is_neg
) {
8228 for (i
= 0; i
< 8; i
++) {
8229 if ((abcdefgh
) & (1 << i
)) {
8230 imm
|= 0xffULL
<< (i
* 8);
8233 } else if (cmode_0
) {
8235 imm
= (abcdefgh
& 0x3f) << 48;
8236 if (abcdefgh
& 0x80) {
8237 imm
|= 0x8000000000000000ULL
;
8239 if (abcdefgh
& 0x40) {
8240 imm
|= 0x3fc0000000000000ULL
;
8242 imm
|= 0x4000000000000000ULL
;
8246 /* FMOV (vector, immediate) - half-precision */
8247 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8248 /* now duplicate across the lanes */
8249 imm
= bitfield_replicate(imm
, 16);
8251 imm
= (abcdefgh
& 0x3f) << 19;
8252 if (abcdefgh
& 0x80) {
8255 if (abcdefgh
& 0x40) {
8266 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
8267 g_assert_not_reached();
8270 if (cmode_3_1
!= 7 && is_neg
) {
8274 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8275 /* MOVI or MVNI, with MVNI negation handled above. */
8276 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8277 vec_full_reg_size(s
), imm
);
8279 /* ORR or BIC, with BIC negation to AND handled above. */
8281 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8283 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8288 /* AdvSIMD scalar copy
8289 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8290 * +-----+----+-----------------+------+---+------+---+------+------+
8291 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8292 * +-----+----+-----------------+------+---+------+---+------+------+
8294 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8296 int rd
= extract32(insn
, 0, 5);
8297 int rn
= extract32(insn
, 5, 5);
8298 int imm4
= extract32(insn
, 11, 4);
8299 int imm5
= extract32(insn
, 16, 5);
8300 int op
= extract32(insn
, 29, 1);
8302 if (op
!= 0 || imm4
!= 0) {
8303 unallocated_encoding(s
);
8307 /* DUP (element, scalar) */
8308 handle_simd_dupes(s
, rd
, rn
, imm5
);
8311 /* AdvSIMD scalar pairwise
8312 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8313 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8314 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8315 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8317 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8319 int u
= extract32(insn
, 29, 1);
8320 int size
= extract32(insn
, 22, 2);
8321 int opcode
= extract32(insn
, 12, 5);
8322 int rn
= extract32(insn
, 5, 5);
8323 int rd
= extract32(insn
, 0, 5);
8326 /* For some ops (the FP ones), size[1] is part of the encoding.
8327 * For ADDP strictly it is not but size[1] is always 1 for valid
8330 opcode
|= (extract32(size
, 1, 1) << 5);
8333 case 0x3b: /* ADDP */
8334 if (u
|| size
!= 3) {
8335 unallocated_encoding(s
);
8338 if (!fp_access_check(s
)) {
8344 case 0xc: /* FMAXNMP */
8345 case 0xd: /* FADDP */
8346 case 0xf: /* FMAXP */
8347 case 0x2c: /* FMINNMP */
8348 case 0x2f: /* FMINP */
8349 /* FP op, size[0] is 32 or 64 bit*/
8351 if (!dc_isar_feature(aa64_fp16
, s
)) {
8352 unallocated_encoding(s
);
8358 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8361 if (!fp_access_check(s
)) {
8365 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8368 unallocated_encoding(s
);
8372 if (size
== MO_64
) {
8373 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8374 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8375 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8377 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8378 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8381 case 0x3b: /* ADDP */
8382 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8384 case 0xc: /* FMAXNMP */
8385 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8387 case 0xd: /* FADDP */
8388 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8390 case 0xf: /* FMAXP */
8391 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8393 case 0x2c: /* FMINNMP */
8394 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8396 case 0x2f: /* FMINP */
8397 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8400 g_assert_not_reached();
8403 write_fp_dreg(s
, rd
, tcg_res
);
8405 tcg_temp_free_i64(tcg_op1
);
8406 tcg_temp_free_i64(tcg_op2
);
8407 tcg_temp_free_i64(tcg_res
);
8409 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8410 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8411 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8413 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8414 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8416 if (size
== MO_16
) {
8418 case 0xc: /* FMAXNMP */
8419 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8421 case 0xd: /* FADDP */
8422 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8424 case 0xf: /* FMAXP */
8425 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8427 case 0x2c: /* FMINNMP */
8428 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8430 case 0x2f: /* FMINP */
8431 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8434 g_assert_not_reached();
8438 case 0xc: /* FMAXNMP */
8439 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8441 case 0xd: /* FADDP */
8442 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8444 case 0xf: /* FMAXP */
8445 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8447 case 0x2c: /* FMINNMP */
8448 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8450 case 0x2f: /* FMINP */
8451 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8454 g_assert_not_reached();
8458 write_fp_sreg(s
, rd
, tcg_res
);
8460 tcg_temp_free_i32(tcg_op1
);
8461 tcg_temp_free_i32(tcg_op2
);
8462 tcg_temp_free_i32(tcg_res
);
8466 tcg_temp_free_ptr(fpst
);
8471 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8473 * This code is handles the common shifting code and is used by both
8474 * the vector and scalar code.
8476 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8477 TCGv_i64 tcg_rnd
, bool accumulate
,
8478 bool is_u
, int size
, int shift
)
8480 bool extended_result
= false;
8481 bool round
= tcg_rnd
!= NULL
;
8483 TCGv_i64 tcg_src_hi
;
8485 if (round
&& size
== 3) {
8486 extended_result
= true;
8487 ext_lshift
= 64 - shift
;
8488 tcg_src_hi
= tcg_temp_new_i64();
8489 } else if (shift
== 64) {
8490 if (!accumulate
&& is_u
) {
8491 /* result is zero */
8492 tcg_gen_movi_i64(tcg_res
, 0);
8497 /* Deal with the rounding step */
8499 if (extended_result
) {
8500 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8502 /* take care of sign extending tcg_res */
8503 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8504 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8505 tcg_src
, tcg_src_hi
,
8508 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8512 tcg_temp_free_i64(tcg_zero
);
8514 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8518 /* Now do the shift right */
8519 if (round
&& extended_result
) {
8520 /* extended case, >64 bit precision required */
8521 if (ext_lshift
== 0) {
8522 /* special case, only high bits matter */
8523 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8525 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8526 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8527 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8532 /* essentially shifting in 64 zeros */
8533 tcg_gen_movi_i64(tcg_src
, 0);
8535 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8539 /* effectively extending the sign-bit */
8540 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8542 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8548 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8550 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8553 if (extended_result
) {
8554 tcg_temp_free_i64(tcg_src_hi
);
8558 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8559 static void handle_scalar_simd_shri(DisasContext
*s
,
8560 bool is_u
, int immh
, int immb
,
8561 int opcode
, int rn
, int rd
)
8564 int immhb
= immh
<< 3 | immb
;
8565 int shift
= 2 * (8 << size
) - immhb
;
8566 bool accumulate
= false;
8568 bool insert
= false;
8573 if (!extract32(immh
, 3, 1)) {
8574 unallocated_encoding(s
);
8578 if (!fp_access_check(s
)) {
8583 case 0x02: /* SSRA / USRA (accumulate) */
8586 case 0x04: /* SRSHR / URSHR (rounding) */
8589 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8590 accumulate
= round
= true;
8592 case 0x08: /* SRI */
8598 uint64_t round_const
= 1ULL << (shift
- 1);
8599 tcg_round
= tcg_const_i64(round_const
);
8604 tcg_rn
= read_fp_dreg(s
, rn
);
8605 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8608 /* shift count same as element size is valid but does nothing;
8609 * special case to avoid potential shift by 64.
8611 int esize
= 8 << size
;
8612 if (shift
!= esize
) {
8613 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8614 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8617 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8618 accumulate
, is_u
, size
, shift
);
8621 write_fp_dreg(s
, rd
, tcg_rd
);
8623 tcg_temp_free_i64(tcg_rn
);
8624 tcg_temp_free_i64(tcg_rd
);
8626 tcg_temp_free_i64(tcg_round
);
8630 /* SHL/SLI - Scalar shift left */
8631 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8632 int immh
, int immb
, int opcode
,
8635 int size
= 32 - clz32(immh
) - 1;
8636 int immhb
= immh
<< 3 | immb
;
8637 int shift
= immhb
- (8 << size
);
8641 if (!extract32(immh
, 3, 1)) {
8642 unallocated_encoding(s
);
8646 if (!fp_access_check(s
)) {
8650 tcg_rn
= read_fp_dreg(s
, rn
);
8651 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8654 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8656 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8659 write_fp_dreg(s
, rd
, tcg_rd
);
8661 tcg_temp_free_i64(tcg_rn
);
8662 tcg_temp_free_i64(tcg_rd
);
8665 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8666 * (signed/unsigned) narrowing */
8667 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8668 bool is_u_shift
, bool is_u_narrow
,
8669 int immh
, int immb
, int opcode
,
8672 int immhb
= immh
<< 3 | immb
;
8673 int size
= 32 - clz32(immh
) - 1;
8674 int esize
= 8 << size
;
8675 int shift
= (2 * esize
) - immhb
;
8676 int elements
= is_scalar
? 1 : (64 / esize
);
8677 bool round
= extract32(opcode
, 0, 1);
8678 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8679 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8680 TCGv_i32 tcg_rd_narrowed
;
8683 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8684 { gen_helper_neon_narrow_sat_s8
,
8685 gen_helper_neon_unarrow_sat8
},
8686 { gen_helper_neon_narrow_sat_s16
,
8687 gen_helper_neon_unarrow_sat16
},
8688 { gen_helper_neon_narrow_sat_s32
,
8689 gen_helper_neon_unarrow_sat32
},
8692 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8693 gen_helper_neon_narrow_sat_u8
,
8694 gen_helper_neon_narrow_sat_u16
,
8695 gen_helper_neon_narrow_sat_u32
,
8698 NeonGenNarrowEnvFn
*narrowfn
;
8704 if (extract32(immh
, 3, 1)) {
8705 unallocated_encoding(s
);
8709 if (!fp_access_check(s
)) {
8714 narrowfn
= unsigned_narrow_fns
[size
];
8716 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8719 tcg_rn
= tcg_temp_new_i64();
8720 tcg_rd
= tcg_temp_new_i64();
8721 tcg_rd_narrowed
= tcg_temp_new_i32();
8722 tcg_final
= tcg_const_i64(0);
8725 uint64_t round_const
= 1ULL << (shift
- 1);
8726 tcg_round
= tcg_const_i64(round_const
);
8731 for (i
= 0; i
< elements
; i
++) {
8732 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8733 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8734 false, is_u_shift
, size
+1, shift
);
8735 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8736 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8737 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8741 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8743 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8747 tcg_temp_free_i64(tcg_round
);
8749 tcg_temp_free_i64(tcg_rn
);
8750 tcg_temp_free_i64(tcg_rd
);
8751 tcg_temp_free_i32(tcg_rd_narrowed
);
8752 tcg_temp_free_i64(tcg_final
);
8754 clear_vec_high(s
, is_q
, rd
);
8757 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8758 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8759 bool src_unsigned
, bool dst_unsigned
,
8760 int immh
, int immb
, int rn
, int rd
)
8762 int immhb
= immh
<< 3 | immb
;
8763 int size
= 32 - clz32(immh
) - 1;
8764 int shift
= immhb
- (8 << size
);
8768 assert(!(scalar
&& is_q
));
8771 if (!is_q
&& extract32(immh
, 3, 1)) {
8772 unallocated_encoding(s
);
8776 /* Since we use the variable-shift helpers we must
8777 * replicate the shift count into each element of
8778 * the tcg_shift value.
8782 shift
|= shift
<< 8;
8785 shift
|= shift
<< 16;
8791 g_assert_not_reached();
8795 if (!fp_access_check(s
)) {
8800 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8801 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8802 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8803 { NULL
, gen_helper_neon_qshl_u64
},
8805 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8806 int maxpass
= is_q
? 2 : 1;
8808 for (pass
= 0; pass
< maxpass
; pass
++) {
8809 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8811 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8812 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8813 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8815 tcg_temp_free_i64(tcg_op
);
8817 tcg_temp_free_i64(tcg_shift
);
8818 clear_vec_high(s
, is_q
, rd
);
8820 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8821 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8823 { gen_helper_neon_qshl_s8
,
8824 gen_helper_neon_qshl_s16
,
8825 gen_helper_neon_qshl_s32
},
8826 { gen_helper_neon_qshlu_s8
,
8827 gen_helper_neon_qshlu_s16
,
8828 gen_helper_neon_qshlu_s32
}
8830 { NULL
, NULL
, NULL
},
8831 { gen_helper_neon_qshl_u8
,
8832 gen_helper_neon_qshl_u16
,
8833 gen_helper_neon_qshl_u32
}
8836 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8837 MemOp memop
= scalar
? size
: MO_32
;
8838 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8840 for (pass
= 0; pass
< maxpass
; pass
++) {
8841 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8843 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8844 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8848 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8851 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8856 g_assert_not_reached();
8858 write_fp_sreg(s
, rd
, tcg_op
);
8860 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8863 tcg_temp_free_i32(tcg_op
);
8865 tcg_temp_free_i32(tcg_shift
);
8868 clear_vec_high(s
, is_q
, rd
);
8873 /* Common vector code for handling integer to FP conversion */
8874 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8875 int elements
, int is_signed
,
8876 int fracbits
, int size
)
8878 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8879 TCGv_i32 tcg_shift
= NULL
;
8881 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8884 if (fracbits
|| size
== MO_64
) {
8885 tcg_shift
= tcg_const_i32(fracbits
);
8888 if (size
== MO_64
) {
8889 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8890 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8892 for (pass
= 0; pass
< elements
; pass
++) {
8893 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8896 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8897 tcg_shift
, tcg_fpst
);
8899 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8900 tcg_shift
, tcg_fpst
);
8902 if (elements
== 1) {
8903 write_fp_dreg(s
, rd
, tcg_double
);
8905 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8909 tcg_temp_free_i64(tcg_int64
);
8910 tcg_temp_free_i64(tcg_double
);
8913 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8914 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8916 for (pass
= 0; pass
< elements
; pass
++) {
8917 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8923 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8924 tcg_shift
, tcg_fpst
);
8926 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8927 tcg_shift
, tcg_fpst
);
8931 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8933 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8940 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8941 tcg_shift
, tcg_fpst
);
8943 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8944 tcg_shift
, tcg_fpst
);
8948 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8950 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8955 g_assert_not_reached();
8958 if (elements
== 1) {
8959 write_fp_sreg(s
, rd
, tcg_float
);
8961 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8965 tcg_temp_free_i32(tcg_int32
);
8966 tcg_temp_free_i32(tcg_float
);
8969 tcg_temp_free_ptr(tcg_fpst
);
8971 tcg_temp_free_i32(tcg_shift
);
8974 clear_vec_high(s
, elements
<< size
== 16, rd
);
8977 /* UCVTF/SCVTF - Integer to FP conversion */
8978 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8979 bool is_q
, bool is_u
,
8980 int immh
, int immb
, int opcode
,
8983 int size
, elements
, fracbits
;
8984 int immhb
= immh
<< 3 | immb
;
8988 if (!is_scalar
&& !is_q
) {
8989 unallocated_encoding(s
);
8992 } else if (immh
& 4) {
8994 } else if (immh
& 2) {
8996 if (!dc_isar_feature(aa64_fp16
, s
)) {
8997 unallocated_encoding(s
);
9001 /* immh == 0 would be a failure of the decode logic */
9002 g_assert(immh
== 1);
9003 unallocated_encoding(s
);
9010 elements
= (8 << is_q
) >> size
;
9012 fracbits
= (16 << size
) - immhb
;
9014 if (!fp_access_check(s
)) {
9018 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
9021 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
9022 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
9023 bool is_q
, bool is_u
,
9024 int immh
, int immb
, int rn
, int rd
)
9026 int immhb
= immh
<< 3 | immb
;
9027 int pass
, size
, fracbits
;
9028 TCGv_ptr tcg_fpstatus
;
9029 TCGv_i32 tcg_rmode
, tcg_shift
;
9033 if (!is_scalar
&& !is_q
) {
9034 unallocated_encoding(s
);
9037 } else if (immh
& 0x4) {
9039 } else if (immh
& 0x2) {
9041 if (!dc_isar_feature(aa64_fp16
, s
)) {
9042 unallocated_encoding(s
);
9046 /* Should have split out AdvSIMD modified immediate earlier. */
9048 unallocated_encoding(s
);
9052 if (!fp_access_check(s
)) {
9056 assert(!(is_scalar
&& is_q
));
9058 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9059 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9060 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9061 fracbits
= (16 << size
) - immhb
;
9062 tcg_shift
= tcg_const_i32(fracbits
);
9064 if (size
== MO_64
) {
9065 int maxpass
= is_scalar
? 1 : 2;
9067 for (pass
= 0; pass
< maxpass
; pass
++) {
9068 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9070 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9072 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9074 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9076 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9077 tcg_temp_free_i64(tcg_op
);
9079 clear_vec_high(s
, is_q
, rd
);
9081 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9082 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9087 fn
= gen_helper_vfp_touhh
;
9089 fn
= gen_helper_vfp_toshh
;
9094 fn
= gen_helper_vfp_touls
;
9096 fn
= gen_helper_vfp_tosls
;
9100 g_assert_not_reached();
9103 for (pass
= 0; pass
< maxpass
; pass
++) {
9104 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9106 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9107 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9109 write_fp_sreg(s
, rd
, tcg_op
);
9111 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9113 tcg_temp_free_i32(tcg_op
);
9116 clear_vec_high(s
, is_q
, rd
);
9120 tcg_temp_free_ptr(tcg_fpstatus
);
9121 tcg_temp_free_i32(tcg_shift
);
9122 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9123 tcg_temp_free_i32(tcg_rmode
);
9126 /* AdvSIMD scalar shift by immediate
9127 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9128 * +-----+---+-------------+------+------+--------+---+------+------+
9129 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9130 * +-----+---+-------------+------+------+--------+---+------+------+
9132 * This is the scalar version so it works on a fixed sized registers
9134 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9136 int rd
= extract32(insn
, 0, 5);
9137 int rn
= extract32(insn
, 5, 5);
9138 int opcode
= extract32(insn
, 11, 5);
9139 int immb
= extract32(insn
, 16, 3);
9140 int immh
= extract32(insn
, 19, 4);
9141 bool is_u
= extract32(insn
, 29, 1);
9144 unallocated_encoding(s
);
9149 case 0x08: /* SRI */
9151 unallocated_encoding(s
);
9155 case 0x00: /* SSHR / USHR */
9156 case 0x02: /* SSRA / USRA */
9157 case 0x04: /* SRSHR / URSHR */
9158 case 0x06: /* SRSRA / URSRA */
9159 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9161 case 0x0a: /* SHL / SLI */
9162 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9164 case 0x1c: /* SCVTF, UCVTF */
9165 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9168 case 0x10: /* SQSHRUN, SQSHRUN2 */
9169 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9171 unallocated_encoding(s
);
9174 handle_vec_simd_sqshrn(s
, true, false, false, true,
9175 immh
, immb
, opcode
, rn
, rd
);
9177 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9178 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9179 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9180 immh
, immb
, opcode
, rn
, rd
);
9182 case 0xc: /* SQSHLU */
9184 unallocated_encoding(s
);
9187 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9189 case 0xe: /* SQSHL, UQSHL */
9190 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9192 case 0x1f: /* FCVTZS, FCVTZU */
9193 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9196 unallocated_encoding(s
);
9201 /* AdvSIMD scalar three different
9202 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9203 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9204 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9205 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9207 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9209 bool is_u
= extract32(insn
, 29, 1);
9210 int size
= extract32(insn
, 22, 2);
9211 int opcode
= extract32(insn
, 12, 4);
9212 int rm
= extract32(insn
, 16, 5);
9213 int rn
= extract32(insn
, 5, 5);
9214 int rd
= extract32(insn
, 0, 5);
9217 unallocated_encoding(s
);
9222 case 0x9: /* SQDMLAL, SQDMLAL2 */
9223 case 0xb: /* SQDMLSL, SQDMLSL2 */
9224 case 0xd: /* SQDMULL, SQDMULL2 */
9225 if (size
== 0 || size
== 3) {
9226 unallocated_encoding(s
);
9231 unallocated_encoding(s
);
9235 if (!fp_access_check(s
)) {
9240 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9241 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9242 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9244 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9245 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9247 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9248 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9251 case 0xd: /* SQDMULL, SQDMULL2 */
9253 case 0xb: /* SQDMLSL, SQDMLSL2 */
9254 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9256 case 0x9: /* SQDMLAL, SQDMLAL2 */
9257 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9258 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9262 g_assert_not_reached();
9265 write_fp_dreg(s
, rd
, tcg_res
);
9267 tcg_temp_free_i64(tcg_op1
);
9268 tcg_temp_free_i64(tcg_op2
);
9269 tcg_temp_free_i64(tcg_res
);
9271 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9272 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9273 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9275 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9276 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9279 case 0xd: /* SQDMULL, SQDMULL2 */
9281 case 0xb: /* SQDMLSL, SQDMLSL2 */
9282 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9284 case 0x9: /* SQDMLAL, SQDMLAL2 */
9286 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9287 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9288 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9290 tcg_temp_free_i64(tcg_op3
);
9294 g_assert_not_reached();
9297 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9298 write_fp_dreg(s
, rd
, tcg_res
);
9300 tcg_temp_free_i32(tcg_op1
);
9301 tcg_temp_free_i32(tcg_op2
);
9302 tcg_temp_free_i64(tcg_res
);
9306 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9307 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9309 /* Handle 64x64->64 opcodes which are shared between the scalar
9310 * and vector 3-same groups. We cover every opcode where size == 3
9311 * is valid in either the three-reg-same (integer, not pairwise)
9312 * or scalar-three-reg-same groups.
9317 case 0x1: /* SQADD */
9319 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9321 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9324 case 0x5: /* SQSUB */
9326 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9328 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9331 case 0x6: /* CMGT, CMHI */
9332 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9333 * We implement this using setcond (test) and then negating.
9335 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9337 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9338 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9340 case 0x7: /* CMGE, CMHS */
9341 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9343 case 0x11: /* CMTST, CMEQ */
9348 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9350 case 0x8: /* SSHL, USHL */
9352 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9354 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9357 case 0x9: /* SQSHL, UQSHL */
9359 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9361 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9364 case 0xa: /* SRSHL, URSHL */
9366 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9368 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9371 case 0xb: /* SQRSHL, UQRSHL */
9373 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9375 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9378 case 0x10: /* ADD, SUB */
9380 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9382 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9386 g_assert_not_reached();
9390 /* Handle the 3-same-operands float operations; shared by the scalar
9391 * and vector encodings. The caller must filter out any encodings
9392 * not allocated for the encoding it is dealing with.
9394 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9395 int fpopcode
, int rd
, int rn
, int rm
)
9398 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9400 for (pass
= 0; pass
< elements
; pass
++) {
9403 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9404 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9405 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9407 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9408 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9411 case 0x39: /* FMLS */
9412 /* As usual for ARM, separate negation for fused multiply-add */
9413 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9415 case 0x19: /* FMLA */
9416 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9417 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9420 case 0x18: /* FMAXNM */
9421 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9423 case 0x1a: /* FADD */
9424 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9426 case 0x1b: /* FMULX */
9427 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9429 case 0x1c: /* FCMEQ */
9430 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9432 case 0x1e: /* FMAX */
9433 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9435 case 0x1f: /* FRECPS */
9436 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9438 case 0x38: /* FMINNM */
9439 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9441 case 0x3a: /* FSUB */
9442 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9444 case 0x3e: /* FMIN */
9445 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9447 case 0x3f: /* FRSQRTS */
9448 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9450 case 0x5b: /* FMUL */
9451 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9453 case 0x5c: /* FCMGE */
9454 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9456 case 0x5d: /* FACGE */
9457 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9459 case 0x5f: /* FDIV */
9460 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9462 case 0x7a: /* FABD */
9463 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9464 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9466 case 0x7c: /* FCMGT */
9467 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9469 case 0x7d: /* FACGT */
9470 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9473 g_assert_not_reached();
9476 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9478 tcg_temp_free_i64(tcg_res
);
9479 tcg_temp_free_i64(tcg_op1
);
9480 tcg_temp_free_i64(tcg_op2
);
9483 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9484 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9485 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9487 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9488 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9491 case 0x39: /* FMLS */
9492 /* As usual for ARM, separate negation for fused multiply-add */
9493 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9495 case 0x19: /* FMLA */
9496 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9497 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9500 case 0x1a: /* FADD */
9501 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9503 case 0x1b: /* FMULX */
9504 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9506 case 0x1c: /* FCMEQ */
9507 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9509 case 0x1e: /* FMAX */
9510 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9512 case 0x1f: /* FRECPS */
9513 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9515 case 0x18: /* FMAXNM */
9516 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9518 case 0x38: /* FMINNM */
9519 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9521 case 0x3a: /* FSUB */
9522 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9524 case 0x3e: /* FMIN */
9525 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9527 case 0x3f: /* FRSQRTS */
9528 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9530 case 0x5b: /* FMUL */
9531 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9533 case 0x5c: /* FCMGE */
9534 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9536 case 0x5d: /* FACGE */
9537 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9539 case 0x5f: /* FDIV */
9540 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9542 case 0x7a: /* FABD */
9543 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9544 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9546 case 0x7c: /* FCMGT */
9547 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9549 case 0x7d: /* FACGT */
9550 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9553 g_assert_not_reached();
9556 if (elements
== 1) {
9557 /* scalar single so clear high part */
9558 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9560 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9561 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9562 tcg_temp_free_i64(tcg_tmp
);
9564 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9567 tcg_temp_free_i32(tcg_res
);
9568 tcg_temp_free_i32(tcg_op1
);
9569 tcg_temp_free_i32(tcg_op2
);
9573 tcg_temp_free_ptr(fpst
);
9575 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9578 /* AdvSIMD scalar three same
9579 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9580 * +-----+---+-----------+------+---+------+--------+---+------+------+
9581 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9582 * +-----+---+-----------+------+---+------+--------+---+------+------+
9584 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9586 int rd
= extract32(insn
, 0, 5);
9587 int rn
= extract32(insn
, 5, 5);
9588 int opcode
= extract32(insn
, 11, 5);
9589 int rm
= extract32(insn
, 16, 5);
9590 int size
= extract32(insn
, 22, 2);
9591 bool u
= extract32(insn
, 29, 1);
9594 if (opcode
>= 0x18) {
9595 /* Floating point: U, size[1] and opcode indicate operation */
9596 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9598 case 0x1b: /* FMULX */
9599 case 0x1f: /* FRECPS */
9600 case 0x3f: /* FRSQRTS */
9601 case 0x5d: /* FACGE */
9602 case 0x7d: /* FACGT */
9603 case 0x1c: /* FCMEQ */
9604 case 0x5c: /* FCMGE */
9605 case 0x7c: /* FCMGT */
9606 case 0x7a: /* FABD */
9609 unallocated_encoding(s
);
9613 if (!fp_access_check(s
)) {
9617 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9622 case 0x1: /* SQADD, UQADD */
9623 case 0x5: /* SQSUB, UQSUB */
9624 case 0x9: /* SQSHL, UQSHL */
9625 case 0xb: /* SQRSHL, UQRSHL */
9627 case 0x8: /* SSHL, USHL */
9628 case 0xa: /* SRSHL, URSHL */
9629 case 0x6: /* CMGT, CMHI */
9630 case 0x7: /* CMGE, CMHS */
9631 case 0x11: /* CMTST, CMEQ */
9632 case 0x10: /* ADD, SUB (vector) */
9634 unallocated_encoding(s
);
9638 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9639 if (size
!= 1 && size
!= 2) {
9640 unallocated_encoding(s
);
9645 unallocated_encoding(s
);
9649 if (!fp_access_check(s
)) {
9653 tcg_rd
= tcg_temp_new_i64();
9656 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9657 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9659 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9660 tcg_temp_free_i64(tcg_rn
);
9661 tcg_temp_free_i64(tcg_rm
);
9663 /* Do a single operation on the lowest element in the vector.
9664 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9665 * no side effects for all these operations.
9666 * OPTME: special-purpose helpers would avoid doing some
9667 * unnecessary work in the helper for the 8 and 16 bit cases.
9669 NeonGenTwoOpEnvFn
*genenvfn
;
9670 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9671 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9672 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9674 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9675 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9678 case 0x1: /* SQADD, UQADD */
9680 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9681 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9682 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9683 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9685 genenvfn
= fns
[size
][u
];
9688 case 0x5: /* SQSUB, UQSUB */
9690 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9691 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9692 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9693 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9695 genenvfn
= fns
[size
][u
];
9698 case 0x9: /* SQSHL, UQSHL */
9700 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9701 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9702 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9703 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9705 genenvfn
= fns
[size
][u
];
9708 case 0xb: /* SQRSHL, UQRSHL */
9710 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9711 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9712 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9713 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9715 genenvfn
= fns
[size
][u
];
9718 case 0x16: /* SQDMULH, SQRDMULH */
9720 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9721 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9722 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9724 assert(size
== 1 || size
== 2);
9725 genenvfn
= fns
[size
- 1][u
];
9729 g_assert_not_reached();
9732 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9733 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9734 tcg_temp_free_i32(tcg_rd32
);
9735 tcg_temp_free_i32(tcg_rn
);
9736 tcg_temp_free_i32(tcg_rm
);
9739 write_fp_dreg(s
, rd
, tcg_rd
);
9741 tcg_temp_free_i64(tcg_rd
);
9744 /* AdvSIMD scalar three same FP16
9745 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9746 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9747 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9748 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9749 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9750 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9752 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9755 int rd
= extract32(insn
, 0, 5);
9756 int rn
= extract32(insn
, 5, 5);
9757 int opcode
= extract32(insn
, 11, 3);
9758 int rm
= extract32(insn
, 16, 5);
9759 bool u
= extract32(insn
, 29, 1);
9760 bool a
= extract32(insn
, 23, 1);
9761 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9768 case 0x03: /* FMULX */
9769 case 0x04: /* FCMEQ (reg) */
9770 case 0x07: /* FRECPS */
9771 case 0x0f: /* FRSQRTS */
9772 case 0x14: /* FCMGE (reg) */
9773 case 0x15: /* FACGE */
9774 case 0x1a: /* FABD */
9775 case 0x1c: /* FCMGT (reg) */
9776 case 0x1d: /* FACGT */
9779 unallocated_encoding(s
);
9783 if (!dc_isar_feature(aa64_fp16
, s
)) {
9784 unallocated_encoding(s
);
9787 if (!fp_access_check(s
)) {
9791 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9793 tcg_op1
= read_fp_hreg(s
, rn
);
9794 tcg_op2
= read_fp_hreg(s
, rm
);
9795 tcg_res
= tcg_temp_new_i32();
9798 case 0x03: /* FMULX */
9799 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9801 case 0x04: /* FCMEQ (reg) */
9802 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9804 case 0x07: /* FRECPS */
9805 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9807 case 0x0f: /* FRSQRTS */
9808 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9810 case 0x14: /* FCMGE (reg) */
9811 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9813 case 0x15: /* FACGE */
9814 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9816 case 0x1a: /* FABD */
9817 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9818 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9820 case 0x1c: /* FCMGT (reg) */
9821 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9823 case 0x1d: /* FACGT */
9824 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9827 g_assert_not_reached();
9830 write_fp_sreg(s
, rd
, tcg_res
);
9833 tcg_temp_free_i32(tcg_res
);
9834 tcg_temp_free_i32(tcg_op1
);
9835 tcg_temp_free_i32(tcg_op2
);
9836 tcg_temp_free_ptr(fpst
);
9839 /* AdvSIMD scalar three same extra
9840 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9841 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9842 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9843 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9845 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9848 int rd
= extract32(insn
, 0, 5);
9849 int rn
= extract32(insn
, 5, 5);
9850 int opcode
= extract32(insn
, 11, 4);
9851 int rm
= extract32(insn
, 16, 5);
9852 int size
= extract32(insn
, 22, 2);
9853 bool u
= extract32(insn
, 29, 1);
9854 TCGv_i32 ele1
, ele2
, ele3
;
9858 switch (u
* 16 + opcode
) {
9859 case 0x10: /* SQRDMLAH (vector) */
9860 case 0x11: /* SQRDMLSH (vector) */
9861 if (size
!= 1 && size
!= 2) {
9862 unallocated_encoding(s
);
9865 feature
= dc_isar_feature(aa64_rdm
, s
);
9868 unallocated_encoding(s
);
9872 unallocated_encoding(s
);
9875 if (!fp_access_check(s
)) {
9879 /* Do a single operation on the lowest element in the vector.
9880 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9881 * with no side effects for all these operations.
9882 * OPTME: special-purpose helpers would avoid doing some
9883 * unnecessary work in the helper for the 16 bit cases.
9885 ele1
= tcg_temp_new_i32();
9886 ele2
= tcg_temp_new_i32();
9887 ele3
= tcg_temp_new_i32();
9889 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9890 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9891 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9894 case 0x0: /* SQRDMLAH */
9896 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9898 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9901 case 0x1: /* SQRDMLSH */
9903 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9905 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9909 g_assert_not_reached();
9911 tcg_temp_free_i32(ele1
);
9912 tcg_temp_free_i32(ele2
);
9914 res
= tcg_temp_new_i64();
9915 tcg_gen_extu_i32_i64(res
, ele3
);
9916 tcg_temp_free_i32(ele3
);
9918 write_fp_dreg(s
, rd
, res
);
9919 tcg_temp_free_i64(res
);
9922 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9923 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9924 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9926 /* Handle 64->64 opcodes which are shared between the scalar and
9927 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9928 * is valid in either group and also the double-precision fp ops.
9929 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9935 case 0x4: /* CLS, CLZ */
9937 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9939 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9943 /* This opcode is shared with CNT and RBIT but we have earlier
9944 * enforced that size == 3 if and only if this is the NOT insn.
9946 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9948 case 0x7: /* SQABS, SQNEG */
9950 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9952 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9955 case 0xa: /* CMLT */
9956 /* 64 bit integer comparison against zero, result is
9957 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9962 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9963 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9965 case 0x8: /* CMGT, CMGE */
9966 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9968 case 0x9: /* CMEQ, CMLE */
9969 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9971 case 0xb: /* ABS, NEG */
9973 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9975 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9978 case 0x2f: /* FABS */
9979 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9981 case 0x6f: /* FNEG */
9982 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9984 case 0x7f: /* FSQRT */
9985 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9987 case 0x1a: /* FCVTNS */
9988 case 0x1b: /* FCVTMS */
9989 case 0x1c: /* FCVTAS */
9990 case 0x3a: /* FCVTPS */
9991 case 0x3b: /* FCVTZS */
9993 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9994 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9995 tcg_temp_free_i32(tcg_shift
);
9998 case 0x5a: /* FCVTNU */
9999 case 0x5b: /* FCVTMU */
10000 case 0x5c: /* FCVTAU */
10001 case 0x7a: /* FCVTPU */
10002 case 0x7b: /* FCVTZU */
10004 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10005 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10006 tcg_temp_free_i32(tcg_shift
);
10009 case 0x18: /* FRINTN */
10010 case 0x19: /* FRINTM */
10011 case 0x38: /* FRINTP */
10012 case 0x39: /* FRINTZ */
10013 case 0x58: /* FRINTA */
10014 case 0x79: /* FRINTI */
10015 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10017 case 0x59: /* FRINTX */
10018 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10020 case 0x1e: /* FRINT32Z */
10021 case 0x5e: /* FRINT32X */
10022 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10024 case 0x1f: /* FRINT64Z */
10025 case 0x5f: /* FRINT64X */
10026 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10029 g_assert_not_reached();
10033 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
10034 bool is_scalar
, bool is_u
, bool is_q
,
10035 int size
, int rn
, int rd
)
10037 bool is_double
= (size
== MO_64
);
10040 if (!fp_access_check(s
)) {
10044 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
10047 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10048 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10049 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10050 NeonGenTwoDoubleOpFn
*genfn
;
10055 case 0x2e: /* FCMLT (zero) */
10058 case 0x2c: /* FCMGT (zero) */
10059 genfn
= gen_helper_neon_cgt_f64
;
10061 case 0x2d: /* FCMEQ (zero) */
10062 genfn
= gen_helper_neon_ceq_f64
;
10064 case 0x6d: /* FCMLE (zero) */
10067 case 0x6c: /* FCMGE (zero) */
10068 genfn
= gen_helper_neon_cge_f64
;
10071 g_assert_not_reached();
10074 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10075 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10077 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10079 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10081 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10083 tcg_temp_free_i64(tcg_res
);
10084 tcg_temp_free_i64(tcg_zero
);
10085 tcg_temp_free_i64(tcg_op
);
10087 clear_vec_high(s
, !is_scalar
, rd
);
10089 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10090 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10091 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10092 NeonGenTwoSingleOpFn
*genfn
;
10094 int pass
, maxpasses
;
10096 if (size
== MO_16
) {
10098 case 0x2e: /* FCMLT (zero) */
10101 case 0x2c: /* FCMGT (zero) */
10102 genfn
= gen_helper_advsimd_cgt_f16
;
10104 case 0x2d: /* FCMEQ (zero) */
10105 genfn
= gen_helper_advsimd_ceq_f16
;
10107 case 0x6d: /* FCMLE (zero) */
10110 case 0x6c: /* FCMGE (zero) */
10111 genfn
= gen_helper_advsimd_cge_f16
;
10114 g_assert_not_reached();
10118 case 0x2e: /* FCMLT (zero) */
10121 case 0x2c: /* FCMGT (zero) */
10122 genfn
= gen_helper_neon_cgt_f32
;
10124 case 0x2d: /* FCMEQ (zero) */
10125 genfn
= gen_helper_neon_ceq_f32
;
10127 case 0x6d: /* FCMLE (zero) */
10130 case 0x6c: /* FCMGE (zero) */
10131 genfn
= gen_helper_neon_cge_f32
;
10134 g_assert_not_reached();
10141 int vector_size
= 8 << is_q
;
10142 maxpasses
= vector_size
>> size
;
10145 for (pass
= 0; pass
< maxpasses
; pass
++) {
10146 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10148 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10150 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10153 write_fp_sreg(s
, rd
, tcg_res
);
10155 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10158 tcg_temp_free_i32(tcg_res
);
10159 tcg_temp_free_i32(tcg_zero
);
10160 tcg_temp_free_i32(tcg_op
);
10162 clear_vec_high(s
, is_q
, rd
);
10166 tcg_temp_free_ptr(fpst
);
10169 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10170 bool is_scalar
, bool is_u
, bool is_q
,
10171 int size
, int rn
, int rd
)
10173 bool is_double
= (size
== 3);
10174 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10177 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10178 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10181 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10182 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10184 case 0x3d: /* FRECPE */
10185 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10187 case 0x3f: /* FRECPX */
10188 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10190 case 0x7d: /* FRSQRTE */
10191 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10194 g_assert_not_reached();
10196 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10198 tcg_temp_free_i64(tcg_res
);
10199 tcg_temp_free_i64(tcg_op
);
10200 clear_vec_high(s
, !is_scalar
, rd
);
10202 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10203 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10204 int pass
, maxpasses
;
10209 maxpasses
= is_q
? 4 : 2;
10212 for (pass
= 0; pass
< maxpasses
; pass
++) {
10213 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10216 case 0x3c: /* URECPE */
10217 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10219 case 0x3d: /* FRECPE */
10220 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10222 case 0x3f: /* FRECPX */
10223 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10225 case 0x7d: /* FRSQRTE */
10226 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10229 g_assert_not_reached();
10233 write_fp_sreg(s
, rd
, tcg_res
);
10235 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10238 tcg_temp_free_i32(tcg_res
);
10239 tcg_temp_free_i32(tcg_op
);
10241 clear_vec_high(s
, is_q
, rd
);
10244 tcg_temp_free_ptr(fpst
);
10247 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10248 int opcode
, bool u
, bool is_q
,
10249 int size
, int rn
, int rd
)
10251 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10252 * in the source becomes a size element in the destination).
10255 TCGv_i32 tcg_res
[2];
10256 int destelt
= is_q
? 2 : 0;
10257 int passes
= scalar
? 1 : 2;
10260 tcg_res
[1] = tcg_const_i32(0);
10263 for (pass
= 0; pass
< passes
; pass
++) {
10264 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10265 NeonGenNarrowFn
*genfn
= NULL
;
10266 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10269 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10271 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10273 tcg_res
[pass
] = tcg_temp_new_i32();
10276 case 0x12: /* XTN, SQXTUN */
10278 static NeonGenNarrowFn
* const xtnfns
[3] = {
10279 gen_helper_neon_narrow_u8
,
10280 gen_helper_neon_narrow_u16
,
10281 tcg_gen_extrl_i64_i32
,
10283 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10284 gen_helper_neon_unarrow_sat8
,
10285 gen_helper_neon_unarrow_sat16
,
10286 gen_helper_neon_unarrow_sat32
,
10289 genenvfn
= sqxtunfns
[size
];
10291 genfn
= xtnfns
[size
];
10295 case 0x14: /* SQXTN, UQXTN */
10297 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10298 { gen_helper_neon_narrow_sat_s8
,
10299 gen_helper_neon_narrow_sat_u8
},
10300 { gen_helper_neon_narrow_sat_s16
,
10301 gen_helper_neon_narrow_sat_u16
},
10302 { gen_helper_neon_narrow_sat_s32
,
10303 gen_helper_neon_narrow_sat_u32
},
10305 genenvfn
= fns
[size
][u
];
10308 case 0x16: /* FCVTN, FCVTN2 */
10309 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10311 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10313 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10314 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10315 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10316 TCGv_i32 ahp
= get_ahp_flag();
10318 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10319 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10320 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10321 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10322 tcg_temp_free_i32(tcg_lo
);
10323 tcg_temp_free_i32(tcg_hi
);
10324 tcg_temp_free_ptr(fpst
);
10325 tcg_temp_free_i32(ahp
);
10328 case 0x56: /* FCVTXN, FCVTXN2 */
10329 /* 64 bit to 32 bit float conversion
10330 * with von Neumann rounding (round to odd)
10333 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10336 g_assert_not_reached();
10340 genfn(tcg_res
[pass
], tcg_op
);
10341 } else if (genenvfn
) {
10342 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10345 tcg_temp_free_i64(tcg_op
);
10348 for (pass
= 0; pass
< 2; pass
++) {
10349 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10350 tcg_temp_free_i32(tcg_res
[pass
]);
10352 clear_vec_high(s
, is_q
, rd
);
10355 /* Remaining saturating accumulating ops */
10356 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10357 bool is_q
, int size
, int rn
, int rd
)
10359 bool is_double
= (size
== 3);
10362 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10363 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10366 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10367 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10368 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10370 if (is_u
) { /* USQADD */
10371 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10372 } else { /* SUQADD */
10373 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10375 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10377 tcg_temp_free_i64(tcg_rd
);
10378 tcg_temp_free_i64(tcg_rn
);
10379 clear_vec_high(s
, !is_scalar
, rd
);
10381 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10382 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10383 int pass
, maxpasses
;
10388 maxpasses
= is_q
? 4 : 2;
10391 for (pass
= 0; pass
< maxpasses
; pass
++) {
10393 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10394 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10396 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10397 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10400 if (is_u
) { /* USQADD */
10403 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10406 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10409 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10412 g_assert_not_reached();
10414 } else { /* SUQADD */
10417 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10420 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10423 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10426 g_assert_not_reached();
10431 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10432 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10433 tcg_temp_free_i64(tcg_zero
);
10435 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10437 tcg_temp_free_i32(tcg_rd
);
10438 tcg_temp_free_i32(tcg_rn
);
10439 clear_vec_high(s
, is_q
, rd
);
10443 /* AdvSIMD scalar two reg misc
10444 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10445 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10446 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10447 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10449 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10451 int rd
= extract32(insn
, 0, 5);
10452 int rn
= extract32(insn
, 5, 5);
10453 int opcode
= extract32(insn
, 12, 5);
10454 int size
= extract32(insn
, 22, 2);
10455 bool u
= extract32(insn
, 29, 1);
10456 bool is_fcvt
= false;
10458 TCGv_i32 tcg_rmode
;
10459 TCGv_ptr tcg_fpstatus
;
10462 case 0x3: /* USQADD / SUQADD*/
10463 if (!fp_access_check(s
)) {
10466 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10468 case 0x7: /* SQABS / SQNEG */
10470 case 0xa: /* CMLT */
10472 unallocated_encoding(s
);
10476 case 0x8: /* CMGT, CMGE */
10477 case 0x9: /* CMEQ, CMLE */
10478 case 0xb: /* ABS, NEG */
10480 unallocated_encoding(s
);
10484 case 0x12: /* SQXTUN */
10486 unallocated_encoding(s
);
10490 case 0x14: /* SQXTN, UQXTN */
10492 unallocated_encoding(s
);
10495 if (!fp_access_check(s
)) {
10498 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10501 case 0x16 ... 0x1d:
10503 /* Floating point: U, size[1] and opcode indicate operation;
10504 * size[0] indicates single or double precision.
10506 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10507 size
= extract32(size
, 0, 1) ? 3 : 2;
10509 case 0x2c: /* FCMGT (zero) */
10510 case 0x2d: /* FCMEQ (zero) */
10511 case 0x2e: /* FCMLT (zero) */
10512 case 0x6c: /* FCMGE (zero) */
10513 case 0x6d: /* FCMLE (zero) */
10514 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10516 case 0x1d: /* SCVTF */
10517 case 0x5d: /* UCVTF */
10519 bool is_signed
= (opcode
== 0x1d);
10520 if (!fp_access_check(s
)) {
10523 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10526 case 0x3d: /* FRECPE */
10527 case 0x3f: /* FRECPX */
10528 case 0x7d: /* FRSQRTE */
10529 if (!fp_access_check(s
)) {
10532 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10534 case 0x1a: /* FCVTNS */
10535 case 0x1b: /* FCVTMS */
10536 case 0x3a: /* FCVTPS */
10537 case 0x3b: /* FCVTZS */
10538 case 0x5a: /* FCVTNU */
10539 case 0x5b: /* FCVTMU */
10540 case 0x7a: /* FCVTPU */
10541 case 0x7b: /* FCVTZU */
10543 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10545 case 0x1c: /* FCVTAS */
10546 case 0x5c: /* FCVTAU */
10547 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10549 rmode
= FPROUNDING_TIEAWAY
;
10551 case 0x56: /* FCVTXN, FCVTXN2 */
10553 unallocated_encoding(s
);
10556 if (!fp_access_check(s
)) {
10559 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10562 unallocated_encoding(s
);
10567 unallocated_encoding(s
);
10571 if (!fp_access_check(s
)) {
10576 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10577 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10578 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10581 tcg_fpstatus
= NULL
;
10585 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10586 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10588 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10589 write_fp_dreg(s
, rd
, tcg_rd
);
10590 tcg_temp_free_i64(tcg_rd
);
10591 tcg_temp_free_i64(tcg_rn
);
10593 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10594 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10596 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10599 case 0x7: /* SQABS, SQNEG */
10601 NeonGenOneOpEnvFn
*genfn
;
10602 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10603 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10604 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10605 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10607 genfn
= fns
[size
][u
];
10608 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10611 case 0x1a: /* FCVTNS */
10612 case 0x1b: /* FCVTMS */
10613 case 0x1c: /* FCVTAS */
10614 case 0x3a: /* FCVTPS */
10615 case 0x3b: /* FCVTZS */
10617 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10618 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10619 tcg_temp_free_i32(tcg_shift
);
10622 case 0x5a: /* FCVTNU */
10623 case 0x5b: /* FCVTMU */
10624 case 0x5c: /* FCVTAU */
10625 case 0x7a: /* FCVTPU */
10626 case 0x7b: /* FCVTZU */
10628 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10629 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10630 tcg_temp_free_i32(tcg_shift
);
10634 g_assert_not_reached();
10637 write_fp_sreg(s
, rd
, tcg_rd
);
10638 tcg_temp_free_i32(tcg_rd
);
10639 tcg_temp_free_i32(tcg_rn
);
10643 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10644 tcg_temp_free_i32(tcg_rmode
);
10645 tcg_temp_free_ptr(tcg_fpstatus
);
10649 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10650 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10651 int immh
, int immb
, int opcode
, int rn
, int rd
)
10653 int size
= 32 - clz32(immh
) - 1;
10654 int immhb
= immh
<< 3 | immb
;
10655 int shift
= 2 * (8 << size
) - immhb
;
10656 GVecGen2iFn
*gvec_fn
;
10658 if (extract32(immh
, 3, 1) && !is_q
) {
10659 unallocated_encoding(s
);
10662 tcg_debug_assert(size
<= 3);
10664 if (!fp_access_check(s
)) {
10669 case 0x02: /* SSRA / USRA (accumulate) */
10670 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10673 case 0x08: /* SRI */
10674 gvec_fn
= gen_gvec_sri
;
10677 case 0x00: /* SSHR / USHR */
10679 if (shift
== 8 << size
) {
10680 /* Shift count the same size as element size produces zero. */
10681 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10682 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10685 gvec_fn
= tcg_gen_gvec_shri
;
10687 /* Shift count the same size as element size produces all sign. */
10688 if (shift
== 8 << size
) {
10691 gvec_fn
= tcg_gen_gvec_sari
;
10695 case 0x04: /* SRSHR / URSHR (rounding) */
10696 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10699 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10700 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10704 g_assert_not_reached();
10707 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10710 /* SHL/SLI - Vector shift left */
10711 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10712 int immh
, int immb
, int opcode
, int rn
, int rd
)
10714 int size
= 32 - clz32(immh
) - 1;
10715 int immhb
= immh
<< 3 | immb
;
10716 int shift
= immhb
- (8 << size
);
10718 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10719 assert(size
>= 0 && size
<= 3);
10721 if (extract32(immh
, 3, 1) && !is_q
) {
10722 unallocated_encoding(s
);
10726 if (!fp_access_check(s
)) {
10731 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10733 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10737 /* USHLL/SHLL - Vector shift left with widening */
10738 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10739 int immh
, int immb
, int opcode
, int rn
, int rd
)
10741 int size
= 32 - clz32(immh
) - 1;
10742 int immhb
= immh
<< 3 | immb
;
10743 int shift
= immhb
- (8 << size
);
10745 int esize
= 8 << size
;
10746 int elements
= dsize
/esize
;
10747 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10748 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10752 unallocated_encoding(s
);
10756 if (!fp_access_check(s
)) {
10760 /* For the LL variants the store is larger than the load,
10761 * so if rd == rn we would overwrite parts of our input.
10762 * So load everything right now and use shifts in the main loop.
10764 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10766 for (i
= 0; i
< elements
; i
++) {
10767 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10768 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10769 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10770 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10774 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10775 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10776 int immh
, int immb
, int opcode
, int rn
, int rd
)
10778 int immhb
= immh
<< 3 | immb
;
10779 int size
= 32 - clz32(immh
) - 1;
10781 int esize
= 8 << size
;
10782 int elements
= dsize
/esize
;
10783 int shift
= (2 * esize
) - immhb
;
10784 bool round
= extract32(opcode
, 0, 1);
10785 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10786 TCGv_i64 tcg_round
;
10789 if (extract32(immh
, 3, 1)) {
10790 unallocated_encoding(s
);
10794 if (!fp_access_check(s
)) {
10798 tcg_rn
= tcg_temp_new_i64();
10799 tcg_rd
= tcg_temp_new_i64();
10800 tcg_final
= tcg_temp_new_i64();
10801 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10804 uint64_t round_const
= 1ULL << (shift
- 1);
10805 tcg_round
= tcg_const_i64(round_const
);
10810 for (i
= 0; i
< elements
; i
++) {
10811 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10812 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10813 false, true, size
+1, shift
);
10815 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10819 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10821 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10824 tcg_temp_free_i64(tcg_round
);
10826 tcg_temp_free_i64(tcg_rn
);
10827 tcg_temp_free_i64(tcg_rd
);
10828 tcg_temp_free_i64(tcg_final
);
10830 clear_vec_high(s
, is_q
, rd
);
10834 /* AdvSIMD shift by immediate
10835 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10836 * +---+---+---+-------------+------+------+--------+---+------+------+
10837 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10838 * +---+---+---+-------------+------+------+--------+---+------+------+
10840 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10842 int rd
= extract32(insn
, 0, 5);
10843 int rn
= extract32(insn
, 5, 5);
10844 int opcode
= extract32(insn
, 11, 5);
10845 int immb
= extract32(insn
, 16, 3);
10846 int immh
= extract32(insn
, 19, 4);
10847 bool is_u
= extract32(insn
, 29, 1);
10848 bool is_q
= extract32(insn
, 30, 1);
10850 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10854 case 0x08: /* SRI */
10856 unallocated_encoding(s
);
10860 case 0x00: /* SSHR / USHR */
10861 case 0x02: /* SSRA / USRA (accumulate) */
10862 case 0x04: /* SRSHR / URSHR (rounding) */
10863 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10864 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10866 case 0x0a: /* SHL / SLI */
10867 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10869 case 0x10: /* SHRN */
10870 case 0x11: /* RSHRN / SQRSHRUN */
10872 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10875 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10878 case 0x12: /* SQSHRN / UQSHRN */
10879 case 0x13: /* SQRSHRN / UQRSHRN */
10880 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10883 case 0x14: /* SSHLL / USHLL */
10884 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10886 case 0x1c: /* SCVTF / UCVTF */
10887 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10890 case 0xc: /* SQSHLU */
10892 unallocated_encoding(s
);
10895 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10897 case 0xe: /* SQSHL, UQSHL */
10898 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10900 case 0x1f: /* FCVTZS/ FCVTZU */
10901 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10904 unallocated_encoding(s
);
10909 /* Generate code to do a "long" addition or subtraction, ie one done in
10910 * TCGv_i64 on vector lanes twice the width specified by size.
10912 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10913 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10915 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10916 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10917 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10918 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10920 NeonGenTwo64OpFn
*genfn
;
10923 genfn
= fns
[size
][is_sub
];
10924 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10927 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10928 int opcode
, int rd
, int rn
, int rm
)
10930 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10931 TCGv_i64 tcg_res
[2];
10934 tcg_res
[0] = tcg_temp_new_i64();
10935 tcg_res
[1] = tcg_temp_new_i64();
10937 /* Does this op do an adding accumulate, a subtracting accumulate,
10938 * or no accumulate at all?
10956 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10957 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10960 /* size == 2 means two 32x32->64 operations; this is worth special
10961 * casing because we can generally handle it inline.
10964 for (pass
= 0; pass
< 2; pass
++) {
10965 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10966 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10967 TCGv_i64 tcg_passres
;
10968 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10970 int elt
= pass
+ is_q
* 2;
10972 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10973 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10976 tcg_passres
= tcg_res
[pass
];
10978 tcg_passres
= tcg_temp_new_i64();
10982 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10983 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10985 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10986 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10988 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10989 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10991 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10992 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10994 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10995 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10996 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10998 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10999 tcg_temp_free_i64(tcg_tmp1
);
11000 tcg_temp_free_i64(tcg_tmp2
);
11003 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11004 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11005 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11006 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11008 case 9: /* SQDMLAL, SQDMLAL2 */
11009 case 11: /* SQDMLSL, SQDMLSL2 */
11010 case 13: /* SQDMULL, SQDMULL2 */
11011 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11012 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
11013 tcg_passres
, tcg_passres
);
11016 g_assert_not_reached();
11019 if (opcode
== 9 || opcode
== 11) {
11020 /* saturating accumulate ops */
11022 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
11024 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
11025 tcg_res
[pass
], tcg_passres
);
11026 } else if (accop
> 0) {
11027 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11028 } else if (accop
< 0) {
11029 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11033 tcg_temp_free_i64(tcg_passres
);
11036 tcg_temp_free_i64(tcg_op1
);
11037 tcg_temp_free_i64(tcg_op2
);
11040 /* size 0 or 1, generally helper functions */
11041 for (pass
= 0; pass
< 2; pass
++) {
11042 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11043 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11044 TCGv_i64 tcg_passres
;
11045 int elt
= pass
+ is_q
* 2;
11047 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
11048 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11051 tcg_passres
= tcg_res
[pass
];
11053 tcg_passres
= tcg_temp_new_i64();
11057 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11058 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11060 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11061 static NeonGenWidenFn
* const widenfns
[2][2] = {
11062 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11063 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11065 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11067 widenfn(tcg_op2_64
, tcg_op2
);
11068 widenfn(tcg_passres
, tcg_op1
);
11069 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11070 tcg_passres
, tcg_op2_64
);
11071 tcg_temp_free_i64(tcg_op2_64
);
11074 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11075 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11078 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11080 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11084 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11086 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11090 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11091 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11092 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11095 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11097 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11101 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11103 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11107 case 9: /* SQDMLAL, SQDMLAL2 */
11108 case 11: /* SQDMLSL, SQDMLSL2 */
11109 case 13: /* SQDMULL, SQDMULL2 */
11111 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11112 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11113 tcg_passres
, tcg_passres
);
11116 g_assert_not_reached();
11118 tcg_temp_free_i32(tcg_op1
);
11119 tcg_temp_free_i32(tcg_op2
);
11122 if (opcode
== 9 || opcode
== 11) {
11123 /* saturating accumulate ops */
11125 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11127 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11131 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11132 tcg_res
[pass
], tcg_passres
);
11134 tcg_temp_free_i64(tcg_passres
);
11139 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11140 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11141 tcg_temp_free_i64(tcg_res
[0]);
11142 tcg_temp_free_i64(tcg_res
[1]);
11145 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11146 int opcode
, int rd
, int rn
, int rm
)
11148 TCGv_i64 tcg_res
[2];
11149 int part
= is_q
? 2 : 0;
11152 for (pass
= 0; pass
< 2; pass
++) {
11153 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11154 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11155 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11156 static NeonGenWidenFn
* const widenfns
[3][2] = {
11157 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11158 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11159 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11161 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11163 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11164 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11165 widenfn(tcg_op2_wide
, tcg_op2
);
11166 tcg_temp_free_i32(tcg_op2
);
11167 tcg_res
[pass
] = tcg_temp_new_i64();
11168 gen_neon_addl(size
, (opcode
== 3),
11169 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11170 tcg_temp_free_i64(tcg_op1
);
11171 tcg_temp_free_i64(tcg_op2_wide
);
11174 for (pass
= 0; pass
< 2; pass
++) {
11175 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11176 tcg_temp_free_i64(tcg_res
[pass
]);
11180 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11182 tcg_gen_addi_i64(in
, in
, 1U << 31);
11183 tcg_gen_extrh_i64_i32(res
, in
);
11186 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11187 int opcode
, int rd
, int rn
, int rm
)
11189 TCGv_i32 tcg_res
[2];
11190 int part
= is_q
? 2 : 0;
11193 for (pass
= 0; pass
< 2; pass
++) {
11194 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11195 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11196 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11197 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11198 { gen_helper_neon_narrow_high_u8
,
11199 gen_helper_neon_narrow_round_high_u8
},
11200 { gen_helper_neon_narrow_high_u16
,
11201 gen_helper_neon_narrow_round_high_u16
},
11202 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11204 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11206 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11207 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11209 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11211 tcg_temp_free_i64(tcg_op1
);
11212 tcg_temp_free_i64(tcg_op2
);
11214 tcg_res
[pass
] = tcg_temp_new_i32();
11215 gennarrow(tcg_res
[pass
], tcg_wideres
);
11216 tcg_temp_free_i64(tcg_wideres
);
11219 for (pass
= 0; pass
< 2; pass
++) {
11220 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11221 tcg_temp_free_i32(tcg_res
[pass
]);
11223 clear_vec_high(s
, is_q
, rd
);
11226 /* AdvSIMD three different
11227 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11228 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11229 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11230 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11232 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11234 /* Instructions in this group fall into three basic classes
11235 * (in each case with the operation working on each element in
11236 * the input vectors):
11237 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11239 * (2) wide 64 x 128 -> 128
11240 * (3) narrowing 128 x 128 -> 64
11241 * Here we do initial decode, catch unallocated cases and
11242 * dispatch to separate functions for each class.
11244 int is_q
= extract32(insn
, 30, 1);
11245 int is_u
= extract32(insn
, 29, 1);
11246 int size
= extract32(insn
, 22, 2);
11247 int opcode
= extract32(insn
, 12, 4);
11248 int rm
= extract32(insn
, 16, 5);
11249 int rn
= extract32(insn
, 5, 5);
11250 int rd
= extract32(insn
, 0, 5);
11253 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11254 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11255 /* 64 x 128 -> 128 */
11257 unallocated_encoding(s
);
11260 if (!fp_access_check(s
)) {
11263 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11265 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11266 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11267 /* 128 x 128 -> 64 */
11269 unallocated_encoding(s
);
11272 if (!fp_access_check(s
)) {
11275 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11277 case 14: /* PMULL, PMULL2 */
11279 unallocated_encoding(s
);
11283 case 0: /* PMULL.P8 */
11284 if (!fp_access_check(s
)) {
11287 /* The Q field specifies lo/hi half input for this insn. */
11288 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11289 gen_helper_neon_pmull_h
);
11292 case 3: /* PMULL.P64 */
11293 if (!dc_isar_feature(aa64_pmull
, s
)) {
11294 unallocated_encoding(s
);
11297 if (!fp_access_check(s
)) {
11300 /* The Q field specifies lo/hi half input for this insn. */
11301 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11302 gen_helper_gvec_pmull_q
);
11306 unallocated_encoding(s
);
11310 case 9: /* SQDMLAL, SQDMLAL2 */
11311 case 11: /* SQDMLSL, SQDMLSL2 */
11312 case 13: /* SQDMULL, SQDMULL2 */
11313 if (is_u
|| size
== 0) {
11314 unallocated_encoding(s
);
11318 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11319 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11320 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11321 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11322 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11323 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11324 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11325 /* 64 x 64 -> 128 */
11327 unallocated_encoding(s
);
11330 if (!fp_access_check(s
)) {
11334 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11337 /* opcode 15 not allocated */
11338 unallocated_encoding(s
);
11343 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11344 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11346 int rd
= extract32(insn
, 0, 5);
11347 int rn
= extract32(insn
, 5, 5);
11348 int rm
= extract32(insn
, 16, 5);
11349 int size
= extract32(insn
, 22, 2);
11350 bool is_u
= extract32(insn
, 29, 1);
11351 bool is_q
= extract32(insn
, 30, 1);
11353 if (!fp_access_check(s
)) {
11357 switch (size
+ 4 * is_u
) {
11359 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11362 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11365 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11368 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11371 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11374 case 5: /* BSL bitwise select */
11375 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11377 case 6: /* BIT, bitwise insert if true */
11378 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11380 case 7: /* BIF, bitwise insert if false */
11381 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11385 g_assert_not_reached();
11389 /* Pairwise op subgroup of C3.6.16.
11391 * This is called directly or via the handle_3same_float for float pairwise
11392 * operations where the opcode and size are calculated differently.
11394 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11395 int size
, int rn
, int rm
, int rd
)
11400 /* Floating point operations need fpst */
11401 if (opcode
>= 0x58) {
11402 fpst
= fpstatus_ptr(FPST_FPCR
);
11407 if (!fp_access_check(s
)) {
11411 /* These operations work on the concatenated rm:rn, with each pair of
11412 * adjacent elements being operated on to produce an element in the result.
11415 TCGv_i64 tcg_res
[2];
11417 for (pass
= 0; pass
< 2; pass
++) {
11418 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11419 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11420 int passreg
= (pass
== 0) ? rn
: rm
;
11422 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11423 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11424 tcg_res
[pass
] = tcg_temp_new_i64();
11427 case 0x17: /* ADDP */
11428 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11430 case 0x58: /* FMAXNMP */
11431 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11433 case 0x5a: /* FADDP */
11434 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11436 case 0x5e: /* FMAXP */
11437 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11439 case 0x78: /* FMINNMP */
11440 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11442 case 0x7e: /* FMINP */
11443 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11446 g_assert_not_reached();
11449 tcg_temp_free_i64(tcg_op1
);
11450 tcg_temp_free_i64(tcg_op2
);
11453 for (pass
= 0; pass
< 2; pass
++) {
11454 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11455 tcg_temp_free_i64(tcg_res
[pass
]);
11458 int maxpass
= is_q
? 4 : 2;
11459 TCGv_i32 tcg_res
[4];
11461 for (pass
= 0; pass
< maxpass
; pass
++) {
11462 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11463 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11464 NeonGenTwoOpFn
*genfn
= NULL
;
11465 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11466 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11468 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11469 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11470 tcg_res
[pass
] = tcg_temp_new_i32();
11473 case 0x17: /* ADDP */
11475 static NeonGenTwoOpFn
* const fns
[3] = {
11476 gen_helper_neon_padd_u8
,
11477 gen_helper_neon_padd_u16
,
11483 case 0x14: /* SMAXP, UMAXP */
11485 static NeonGenTwoOpFn
* const fns
[3][2] = {
11486 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11487 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11488 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11490 genfn
= fns
[size
][u
];
11493 case 0x15: /* SMINP, UMINP */
11495 static NeonGenTwoOpFn
* const fns
[3][2] = {
11496 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11497 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11498 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11500 genfn
= fns
[size
][u
];
11503 /* The FP operations are all on single floats (32 bit) */
11504 case 0x58: /* FMAXNMP */
11505 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11507 case 0x5a: /* FADDP */
11508 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11510 case 0x5e: /* FMAXP */
11511 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11513 case 0x78: /* FMINNMP */
11514 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11516 case 0x7e: /* FMINP */
11517 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11520 g_assert_not_reached();
11523 /* FP ops called directly, otherwise call now */
11525 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11528 tcg_temp_free_i32(tcg_op1
);
11529 tcg_temp_free_i32(tcg_op2
);
11532 for (pass
= 0; pass
< maxpass
; pass
++) {
11533 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11534 tcg_temp_free_i32(tcg_res
[pass
]);
11536 clear_vec_high(s
, is_q
, rd
);
11540 tcg_temp_free_ptr(fpst
);
11544 /* Floating point op subgroup of C3.6.16. */
11545 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11547 /* For floating point ops, the U, size[1] and opcode bits
11548 * together indicate the operation. size[0] indicates single
11551 int fpopcode
= extract32(insn
, 11, 5)
11552 | (extract32(insn
, 23, 1) << 5)
11553 | (extract32(insn
, 29, 1) << 6);
11554 int is_q
= extract32(insn
, 30, 1);
11555 int size
= extract32(insn
, 22, 1);
11556 int rm
= extract32(insn
, 16, 5);
11557 int rn
= extract32(insn
, 5, 5);
11558 int rd
= extract32(insn
, 0, 5);
11560 int datasize
= is_q
? 128 : 64;
11561 int esize
= 32 << size
;
11562 int elements
= datasize
/ esize
;
11564 if (size
== 1 && !is_q
) {
11565 unallocated_encoding(s
);
11569 switch (fpopcode
) {
11570 case 0x58: /* FMAXNMP */
11571 case 0x5a: /* FADDP */
11572 case 0x5e: /* FMAXP */
11573 case 0x78: /* FMINNMP */
11574 case 0x7e: /* FMINP */
11575 if (size
&& !is_q
) {
11576 unallocated_encoding(s
);
11579 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11582 case 0x1b: /* FMULX */
11583 case 0x1f: /* FRECPS */
11584 case 0x3f: /* FRSQRTS */
11585 case 0x5d: /* FACGE */
11586 case 0x7d: /* FACGT */
11587 case 0x19: /* FMLA */
11588 case 0x39: /* FMLS */
11589 case 0x18: /* FMAXNM */
11590 case 0x1a: /* FADD */
11591 case 0x1c: /* FCMEQ */
11592 case 0x1e: /* FMAX */
11593 case 0x38: /* FMINNM */
11594 case 0x3a: /* FSUB */
11595 case 0x3e: /* FMIN */
11596 case 0x5b: /* FMUL */
11597 case 0x5c: /* FCMGE */
11598 case 0x5f: /* FDIV */
11599 case 0x7a: /* FABD */
11600 case 0x7c: /* FCMGT */
11601 if (!fp_access_check(s
)) {
11604 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11607 case 0x1d: /* FMLAL */
11608 case 0x3d: /* FMLSL */
11609 case 0x59: /* FMLAL2 */
11610 case 0x79: /* FMLSL2 */
11611 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11612 unallocated_encoding(s
);
11615 if (fp_access_check(s
)) {
11616 int is_s
= extract32(insn
, 23, 1);
11617 int is_2
= extract32(insn
, 29, 1);
11618 int data
= (is_2
<< 1) | is_s
;
11619 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11620 vec_full_reg_offset(s
, rn
),
11621 vec_full_reg_offset(s
, rm
), cpu_env
,
11622 is_q
? 16 : 8, vec_full_reg_size(s
),
11623 data
, gen_helper_gvec_fmlal_a64
);
11628 unallocated_encoding(s
);
11633 /* Integer op subgroup of C3.6.16. */
11634 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11636 int is_q
= extract32(insn
, 30, 1);
11637 int u
= extract32(insn
, 29, 1);
11638 int size
= extract32(insn
, 22, 2);
11639 int opcode
= extract32(insn
, 11, 5);
11640 int rm
= extract32(insn
, 16, 5);
11641 int rn
= extract32(insn
, 5, 5);
11642 int rd
= extract32(insn
, 0, 5);
11647 case 0x13: /* MUL, PMUL */
11648 if (u
&& size
!= 0) {
11649 unallocated_encoding(s
);
11653 case 0x0: /* SHADD, UHADD */
11654 case 0x2: /* SRHADD, URHADD */
11655 case 0x4: /* SHSUB, UHSUB */
11656 case 0xc: /* SMAX, UMAX */
11657 case 0xd: /* SMIN, UMIN */
11658 case 0xe: /* SABD, UABD */
11659 case 0xf: /* SABA, UABA */
11660 case 0x12: /* MLA, MLS */
11662 unallocated_encoding(s
);
11666 case 0x16: /* SQDMULH, SQRDMULH */
11667 if (size
== 0 || size
== 3) {
11668 unallocated_encoding(s
);
11673 if (size
== 3 && !is_q
) {
11674 unallocated_encoding(s
);
11680 if (!fp_access_check(s
)) {
11685 case 0x01: /* SQADD, UQADD */
11687 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11689 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11692 case 0x05: /* SQSUB, UQSUB */
11694 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11696 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11699 case 0x08: /* SSHL, USHL */
11701 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11703 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11706 case 0x0c: /* SMAX, UMAX */
11708 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11710 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11713 case 0x0d: /* SMIN, UMIN */
11715 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11717 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11720 case 0xe: /* SABD, UABD */
11722 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11724 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11727 case 0xf: /* SABA, UABA */
11729 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11731 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11734 case 0x10: /* ADD, SUB */
11736 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11738 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11741 case 0x13: /* MUL, PMUL */
11742 if (!u
) { /* MUL */
11743 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11744 } else { /* PMUL */
11745 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11748 case 0x12: /* MLA, MLS */
11750 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11752 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11755 case 0x16: /* SQDMULH, SQRDMULH */
11757 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11758 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11759 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11761 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11765 if (!u
) { /* CMTST */
11766 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11770 cond
= TCG_COND_EQ
;
11772 case 0x06: /* CMGT, CMHI */
11773 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11775 case 0x07: /* CMGE, CMHS */
11776 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11778 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11779 vec_full_reg_offset(s
, rn
),
11780 vec_full_reg_offset(s
, rm
),
11781 is_q
? 16 : 8, vec_full_reg_size(s
));
11787 for (pass
= 0; pass
< 2; pass
++) {
11788 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11789 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11790 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11792 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11793 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11795 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11797 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11799 tcg_temp_free_i64(tcg_res
);
11800 tcg_temp_free_i64(tcg_op1
);
11801 tcg_temp_free_i64(tcg_op2
);
11804 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11805 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11806 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11807 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11808 NeonGenTwoOpFn
*genfn
= NULL
;
11809 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11811 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11812 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11815 case 0x0: /* SHADD, UHADD */
11817 static NeonGenTwoOpFn
* const fns
[3][2] = {
11818 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11819 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11820 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11822 genfn
= fns
[size
][u
];
11825 case 0x2: /* SRHADD, URHADD */
11827 static NeonGenTwoOpFn
* const fns
[3][2] = {
11828 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11829 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11830 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11832 genfn
= fns
[size
][u
];
11835 case 0x4: /* SHSUB, UHSUB */
11837 static NeonGenTwoOpFn
* const fns
[3][2] = {
11838 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11839 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11840 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11842 genfn
= fns
[size
][u
];
11845 case 0x9: /* SQSHL, UQSHL */
11847 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11848 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11849 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11850 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11852 genenvfn
= fns
[size
][u
];
11855 case 0xa: /* SRSHL, URSHL */
11857 static NeonGenTwoOpFn
* const fns
[3][2] = {
11858 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11859 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11860 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11862 genfn
= fns
[size
][u
];
11865 case 0xb: /* SQRSHL, UQRSHL */
11867 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11868 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11869 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11870 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11872 genenvfn
= fns
[size
][u
];
11876 g_assert_not_reached();
11880 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11882 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11885 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11887 tcg_temp_free_i32(tcg_res
);
11888 tcg_temp_free_i32(tcg_op1
);
11889 tcg_temp_free_i32(tcg_op2
);
11892 clear_vec_high(s
, is_q
, rd
);
11895 /* AdvSIMD three same
11896 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11897 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11898 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11899 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11901 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11903 int opcode
= extract32(insn
, 11, 5);
11906 case 0x3: /* logic ops */
11907 disas_simd_3same_logic(s
, insn
);
11909 case 0x17: /* ADDP */
11910 case 0x14: /* SMAXP, UMAXP */
11911 case 0x15: /* SMINP, UMINP */
11913 /* Pairwise operations */
11914 int is_q
= extract32(insn
, 30, 1);
11915 int u
= extract32(insn
, 29, 1);
11916 int size
= extract32(insn
, 22, 2);
11917 int rm
= extract32(insn
, 16, 5);
11918 int rn
= extract32(insn
, 5, 5);
11919 int rd
= extract32(insn
, 0, 5);
11920 if (opcode
== 0x17) {
11921 if (u
|| (size
== 3 && !is_q
)) {
11922 unallocated_encoding(s
);
11927 unallocated_encoding(s
);
11931 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11934 case 0x18 ... 0x31:
11935 /* floating point ops, sz[1] and U are part of opcode */
11936 disas_simd_3same_float(s
, insn
);
11939 disas_simd_3same_int(s
, insn
);
11945 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11947 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11948 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11949 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11950 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11952 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11953 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11956 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11958 int opcode
, fpopcode
;
11959 int is_q
, u
, a
, rm
, rn
, rd
;
11960 int datasize
, elements
;
11963 bool pairwise
= false;
11965 if (!dc_isar_feature(aa64_fp16
, s
)) {
11966 unallocated_encoding(s
);
11970 if (!fp_access_check(s
)) {
11974 /* For these floating point ops, the U, a and opcode bits
11975 * together indicate the operation.
11977 opcode
= extract32(insn
, 11, 3);
11978 u
= extract32(insn
, 29, 1);
11979 a
= extract32(insn
, 23, 1);
11980 is_q
= extract32(insn
, 30, 1);
11981 rm
= extract32(insn
, 16, 5);
11982 rn
= extract32(insn
, 5, 5);
11983 rd
= extract32(insn
, 0, 5);
11985 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11986 datasize
= is_q
? 128 : 64;
11987 elements
= datasize
/ 16;
11989 switch (fpopcode
) {
11990 case 0x10: /* FMAXNMP */
11991 case 0x12: /* FADDP */
11992 case 0x16: /* FMAXP */
11993 case 0x18: /* FMINNMP */
11994 case 0x1e: /* FMINP */
11999 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
12002 int maxpass
= is_q
? 8 : 4;
12003 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12004 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12005 TCGv_i32 tcg_res
[8];
12007 for (pass
= 0; pass
< maxpass
; pass
++) {
12008 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
12009 int passelt
= (pass
<< 1) & (maxpass
- 1);
12011 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
12012 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
12013 tcg_res
[pass
] = tcg_temp_new_i32();
12015 switch (fpopcode
) {
12016 case 0x10: /* FMAXNMP */
12017 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12020 case 0x12: /* FADDP */
12021 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12023 case 0x16: /* FMAXP */
12024 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12026 case 0x18: /* FMINNMP */
12027 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12030 case 0x1e: /* FMINP */
12031 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12034 g_assert_not_reached();
12038 for (pass
= 0; pass
< maxpass
; pass
++) {
12039 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12040 tcg_temp_free_i32(tcg_res
[pass
]);
12043 tcg_temp_free_i32(tcg_op1
);
12044 tcg_temp_free_i32(tcg_op2
);
12047 for (pass
= 0; pass
< elements
; pass
++) {
12048 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12049 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12050 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12052 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12053 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12055 switch (fpopcode
) {
12056 case 0x0: /* FMAXNM */
12057 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12059 case 0x1: /* FMLA */
12060 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12061 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12064 case 0x2: /* FADD */
12065 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12067 case 0x3: /* FMULX */
12068 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12070 case 0x4: /* FCMEQ */
12071 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12073 case 0x6: /* FMAX */
12074 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12076 case 0x7: /* FRECPS */
12077 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12079 case 0x8: /* FMINNM */
12080 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12082 case 0x9: /* FMLS */
12083 /* As usual for ARM, separate negation for fused multiply-add */
12084 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12085 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12086 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12089 case 0xa: /* FSUB */
12090 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12092 case 0xe: /* FMIN */
12093 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12095 case 0xf: /* FRSQRTS */
12096 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12098 case 0x13: /* FMUL */
12099 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12101 case 0x14: /* FCMGE */
12102 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12104 case 0x15: /* FACGE */
12105 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12107 case 0x17: /* FDIV */
12108 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12110 case 0x1a: /* FABD */
12111 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12112 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12114 case 0x1c: /* FCMGT */
12115 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12117 case 0x1d: /* FACGT */
12118 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12121 fprintf(stderr
, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64
"\n",
12122 __func__
, insn
, fpopcode
, s
->pc_curr
);
12123 g_assert_not_reached();
12126 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12127 tcg_temp_free_i32(tcg_res
);
12128 tcg_temp_free_i32(tcg_op1
);
12129 tcg_temp_free_i32(tcg_op2
);
12133 tcg_temp_free_ptr(fpst
);
12135 clear_vec_high(s
, is_q
, rd
);
12138 /* AdvSIMD three same extra
12139 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12140 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12141 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12142 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12144 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12146 int rd
= extract32(insn
, 0, 5);
12147 int rn
= extract32(insn
, 5, 5);
12148 int opcode
= extract32(insn
, 11, 4);
12149 int rm
= extract32(insn
, 16, 5);
12150 int size
= extract32(insn
, 22, 2);
12151 bool u
= extract32(insn
, 29, 1);
12152 bool is_q
= extract32(insn
, 30, 1);
12156 switch (u
* 16 + opcode
) {
12157 case 0x10: /* SQRDMLAH (vector) */
12158 case 0x11: /* SQRDMLSH (vector) */
12159 if (size
!= 1 && size
!= 2) {
12160 unallocated_encoding(s
);
12163 feature
= dc_isar_feature(aa64_rdm
, s
);
12165 case 0x02: /* SDOT (vector) */
12166 case 0x12: /* UDOT (vector) */
12167 if (size
!= MO_32
) {
12168 unallocated_encoding(s
);
12171 feature
= dc_isar_feature(aa64_dp
, s
);
12173 case 0x18: /* FCMLA, #0 */
12174 case 0x19: /* FCMLA, #90 */
12175 case 0x1a: /* FCMLA, #180 */
12176 case 0x1b: /* FCMLA, #270 */
12177 case 0x1c: /* FCADD, #90 */
12178 case 0x1e: /* FCADD, #270 */
12180 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12181 || (size
== 3 && !is_q
)) {
12182 unallocated_encoding(s
);
12185 feature
= dc_isar_feature(aa64_fcma
, s
);
12188 unallocated_encoding(s
);
12192 unallocated_encoding(s
);
12195 if (!fp_access_check(s
)) {
12200 case 0x0: /* SQRDMLAH (vector) */
12201 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12204 case 0x1: /* SQRDMLSH (vector) */
12205 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12208 case 0x2: /* SDOT / UDOT */
12209 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
12210 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12213 case 0x8: /* FCMLA, #0 */
12214 case 0x9: /* FCMLA, #90 */
12215 case 0xa: /* FCMLA, #180 */
12216 case 0xb: /* FCMLA, #270 */
12217 rot
= extract32(opcode
, 0, 2);
12220 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
12221 gen_helper_gvec_fcmlah
);
12224 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12225 gen_helper_gvec_fcmlas
);
12228 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12229 gen_helper_gvec_fcmlad
);
12232 g_assert_not_reached();
12236 case 0xc: /* FCADD, #90 */
12237 case 0xe: /* FCADD, #270 */
12238 rot
= extract32(opcode
, 1, 1);
12241 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12242 gen_helper_gvec_fcaddh
);
12245 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12246 gen_helper_gvec_fcadds
);
12249 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12250 gen_helper_gvec_fcaddd
);
12253 g_assert_not_reached();
12258 g_assert_not_reached();
12262 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12263 int size
, int rn
, int rd
)
12265 /* Handle 2-reg-misc ops which are widening (so each size element
12266 * in the source becomes a 2*size element in the destination.
12267 * The only instruction like this is FCVTL.
12272 /* 32 -> 64 bit fp conversion */
12273 TCGv_i64 tcg_res
[2];
12274 int srcelt
= is_q
? 2 : 0;
12276 for (pass
= 0; pass
< 2; pass
++) {
12277 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12278 tcg_res
[pass
] = tcg_temp_new_i64();
12280 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12281 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12282 tcg_temp_free_i32(tcg_op
);
12284 for (pass
= 0; pass
< 2; pass
++) {
12285 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12286 tcg_temp_free_i64(tcg_res
[pass
]);
12289 /* 16 -> 32 bit fp conversion */
12290 int srcelt
= is_q
? 4 : 0;
12291 TCGv_i32 tcg_res
[4];
12292 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12293 TCGv_i32 ahp
= get_ahp_flag();
12295 for (pass
= 0; pass
< 4; pass
++) {
12296 tcg_res
[pass
] = tcg_temp_new_i32();
12298 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12299 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12302 for (pass
= 0; pass
< 4; pass
++) {
12303 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12304 tcg_temp_free_i32(tcg_res
[pass
]);
12307 tcg_temp_free_ptr(fpst
);
12308 tcg_temp_free_i32(ahp
);
12312 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12313 bool is_q
, int size
, int rn
, int rd
)
12315 int op
= (opcode
<< 1) | u
;
12316 int opsz
= op
+ size
;
12317 int grp_size
= 3 - opsz
;
12318 int dsize
= is_q
? 128 : 64;
12322 unallocated_encoding(s
);
12326 if (!fp_access_check(s
)) {
12331 /* Special case bytes, use bswap op on each group of elements */
12332 int groups
= dsize
/ (8 << grp_size
);
12334 for (i
= 0; i
< groups
; i
++) {
12335 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12337 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12338 switch (grp_size
) {
12340 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
12343 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
12346 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12349 g_assert_not_reached();
12351 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12352 tcg_temp_free_i64(tcg_tmp
);
12354 clear_vec_high(s
, is_q
, rd
);
12356 int revmask
= (1 << grp_size
) - 1;
12357 int esize
= 8 << size
;
12358 int elements
= dsize
/ esize
;
12359 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12360 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12361 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12363 for (i
= 0; i
< elements
; i
++) {
12364 int e_rev
= (i
& 0xf) ^ revmask
;
12365 int off
= e_rev
* esize
;
12366 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12368 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12369 tcg_rn
, off
- 64, esize
);
12371 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12374 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12375 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12377 tcg_temp_free_i64(tcg_rd_hi
);
12378 tcg_temp_free_i64(tcg_rd
);
12379 tcg_temp_free_i64(tcg_rn
);
12383 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12384 bool is_q
, int size
, int rn
, int rd
)
12386 /* Implement the pairwise operations from 2-misc:
12387 * SADDLP, UADDLP, SADALP, UADALP.
12388 * These all add pairs of elements in the input to produce a
12389 * double-width result element in the output (possibly accumulating).
12391 bool accum
= (opcode
== 0x6);
12392 int maxpass
= is_q
? 2 : 1;
12394 TCGv_i64 tcg_res
[2];
12397 /* 32 + 32 -> 64 op */
12398 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12400 for (pass
= 0; pass
< maxpass
; pass
++) {
12401 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12402 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12404 tcg_res
[pass
] = tcg_temp_new_i64();
12406 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12407 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12408 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12410 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12411 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12414 tcg_temp_free_i64(tcg_op1
);
12415 tcg_temp_free_i64(tcg_op2
);
12418 for (pass
= 0; pass
< maxpass
; pass
++) {
12419 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12420 NeonGenOne64OpFn
*genfn
;
12421 static NeonGenOne64OpFn
* const fns
[2][2] = {
12422 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12423 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12426 genfn
= fns
[size
][u
];
12428 tcg_res
[pass
] = tcg_temp_new_i64();
12430 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12431 genfn(tcg_res
[pass
], tcg_op
);
12434 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12436 gen_helper_neon_addl_u16(tcg_res
[pass
],
12437 tcg_res
[pass
], tcg_op
);
12439 gen_helper_neon_addl_u32(tcg_res
[pass
],
12440 tcg_res
[pass
], tcg_op
);
12443 tcg_temp_free_i64(tcg_op
);
12447 tcg_res
[1] = tcg_const_i64(0);
12449 for (pass
= 0; pass
< 2; pass
++) {
12450 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12451 tcg_temp_free_i64(tcg_res
[pass
]);
12455 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12457 /* Implement SHLL and SHLL2 */
12459 int part
= is_q
? 2 : 0;
12460 TCGv_i64 tcg_res
[2];
12462 for (pass
= 0; pass
< 2; pass
++) {
12463 static NeonGenWidenFn
* const widenfns
[3] = {
12464 gen_helper_neon_widen_u8
,
12465 gen_helper_neon_widen_u16
,
12466 tcg_gen_extu_i32_i64
,
12468 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12469 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12471 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12472 tcg_res
[pass
] = tcg_temp_new_i64();
12473 widenfn(tcg_res
[pass
], tcg_op
);
12474 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12476 tcg_temp_free_i32(tcg_op
);
12479 for (pass
= 0; pass
< 2; pass
++) {
12480 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12481 tcg_temp_free_i64(tcg_res
[pass
]);
12485 /* AdvSIMD two reg misc
12486 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12487 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12488 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12489 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12491 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12493 int size
= extract32(insn
, 22, 2);
12494 int opcode
= extract32(insn
, 12, 5);
12495 bool u
= extract32(insn
, 29, 1);
12496 bool is_q
= extract32(insn
, 30, 1);
12497 int rn
= extract32(insn
, 5, 5);
12498 int rd
= extract32(insn
, 0, 5);
12499 bool need_fpstatus
= false;
12500 bool need_rmode
= false;
12502 TCGv_i32 tcg_rmode
;
12503 TCGv_ptr tcg_fpstatus
;
12506 case 0x0: /* REV64, REV32 */
12507 case 0x1: /* REV16 */
12508 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12510 case 0x5: /* CNT, NOT, RBIT */
12511 if (u
&& size
== 0) {
12514 } else if (u
&& size
== 1) {
12517 } else if (!u
&& size
== 0) {
12521 unallocated_encoding(s
);
12523 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12524 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12526 unallocated_encoding(s
);
12529 if (!fp_access_check(s
)) {
12533 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12535 case 0x4: /* CLS, CLZ */
12537 unallocated_encoding(s
);
12541 case 0x2: /* SADDLP, UADDLP */
12542 case 0x6: /* SADALP, UADALP */
12544 unallocated_encoding(s
);
12547 if (!fp_access_check(s
)) {
12550 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12552 case 0x13: /* SHLL, SHLL2 */
12553 if (u
== 0 || size
== 3) {
12554 unallocated_encoding(s
);
12557 if (!fp_access_check(s
)) {
12560 handle_shll(s
, is_q
, size
, rn
, rd
);
12562 case 0xa: /* CMLT */
12564 unallocated_encoding(s
);
12568 case 0x8: /* CMGT, CMGE */
12569 case 0x9: /* CMEQ, CMLE */
12570 case 0xb: /* ABS, NEG */
12571 if (size
== 3 && !is_q
) {
12572 unallocated_encoding(s
);
12576 case 0x3: /* SUQADD, USQADD */
12577 if (size
== 3 && !is_q
) {
12578 unallocated_encoding(s
);
12581 if (!fp_access_check(s
)) {
12584 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12586 case 0x7: /* SQABS, SQNEG */
12587 if (size
== 3 && !is_q
) {
12588 unallocated_encoding(s
);
12593 case 0x16 ... 0x1f:
12595 /* Floating point: U, size[1] and opcode indicate operation;
12596 * size[0] indicates single or double precision.
12598 int is_double
= extract32(size
, 0, 1);
12599 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12600 size
= is_double
? 3 : 2;
12602 case 0x2f: /* FABS */
12603 case 0x6f: /* FNEG */
12604 if (size
== 3 && !is_q
) {
12605 unallocated_encoding(s
);
12609 case 0x1d: /* SCVTF */
12610 case 0x5d: /* UCVTF */
12612 bool is_signed
= (opcode
== 0x1d) ? true : false;
12613 int elements
= is_double
? 2 : is_q
? 4 : 2;
12614 if (is_double
&& !is_q
) {
12615 unallocated_encoding(s
);
12618 if (!fp_access_check(s
)) {
12621 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12624 case 0x2c: /* FCMGT (zero) */
12625 case 0x2d: /* FCMEQ (zero) */
12626 case 0x2e: /* FCMLT (zero) */
12627 case 0x6c: /* FCMGE (zero) */
12628 case 0x6d: /* FCMLE (zero) */
12629 if (size
== 3 && !is_q
) {
12630 unallocated_encoding(s
);
12633 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12635 case 0x7f: /* FSQRT */
12636 if (size
== 3 && !is_q
) {
12637 unallocated_encoding(s
);
12641 case 0x1a: /* FCVTNS */
12642 case 0x1b: /* FCVTMS */
12643 case 0x3a: /* FCVTPS */
12644 case 0x3b: /* FCVTZS */
12645 case 0x5a: /* FCVTNU */
12646 case 0x5b: /* FCVTMU */
12647 case 0x7a: /* FCVTPU */
12648 case 0x7b: /* FCVTZU */
12649 need_fpstatus
= true;
12651 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12652 if (size
== 3 && !is_q
) {
12653 unallocated_encoding(s
);
12657 case 0x5c: /* FCVTAU */
12658 case 0x1c: /* FCVTAS */
12659 need_fpstatus
= true;
12661 rmode
= FPROUNDING_TIEAWAY
;
12662 if (size
== 3 && !is_q
) {
12663 unallocated_encoding(s
);
12667 case 0x3c: /* URECPE */
12669 unallocated_encoding(s
);
12673 case 0x3d: /* FRECPE */
12674 case 0x7d: /* FRSQRTE */
12675 if (size
== 3 && !is_q
) {
12676 unallocated_encoding(s
);
12679 if (!fp_access_check(s
)) {
12682 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12684 case 0x56: /* FCVTXN, FCVTXN2 */
12686 unallocated_encoding(s
);
12690 case 0x16: /* FCVTN, FCVTN2 */
12691 /* handle_2misc_narrow does a 2*size -> size operation, but these
12692 * instructions encode the source size rather than dest size.
12694 if (!fp_access_check(s
)) {
12697 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12699 case 0x17: /* FCVTL, FCVTL2 */
12700 if (!fp_access_check(s
)) {
12703 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12705 case 0x18: /* FRINTN */
12706 case 0x19: /* FRINTM */
12707 case 0x38: /* FRINTP */
12708 case 0x39: /* FRINTZ */
12710 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12712 case 0x59: /* FRINTX */
12713 case 0x79: /* FRINTI */
12714 need_fpstatus
= true;
12715 if (size
== 3 && !is_q
) {
12716 unallocated_encoding(s
);
12720 case 0x58: /* FRINTA */
12722 rmode
= FPROUNDING_TIEAWAY
;
12723 need_fpstatus
= true;
12724 if (size
== 3 && !is_q
) {
12725 unallocated_encoding(s
);
12729 case 0x7c: /* URSQRTE */
12731 unallocated_encoding(s
);
12735 case 0x1e: /* FRINT32Z */
12736 case 0x1f: /* FRINT64Z */
12738 rmode
= FPROUNDING_ZERO
;
12740 case 0x5e: /* FRINT32X */
12741 case 0x5f: /* FRINT64X */
12742 need_fpstatus
= true;
12743 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12744 unallocated_encoding(s
);
12749 unallocated_encoding(s
);
12755 unallocated_encoding(s
);
12759 if (!fp_access_check(s
)) {
12763 if (need_fpstatus
|| need_rmode
) {
12764 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12766 tcg_fpstatus
= NULL
;
12769 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12770 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12777 if (u
&& size
== 0) { /* NOT */
12778 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12782 case 0x8: /* CMGT, CMGE */
12784 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12786 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12789 case 0x9: /* CMEQ, CMLE */
12791 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12793 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12796 case 0xa: /* CMLT */
12797 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12800 if (u
) { /* ABS, NEG */
12801 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12803 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12809 /* All 64-bit element operations can be shared with scalar 2misc */
12812 /* Coverity claims (size == 3 && !is_q) has been eliminated
12813 * from all paths leading to here.
12815 tcg_debug_assert(is_q
);
12816 for (pass
= 0; pass
< 2; pass
++) {
12817 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12818 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12820 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12822 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12823 tcg_rmode
, tcg_fpstatus
);
12825 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12827 tcg_temp_free_i64(tcg_res
);
12828 tcg_temp_free_i64(tcg_op
);
12833 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12834 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12835 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12837 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12840 /* Special cases for 32 bit elements */
12842 case 0x4: /* CLS */
12844 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12846 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12849 case 0x7: /* SQABS, SQNEG */
12851 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12853 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12856 case 0x2f: /* FABS */
12857 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12859 case 0x6f: /* FNEG */
12860 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12862 case 0x7f: /* FSQRT */
12863 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12865 case 0x1a: /* FCVTNS */
12866 case 0x1b: /* FCVTMS */
12867 case 0x1c: /* FCVTAS */
12868 case 0x3a: /* FCVTPS */
12869 case 0x3b: /* FCVTZS */
12871 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12872 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12873 tcg_shift
, tcg_fpstatus
);
12874 tcg_temp_free_i32(tcg_shift
);
12877 case 0x5a: /* FCVTNU */
12878 case 0x5b: /* FCVTMU */
12879 case 0x5c: /* FCVTAU */
12880 case 0x7a: /* FCVTPU */
12881 case 0x7b: /* FCVTZU */
12883 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12884 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12885 tcg_shift
, tcg_fpstatus
);
12886 tcg_temp_free_i32(tcg_shift
);
12889 case 0x18: /* FRINTN */
12890 case 0x19: /* FRINTM */
12891 case 0x38: /* FRINTP */
12892 case 0x39: /* FRINTZ */
12893 case 0x58: /* FRINTA */
12894 case 0x79: /* FRINTI */
12895 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12897 case 0x59: /* FRINTX */
12898 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12900 case 0x7c: /* URSQRTE */
12901 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12903 case 0x1e: /* FRINT32Z */
12904 case 0x5e: /* FRINT32X */
12905 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12907 case 0x1f: /* FRINT64Z */
12908 case 0x5f: /* FRINT64X */
12909 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12912 g_assert_not_reached();
12915 /* Use helpers for 8 and 16 bit elements */
12917 case 0x5: /* CNT, RBIT */
12918 /* For these two insns size is part of the opcode specifier
12919 * (handled earlier); they always operate on byte elements.
12922 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12924 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12927 case 0x7: /* SQABS, SQNEG */
12929 NeonGenOneOpEnvFn
*genfn
;
12930 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12931 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12932 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12934 genfn
= fns
[size
][u
];
12935 genfn(tcg_res
, cpu_env
, tcg_op
);
12938 case 0x4: /* CLS, CLZ */
12941 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12943 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12947 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12949 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12954 g_assert_not_reached();
12958 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12960 tcg_temp_free_i32(tcg_res
);
12961 tcg_temp_free_i32(tcg_op
);
12964 clear_vec_high(s
, is_q
, rd
);
12967 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12968 tcg_temp_free_i32(tcg_rmode
);
12970 if (need_fpstatus
) {
12971 tcg_temp_free_ptr(tcg_fpstatus
);
12975 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12977 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12978 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12979 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12980 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12981 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12982 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12984 * This actually covers two groups where scalar access is governed by
12985 * bit 28. A bunch of the instructions (float to integral) only exist
12986 * in the vector form and are un-allocated for the scalar decode. Also
12987 * in the scalar decode Q is always 1.
12989 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12991 int fpop
, opcode
, a
, u
;
12995 bool only_in_vector
= false;
12998 TCGv_i32 tcg_rmode
= NULL
;
12999 TCGv_ptr tcg_fpstatus
= NULL
;
13000 bool need_rmode
= false;
13001 bool need_fpst
= true;
13004 if (!dc_isar_feature(aa64_fp16
, s
)) {
13005 unallocated_encoding(s
);
13009 rd
= extract32(insn
, 0, 5);
13010 rn
= extract32(insn
, 5, 5);
13012 a
= extract32(insn
, 23, 1);
13013 u
= extract32(insn
, 29, 1);
13014 is_scalar
= extract32(insn
, 28, 1);
13015 is_q
= extract32(insn
, 30, 1);
13017 opcode
= extract32(insn
, 12, 5);
13018 fpop
= deposit32(opcode
, 5, 1, a
);
13019 fpop
= deposit32(fpop
, 6, 1, u
);
13022 case 0x1d: /* SCVTF */
13023 case 0x5d: /* UCVTF */
13030 elements
= (is_q
? 8 : 4);
13033 if (!fp_access_check(s
)) {
13036 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13040 case 0x2c: /* FCMGT (zero) */
13041 case 0x2d: /* FCMEQ (zero) */
13042 case 0x2e: /* FCMLT (zero) */
13043 case 0x6c: /* FCMGE (zero) */
13044 case 0x6d: /* FCMLE (zero) */
13045 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13047 case 0x3d: /* FRECPE */
13048 case 0x3f: /* FRECPX */
13050 case 0x18: /* FRINTN */
13052 only_in_vector
= true;
13053 rmode
= FPROUNDING_TIEEVEN
;
13055 case 0x19: /* FRINTM */
13057 only_in_vector
= true;
13058 rmode
= FPROUNDING_NEGINF
;
13060 case 0x38: /* FRINTP */
13062 only_in_vector
= true;
13063 rmode
= FPROUNDING_POSINF
;
13065 case 0x39: /* FRINTZ */
13067 only_in_vector
= true;
13068 rmode
= FPROUNDING_ZERO
;
13070 case 0x58: /* FRINTA */
13072 only_in_vector
= true;
13073 rmode
= FPROUNDING_TIEAWAY
;
13075 case 0x59: /* FRINTX */
13076 case 0x79: /* FRINTI */
13077 only_in_vector
= true;
13078 /* current rounding mode */
13080 case 0x1a: /* FCVTNS */
13082 rmode
= FPROUNDING_TIEEVEN
;
13084 case 0x1b: /* FCVTMS */
13086 rmode
= FPROUNDING_NEGINF
;
13088 case 0x1c: /* FCVTAS */
13090 rmode
= FPROUNDING_TIEAWAY
;
13092 case 0x3a: /* FCVTPS */
13094 rmode
= FPROUNDING_POSINF
;
13096 case 0x3b: /* FCVTZS */
13098 rmode
= FPROUNDING_ZERO
;
13100 case 0x5a: /* FCVTNU */
13102 rmode
= FPROUNDING_TIEEVEN
;
13104 case 0x5b: /* FCVTMU */
13106 rmode
= FPROUNDING_NEGINF
;
13108 case 0x5c: /* FCVTAU */
13110 rmode
= FPROUNDING_TIEAWAY
;
13112 case 0x7a: /* FCVTPU */
13114 rmode
= FPROUNDING_POSINF
;
13116 case 0x7b: /* FCVTZU */
13118 rmode
= FPROUNDING_ZERO
;
13120 case 0x2f: /* FABS */
13121 case 0x6f: /* FNEG */
13124 case 0x7d: /* FRSQRTE */
13125 case 0x7f: /* FSQRT (vector) */
13128 fprintf(stderr
, "%s: insn 0x%04x fpop 0x%2x\n", __func__
, insn
, fpop
);
13129 g_assert_not_reached();
13133 /* Check additional constraints for the scalar encoding */
13136 unallocated_encoding(s
);
13139 /* FRINTxx is only in the vector form */
13140 if (only_in_vector
) {
13141 unallocated_encoding(s
);
13146 if (!fp_access_check(s
)) {
13150 if (need_rmode
|| need_fpst
) {
13151 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13155 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13156 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13160 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13161 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13164 case 0x1a: /* FCVTNS */
13165 case 0x1b: /* FCVTMS */
13166 case 0x1c: /* FCVTAS */
13167 case 0x3a: /* FCVTPS */
13168 case 0x3b: /* FCVTZS */
13169 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13171 case 0x3d: /* FRECPE */
13172 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13174 case 0x3f: /* FRECPX */
13175 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13177 case 0x5a: /* FCVTNU */
13178 case 0x5b: /* FCVTMU */
13179 case 0x5c: /* FCVTAU */
13180 case 0x7a: /* FCVTPU */
13181 case 0x7b: /* FCVTZU */
13182 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13184 case 0x6f: /* FNEG */
13185 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13187 case 0x7d: /* FRSQRTE */
13188 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13191 g_assert_not_reached();
13194 /* limit any sign extension going on */
13195 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13196 write_fp_sreg(s
, rd
, tcg_res
);
13198 tcg_temp_free_i32(tcg_res
);
13199 tcg_temp_free_i32(tcg_op
);
13201 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13202 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13203 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13205 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13208 case 0x1a: /* FCVTNS */
13209 case 0x1b: /* FCVTMS */
13210 case 0x1c: /* FCVTAS */
13211 case 0x3a: /* FCVTPS */
13212 case 0x3b: /* FCVTZS */
13213 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13215 case 0x3d: /* FRECPE */
13216 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13218 case 0x5a: /* FCVTNU */
13219 case 0x5b: /* FCVTMU */
13220 case 0x5c: /* FCVTAU */
13221 case 0x7a: /* FCVTPU */
13222 case 0x7b: /* FCVTZU */
13223 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13225 case 0x18: /* FRINTN */
13226 case 0x19: /* FRINTM */
13227 case 0x38: /* FRINTP */
13228 case 0x39: /* FRINTZ */
13229 case 0x58: /* FRINTA */
13230 case 0x79: /* FRINTI */
13231 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13233 case 0x59: /* FRINTX */
13234 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13236 case 0x2f: /* FABS */
13237 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13239 case 0x6f: /* FNEG */
13240 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13242 case 0x7d: /* FRSQRTE */
13243 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13245 case 0x7f: /* FSQRT */
13246 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13249 g_assert_not_reached();
13252 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13254 tcg_temp_free_i32(tcg_res
);
13255 tcg_temp_free_i32(tcg_op
);
13258 clear_vec_high(s
, is_q
, rd
);
13262 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13263 tcg_temp_free_i32(tcg_rmode
);
13266 if (tcg_fpstatus
) {
13267 tcg_temp_free_ptr(tcg_fpstatus
);
13271 /* AdvSIMD scalar x indexed element
13272 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13273 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13274 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13275 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13276 * AdvSIMD vector x indexed element
13277 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13278 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13279 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13280 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13282 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13284 /* This encoding has two kinds of instruction:
13285 * normal, where we perform elt x idxelt => elt for each
13286 * element in the vector
13287 * long, where we perform elt x idxelt and generate a result of
13288 * double the width of the input element
13289 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13291 bool is_scalar
= extract32(insn
, 28, 1);
13292 bool is_q
= extract32(insn
, 30, 1);
13293 bool u
= extract32(insn
, 29, 1);
13294 int size
= extract32(insn
, 22, 2);
13295 int l
= extract32(insn
, 21, 1);
13296 int m
= extract32(insn
, 20, 1);
13297 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13298 int rm
= extract32(insn
, 16, 4);
13299 int opcode
= extract32(insn
, 12, 4);
13300 int h
= extract32(insn
, 11, 1);
13301 int rn
= extract32(insn
, 5, 5);
13302 int rd
= extract32(insn
, 0, 5);
13303 bool is_long
= false;
13305 bool is_fp16
= false;
13309 switch (16 * u
+ opcode
) {
13310 case 0x08: /* MUL */
13311 case 0x10: /* MLA */
13312 case 0x14: /* MLS */
13314 unallocated_encoding(s
);
13318 case 0x02: /* SMLAL, SMLAL2 */
13319 case 0x12: /* UMLAL, UMLAL2 */
13320 case 0x06: /* SMLSL, SMLSL2 */
13321 case 0x16: /* UMLSL, UMLSL2 */
13322 case 0x0a: /* SMULL, SMULL2 */
13323 case 0x1a: /* UMULL, UMULL2 */
13325 unallocated_encoding(s
);
13330 case 0x03: /* SQDMLAL, SQDMLAL2 */
13331 case 0x07: /* SQDMLSL, SQDMLSL2 */
13332 case 0x0b: /* SQDMULL, SQDMULL2 */
13335 case 0x0c: /* SQDMULH */
13336 case 0x0d: /* SQRDMULH */
13338 case 0x01: /* FMLA */
13339 case 0x05: /* FMLS */
13340 case 0x09: /* FMUL */
13341 case 0x19: /* FMULX */
13344 case 0x1d: /* SQRDMLAH */
13345 case 0x1f: /* SQRDMLSH */
13346 if (!dc_isar_feature(aa64_rdm
, s
)) {
13347 unallocated_encoding(s
);
13351 case 0x0e: /* SDOT */
13352 case 0x1e: /* UDOT */
13353 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13354 unallocated_encoding(s
);
13358 case 0x11: /* FCMLA #0 */
13359 case 0x13: /* FCMLA #90 */
13360 case 0x15: /* FCMLA #180 */
13361 case 0x17: /* FCMLA #270 */
13362 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13363 unallocated_encoding(s
);
13368 case 0x00: /* FMLAL */
13369 case 0x04: /* FMLSL */
13370 case 0x18: /* FMLAL2 */
13371 case 0x1c: /* FMLSL2 */
13372 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13373 unallocated_encoding(s
);
13377 /* is_fp, but we pass cpu_env not fp_status. */
13380 unallocated_encoding(s
);
13385 case 1: /* normal fp */
13386 /* convert insn encoded size to MemOp size */
13388 case 0: /* half-precision */
13392 case MO_32
: /* single precision */
13393 case MO_64
: /* double precision */
13396 unallocated_encoding(s
);
13401 case 2: /* complex fp */
13402 /* Each indexable element is a complex pair. */
13407 unallocated_encoding(s
);
13415 unallocated_encoding(s
);
13420 default: /* integer */
13424 unallocated_encoding(s
);
13429 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13430 unallocated_encoding(s
);
13434 /* Given MemOp size, adjust register and indexing. */
13437 index
= h
<< 2 | l
<< 1 | m
;
13440 index
= h
<< 1 | l
;
13445 unallocated_encoding(s
);
13452 g_assert_not_reached();
13455 if (!fp_access_check(s
)) {
13460 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13465 switch (16 * u
+ opcode
) {
13466 case 0x0e: /* SDOT */
13467 case 0x1e: /* UDOT */
13468 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13469 u
? gen_helper_gvec_udot_idx_b
13470 : gen_helper_gvec_sdot_idx_b
);
13472 case 0x11: /* FCMLA #0 */
13473 case 0x13: /* FCMLA #90 */
13474 case 0x15: /* FCMLA #180 */
13475 case 0x17: /* FCMLA #270 */
13477 int rot
= extract32(insn
, 13, 2);
13478 int data
= (index
<< 2) | rot
;
13479 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13480 vec_full_reg_offset(s
, rn
),
13481 vec_full_reg_offset(s
, rm
), fpst
,
13482 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13484 ? gen_helper_gvec_fcmlas_idx
13485 : gen_helper_gvec_fcmlah_idx
);
13486 tcg_temp_free_ptr(fpst
);
13490 case 0x00: /* FMLAL */
13491 case 0x04: /* FMLSL */
13492 case 0x18: /* FMLAL2 */
13493 case 0x1c: /* FMLSL2 */
13495 int is_s
= extract32(opcode
, 2, 1);
13497 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13498 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13499 vec_full_reg_offset(s
, rn
),
13500 vec_full_reg_offset(s
, rm
), cpu_env
,
13501 is_q
? 16 : 8, vec_full_reg_size(s
),
13502 data
, gen_helper_gvec_fmlal_idx_a64
);
13506 case 0x08: /* MUL */
13507 if (!is_long
&& !is_scalar
) {
13508 static gen_helper_gvec_3
* const fns
[3] = {
13509 gen_helper_gvec_mul_idx_h
,
13510 gen_helper_gvec_mul_idx_s
,
13511 gen_helper_gvec_mul_idx_d
,
13513 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13514 vec_full_reg_offset(s
, rn
),
13515 vec_full_reg_offset(s
, rm
),
13516 is_q
? 16 : 8, vec_full_reg_size(s
),
13517 index
, fns
[size
- 1]);
13522 case 0x10: /* MLA */
13523 if (!is_long
&& !is_scalar
) {
13524 static gen_helper_gvec_4
* const fns
[3] = {
13525 gen_helper_gvec_mla_idx_h
,
13526 gen_helper_gvec_mla_idx_s
,
13527 gen_helper_gvec_mla_idx_d
,
13529 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13530 vec_full_reg_offset(s
, rn
),
13531 vec_full_reg_offset(s
, rm
),
13532 vec_full_reg_offset(s
, rd
),
13533 is_q
? 16 : 8, vec_full_reg_size(s
),
13534 index
, fns
[size
- 1]);
13539 case 0x14: /* MLS */
13540 if (!is_long
&& !is_scalar
) {
13541 static gen_helper_gvec_4
* const fns
[3] = {
13542 gen_helper_gvec_mls_idx_h
,
13543 gen_helper_gvec_mls_idx_s
,
13544 gen_helper_gvec_mls_idx_d
,
13546 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13547 vec_full_reg_offset(s
, rn
),
13548 vec_full_reg_offset(s
, rm
),
13549 vec_full_reg_offset(s
, rd
),
13550 is_q
? 16 : 8, vec_full_reg_size(s
),
13551 index
, fns
[size
- 1]);
13558 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13561 assert(is_fp
&& is_q
&& !is_long
);
13563 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13565 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13566 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13567 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13569 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13571 switch (16 * u
+ opcode
) {
13572 case 0x05: /* FMLS */
13573 /* As usual for ARM, separate negation for fused multiply-add */
13574 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13576 case 0x01: /* FMLA */
13577 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13578 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13580 case 0x09: /* FMUL */
13581 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13583 case 0x19: /* FMULX */
13584 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13587 g_assert_not_reached();
13590 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13591 tcg_temp_free_i64(tcg_op
);
13592 tcg_temp_free_i64(tcg_res
);
13595 tcg_temp_free_i64(tcg_idx
);
13596 clear_vec_high(s
, !is_scalar
, rd
);
13597 } else if (!is_long
) {
13598 /* 32 bit floating point, or 16 or 32 bit integer.
13599 * For the 16 bit scalar case we use the usual Neon helpers and
13600 * rely on the fact that 0 op 0 == 0 with no side effects.
13602 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13603 int pass
, maxpasses
;
13608 maxpasses
= is_q
? 4 : 2;
13611 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13613 if (size
== 1 && !is_scalar
) {
13614 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13615 * the index into both halves of the 32 bit tcg_idx and then use
13616 * the usual Neon helpers.
13618 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13621 for (pass
= 0; pass
< maxpasses
; pass
++) {
13622 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13623 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13625 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13627 switch (16 * u
+ opcode
) {
13628 case 0x08: /* MUL */
13629 case 0x10: /* MLA */
13630 case 0x14: /* MLS */
13632 static NeonGenTwoOpFn
* const fns
[2][2] = {
13633 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13634 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13636 NeonGenTwoOpFn
*genfn
;
13637 bool is_sub
= opcode
== 0x4;
13640 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13642 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13644 if (opcode
== 0x8) {
13647 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13648 genfn
= fns
[size
- 1][is_sub
];
13649 genfn(tcg_res
, tcg_op
, tcg_res
);
13652 case 0x05: /* FMLS */
13653 case 0x01: /* FMLA */
13654 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13655 is_scalar
? size
: MO_32
);
13658 if (opcode
== 0x5) {
13659 /* As usual for ARM, separate negation for fused
13661 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13664 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13667 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13672 if (opcode
== 0x5) {
13673 /* As usual for ARM, separate negation for
13674 * fused multiply-add */
13675 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13677 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13681 g_assert_not_reached();
13684 case 0x09: /* FMUL */
13688 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13691 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13696 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13699 g_assert_not_reached();
13702 case 0x19: /* FMULX */
13706 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13709 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13714 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13717 g_assert_not_reached();
13720 case 0x0c: /* SQDMULH */
13722 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13725 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13729 case 0x0d: /* SQRDMULH */
13731 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13734 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13738 case 0x1d: /* SQRDMLAH */
13739 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13740 is_scalar
? size
: MO_32
);
13742 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13743 tcg_op
, tcg_idx
, tcg_res
);
13745 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13746 tcg_op
, tcg_idx
, tcg_res
);
13749 case 0x1f: /* SQRDMLSH */
13750 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13751 is_scalar
? size
: MO_32
);
13753 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13754 tcg_op
, tcg_idx
, tcg_res
);
13756 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13757 tcg_op
, tcg_idx
, tcg_res
);
13761 g_assert_not_reached();
13765 write_fp_sreg(s
, rd
, tcg_res
);
13767 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13770 tcg_temp_free_i32(tcg_op
);
13771 tcg_temp_free_i32(tcg_res
);
13774 tcg_temp_free_i32(tcg_idx
);
13775 clear_vec_high(s
, is_q
, rd
);
13777 /* long ops: 16x16->32 or 32x32->64 */
13778 TCGv_i64 tcg_res
[2];
13780 bool satop
= extract32(opcode
, 0, 1);
13781 MemOp memop
= MO_32
;
13788 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13790 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13792 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13793 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13794 TCGv_i64 tcg_passres
;
13800 passelt
= pass
+ (is_q
* 2);
13803 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13805 tcg_res
[pass
] = tcg_temp_new_i64();
13807 if (opcode
== 0xa || opcode
== 0xb) {
13808 /* Non-accumulating ops */
13809 tcg_passres
= tcg_res
[pass
];
13811 tcg_passres
= tcg_temp_new_i64();
13814 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13815 tcg_temp_free_i64(tcg_op
);
13818 /* saturating, doubling */
13819 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13820 tcg_passres
, tcg_passres
);
13823 if (opcode
== 0xa || opcode
== 0xb) {
13827 /* Accumulating op: handle accumulate step */
13828 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13831 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13832 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13834 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13835 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13837 case 0x7: /* SQDMLSL, SQDMLSL2 */
13838 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13840 case 0x3: /* SQDMLAL, SQDMLAL2 */
13841 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13846 g_assert_not_reached();
13848 tcg_temp_free_i64(tcg_passres
);
13850 tcg_temp_free_i64(tcg_idx
);
13852 clear_vec_high(s
, !is_scalar
, rd
);
13854 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13857 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13860 /* The simplest way to handle the 16x16 indexed ops is to
13861 * duplicate the index into both halves of the 32 bit tcg_idx
13862 * and then use the usual Neon helpers.
13864 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13867 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13868 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13869 TCGv_i64 tcg_passres
;
13872 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13874 read_vec_element_i32(s
, tcg_op
, rn
,
13875 pass
+ (is_q
* 2), MO_32
);
13878 tcg_res
[pass
] = tcg_temp_new_i64();
13880 if (opcode
== 0xa || opcode
== 0xb) {
13881 /* Non-accumulating ops */
13882 tcg_passres
= tcg_res
[pass
];
13884 tcg_passres
= tcg_temp_new_i64();
13887 if (memop
& MO_SIGN
) {
13888 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13890 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13893 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13894 tcg_passres
, tcg_passres
);
13896 tcg_temp_free_i32(tcg_op
);
13898 if (opcode
== 0xa || opcode
== 0xb) {
13902 /* Accumulating op: handle accumulate step */
13903 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13906 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13907 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13910 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13911 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13914 case 0x7: /* SQDMLSL, SQDMLSL2 */
13915 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13917 case 0x3: /* SQDMLAL, SQDMLAL2 */
13918 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13923 g_assert_not_reached();
13925 tcg_temp_free_i64(tcg_passres
);
13927 tcg_temp_free_i32(tcg_idx
);
13930 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13935 tcg_res
[1] = tcg_const_i64(0);
13938 for (pass
= 0; pass
< 2; pass
++) {
13939 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13940 tcg_temp_free_i64(tcg_res
[pass
]);
13945 tcg_temp_free_ptr(fpst
);
13950 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13951 * +-----------------+------+-----------+--------+-----+------+------+
13952 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13953 * +-----------------+------+-----------+--------+-----+------+------+
13955 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13957 int size
= extract32(insn
, 22, 2);
13958 int opcode
= extract32(insn
, 12, 5);
13959 int rn
= extract32(insn
, 5, 5);
13960 int rd
= extract32(insn
, 0, 5);
13962 gen_helper_gvec_2
*genfn2
= NULL
;
13963 gen_helper_gvec_3
*genfn3
= NULL
;
13965 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13966 unallocated_encoding(s
);
13971 case 0x4: /* AESE */
13973 genfn3
= gen_helper_crypto_aese
;
13975 case 0x6: /* AESMC */
13977 genfn2
= gen_helper_crypto_aesmc
;
13979 case 0x5: /* AESD */
13981 genfn3
= gen_helper_crypto_aese
;
13983 case 0x7: /* AESIMC */
13985 genfn2
= gen_helper_crypto_aesmc
;
13988 unallocated_encoding(s
);
13992 if (!fp_access_check(s
)) {
13996 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13998 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
14002 /* Crypto three-reg SHA
14003 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
14004 * +-----------------+------+---+------+---+--------+-----+------+------+
14005 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
14006 * +-----------------+------+---+------+---+--------+-----+------+------+
14008 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
14010 int size
= extract32(insn
, 22, 2);
14011 int opcode
= extract32(insn
, 12, 3);
14012 int rm
= extract32(insn
, 16, 5);
14013 int rn
= extract32(insn
, 5, 5);
14014 int rd
= extract32(insn
, 0, 5);
14015 gen_helper_gvec_3
*genfn
;
14019 unallocated_encoding(s
);
14024 case 0: /* SHA1C */
14025 genfn
= gen_helper_crypto_sha1c
;
14026 feature
= dc_isar_feature(aa64_sha1
, s
);
14028 case 1: /* SHA1P */
14029 genfn
= gen_helper_crypto_sha1p
;
14030 feature
= dc_isar_feature(aa64_sha1
, s
);
14032 case 2: /* SHA1M */
14033 genfn
= gen_helper_crypto_sha1m
;
14034 feature
= dc_isar_feature(aa64_sha1
, s
);
14036 case 3: /* SHA1SU0 */
14037 genfn
= gen_helper_crypto_sha1su0
;
14038 feature
= dc_isar_feature(aa64_sha1
, s
);
14040 case 4: /* SHA256H */
14041 genfn
= gen_helper_crypto_sha256h
;
14042 feature
= dc_isar_feature(aa64_sha256
, s
);
14044 case 5: /* SHA256H2 */
14045 genfn
= gen_helper_crypto_sha256h2
;
14046 feature
= dc_isar_feature(aa64_sha256
, s
);
14048 case 6: /* SHA256SU1 */
14049 genfn
= gen_helper_crypto_sha256su1
;
14050 feature
= dc_isar_feature(aa64_sha256
, s
);
14053 unallocated_encoding(s
);
14058 unallocated_encoding(s
);
14062 if (!fp_access_check(s
)) {
14065 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14068 /* Crypto two-reg SHA
14069 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14070 * +-----------------+------+-----------+--------+-----+------+------+
14071 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14072 * +-----------------+------+-----------+--------+-----+------+------+
14074 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14076 int size
= extract32(insn
, 22, 2);
14077 int opcode
= extract32(insn
, 12, 5);
14078 int rn
= extract32(insn
, 5, 5);
14079 int rd
= extract32(insn
, 0, 5);
14080 gen_helper_gvec_2
*genfn
;
14084 unallocated_encoding(s
);
14089 case 0: /* SHA1H */
14090 feature
= dc_isar_feature(aa64_sha1
, s
);
14091 genfn
= gen_helper_crypto_sha1h
;
14093 case 1: /* SHA1SU1 */
14094 feature
= dc_isar_feature(aa64_sha1
, s
);
14095 genfn
= gen_helper_crypto_sha1su1
;
14097 case 2: /* SHA256SU0 */
14098 feature
= dc_isar_feature(aa64_sha256
, s
);
14099 genfn
= gen_helper_crypto_sha256su0
;
14102 unallocated_encoding(s
);
14107 unallocated_encoding(s
);
14111 if (!fp_access_check(s
)) {
14114 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14117 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14119 tcg_gen_rotli_i64(d
, m
, 1);
14120 tcg_gen_xor_i64(d
, d
, n
);
14123 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14125 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14126 tcg_gen_xor_vec(vece
, d
, d
, n
);
14129 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14130 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14132 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14133 static const GVecGen3 op
= {
14134 .fni8
= gen_rax1_i64
,
14135 .fniv
= gen_rax1_vec
,
14136 .opt_opc
= vecop_list
,
14137 .fno
= gen_helper_crypto_rax1
,
14140 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14143 /* Crypto three-reg SHA512
14144 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14145 * +-----------------------+------+---+---+-----+--------+------+------+
14146 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14147 * +-----------------------+------+---+---+-----+--------+------+------+
14149 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14151 int opcode
= extract32(insn
, 10, 2);
14152 int o
= extract32(insn
, 14, 1);
14153 int rm
= extract32(insn
, 16, 5);
14154 int rn
= extract32(insn
, 5, 5);
14155 int rd
= extract32(insn
, 0, 5);
14157 gen_helper_gvec_3
*oolfn
= NULL
;
14158 GVecGen3Fn
*gvecfn
= NULL
;
14162 case 0: /* SHA512H */
14163 feature
= dc_isar_feature(aa64_sha512
, s
);
14164 oolfn
= gen_helper_crypto_sha512h
;
14166 case 1: /* SHA512H2 */
14167 feature
= dc_isar_feature(aa64_sha512
, s
);
14168 oolfn
= gen_helper_crypto_sha512h2
;
14170 case 2: /* SHA512SU1 */
14171 feature
= dc_isar_feature(aa64_sha512
, s
);
14172 oolfn
= gen_helper_crypto_sha512su1
;
14175 feature
= dc_isar_feature(aa64_sha3
, s
);
14176 gvecfn
= gen_gvec_rax1
;
14179 g_assert_not_reached();
14183 case 0: /* SM3PARTW1 */
14184 feature
= dc_isar_feature(aa64_sm3
, s
);
14185 oolfn
= gen_helper_crypto_sm3partw1
;
14187 case 1: /* SM3PARTW2 */
14188 feature
= dc_isar_feature(aa64_sm3
, s
);
14189 oolfn
= gen_helper_crypto_sm3partw2
;
14191 case 2: /* SM4EKEY */
14192 feature
= dc_isar_feature(aa64_sm4
, s
);
14193 oolfn
= gen_helper_crypto_sm4ekey
;
14196 unallocated_encoding(s
);
14202 unallocated_encoding(s
);
14206 if (!fp_access_check(s
)) {
14211 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14213 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14217 /* Crypto two-reg SHA512
14218 * 31 12 11 10 9 5 4 0
14219 * +-----------------------------------------+--------+------+------+
14220 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14221 * +-----------------------------------------+--------+------+------+
14223 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14225 int opcode
= extract32(insn
, 10, 2);
14226 int rn
= extract32(insn
, 5, 5);
14227 int rd
= extract32(insn
, 0, 5);
14231 case 0: /* SHA512SU0 */
14232 feature
= dc_isar_feature(aa64_sha512
, s
);
14235 feature
= dc_isar_feature(aa64_sm4
, s
);
14238 unallocated_encoding(s
);
14243 unallocated_encoding(s
);
14247 if (!fp_access_check(s
)) {
14252 case 0: /* SHA512SU0 */
14253 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14256 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14259 g_assert_not_reached();
14263 /* Crypto four-register
14264 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14265 * +-------------------+-----+------+---+------+------+------+
14266 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14267 * +-------------------+-----+------+---+------+------+------+
14269 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14271 int op0
= extract32(insn
, 21, 2);
14272 int rm
= extract32(insn
, 16, 5);
14273 int ra
= extract32(insn
, 10, 5);
14274 int rn
= extract32(insn
, 5, 5);
14275 int rd
= extract32(insn
, 0, 5);
14281 feature
= dc_isar_feature(aa64_sha3
, s
);
14283 case 2: /* SM3SS1 */
14284 feature
= dc_isar_feature(aa64_sm3
, s
);
14287 unallocated_encoding(s
);
14292 unallocated_encoding(s
);
14296 if (!fp_access_check(s
)) {
14301 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14304 tcg_op1
= tcg_temp_new_i64();
14305 tcg_op2
= tcg_temp_new_i64();
14306 tcg_op3
= tcg_temp_new_i64();
14307 tcg_res
[0] = tcg_temp_new_i64();
14308 tcg_res
[1] = tcg_temp_new_i64();
14310 for (pass
= 0; pass
< 2; pass
++) {
14311 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14312 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14313 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14317 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14320 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14322 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14324 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14325 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14327 tcg_temp_free_i64(tcg_op1
);
14328 tcg_temp_free_i64(tcg_op2
);
14329 tcg_temp_free_i64(tcg_op3
);
14330 tcg_temp_free_i64(tcg_res
[0]);
14331 tcg_temp_free_i64(tcg_res
[1]);
14333 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14335 tcg_op1
= tcg_temp_new_i32();
14336 tcg_op2
= tcg_temp_new_i32();
14337 tcg_op3
= tcg_temp_new_i32();
14338 tcg_res
= tcg_temp_new_i32();
14339 tcg_zero
= tcg_const_i32(0);
14341 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14342 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14343 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14345 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14346 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14347 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14348 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14350 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14351 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14352 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14353 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14355 tcg_temp_free_i32(tcg_op1
);
14356 tcg_temp_free_i32(tcg_op2
);
14357 tcg_temp_free_i32(tcg_op3
);
14358 tcg_temp_free_i32(tcg_res
);
14359 tcg_temp_free_i32(tcg_zero
);
14364 * 31 21 20 16 15 10 9 5 4 0
14365 * +-----------------------+------+--------+------+------+
14366 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14367 * +-----------------------+------+--------+------+------+
14369 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14371 int rm
= extract32(insn
, 16, 5);
14372 int imm6
= extract32(insn
, 10, 6);
14373 int rn
= extract32(insn
, 5, 5);
14374 int rd
= extract32(insn
, 0, 5);
14375 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
14378 if (!dc_isar_feature(aa64_sha3
, s
)) {
14379 unallocated_encoding(s
);
14383 if (!fp_access_check(s
)) {
14387 tcg_op1
= tcg_temp_new_i64();
14388 tcg_op2
= tcg_temp_new_i64();
14389 tcg_res
[0] = tcg_temp_new_i64();
14390 tcg_res
[1] = tcg_temp_new_i64();
14392 for (pass
= 0; pass
< 2; pass
++) {
14393 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14394 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14396 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
14397 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
14399 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14400 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14402 tcg_temp_free_i64(tcg_op1
);
14403 tcg_temp_free_i64(tcg_op2
);
14404 tcg_temp_free_i64(tcg_res
[0]);
14405 tcg_temp_free_i64(tcg_res
[1]);
14408 /* Crypto three-reg imm2
14409 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14410 * +-----------------------+------+-----+------+--------+------+------+
14411 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14412 * +-----------------------+------+-----+------+--------+------+------+
14414 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14416 static gen_helper_gvec_3
* const fns
[4] = {
14417 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14418 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14420 int opcode
= extract32(insn
, 10, 2);
14421 int imm2
= extract32(insn
, 12, 2);
14422 int rm
= extract32(insn
, 16, 5);
14423 int rn
= extract32(insn
, 5, 5);
14424 int rd
= extract32(insn
, 0, 5);
14426 if (!dc_isar_feature(aa64_sm3
, s
)) {
14427 unallocated_encoding(s
);
14431 if (!fp_access_check(s
)) {
14435 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14438 /* C3.6 Data processing - SIMD, inc Crypto
14440 * As the decode gets a little complex we are using a table based
14441 * approach for this part of the decode.
14443 static const AArch64DecodeTable data_proc_simd
[] = {
14444 /* pattern , mask , fn */
14445 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14446 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14447 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14448 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14449 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14450 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14451 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14452 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14453 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14454 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14455 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14456 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14457 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14458 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14459 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14460 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14461 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14462 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14463 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14464 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14465 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14466 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14467 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14468 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14469 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14470 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14471 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14472 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14473 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14474 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14475 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14476 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14477 { 0x00000000, 0x00000000, NULL
}
14480 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14482 /* Note that this is called with all non-FP cases from
14483 * table C3-6 so it must UNDEF for entries not specifically
14484 * allocated to instructions in that table.
14486 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14490 unallocated_encoding(s
);
14494 /* C3.6 Data processing - SIMD and floating point */
14495 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14497 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14498 disas_data_proc_fp(s
, insn
);
14500 /* SIMD, including crypto */
14501 disas_data_proc_simd(s
, insn
);
14507 * @env: The cpu environment
14508 * @s: The DisasContext
14510 * Return true if the page is guarded.
14512 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14514 uint64_t addr
= s
->base
.pc_first
;
14515 #ifdef CONFIG_USER_ONLY
14516 return page_get_flags(addr
) & PAGE_BTI
;
14518 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14519 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14520 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14523 * We test this immediately after reading an insn, which means
14524 * that any normal page must be in the TLB. The only exception
14525 * would be for executing from flash or device memory, which
14526 * does not retain the TLB entry.
14528 * FIXME: Assume false for those, for now. We could use
14529 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14530 * table entry even for that case.
14532 return (tlb_hit(entry
->addr_code
, addr
) &&
14533 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14538 * btype_destination_ok:
14539 * @insn: The instruction at the branch destination
14540 * @bt: SCTLR_ELx.BT
14541 * @btype: PSTATE.BTYPE, and is non-zero
14543 * On a guarded page, there are a limited number of insns
14544 * that may be present at the branch target:
14545 * - branch target identifiers,
14546 * - paciasp, pacibsp,
14549 * Anything else causes a Branch Target Exception.
14551 * Return true if the branch is compatible, false to raise BTITRAP.
14553 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14555 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14557 switch (extract32(insn
, 5, 7)) {
14558 case 0b011001: /* PACIASP */
14559 case 0b011011: /* PACIBSP */
14561 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14562 * with btype == 3. Otherwise all btype are ok.
14564 return !bt
|| btype
!= 3;
14565 case 0b100000: /* BTI */
14566 /* Not compatible with any btype. */
14568 case 0b100010: /* BTI c */
14569 /* Not compatible with btype == 3 */
14571 case 0b100100: /* BTI j */
14572 /* Not compatible with btype == 2 */
14574 case 0b100110: /* BTI jc */
14575 /* Compatible with any btype. */
14579 switch (insn
& 0xffe0001fu
) {
14580 case 0xd4200000u
: /* BRK */
14581 case 0xd4400000u
: /* HLT */
14582 /* Give priority to the breakpoint exception. */
14589 /* C3.1 A64 instruction index by encoding */
14590 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14594 s
->pc_curr
= s
->base
.pc_next
;
14595 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14597 s
->base
.pc_next
+= 4;
14599 s
->fp_access_checked
= false;
14600 s
->sve_access_checked
= false;
14602 if (dc_isar_feature(aa64_bti
, s
)) {
14603 if (s
->base
.num_insns
== 1) {
14605 * At the first insn of the TB, compute s->guarded_page.
14606 * We delayed computing this until successfully reading
14607 * the first insn of the TB, above. This (mostly) ensures
14608 * that the softmmu tlb entry has been populated, and the
14609 * page table GP bit is available.
14611 * Note that we need to compute this even if btype == 0,
14612 * because this value is used for BR instructions later
14613 * where ENV is not available.
14615 s
->guarded_page
= is_guarded_page(env
, s
);
14617 /* First insn can have btype set to non-zero. */
14618 tcg_debug_assert(s
->btype
>= 0);
14621 * Note that the Branch Target Exception has fairly high
14622 * priority -- below debugging exceptions but above most
14623 * everything else. This allows us to handle this now
14624 * instead of waiting until the insn is otherwise decoded.
14628 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14629 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14630 syn_btitrap(s
->btype
),
14631 default_exception_el(s
));
14635 /* Not the first insn: btype must be 0. */
14636 tcg_debug_assert(s
->btype
== 0);
14640 switch (extract32(insn
, 25, 4)) {
14641 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14642 unallocated_encoding(s
);
14645 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14646 unallocated_encoding(s
);
14649 case 0x8: case 0x9: /* Data processing - immediate */
14650 disas_data_proc_imm(s
, insn
);
14652 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14653 disas_b_exc_sys(s
, insn
);
14658 case 0xe: /* Loads and stores */
14659 disas_ldst(s
, insn
);
14662 case 0xd: /* Data processing - register */
14663 disas_data_proc_reg(s
, insn
);
14666 case 0xf: /* Data processing - SIMD and floating point */
14667 disas_data_proc_simd_fp(s
, insn
);
14670 assert(FALSE
); /* all 15 cases should be handled above */
14674 /* if we allocated any temporaries, free them here */
14678 * After execution of most insns, btype is reset to 0.
14679 * Note that we set btype == -1 when the insn sets btype.
14681 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14686 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14689 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14690 CPUARMState
*env
= cpu
->env_ptr
;
14691 ARMCPU
*arm_cpu
= env_archcpu(env
);
14692 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14693 int bound
, core_mmu_idx
;
14695 dc
->isar
= &arm_cpu
->isar
;
14699 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14700 * there is no secure EL1, so we route exceptions to EL3.
14702 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14703 !arm_el_is_aa64(env
, 3);
14706 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14707 dc
->condexec_mask
= 0;
14708 dc
->condexec_cond
= 0;
14709 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14710 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14711 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14712 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14713 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14714 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14715 #if !defined(CONFIG_USER_ONLY)
14716 dc
->user
= (dc
->current_el
== 0);
14718 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14719 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14720 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14721 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14722 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14723 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14724 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14725 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14726 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14727 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14729 dc
->vec_stride
= 0;
14730 dc
->cp_regs
= arm_cpu
->cp_regs
;
14731 dc
->features
= env
->features
;
14732 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14734 #ifdef CONFIG_USER_ONLY
14735 /* In sve_probe_page, we assume TBI is enabled. */
14736 tcg_debug_assert(dc
->tbid
& 1);
14739 /* Single step state. The code-generation logic here is:
14741 * generate code with no special handling for single-stepping (except
14742 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14743 * this happens anyway because those changes are all system register or
14745 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14746 * emit code for one insn
14747 * emit code to clear PSTATE.SS
14748 * emit code to generate software step exception for completed step
14749 * end TB (as usual for having generated an exception)
14750 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14751 * emit code to generate a software step exception
14754 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14755 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14756 dc
->is_ldex
= false;
14757 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14759 /* Bound the number of insns to execute to those left on the page. */
14760 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14762 /* If architectural single step active, limit to 1. */
14763 if (dc
->ss_active
) {
14766 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14768 init_tmp_a64_array(dc
);
14771 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14775 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14777 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14779 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14780 dc
->insn_start
= tcg_last_op();
14783 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14784 const CPUBreakpoint
*bp
)
14786 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14788 if (bp
->flags
& BP_CPU
) {
14789 gen_a64_set_pc_im(dc
->base
.pc_next
);
14790 gen_helper_check_breakpoints(cpu_env
);
14791 /* End the TB early; it likely won't be executed */
14792 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14794 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14795 /* The address covered by the breakpoint must be
14796 included in [tb->pc, tb->pc + tb->size) in order
14797 to for it to be properly cleared -- thus we
14798 increment the PC here so that the logic setting
14799 tb->size below does the right thing. */
14800 dc
->base
.pc_next
+= 4;
14801 dc
->base
.is_jmp
= DISAS_NORETURN
;
14807 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14809 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14810 CPUARMState
*env
= cpu
->env_ptr
;
14812 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14813 /* Singlestep state is Active-pending.
14814 * If we're in this state at the start of a TB then either
14815 * a) we just took an exception to an EL which is being debugged
14816 * and this is the first insn in the exception handler
14817 * b) debug exceptions were masked and we just unmasked them
14818 * without changing EL (eg by clearing PSTATE.D)
14819 * In either case we're going to take a swstep exception in the
14820 * "did not step an insn" case, and so the syndrome ISV and EX
14821 * bits should be zero.
14823 assert(dc
->base
.num_insns
== 1);
14824 gen_swstep_exception(dc
, 0, 0);
14825 dc
->base
.is_jmp
= DISAS_NORETURN
;
14827 disas_a64_insn(env
, dc
);
14830 translator_loop_temp_check(&dc
->base
);
14833 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14835 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14837 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14838 /* Note that this means single stepping WFI doesn't halt the CPU.
14839 * For conditional branch insns this is harmless unreachable code as
14840 * gen_goto_tb() has already handled emitting the debug exception
14841 * (and thus a tb-jump is not possible when singlestepping).
14843 switch (dc
->base
.is_jmp
) {
14845 gen_a64_set_pc_im(dc
->base
.pc_next
);
14849 if (dc
->base
.singlestep_enabled
) {
14850 gen_exception_internal(EXCP_DEBUG
);
14852 gen_step_complete_exception(dc
);
14855 case DISAS_NORETURN
:
14859 switch (dc
->base
.is_jmp
) {
14861 case DISAS_TOO_MANY
:
14862 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14865 case DISAS_UPDATE_EXIT
:
14866 gen_a64_set_pc_im(dc
->base
.pc_next
);
14869 tcg_gen_exit_tb(NULL
, 0);
14871 case DISAS_UPDATE_NOCHAIN
:
14872 gen_a64_set_pc_im(dc
->base
.pc_next
);
14875 tcg_gen_lookup_and_goto_ptr();
14877 case DISAS_NORETURN
:
14881 gen_a64_set_pc_im(dc
->base
.pc_next
);
14882 gen_helper_wfe(cpu_env
);
14885 gen_a64_set_pc_im(dc
->base
.pc_next
);
14886 gen_helper_yield(cpu_env
);
14890 /* This is a special case because we don't want to just halt the CPU
14891 * if trying to debug across a WFI.
14893 TCGv_i32 tmp
= tcg_const_i32(4);
14895 gen_a64_set_pc_im(dc
->base
.pc_next
);
14896 gen_helper_wfi(cpu_env
, tmp
);
14897 tcg_temp_free_i32(tmp
);
14898 /* The helper doesn't necessarily throw an exception, but we
14899 * must go back to the main loop to check for interrupts anyway.
14901 tcg_gen_exit_tb(NULL
, 0);
14908 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14911 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14913 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14914 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14917 const TranslatorOps aarch64_translator_ops
= {
14918 .init_disas_context
= aarch64_tr_init_disas_context
,
14919 .tb_start
= aarch64_tr_tb_start
,
14920 .insn_start
= aarch64_tr_insn_start
,
14921 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14922 .translate_insn
= aarch64_tr_translate_insn
,
14923 .tb_stop
= aarch64_tr_tb_stop
,
14924 .disas_log
= aarch64_tr_disas_log
,