hw/display/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu-common.h"
  27 #include "qapi/error.h"
  28 #include "ui/console.h"
  29 #include "ui/pixel_ops.h"
  30 #include "hw/loader.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/sysbus.h"
  33 #include "migration/vmstate.h"
  34 #include "qemu/error-report.h"
  35 #include "qemu/module.h"
  36 #include "qom/object.h"
  37
  38 #define TCX_ROM_FILE "QEMU,tcx.bin"
  39 #define FCODE_MAX_ROM_SIZE 0x10000
  40
  41 #define MAXX 1024
  42 #define MAXY 768
  43 #define TCX_DAC_NREGS    16
  44 #define TCX_THC_NREGS    0x1000
  45 #define TCX_DHC_NREGS    0x4000
  46 #define TCX_TEC_NREGS    0x1000
  47 #define TCX_ALT_NREGS    0x8000
  48 #define TCX_STIP_NREGS   0x800000
  49 #define TCX_BLIT_NREGS   0x800000
  50 #define TCX_RSTIP_NREGS  0x800000
  51 #define TCX_RBLIT_NREGS  0x800000
  52
  53 #define TCX_THC_MISC     0x818
  54 #define TCX_THC_CURSXY   0x8fc
  55 #define TCX_THC_CURSMASK 0x900
  56 #define TCX_THC_CURSBITS 0x980
  57
  58 #define TYPE_TCX "SUNW,tcx"
  59 typedef struct TCXState TCXState;
  60 DECLARE_INSTANCE_CHECKER(TCXState, TCX,
  61                          TYPE_TCX)
  62
  63 struct TCXState {
  64     SysBusDevice parent_obj;
  65
  66     QemuConsole *con;
  67     qemu_irq irq;
  68     uint8_t *vram;
  69     uint32_t *vram24, *cplane;
  70     hwaddr prom_addr;
  71     MemoryRegion rom;
  72     MemoryRegion vram_mem;
  73     MemoryRegion vram_8bit;
  74     MemoryRegion vram_24bit;
  75     MemoryRegion stip;
  76     MemoryRegion blit;
  77     MemoryRegion vram_cplane;
  78     MemoryRegion rstip;
  79     MemoryRegion rblit;
  80     MemoryRegion tec;
  81     MemoryRegion dac;
  82     MemoryRegion thc;
  83     MemoryRegion dhc;
  84     MemoryRegion alt;
  85     MemoryRegion thc24;
  86
  87     ram_addr_t vram24_offset, cplane_offset;
  88     uint32_t tmpblit;
  89     uint32_t vram_size;
  90     uint32_t palette[260];
  91     uint8_t r[260], g[260], b[260];
  92     uint16_t width, height, depth;
  93     uint8_t dac_index, dac_state;
  94     uint32_t thcmisc;
  95     uint32_t cursmask[32];
  96     uint32_t cursbits[32];
  97     uint16_t cursx;
  98     uint16_t cursy;
  99 };
 100
 101 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len)
 102 {
 103     memory_region_set_dirty(&s->vram_mem, addr, len);
 104
 105     if (s->depth == 24) {
 106         memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4,
 107                                 len * 4);
 108         memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4,
 109                                 len * 4);
 110     }
 111 }
 112
 113 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap,
 114                            ram_addr_t addr, int len)
 115 {
 116     int ret;
 117
 118     ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len);
 119
 120     if (s->depth == 24) {
 121         ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
 122                                        s->vram24_offset + addr * 4, len * 4);
 123         ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
 124                                        s->cplane_offset + addr * 4, len * 4);
 125     }
 126
 127     return ret;
 128 }
 129
 130 static void update_palette_entries(TCXState *s, int start, int end)
 131 {
 132     DisplaySurface *surface = qemu_console_surface(s->con);
 133     int i;
 134
 135     for (i = start; i < end; i++) {
 136         if (is_surface_bgr(surface)) {
 137             s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
 138         } else {
 139             s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
 140         }
 141     }
 142     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 143 }
 144
 145 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
 146                             const uint8_t *s, int width)
 147 {
 148     int x;
 149     uint8_t val;
 150     uint32_t *p = (uint32_t *)d;
 151
 152     for (x = 0; x < width; x++) {
 153         val = *s++;
 154         *p++ = s1->palette[val];
 155     }
 156 }
 157
 158 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
 159                               int y, int width)
 160 {
 161     int x, len;
 162     uint32_t mask, bits;
 163     uint32_t *p = (uint32_t *)d;
 164
 165     y = y - s1->cursy;
 166     mask = s1->cursmask[y];
 167     bits = s1->cursbits[y];
 168     len = MIN(width - s1->cursx, 32);
 169     p = &p[s1->cursx];
 170     for (x = 0; x < len; x++) {
 171         if (mask & 0x80000000) {
 172             if (bits & 0x80000000) {
 173                 *p = s1->palette[259];
 174             } else {
 175                 *p = s1->palette[258];
 176             }
 177         }
 178         p++;
 179         mask <<= 1;
 180         bits <<= 1;
 181     }
 182 }
 183
 184 /*
 185   XXX Could be much more optimal:
 186   * detect if line/page/whole screen is in 24 bit mode
 187   * if destination is also BGR, use memcpy
 188   */
 189 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 190                                      const uint8_t *s, int width,
 191                                      const uint32_t *cplane,
 192                                      const uint32_t *s24)
 193 {
 194     DisplaySurface *surface = qemu_console_surface(s1->con);
 195     int x, bgr, r, g, b;
 196     uint8_t val, *p8;
 197     uint32_t *p = (uint32_t *)d;
 198     uint32_t dval;
 199     bgr = is_surface_bgr(surface);
 200     for(x = 0; x < width; x++, s++, s24++) {
 201         if (be32_to_cpu(*cplane) & 0x03000000) {
 202             /* 24-bit direct, BGR order */
 203             p8 = (uint8_t *)s24;
 204             p8++;
 205             b = *p8++;
 206             g = *p8++;
 207             r = *p8;
 208             if (bgr)
 209                 dval = rgb_to_pixel32bgr(r, g, b);
 210             else
 211                 dval = rgb_to_pixel32(r, g, b);
 212         } else {
 213             /* 8-bit pseudocolor */
 214             val = *s;
 215             dval = s1->palette[val];
 216         }
 217         *p++ = dval;
 218         cplane++;
 219     }
 220 }
 221
 222 /* Fixed line length 1024 allows us to do nice tricks not possible on
 223    VGA... */
 224
 225 static void tcx_update_display(void *opaque)
 226 {
 227     TCXState *ts = opaque;
 228     DisplaySurface *surface = qemu_console_surface(ts->con);
 229     ram_addr_t page;
 230     DirtyBitmapSnapshot *snap = NULL;
 231     int y, y_start, dd, ds;
 232     uint8_t *d, *s;
 233
 234     if (surface_bits_per_pixel(surface) != 32) {
 235         return;
 236     }
 237
 238     page = 0;
 239     y_start = -1;
 240     d = surface_data(surface);
 241     s = ts->vram;
 242     dd = surface_stride(surface);
 243     ds = 1024;
 244
 245     snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
 246                                              memory_region_size(&ts->vram_mem),
 247                                              DIRTY_MEMORY_VGA);
 248
 249     for (y = 0; y < ts->height; y++, page += ds) {
 250         if (tcx_check_dirty(ts, snap, page, ds)) {
 251             if (y_start < 0)
 252                 y_start = y;
 253
 254             tcx_draw_line32(ts, d, s, ts->width);
 255             if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
 256                 tcx_draw_cursor32(ts, d, y, ts->width);
 257             }
 258         } else {
 259             if (y_start >= 0) {
 260                 /* flush to display */
 261                 dpy_gfx_update(ts->con, 0, y_start,
 262                                ts->width, y - y_start);
 263                 y_start = -1;
 264             }
 265         }
 266         s += ds;
 267         d += dd;
 268     }
 269     if (y_start >= 0) {
 270         /* flush to display */
 271         dpy_gfx_update(ts->con, 0, y_start,
 272                        ts->width, y - y_start);
 273     }
 274     g_free(snap);
 275 }
 276
 277 static void tcx24_update_display(void *opaque)
 278 {
 279     TCXState *ts = opaque;
 280     DisplaySurface *surface = qemu_console_surface(ts->con);
 281     ram_addr_t page;
 282     DirtyBitmapSnapshot *snap = NULL;
 283     int y, y_start, dd, ds;
 284     uint8_t *d, *s;
 285     uint32_t *cptr, *s24;
 286
 287     if (surface_bits_per_pixel(surface) != 32) {
 288             return;
 289     }
 290
 291     page = 0;
 292     y_start = -1;
 293     d = surface_data(surface);
 294     s = ts->vram;
 295     s24 = ts->vram24;
 296     cptr = ts->cplane;
 297     dd = surface_stride(surface);
 298     ds = 1024;
 299
 300     snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
 301                                              memory_region_size(&ts->vram_mem),
 302                                              DIRTY_MEMORY_VGA);
 303
 304     for (y = 0; y < ts->height; y++, page += ds) {
 305         if (tcx_check_dirty(ts, snap, page, ds)) {
 306             if (y_start < 0)
 307                 y_start = y;
 308
 309             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 310             if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
 311                 tcx_draw_cursor32(ts, d, y, ts->width);
 312             }
 313         } else {
 314             if (y_start >= 0) {
 315                 /* flush to display */
 316                 dpy_gfx_update(ts->con, 0, y_start,
 317                                ts->width, y - y_start);
 318                 y_start = -1;
 319             }
 320         }
 321         d += dd;
 322         s += ds;
 323         cptr += ds;
 324         s24 += ds;
 325     }
 326     if (y_start >= 0) {
 327         /* flush to display */
 328         dpy_gfx_update(ts->con, 0, y_start,
 329                        ts->width, y - y_start);
 330     }
 331     g_free(snap);
 332 }
 333
 334 static void tcx_invalidate_display(void *opaque)
 335 {
 336     TCXState *s = opaque;
 337
 338     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 339     qemu_console_resize(s->con, s->width, s->height);
 340 }
 341
 342 static void tcx24_invalidate_display(void *opaque)
 343 {
 344     TCXState *s = opaque;
 345
 346     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 347     qemu_console_resize(s->con, s->width, s->height);
 348 }
 349
 350 static int vmstate_tcx_post_load(void *opaque, int version_id)
 351 {
 352     TCXState *s = opaque;
 353
 354     update_palette_entries(s, 0, 256);
 355     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 356     return 0;
 357 }
 358
 359 static const VMStateDescription vmstate_tcx = {
 360     .name ="tcx",
 361     .version_id = 4,
 362     .minimum_version_id = 4,
 363     .post_load = vmstate_tcx_post_load,
 364     .fields = (VMStateField[]) {
 365         VMSTATE_UINT16(height, TCXState),
 366         VMSTATE_UINT16(width, TCXState),
 367         VMSTATE_UINT16(depth, TCXState),
 368         VMSTATE_BUFFER(r, TCXState),
 369         VMSTATE_BUFFER(g, TCXState),
 370         VMSTATE_BUFFER(b, TCXState),
 371         VMSTATE_UINT8(dac_index, TCXState),
 372         VMSTATE_UINT8(dac_state, TCXState),
 373         VMSTATE_END_OF_LIST()
 374     }
 375 };
 376
 377 static void tcx_reset(DeviceState *d)
 378 {
 379     TCXState *s = TCX(d);
 380
 381     /* Initialize palette */
 382     memset(s->r, 0, 260);
 383     memset(s->g, 0, 260);
 384     memset(s->b, 0, 260);
 385     s->r[255] = s->g[255] = s->b[255] = 255;
 386     s->r[256] = s->g[256] = s->b[256] = 255;
 387     s->r[258] = s->g[258] = s->b[258] = 255;
 388     update_palette_entries(s, 0, 260);
 389     memset(s->vram, 0, MAXX*MAXY);
 390     memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
 391                               DIRTY_MEMORY_VGA);
 392     s->dac_index = 0;
 393     s->dac_state = 0;
 394     s->cursx = 0xf000; /* Put cursor off screen */
 395     s->cursy = 0xf000;
 396 }
 397
 398 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
 399                               unsigned size)
 400 {
 401     TCXState *s = opaque;
 402     uint32_t val = 0;
 403
 404     switch (s->dac_state) {
 405     case 0:
 406         val = s->r[s->dac_index] << 24;
 407         s->dac_state++;
 408         break;
 409     case 1:
 410         val = s->g[s->dac_index] << 24;
 411         s->dac_state++;
 412         break;
 413     case 2:
 414         val = s->b[s->dac_index] << 24;
 415         s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
 416         /* fall through */
 417     default:
 418         s->dac_state = 0;
 419         break;
 420     }
 421
 422     return val;
 423 }
 424
 425 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
 426                            unsigned size)
 427 {
 428     TCXState *s = opaque;
 429     unsigned index;
 430
 431     switch (addr) {
 432     case 0: /* Address */
 433         s->dac_index = val >> 24;
 434         s->dac_state = 0;
 435         break;
 436     case 4:  /* Pixel colours */
 437     case 12: /* Overlay (cursor) colours */
 438         if (addr & 8) {
 439             index = (s->dac_index & 3) + 256;
 440         } else {
 441             index = s->dac_index;
 442         }
 443         switch (s->dac_state) {
 444         case 0:
 445             s->r[index] = val >> 24;
 446             update_palette_entries(s, index, index + 1);
 447             s->dac_state++;
 448             break;
 449         case 1:
 450             s->g[index] = val >> 24;
 451             update_palette_entries(s, index, index + 1);
 452             s->dac_state++;
 453             break;
 454         case 2:
 455             s->b[index] = val >> 24;
 456             update_palette_entries(s, index, index + 1);
 457             s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
 458             /* fall through */
 459         default:
 460             s->dac_state = 0;
 461             break;
 462         }
 463         break;
 464     default: /* Control registers */
 465         break;
 466     }
 467 }
 468
 469 static const MemoryRegionOps tcx_dac_ops = {
 470     .read = tcx_dac_readl,
 471     .write = tcx_dac_writel,
 472     .endianness = DEVICE_NATIVE_ENDIAN,
 473     .valid = {
 474         .min_access_size = 4,
 475         .max_access_size = 4,
 476     },
 477 };
 478
 479 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr,
 480                                unsigned size)
 481 {
 482     return 0;
 483 }
 484
 485 static void tcx_stip_writel(void *opaque, hwaddr addr,
 486                             uint64_t val, unsigned size)
 487 {
 488     TCXState *s = opaque;
 489     int i;
 490     uint32_t col;
 491
 492     if (!(addr & 4)) {
 493         s->tmpblit = val;
 494     } else {
 495         addr = (addr >> 3) & 0xfffff;
 496         col = cpu_to_be32(s->tmpblit);
 497         if (s->depth == 24) {
 498             for (i = 0; i < 32; i++)  {
 499                 if (val & 0x80000000) {
 500                     s->vram[addr + i] = s->tmpblit;
 501                     s->vram24[addr + i] = col;
 502                 }
 503                 val <<= 1;
 504             }
 505         } else {
 506             for (i = 0; i < 32; i++)  {
 507                 if (val & 0x80000000) {
 508                     s->vram[addr + i] = s->tmpblit;
 509                 }
 510                 val <<= 1;
 511             }
 512         }
 513         tcx_set_dirty(s, addr, 32);
 514     }
 515 }
 516
 517 static void tcx_rstip_writel(void *opaque, hwaddr addr,
 518                              uint64_t val, unsigned size)
 519 {
 520     TCXState *s = opaque;
 521     int i;
 522     uint32_t col;
 523
 524     if (!(addr & 4)) {
 525         s->tmpblit = val;
 526     } else {
 527         addr = (addr >> 3) & 0xfffff;
 528         col = cpu_to_be32(s->tmpblit);
 529         if (s->depth == 24) {
 530             for (i = 0; i < 32; i++) {
 531                 if (val & 0x80000000) {
 532                     s->vram[addr + i] = s->tmpblit;
 533                     s->vram24[addr + i] = col;
 534                     s->cplane[addr + i] = col;
 535                 }
 536                 val <<= 1;
 537             }
 538         } else {
 539             for (i = 0; i < 32; i++)  {
 540                 if (val & 0x80000000) {
 541                     s->vram[addr + i] = s->tmpblit;
 542                 }
 543                 val <<= 1;
 544             }
 545         }
 546         tcx_set_dirty(s, addr, 32);
 547     }
 548 }
 549
 550 static const MemoryRegionOps tcx_stip_ops = {
 551     .read = tcx_stip_readl,
 552     .write = tcx_stip_writel,
 553     .endianness = DEVICE_NATIVE_ENDIAN,
 554     .valid = {
 555         .min_access_size = 4,
 556         .max_access_size = 4,
 557     },
 558 };
 559
 560 static const MemoryRegionOps tcx_rstip_ops = {
 561     .read = tcx_stip_readl,
 562     .write = tcx_rstip_writel,
 563     .endianness = DEVICE_NATIVE_ENDIAN,
 564     .valid = {
 565         .min_access_size = 4,
 566         .max_access_size = 4,
 567     },
 568 };
 569
 570 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
 571                                unsigned size)
 572 {
 573     return 0;
 574 }
 575
 576 static void tcx_blit_writel(void *opaque, hwaddr addr,
 577                             uint64_t val, unsigned size)
 578 {
 579     TCXState *s = opaque;
 580     uint32_t adsr, len;
 581     int i;
 582
 583     if (!(addr & 4)) {
 584         s->tmpblit = val;
 585     } else {
 586         addr = (addr >> 3) & 0xfffff;
 587         adsr = val & 0xffffff;
 588         len = ((val >> 24) & 0x1f) + 1;
 589         if (adsr == 0xffffff) {
 590             memset(&s->vram[addr], s->tmpblit, len);
 591             if (s->depth == 24) {
 592                 val = s->tmpblit & 0xffffff;
 593                 val = cpu_to_be32(val);
 594                 for (i = 0; i < len; i++) {
 595                     s->vram24[addr + i] = val;
 596                 }
 597             }
 598         } else {
 599             memcpy(&s->vram[addr], &s->vram[adsr], len);
 600             if (s->depth == 24) {
 601                 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
 602             }
 603         }
 604         tcx_set_dirty(s, addr, len);
 605     }
 606 }
 607
 608 static void tcx_rblit_writel(void *opaque, hwaddr addr,
 609                          uint64_t val, unsigned size)
 610 {
 611     TCXState *s = opaque;
 612     uint32_t adsr, len;
 613     int i;
 614
 615     if (!(addr & 4)) {
 616         s->tmpblit = val;
 617     } else {
 618         addr = (addr >> 3) & 0xfffff;
 619         adsr = val & 0xffffff;
 620         len = ((val >> 24) & 0x1f) + 1;
 621         if (adsr == 0xffffff) {
 622             memset(&s->vram[addr], s->tmpblit, len);
 623             if (s->depth == 24) {
 624                 val = s->tmpblit & 0xffffff;
 625                 val = cpu_to_be32(val);
 626                 for (i = 0; i < len; i++) {
 627                     s->vram24[addr + i] = val;
 628                     s->cplane[addr + i] = val;
 629                 }
 630             }
 631         } else {
 632             memcpy(&s->vram[addr], &s->vram[adsr], len);
 633             if (s->depth == 24) {
 634                 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
 635                 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4);
 636             }
 637         }
 638         tcx_set_dirty(s, addr, len);
 639     }
 640 }
 641
 642 static const MemoryRegionOps tcx_blit_ops = {
 643     .read = tcx_blit_readl,
 644     .write = tcx_blit_writel,
 645     .endianness = DEVICE_NATIVE_ENDIAN,
 646     .valid = {
 647         .min_access_size = 4,
 648         .max_access_size = 4,
 649     },
 650 };
 651
 652 static const MemoryRegionOps tcx_rblit_ops = {
 653     .read = tcx_blit_readl,
 654     .write = tcx_rblit_writel,
 655     .endianness = DEVICE_NATIVE_ENDIAN,
 656     .valid = {
 657         .min_access_size = 4,
 658         .max_access_size = 4,
 659     },
 660 };
 661
 662 static void tcx_invalidate_cursor_position(TCXState *s)
 663 {
 664     int ymin, ymax, start, end;
 665
 666     /* invalidate only near the cursor */
 667     ymin = s->cursy;
 668     if (ymin >= s->height) {
 669         return;
 670     }
 671     ymax = MIN(s->height, ymin + 32);
 672     start = ymin * 1024;
 673     end   = ymax * 1024;
 674
 675     tcx_set_dirty(s, start, end - start);
 676 }
 677
 678 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr,
 679                             unsigned size)
 680 {
 681     TCXState *s = opaque;
 682     uint64_t val;
 683
 684     if (addr == TCX_THC_MISC) {
 685         val = s->thcmisc | 0x02000000;
 686     } else {
 687         val = 0;
 688     }
 689     return val;
 690 }
 691
 692 static void tcx_thc_writel(void *opaque, hwaddr addr,
 693                          uint64_t val, unsigned size)
 694 {
 695     TCXState *s = opaque;
 696
 697     if (addr == TCX_THC_CURSXY) {
 698         tcx_invalidate_cursor_position(s);
 699         s->cursx = val >> 16;
 700         s->cursy = val;
 701         tcx_invalidate_cursor_position(s);
 702     } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) {
 703         s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val;
 704         tcx_invalidate_cursor_position(s);
 705     } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) {
 706         s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val;
 707         tcx_invalidate_cursor_position(s);
 708     } else if (addr == TCX_THC_MISC) {
 709         s->thcmisc = val;
 710     }
 711
 712 }
 713
 714 static const MemoryRegionOps tcx_thc_ops = {
 715     .read = tcx_thc_readl,
 716     .write = tcx_thc_writel,
 717     .endianness = DEVICE_NATIVE_ENDIAN,
 718     .valid = {
 719         .min_access_size = 4,
 720         .max_access_size = 4,
 721     },
 722 };
 723
 724 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr,
 725                             unsigned size)
 726 {
 727     return 0;
 728 }
 729
 730 static void tcx_dummy_writel(void *opaque, hwaddr addr,
 731                          uint64_t val, unsigned size)
 732 {
 733     return;
 734 }
 735
 736 static const MemoryRegionOps tcx_dummy_ops = {
 737     .read = tcx_dummy_readl,
 738     .write = tcx_dummy_writel,
 739     .endianness = DEVICE_NATIVE_ENDIAN,
 740     .valid = {
 741         .min_access_size = 4,
 742         .max_access_size = 4,
 743     },
 744 };
 745
 746 static const GraphicHwOps tcx_ops = {
 747     .invalidate = tcx_invalidate_display,
 748     .gfx_update = tcx_update_display,
 749 };
 750
 751 static const GraphicHwOps tcx24_ops = {
 752     .invalidate = tcx24_invalidate_display,
 753     .gfx_update = tcx24_update_display,
 754 };
 755
 756 static void tcx_initfn(Object *obj)
 757 {
 758     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 759     TCXState *s = TCX(obj);
 760
 761     memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom",
 762                                      FCODE_MAX_ROM_SIZE, &error_fatal);
 763     sysbus_init_mmio(sbd, &s->rom);
 764
 765     /* 2/STIP : Stippler */
 766     memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip",
 767                           TCX_STIP_NREGS);
 768     sysbus_init_mmio(sbd, &s->stip);
 769
 770     /* 3/BLIT : Blitter */
 771     memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit",
 772                           TCX_BLIT_NREGS);
 773     sysbus_init_mmio(sbd, &s->blit);
 774
 775     /* 5/RSTIP : Raw Stippler */
 776     memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip",
 777                           TCX_RSTIP_NREGS);
 778     sysbus_init_mmio(sbd, &s->rstip);
 779
 780     /* 6/RBLIT : Raw Blitter */
 781     memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit",
 782                           TCX_RBLIT_NREGS);
 783     sysbus_init_mmio(sbd, &s->rblit);
 784
 785     /* 7/TEC : ??? */
 786     memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec",
 787                           TCX_TEC_NREGS);
 788     sysbus_init_mmio(sbd, &s->tec);
 789
 790     /* 8/CMAP : DAC */
 791     memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac",
 792                           TCX_DAC_NREGS);
 793     sysbus_init_mmio(sbd, &s->dac);
 794
 795     /* 9/THC : Cursor */
 796     memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc",
 797                           TCX_THC_NREGS);
 798     sysbus_init_mmio(sbd, &s->thc);
 799
 800     /* 11/DHC : ??? */
 801     memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc",
 802                           TCX_DHC_NREGS);
 803     sysbus_init_mmio(sbd, &s->dhc);
 804
 805     /* 12/ALT : ??? */
 806     memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt",
 807                           TCX_ALT_NREGS);
 808     sysbus_init_mmio(sbd, &s->alt);
 809 }
 810
 811 static void tcx_realizefn(DeviceState *dev, Error **errp)
 812 {
 813     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 814     TCXState *s = TCX(dev);
 815     ram_addr_t vram_offset = 0;
 816     int size, ret;
 817     uint8_t *vram_base;
 818     char *fcode_filename;
 819
 820     memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram",
 821                            s->vram_size * (1 + 4 + 4), &error_fatal);
 822     vmstate_register_ram_global(&s->vram_mem);
 823     memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
 824     vram_base = memory_region_get_ram_ptr(&s->vram_mem);
 825
 826     /* 10/ROM : FCode ROM */
 827     vmstate_register_ram_global(&s->rom);
 828     fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
 829     if (fcode_filename) {
 830         ret = load_image_mr(fcode_filename, &s->rom);
 831         g_free(fcode_filename);
 832         if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
 833             warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
 834         }
 835     }
 836
 837     /* 0/DFB8 : 8-bit plane */
 838     s->vram = vram_base;
 839     size = s->vram_size;
 840     memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
 841                              &s->vram_mem, vram_offset, size);
 842     sysbus_init_mmio(sbd, &s->vram_8bit);
 843     vram_offset += size;
 844     vram_base += size;
 845
 846     /* 1/DFB24 : 24bit plane */
 847     size = s->vram_size * 4;
 848     s->vram24 = (uint32_t *)vram_base;
 849     s->vram24_offset = vram_offset;
 850     memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
 851                              &s->vram_mem, vram_offset, size);
 852     sysbus_init_mmio(sbd, &s->vram_24bit);
 853     vram_offset += size;
 854     vram_base += size;
 855
 856     /* 4/RDFB32 : Raw Framebuffer */
 857     size = s->vram_size * 4;
 858     s->cplane = (uint32_t *)vram_base;
 859     s->cplane_offset = vram_offset;
 860     memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
 861                              &s->vram_mem, vram_offset, size);
 862     sysbus_init_mmio(sbd, &s->vram_cplane);
 863
 864     /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
 865     if (s->depth == 8) {
 866         memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s,
 867                               "tcx.thc24", TCX_THC_NREGS);
 868         sysbus_init_mmio(sbd, &s->thc24);
 869     }
 870
 871     sysbus_init_irq(sbd, &s->irq);
 872
 873     if (s->depth == 8) {
 874         s->con = graphic_console_init(dev, 0, &tcx_ops, s);
 875     } else {
 876         s->con = graphic_console_init(dev, 0, &tcx24_ops, s);
 877     }
 878     s->thcmisc = 0;
 879
 880     qemu_console_resize(s->con, s->width, s->height);
 881 }
 882
 883 static Property tcx_properties[] = {
 884     DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1),
 885     DEFINE_PROP_UINT16("width",    TCXState, width,     -1),
 886     DEFINE_PROP_UINT16("height",   TCXState, height,    -1),
 887     DEFINE_PROP_UINT16("depth",    TCXState, depth,     -1),
 888     DEFINE_PROP_END_OF_LIST(),
 889 };
 890
 891 static void tcx_class_init(ObjectClass *klass, void *data)
 892 {
 893     DeviceClass *dc = DEVICE_CLASS(klass);
 894
 895     dc->realize = tcx_realizefn;
 896     dc->reset = tcx_reset;
 897     dc->vmsd = &vmstate_tcx;
 898     device_class_set_props(dc, tcx_properties);
 899 }
 900
 901 static const TypeInfo tcx_info = {
 902     .name          = TYPE_TCX,
 903     .parent        = TYPE_SYS_BUS_DEVICE,
 904     .instance_size = sizeof(TCXState),
 905     .instance_init = tcx_initfn,
 906     .class_init    = tcx_class_init,
 907 };
 908
 909 static void tcx_register_types(void)
 910 {
 911     type_register_static(&tcx_info);
 912 }
 913
 914 type_init(tcx_register_types)