2 * QEMU model of the Milkymist SD Card Controller.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://milkymist.walle.cc/socdoc/memcard.pdf
24 #include "qemu/osdep.h"
26 #include "qemu/module.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
30 #include "qapi/error.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/blockdev.h"
33 #include "hw/qdev-properties.h"
35 #include "qom/object.h"
38 ENABLE_CMD_TX
= (1<<0),
39 ENABLE_CMD_RX
= (1<<1),
40 ENABLE_DAT_TX
= (1<<2),
41 ENABLE_DAT_RX
= (1<<3),
45 PENDING_CMD_TX
= (1<<0),
46 PENDING_CMD_RX
= (1<<1),
47 PENDING_DAT_TX
= (1<<2),
48 PENDING_DAT_RX
= (1<<3),
52 START_CMD_TX
= (1<<0),
53 START_DAT_RX
= (1<<1),
66 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
67 typedef struct MilkymistMemcardState MilkymistMemcardState
;
68 DECLARE_INSTANCE_CHECKER(MilkymistMemcardState
, MILKYMIST_MEMCARD
,
69 TYPE_MILKYMIST_MEMCARD
)
71 #define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
73 struct MilkymistMemcardState
{
74 SysBusDevice parent_obj
;
76 MemoryRegion regs_region
;
79 int command_write_ptr
;
80 int response_read_ptr
;
89 static void update_pending_bits(MilkymistMemcardState
*s
)
91 /* transmits are instantaneous, thus tx pending bits are never set */
92 s
->regs
[R_PENDING
] = 0;
93 /* if rx is enabled the corresponding pending bits are always set */
94 if (s
->regs
[R_ENABLE
] & ENABLE_CMD_RX
) {
95 s
->regs
[R_PENDING
] |= PENDING_CMD_RX
;
97 if (s
->regs
[R_ENABLE
] & ENABLE_DAT_RX
) {
98 s
->regs
[R_PENDING
] |= PENDING_DAT_RX
;
102 static void memcard_sd_command(MilkymistMemcardState
*s
)
106 req
.cmd
= s
->command
[0] & 0x3f;
107 req
.arg
= ldl_be_p(s
->command
+ 1);
108 req
.crc
= s
->command
[5];
110 s
->response
[0] = req
.cmd
;
111 s
->response_len
= sdbus_do_command(&s
->sdbus
, &req
, s
->response
+ 1);
112 s
->response_read_ptr
= 0;
114 if (s
->response_len
== 16) {
116 s
->response
[0] = 0x3f;
117 s
->response_len
+= 1;
118 } else if (s
->response_len
== 4) {
119 /* no crc calculation, insert dummy byte */
121 s
->response_len
+= 2;
125 /* next write is a dummy byte to clock the initialization of the sd
127 s
->ignore_next_cmd
= 1;
131 static uint64_t memcard_read(void *opaque
, hwaddr addr
,
134 MilkymistMemcardState
*s
= opaque
;
143 r
= s
->response
[s
->response_read_ptr
++];
144 if (s
->response_read_ptr
> s
->response_len
) {
145 qemu_log_mask(LOG_GUEST_ERROR
, "milkymist_memcard: "
146 "read more cmd bytes than available: clipping\n");
147 s
->response_read_ptr
= 0;
155 sdbus_read_data(&s
->sdbus
, &r
, sizeof(r
));
167 qemu_log_mask(LOG_UNIMP
, "milkymist_memcard: "
168 "read access to unknown register 0x%" HWADDR_PRIx
"\n",
173 trace_milkymist_memcard_memory_read(addr
<< 2, r
);
178 static void memcard_write(void *opaque
, hwaddr addr
, uint64_t value
,
181 MilkymistMemcardState
*s
= opaque
;
184 trace_milkymist_memcard_memory_write(addr
, value
);
189 /* clear rx pending bits */
190 s
->regs
[R_PENDING
] &= ~(value
& (PENDING_CMD_RX
| PENDING_DAT_RX
));
191 update_pending_bits(s
);
197 if (s
->ignore_next_cmd
) {
198 s
->ignore_next_cmd
= 0;
201 s
->command
[s
->command_write_ptr
] = value
& 0xff;
202 s
->command_write_ptr
= (s
->command_write_ptr
+ 1) % 6;
203 if (s
->command_write_ptr
== 0) {
204 memcard_sd_command(s
);
211 val32
= cpu_to_be32(value
);
212 sdbus_write_data(&s
->sdbus
, &val32
, sizeof(val32
));
215 s
->regs
[addr
] = value
;
216 update_pending_bits(s
);
220 s
->regs
[addr
] = value
;
224 qemu_log_mask(LOG_UNIMP
, "milkymist_memcard: "
225 "write access to unknown register 0x%" HWADDR_PRIx
" "
226 "(value 0x%" PRIx64
")\n", addr
<< 2, value
);
231 static const MemoryRegionOps memcard_mmio_ops
= {
232 .read
= memcard_read
,
233 .write
= memcard_write
,
235 .min_access_size
= 4,
236 .max_access_size
= 4,
238 .endianness
= DEVICE_NATIVE_ENDIAN
,
241 static void milkymist_memcard_reset(DeviceState
*d
)
243 MilkymistMemcardState
*s
= MILKYMIST_MEMCARD(d
);
246 s
->command_write_ptr
= 0;
247 s
->response_read_ptr
= 0;
250 for (i
= 0; i
< R_MAX
; i
++) {
255 static void milkymist_memcard_set_readonly(DeviceState
*dev
, bool level
)
257 qemu_log_mask(LOG_UNIMP
,
258 "milkymist_memcard: read-only mode not supported\n");
261 static void milkymist_memcard_set_inserted(DeviceState
*dev
, bool level
)
263 MilkymistMemcardState
*s
= MILKYMIST_MEMCARD(dev
);
265 s
->enabled
= !!level
;
268 static void milkymist_memcard_init(Object
*obj
)
270 MilkymistMemcardState
*s
= MILKYMIST_MEMCARD(obj
);
271 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
273 memory_region_init_io(&s
->regs_region
, OBJECT(s
), &memcard_mmio_ops
, s
,
274 "milkymist-memcard", R_MAX
* 4);
275 sysbus_init_mmio(dev
, &s
->regs_region
);
277 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
), TYPE_SD_BUS
,
278 DEVICE(obj
), "sd-bus");
281 static const VMStateDescription vmstate_milkymist_memcard
= {
282 .name
= "milkymist-memcard",
284 .minimum_version_id
= 1,
285 .fields
= (VMStateField
[]) {
286 VMSTATE_INT32(command_write_ptr
, MilkymistMemcardState
),
287 VMSTATE_INT32(response_read_ptr
, MilkymistMemcardState
),
288 VMSTATE_INT32(response_len
, MilkymistMemcardState
),
289 VMSTATE_INT32(ignore_next_cmd
, MilkymistMemcardState
),
290 VMSTATE_INT32(enabled
, MilkymistMemcardState
),
291 VMSTATE_UINT8_ARRAY(command
, MilkymistMemcardState
, 6),
292 VMSTATE_UINT8_ARRAY(response
, MilkymistMemcardState
, 17),
293 VMSTATE_UINT32_ARRAY(regs
, MilkymistMemcardState
, R_MAX
),
294 VMSTATE_END_OF_LIST()
298 static void milkymist_memcard_class_init(ObjectClass
*klass
, void *data
)
300 DeviceClass
*dc
= DEVICE_CLASS(klass
);
302 dc
->reset
= milkymist_memcard_reset
;
303 dc
->vmsd
= &vmstate_milkymist_memcard
;
304 /* Reason: output IRQs should be wired up */
305 dc
->user_creatable
= false;
308 static const TypeInfo milkymist_memcard_info
= {
309 .name
= TYPE_MILKYMIST_MEMCARD
,
310 .parent
= TYPE_SYS_BUS_DEVICE
,
311 .instance_size
= sizeof(MilkymistMemcardState
),
312 .instance_init
= milkymist_memcard_init
,
313 .class_init
= milkymist_memcard_class_init
,
316 static void milkymist_sdbus_class_init(ObjectClass
*klass
, void *data
)
318 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
320 sbc
->set_inserted
= milkymist_memcard_set_inserted
;
321 sbc
->set_readonly
= milkymist_memcard_set_readonly
;
324 static const TypeInfo milkymist_sdbus_info
= {
325 .name
= TYPE_MILKYMIST_SDBUS
,
326 .parent
= TYPE_SD_BUS
,
327 .instance_size
= sizeof(SDBus
),
328 .class_init
= milkymist_sdbus_class_init
,
331 static void milkymist_memcard_register_types(void)
333 type_register_static(&milkymist_memcard_info
);
334 type_register_static(&milkymist_sdbus_info
);
337 type_init(milkymist_memcard_register_types
)