2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
14 #include "hw/i386/pc.h"
15 #include "hw/isa/vt82c686.h"
16 #include "hw/i2c/i2c.h"
17 #include "hw/i2c/smbus.h"
18 #include "hw/pci/pci.h"
19 #include "hw/isa/isa.h"
20 #include "hw/sysbus.h"
21 #include "hw/mips/mips.h"
22 #include "hw/isa/apm.h"
23 #include "hw/acpi/acpi.h"
24 #include "hw/i2c/pm_smbus.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/timer.h"
27 #include "exec/address-spaces.h"
29 //#define DEBUG_VT82C686B
31 #ifdef DEBUG_VT82C686B
32 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
34 #define DPRINTF(fmt, ...)
37 typedef struct SuperIOConfig
44 typedef struct VT82C686BState
{
47 SuperIOConfig superio_conf
;
50 static void superio_ioport_writeb(void *opaque
, hwaddr addr
, uint64_t data
,
54 SuperIOConfig
*superio_conf
= opaque
;
56 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr
, data
);
58 superio_conf
->index
= data
& 0xff;
61 switch (superio_conf
->index
) {
77 switch (superio_conf
->index
) {
79 if ((data
& 0xff) != 0xfe) {
80 DPRINTF("chage uart 1 base. unsupported yet\n");
84 if ((data
& 0xff) != 0xbe) {
85 DPRINTF("chage uart 2 base. unsupported yet\n");
90 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
94 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
98 static uint64_t superio_ioport_readb(void *opaque
, hwaddr addr
, unsigned size
)
100 SuperIOConfig
*superio_conf
= opaque
;
102 DPRINTF("superio_ioport_readb address 0x%x\n", addr
);
103 return (superio_conf
->config
[superio_conf
->index
]);
106 static const MemoryRegionOps superio_ops
= {
107 .read
= superio_ioport_readb
,
108 .write
= superio_ioport_writeb
,
109 .endianness
= DEVICE_NATIVE_ENDIAN
,
111 .min_access_size
= 1,
112 .max_access_size
= 1,
116 static void vt82c686b_reset(void * opaque
)
118 PCIDevice
*d
= opaque
;
119 uint8_t *pci_conf
= d
->config
;
120 VT82C686BState
*vt82c
= DO_UPCAST(VT82C686BState
, dev
, d
);
122 pci_set_long(pci_conf
+ PCI_CAPABILITY_LIST
, 0x000000c0);
123 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
124 PCI_COMMAND_MASTER
| PCI_COMMAND_SPECIAL
);
125 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
127 pci_conf
[0x48] = 0x01; /* Miscellaneous Control 3 */
128 pci_conf
[0x4a] = 0x04; /* IDE interrupt Routing */
129 pci_conf
[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
130 pci_conf
[0x50] = 0x2d; /* PnP DMA Request Control */
131 pci_conf
[0x59] = 0x04;
132 pci_conf
[0x5a] = 0x04; /* KBC/RTC Control*/
133 pci_conf
[0x5f] = 0x04;
134 pci_conf
[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
136 vt82c
->superio_conf
.config
[0xe0] = 0x3c;
137 vt82c
->superio_conf
.config
[0xe2] = 0x03;
138 vt82c
->superio_conf
.config
[0xe3] = 0xfc;
139 vt82c
->superio_conf
.config
[0xe6] = 0xde;
140 vt82c
->superio_conf
.config
[0xe7] = 0xfe;
141 vt82c
->superio_conf
.config
[0xe8] = 0xbe;
144 /* write config pci function0 registers. PCI-ISA bridge */
145 static void vt82c686b_write_config(PCIDevice
* d
, uint32_t address
,
146 uint32_t val
, int len
)
148 VT82C686BState
*vt686
= DO_UPCAST(VT82C686BState
, dev
, d
);
150 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
153 pci_default_write_config(d
, address
, val
, len
);
154 if (address
== 0x85) { /* enable or disable super IO configure */
155 memory_region_set_enabled(&vt686
->superio
, val
& 0x2);
159 #define ACPI_DBG_IO_ADDR 0xb044
161 typedef struct VT686PMState
{
167 uint32_t smb_io_base
;
170 typedef struct VT686AC97State
{
174 typedef struct VT686MC97State
{
178 static void pm_update_sci(VT686PMState
*s
)
180 int sci_level
, pmsts
;
182 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
183 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
184 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
185 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
186 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
187 ACPI_BITMASK_TIMER_ENABLE
)) != 0);
188 qemu_set_irq(s
->dev
.irq
[0], sci_level
);
189 /* schedule a timer interruption if needed */
190 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
191 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
194 static void pm_tmr_timer(ACPIREGS
*ar
)
196 VT686PMState
*s
= container_of(ar
, VT686PMState
, ar
);
200 static void pm_io_space_update(VT686PMState
*s
)
204 pm_io_base
= pci_get_long(s
->dev
.config
+ 0x40);
205 pm_io_base
&= 0xffc0;
207 memory_region_transaction_begin();
208 memory_region_set_enabled(&s
->io
, s
->dev
.config
[0x80] & 1);
209 memory_region_set_address(&s
->io
, pm_io_base
);
210 memory_region_transaction_commit();
213 static void pm_write_config(PCIDevice
*d
,
214 uint32_t address
, uint32_t val
, int len
)
216 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
218 pci_default_write_config(d
, address
, val
, len
);
221 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
223 VT686PMState
*s
= opaque
;
225 pm_io_space_update(s
);
229 static const VMStateDescription vmstate_acpi
= {
230 .name
= "vt82c686b_pm",
232 .minimum_version_id
= 1,
233 .minimum_version_id_old
= 1,
234 .post_load
= vmstate_acpi_post_load
,
235 .fields
= (VMStateField
[]) {
236 VMSTATE_PCI_DEVICE(dev
, VT686PMState
),
237 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, VT686PMState
),
238 VMSTATE_UINT16(ar
.pm1
.evt
.en
, VT686PMState
),
239 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, VT686PMState
),
240 VMSTATE_STRUCT(apm
, VT686PMState
, 0, vmstate_apm
, APMState
),
241 VMSTATE_TIMER(ar
.tmr
.timer
, VT686PMState
),
242 VMSTATE_INT64(ar
.tmr
.overflow_time
, VT686PMState
),
243 VMSTATE_END_OF_LIST()
248 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
249 * just register a PCI device now, functionalities will be implemented later.
252 static int vt82c686b_ac97_initfn(PCIDevice
*dev
)
254 VT686AC97State
*s
= DO_UPCAST(VT686AC97State
, dev
, dev
);
255 uint8_t *pci_conf
= s
->dev
.config
;
257 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
259 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_CAP_LIST
|
260 PCI_STATUS_DEVSEL_MEDIUM
);
261 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
266 void vt82c686b_ac97_init(PCIBus
*bus
, int devfn
)
270 dev
= pci_create(bus
, devfn
, "VT82C686B_AC97");
271 qdev_init_nofail(&dev
->qdev
);
274 static void via_ac97_class_init(ObjectClass
*klass
, void *data
)
276 DeviceClass
*dc
= DEVICE_CLASS(klass
);
277 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
279 k
->init
= vt82c686b_ac97_initfn
;
280 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
281 k
->device_id
= PCI_DEVICE_ID_VIA_AC97
;
283 k
->class_id
= PCI_CLASS_MULTIMEDIA_AUDIO
;
287 static const TypeInfo via_ac97_info
= {
288 .name
= "VT82C686B_AC97",
289 .parent
= TYPE_PCI_DEVICE
,
290 .instance_size
= sizeof(VT686AC97State
),
291 .class_init
= via_ac97_class_init
,
294 static int vt82c686b_mc97_initfn(PCIDevice
*dev
)
296 VT686MC97State
*s
= DO_UPCAST(VT686MC97State
, dev
, dev
);
297 uint8_t *pci_conf
= s
->dev
.config
;
299 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
300 PCI_COMMAND_VGA_PALETTE
);
301 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
302 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
307 void vt82c686b_mc97_init(PCIBus
*bus
, int devfn
)
311 dev
= pci_create(bus
, devfn
, "VT82C686B_MC97");
312 qdev_init_nofail(&dev
->qdev
);
315 static void via_mc97_class_init(ObjectClass
*klass
, void *data
)
317 DeviceClass
*dc
= DEVICE_CLASS(klass
);
318 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
320 k
->init
= vt82c686b_mc97_initfn
;
321 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
322 k
->device_id
= PCI_DEVICE_ID_VIA_MC97
;
323 k
->class_id
= PCI_CLASS_COMMUNICATION_OTHER
;
328 static const TypeInfo via_mc97_info
= {
329 .name
= "VT82C686B_MC97",
330 .parent
= TYPE_PCI_DEVICE
,
331 .instance_size
= sizeof(VT686MC97State
),
332 .class_init
= via_mc97_class_init
,
335 /* vt82c686 pm init */
336 static int vt82c686b_pm_initfn(PCIDevice
*dev
)
338 VT686PMState
*s
= DO_UPCAST(VT686PMState
, dev
, dev
);
341 pci_conf
= s
->dev
.config
;
342 pci_set_word(pci_conf
+ PCI_COMMAND
, 0);
343 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_FAST_BACK
|
344 PCI_STATUS_DEVSEL_MEDIUM
);
346 /* 0x48-0x4B is Power Management I/O Base */
347 pci_set_long(pci_conf
+ 0x48, 0x00000001);
349 /* SMB ports:0xeee0~0xeeef */
350 s
->smb_io_base
=((s
->smb_io_base
& 0xfff0) + 0x0);
351 pci_conf
[0x90] = s
->smb_io_base
| 1;
352 pci_conf
[0x91] = s
->smb_io_base
>> 8;
353 pci_conf
[0xd2] = 0x90;
354 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
355 memory_region_add_subregion(get_system_io(), s
->smb_io_base
, &s
->smb
.io
);
357 apm_init(dev
, &s
->apm
, NULL
, s
);
359 memory_region_init(&s
->io
, OBJECT(dev
), "vt82c686-pm", 64);
360 memory_region_set_enabled(&s
->io
, false);
361 memory_region_add_subregion(get_system_io(), 0, &s
->io
);
363 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
364 acpi_pm1_evt_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
365 acpi_pm1_cnt_init(&s
->ar
, &s
->io
, 2);
370 i2c_bus
*vt82c686b_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
376 dev
= pci_create(bus
, devfn
, "VT82C686B_PM");
377 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
379 s
= DO_UPCAST(VT686PMState
, dev
, dev
);
381 qdev_init_nofail(&dev
->qdev
);
386 static Property via_pm_properties
[] = {
387 DEFINE_PROP_UINT32("smb_io_base", VT686PMState
, smb_io_base
, 0),
388 DEFINE_PROP_END_OF_LIST(),
391 static void via_pm_class_init(ObjectClass
*klass
, void *data
)
393 DeviceClass
*dc
= DEVICE_CLASS(klass
);
394 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
396 k
->init
= vt82c686b_pm_initfn
;
397 k
->config_write
= pm_write_config
;
398 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
399 k
->device_id
= PCI_DEVICE_ID_VIA_ACPI
;
400 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
403 dc
->vmsd
= &vmstate_acpi
;
404 dc
->props
= via_pm_properties
;
407 static const TypeInfo via_pm_info
= {
408 .name
= "VT82C686B_PM",
409 .parent
= TYPE_PCI_DEVICE
,
410 .instance_size
= sizeof(VT686PMState
),
411 .class_init
= via_pm_class_init
,
414 static const VMStateDescription vmstate_via
= {
417 .minimum_version_id
= 1,
418 .minimum_version_id_old
= 1,
419 .fields
= (VMStateField
[]) {
420 VMSTATE_PCI_DEVICE(dev
, VT82C686BState
),
421 VMSTATE_END_OF_LIST()
425 /* init the PCI-to-ISA bridge */
426 static int vt82c686b_initfn(PCIDevice
*d
)
428 VT82C686BState
*vt82c
= DO_UPCAST(VT82C686BState
, dev
, d
);
434 isa_bus
= isa_bus_new(&d
->qdev
, pci_address_space_io(d
));
436 pci_conf
= d
->config
;
437 pci_config_set_prog_interface(pci_conf
, 0x0);
440 for (i
= 0x00; i
< 0xff; i
++) {
441 if (i
<=0x03 || (i
>=0x08 && i
<=0x3f)) {
446 memory_region_init_io(&vt82c
->superio
, OBJECT(d
), &superio_ops
,
447 &vt82c
->superio_conf
, "superio", 2);
448 memory_region_set_enabled(&vt82c
->superio
, false);
449 /* The floppy also uses 0x3f0 and 0x3f1.
450 * But we do not emulate a floppy, so just set it here. */
451 memory_region_add_subregion(isa_bus
->address_space_io
, 0x3f0,
454 qemu_register_reset(vt82c686b_reset
, d
);
459 ISABus
*vt82c686b_init(PCIBus
*bus
, int devfn
)
463 d
= pci_create_simple_multifunction(bus
, devfn
, true, "VT82C686B");
465 return ISA_BUS(qdev_get_child_bus(DEVICE(d
), "isa.0"));
468 static void via_class_init(ObjectClass
*klass
, void *data
)
470 DeviceClass
*dc
= DEVICE_CLASS(klass
);
471 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
473 k
->init
= vt82c686b_initfn
;
474 k
->config_write
= vt82c686b_write_config
;
475 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
476 k
->device_id
= PCI_DEVICE_ID_VIA_ISA_BRIDGE
;
477 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
479 dc
->desc
= "ISA bridge";
481 dc
->vmsd
= &vmstate_via
;
484 static const TypeInfo via_info
= {
486 .parent
= TYPE_PCI_DEVICE
,
487 .instance_size
= sizeof(VT82C686BState
),
488 .class_init
= via_class_init
,
491 static void vt82c686b_register_types(void)
493 type_register_static(&via_ac97_info
);
494 type_register_static(&via_mc97_info
);
495 type_register_static(&via_pm_info
);
496 type_register_static(&via_info
);
499 type_init(vt82c686b_register_types
)