4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
25 #include "internals.h"
26 #include "exec/exec-all.h"
27 #include "qapi/error.h"
28 #include "qemu/error-report.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "fpu/softfloat-helpers.h"
33 /* RISC-V CPU definitions */
35 static const char riscv_exts
[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
37 const char * const riscv_int_regnames
[] = {
38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
42 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
45 const char * const riscv_fpr_regnames
[] = {
46 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
47 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
48 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
49 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
50 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
51 "f30/ft10", "f31/ft11"
54 static const char * const riscv_excp_names
[] = {
57 "illegal_instruction",
75 "guest_exec_page_fault",
76 "guest_load_page_fault",
78 "guest_store_page_fault",
81 static const char * const riscv_intr_names
[] = {
100 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
)
103 return (cause
< ARRAY_SIZE(riscv_intr_names
)) ?
104 riscv_intr_names
[cause
] : "(unknown)";
106 return (cause
< ARRAY_SIZE(riscv_excp_names
)) ?
107 riscv_excp_names
[cause
] : "(unknown)";
111 static void set_misa(CPURISCVState
*env
, RISCVMXL mxl
, uint32_t ext
)
113 env
->misa_mxl_max
= env
->misa_mxl
= mxl
;
114 env
->misa_ext_mask
= env
->misa_ext
= ext
;
117 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
119 env
->priv_ver
= priv_ver
;
122 static void set_vext_version(CPURISCVState
*env
, int vext_ver
)
124 env
->vext_ver
= vext_ver
;
127 static void set_feature(CPURISCVState
*env
, int feature
)
129 env
->features
|= (1ULL << feature
);
132 static void set_resetvec(CPURISCVState
*env
, target_ulong resetvec
)
134 #ifndef CONFIG_USER_ONLY
135 env
->resetvec
= resetvec
;
139 static void riscv_any_cpu_init(Object
*obj
)
141 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
142 #if defined(TARGET_RISCV32)
143 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
144 #elif defined(TARGET_RISCV64)
145 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
147 set_priv_version(env
, PRIV_VERSION_1_11_0
);
150 #if defined(TARGET_RISCV64)
151 static void rv64_base_cpu_init(Object
*obj
)
153 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
154 /* We set this in the realise function */
155 set_misa(env
, MXL_RV64
, 0);
158 static void rv64_sifive_u_cpu_init(Object
*obj
)
160 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
161 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
162 set_priv_version(env
, PRIV_VERSION_1_10_0
);
165 static void rv64_sifive_e_cpu_init(Object
*obj
)
167 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
168 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVC
| RVU
);
169 set_priv_version(env
, PRIV_VERSION_1_10_0
);
170 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
173 static void rv32_base_cpu_init(Object
*obj
)
175 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
176 /* We set this in the realise function */
177 set_misa(env
, MXL_RV32
, 0);
180 static void rv32_sifive_u_cpu_init(Object
*obj
)
182 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
183 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
184 set_priv_version(env
, PRIV_VERSION_1_10_0
);
187 static void rv32_sifive_e_cpu_init(Object
*obj
)
189 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
190 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVC
| RVU
);
191 set_priv_version(env
, PRIV_VERSION_1_10_0
);
192 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
195 static void rv32_ibex_cpu_init(Object
*obj
)
197 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
198 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVC
| RVU
);
199 set_priv_version(env
, PRIV_VERSION_1_10_0
);
200 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
201 qdev_prop_set_bit(DEVICE(obj
), "x-epmp", true);
204 static void rv32_imafcu_nommu_cpu_init(Object
*obj
)
206 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
207 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVC
| RVU
);
208 set_priv_version(env
, PRIV_VERSION_1_10_0
);
209 set_resetvec(env
, DEFAULT_RSTVEC
);
210 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
214 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
220 cpuname
= g_strsplit(cpu_model
, ",", 1);
221 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
222 oc
= object_class_by_name(typename
);
225 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
226 object_class_is_abstract(oc
)) {
232 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
234 RISCVCPU
*cpu
= RISCV_CPU(cs
);
235 CPURISCVState
*env
= &cpu
->env
;
238 #if !defined(CONFIG_USER_ONLY)
239 if (riscv_has_ext(env
, RVH
)) {
240 qemu_fprintf(f
, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env
));
243 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
244 #ifndef CONFIG_USER_ONLY
246 static const int dump_csrs
[] = {
283 for (int i
= 0; i
< ARRAY_SIZE(dump_csrs
); ++i
) {
284 int csrno
= dump_csrs
[i
];
285 target_ulong val
= 0;
286 RISCVException res
= riscv_csrrw_debug(env
, csrno
, &val
, 0, 0);
289 * Rely on the smode, hmode, etc, predicates within csr.c
290 * to do the filtering of the registers that are present.
292 if (res
== RISCV_EXCP_NONE
) {
293 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
"\n",
294 csr_ops
[csrno
].name
, val
);
300 for (i
= 0; i
< 32; i
++) {
301 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
,
302 riscv_int_regnames
[i
], env
->gpr
[i
]);
304 qemu_fprintf(f
, "\n");
307 if (flags
& CPU_DUMP_FPU
) {
308 for (i
= 0; i
< 32; i
++) {
309 qemu_fprintf(f
, " %-8s %016" PRIx64
,
310 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
312 qemu_fprintf(f
, "\n");
318 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
320 RISCVCPU
*cpu
= RISCV_CPU(cs
);
321 CPURISCVState
*env
= &cpu
->env
;
325 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
,
326 const TranslationBlock
*tb
)
328 RISCVCPU
*cpu
= RISCV_CPU(cs
);
329 CPURISCVState
*env
= &cpu
->env
;
333 static bool riscv_cpu_has_work(CPUState
*cs
)
335 #ifndef CONFIG_USER_ONLY
336 RISCVCPU
*cpu
= RISCV_CPU(cs
);
337 CPURISCVState
*env
= &cpu
->env
;
339 * Definition of the WFI instruction requires it to ignore the privilege
340 * mode and delegation registers, but respect individual enables
342 return (env
->mip
& env
->mie
) != 0;
348 void restore_state_to_opc(CPURISCVState
*env
, TranslationBlock
*tb
,
354 static void riscv_cpu_reset(DeviceState
*dev
)
356 CPUState
*cs
= CPU(dev
);
357 RISCVCPU
*cpu
= RISCV_CPU(cs
);
358 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
359 CPURISCVState
*env
= &cpu
->env
;
361 mcc
->parent_reset(dev
);
362 #ifndef CONFIG_USER_ONLY
363 env
->misa_mxl
= env
->misa_mxl_max
;
365 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
366 if (env
->misa_mxl
> MXL_RV32
) {
368 * The reset status of SXL/UXL is undefined, but mstatus is WARL
369 * and we must ensure that the value after init is valid for read.
371 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_SXL
, env
->misa_mxl
);
372 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_UXL
, env
->misa_mxl
);
375 env
->pc
= env
->resetvec
;
376 env
->two_stage_lookup
= false;
377 /* mmte is supposed to have pm.current hardwired to 1 */
378 env
->mmte
|= (PM_EXT_INITIAL
| MMTE_M_PM_CURRENT
);
380 cs
->exception_index
= RISCV_EXCP_NONE
;
382 set_default_nan_mode(1, &env
->fp_status
);
385 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
387 RISCVCPU
*cpu
= RISCV_CPU(s
);
389 switch (riscv_cpu_mxl(&cpu
->env
)) {
391 info
->print_insn
= print_insn_riscv32
;
394 info
->print_insn
= print_insn_riscv64
;
397 g_assert_not_reached();
401 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
403 CPUState
*cs
= CPU(dev
);
404 RISCVCPU
*cpu
= RISCV_CPU(dev
);
405 CPURISCVState
*env
= &cpu
->env
;
406 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
407 int priv_version
= 0;
408 Error
*local_err
= NULL
;
410 cpu_exec_realizefn(cs
, &local_err
);
411 if (local_err
!= NULL
) {
412 error_propagate(errp
, local_err
);
416 if (cpu
->cfg
.priv_spec
) {
417 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
418 priv_version
= PRIV_VERSION_1_11_0
;
419 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
420 priv_version
= PRIV_VERSION_1_10_0
;
423 "Unsupported privilege spec version '%s'",
430 set_priv_version(env
, priv_version
);
431 } else if (!env
->priv_ver
) {
432 set_priv_version(env
, PRIV_VERSION_1_11_0
);
436 set_feature(env
, RISCV_FEATURE_MMU
);
440 set_feature(env
, RISCV_FEATURE_PMP
);
443 * Enhanced PMP should only be available
444 * on harts with PMP support
447 set_feature(env
, RISCV_FEATURE_EPMP
);
451 set_resetvec(env
, cpu
->cfg
.resetvec
);
453 /* Validate that MISA_MXL is set properly. */
454 switch (env
->misa_mxl_max
) {
455 #ifdef TARGET_RISCV64
462 g_assert_not_reached();
464 assert(env
->misa_mxl_max
== env
->misa_mxl
);
466 /* If only MISA_EXT is unset for misa, then set it from properties */
467 if (env
->misa_ext
== 0) {
470 /* Do some ISA extension error checking */
471 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
473 "I and E extensions are incompatible");
477 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
479 "Either I or E extension must be set");
483 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
& cpu
->cfg
.ext_m
&
484 cpu
->cfg
.ext_a
& cpu
->cfg
.ext_f
&
486 warn_report("Setting G will also set IMAFD");
487 cpu
->cfg
.ext_i
= true;
488 cpu
->cfg
.ext_m
= true;
489 cpu
->cfg
.ext_a
= true;
490 cpu
->cfg
.ext_f
= true;
491 cpu
->cfg
.ext_d
= true;
494 /* Set the ISA extensions, checks should have happened above */
495 if (cpu
->cfg
.ext_i
) {
498 if (cpu
->cfg
.ext_e
) {
501 if (cpu
->cfg
.ext_m
) {
504 if (cpu
->cfg
.ext_a
) {
507 if (cpu
->cfg
.ext_f
) {
510 if (cpu
->cfg
.ext_d
) {
513 if (cpu
->cfg
.ext_c
) {
516 if (cpu
->cfg
.ext_s
) {
519 if (cpu
->cfg
.ext_u
) {
522 if (cpu
->cfg
.ext_h
) {
525 if (cpu
->cfg
.ext_v
) {
526 int vext_version
= VEXT_VERSION_0_07_1
;
528 if (!is_power_of_2(cpu
->cfg
.vlen
)) {
530 "Vector extension VLEN must be power of 2");
533 if (cpu
->cfg
.vlen
> RV_VLEN_MAX
|| cpu
->cfg
.vlen
< 128) {
535 "Vector extension implementation only supports VLEN "
536 "in the range [128, %d]", RV_VLEN_MAX
);
539 if (!is_power_of_2(cpu
->cfg
.elen
)) {
541 "Vector extension ELEN must be power of 2");
544 if (cpu
->cfg
.elen
> 64 || cpu
->cfg
.vlen
< 8) {
546 "Vector extension implementation only supports ELEN "
547 "in the range [8, 64]");
550 if (cpu
->cfg
.vext_spec
) {
551 if (!g_strcmp0(cpu
->cfg
.vext_spec
, "v0.7.1")) {
552 vext_version
= VEXT_VERSION_0_07_1
;
555 "Unsupported vector spec version '%s'",
560 qemu_log("vector version is not specified, "
561 "use the default value v0.7.1\n");
563 set_vext_version(env
, vext_version
);
565 if (cpu
->cfg
.ext_j
) {
569 set_misa(env
, env
->misa_mxl
, ext
);
572 riscv_cpu_register_gdb_regs_for_features(cs
);
577 mcc
->parent_realize(dev
, errp
);
580 #ifndef CONFIG_USER_ONLY
581 static void riscv_cpu_set_irq(void *opaque
, int irq
, int level
)
583 RISCVCPU
*cpu
= RISCV_CPU(opaque
);
598 riscv_cpu_update_mip(cpu
, 1 << irq
, BOOL_TO_MASK(level
));
601 g_assert_not_reached();
604 #endif /* CONFIG_USER_ONLY */
606 static void riscv_cpu_init(Object
*obj
)
608 RISCVCPU
*cpu
= RISCV_CPU(obj
);
610 cpu_set_cpustate_pointers(cpu
);
612 #ifndef CONFIG_USER_ONLY
613 qdev_init_gpio_in(DEVICE(cpu
), riscv_cpu_set_irq
, 12);
614 #endif /* CONFIG_USER_ONLY */
617 static Property riscv_cpu_properties
[] = {
618 /* Defaults for standard extensions */
619 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
620 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
621 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, true),
622 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
623 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
624 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
625 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
626 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
627 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
628 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
629 DEFINE_PROP_BOOL("Counters", RISCVCPU
, cfg
.ext_counters
, true),
630 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
631 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
632 DEFINE_PROP_BOOL("Zfh", RISCVCPU
, cfg
.ext_zfh
, false),
633 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
634 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
636 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
638 /* These are experimental so mark with 'x-' */
639 DEFINE_PROP_BOOL("x-zba", RISCVCPU
, cfg
.ext_zba
, false),
640 DEFINE_PROP_BOOL("x-zbb", RISCVCPU
, cfg
.ext_zbb
, false),
641 DEFINE_PROP_BOOL("x-zbc", RISCVCPU
, cfg
.ext_zbc
, false),
642 DEFINE_PROP_BOOL("x-zbs", RISCVCPU
, cfg
.ext_zbs
, false),
643 DEFINE_PROP_BOOL("x-h", RISCVCPU
, cfg
.ext_h
, false),
644 DEFINE_PROP_BOOL("x-j", RISCVCPU
, cfg
.ext_j
, false),
645 DEFINE_PROP_BOOL("x-v", RISCVCPU
, cfg
.ext_v
, false),
646 DEFINE_PROP_STRING("vext_spec", RISCVCPU
, cfg
.vext_spec
),
647 DEFINE_PROP_UINT16("vlen", RISCVCPU
, cfg
.vlen
, 128),
648 DEFINE_PROP_UINT16("elen", RISCVCPU
, cfg
.elen
, 64),
650 DEFINE_PROP_BOOL("x-epmp", RISCVCPU
, cfg
.epmp
, false),
652 DEFINE_PROP_UINT64("resetvec", RISCVCPU
, cfg
.resetvec
, DEFAULT_RSTVEC
),
653 DEFINE_PROP_END_OF_LIST(),
656 static gchar
*riscv_gdb_arch_name(CPUState
*cs
)
658 RISCVCPU
*cpu
= RISCV_CPU(cs
);
659 CPURISCVState
*env
= &cpu
->env
;
661 switch (riscv_cpu_mxl(env
)) {
663 return g_strdup("riscv:rv32");
665 return g_strdup("riscv:rv64");
667 g_assert_not_reached();
671 static const char *riscv_gdb_get_dynamic_xml(CPUState
*cs
, const char *xmlname
)
673 RISCVCPU
*cpu
= RISCV_CPU(cs
);
675 if (strcmp(xmlname
, "riscv-csr.xml") == 0) {
676 return cpu
->dyn_csr_xml
;
682 #ifndef CONFIG_USER_ONLY
683 #include "hw/core/sysemu-cpu-ops.h"
685 static const struct SysemuCPUOps riscv_sysemu_ops
= {
686 .get_phys_page_debug
= riscv_cpu_get_phys_page_debug
,
687 .write_elf64_note
= riscv_cpu_write_elf64_note
,
688 .write_elf32_note
= riscv_cpu_write_elf32_note
,
689 .legacy_vmsd
= &vmstate_riscv_cpu
,
693 #include "hw/core/tcg-cpu-ops.h"
695 static const struct TCGCPUOps riscv_tcg_ops
= {
696 .initialize
= riscv_translate_init
,
697 .synchronize_from_tb
= riscv_cpu_synchronize_from_tb
,
699 #ifndef CONFIG_USER_ONLY
700 .tlb_fill
= riscv_cpu_tlb_fill
,
701 .cpu_exec_interrupt
= riscv_cpu_exec_interrupt
,
702 .do_interrupt
= riscv_cpu_do_interrupt
,
703 .do_transaction_failed
= riscv_cpu_do_transaction_failed
,
704 .do_unaligned_access
= riscv_cpu_do_unaligned_access
,
705 #endif /* !CONFIG_USER_ONLY */
708 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
710 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
711 CPUClass
*cc
= CPU_CLASS(c
);
712 DeviceClass
*dc
= DEVICE_CLASS(c
);
714 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
715 &mcc
->parent_realize
);
717 device_class_set_parent_reset(dc
, riscv_cpu_reset
, &mcc
->parent_reset
);
719 cc
->class_by_name
= riscv_cpu_class_by_name
;
720 cc
->has_work
= riscv_cpu_has_work
;
721 cc
->dump_state
= riscv_cpu_dump_state
;
722 cc
->set_pc
= riscv_cpu_set_pc
;
723 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
724 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
725 cc
->gdb_num_core_regs
= 33;
726 #if defined(TARGET_RISCV32)
727 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
728 #elif defined(TARGET_RISCV64)
729 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
731 cc
->gdb_stop_before_watchpoint
= true;
732 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
733 #ifndef CONFIG_USER_ONLY
734 cc
->sysemu_ops
= &riscv_sysemu_ops
;
736 cc
->gdb_arch_name
= riscv_gdb_arch_name
;
737 cc
->gdb_get_dynamic_xml
= riscv_gdb_get_dynamic_xml
;
738 cc
->tcg_ops
= &riscv_tcg_ops
;
740 device_class_set_props(dc
, riscv_cpu_properties
);
743 char *riscv_isa_string(RISCVCPU
*cpu
)
746 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_exts
) + 1;
747 char *isa_str
= g_new(char, maxlen
);
748 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
749 for (i
= 0; i
< sizeof(riscv_exts
); i
++) {
750 if (cpu
->env
.misa_ext
& RV(riscv_exts
[i
])) {
751 *p
++ = qemu_tolower(riscv_exts
[i
]);
758 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
760 ObjectClass
*class_a
= (ObjectClass
*)a
;
761 ObjectClass
*class_b
= (ObjectClass
*)b
;
762 const char *name_a
, *name_b
;
764 name_a
= object_class_get_name(class_a
);
765 name_b
= object_class_get_name(class_b
);
766 return strcmp(name_a
, name_b
);
769 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
771 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
772 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
774 qemu_printf("%.*s\n", len
, typename
);
777 void riscv_cpu_list(void)
781 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
782 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
783 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
787 #define DEFINE_CPU(type_name, initfn) \
790 .parent = TYPE_RISCV_CPU, \
791 .instance_init = initfn \
794 static const TypeInfo riscv_cpu_type_infos
[] = {
796 .name
= TYPE_RISCV_CPU
,
798 .instance_size
= sizeof(RISCVCPU
),
799 .instance_align
= __alignof__(RISCVCPU
),
800 .instance_init
= riscv_cpu_init
,
802 .class_size
= sizeof(RISCVCPUClass
),
803 .class_init
= riscv_cpu_class_init
,
805 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
806 #if defined(TARGET_RISCV32)
807 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, rv32_base_cpu_init
),
808 DEFINE_CPU(TYPE_RISCV_CPU_IBEX
, rv32_ibex_cpu_init
),
809 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rv32_sifive_e_cpu_init
),
810 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34
, rv32_imafcu_nommu_cpu_init
),
811 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rv32_sifive_u_cpu_init
),
812 #elif defined(TARGET_RISCV64)
813 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, rv64_base_cpu_init
),
814 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rv64_sifive_e_cpu_init
),
815 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rv64_sifive_u_cpu_init
),
816 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C
, rv64_sifive_u_cpu_init
),
820 DEFINE_TYPES(riscv_cpu_type_infos
)