target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25 #include "qemu/error-report.h"
  26 #include "sysemu/kvm.h"
  27 #include "qemu/error-report.h"
  28 #include "kvm_ppc.h"
  29 #include "mmu-hash64.h"
  30 #include "exec/log.h"
  31
  32 //#define DEBUG_SLB
  33
  34 #ifdef DEBUG_SLB
  35 #  define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
  36 #else
  37 #  define LOG_SLB(...) do { } while (0)
  38 #endif
  39
  40 /*
  41  * Used to indicate that a CPU has its hash page table (HPT) managed
  42  * within the host kernel
  43  */
  44 #define MMU_HASH64_KVM_MANAGED_HPT      ((void *)-1)
  45
  46 /*
  47  * SLB handling
  48  */
  49
  50 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
  51 {
  52     CPUPPCState *env = &cpu->env;
  53     uint64_t esid_256M, esid_1T;
  54     int n;
  55
  56     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  57
  58     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  59     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  60
  61     for (n = 0; n < env->slb_nr; n++) {
  62         ppc_slb_t *slb = &env->slb[n];
  63
  64         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  65                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  66         /* We check for 1T matches on all MMUs here - if the MMU
  67          * doesn't have 1T segment support, we will have prevented 1T
  68          * entries from being inserted in the slbmte code. */
  69         if (((slb->esid == esid_256M) &&
  70              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  71             || ((slb->esid == esid_1T) &&
  72                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  73             return slb;
  74         }
  75     }
  76
  77     return NULL;
  78 }
  79
  80 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
  81 {
  82     CPUPPCState *env = &cpu->env;
  83     int i;
  84     uint64_t slbe, slbv;
  85
  86     cpu_synchronize_state(CPU(cpu));
  87
  88     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  89     for (i = 0; i < env->slb_nr; i++) {
  90         slbe = env->slb[i].esid;
  91         slbv = env->slb[i].vsid;
  92         if (slbe == 0 && slbv == 0) {
  93             continue;
  94         }
  95         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  96                     i, slbe, slbv);
  97     }
  98 }
  99
 100 void helper_slbia(CPUPPCState *env)
 101 {
 102     int n;
 103
 104     /* XXX: Warning: slbia never invalidates the first segment */
 105     for (n = 1; n < env->slb_nr; n++) {
 106         ppc_slb_t *slb = &env->slb[n];
 107
 108         if (slb->esid & SLB_ESID_V) {
 109             slb->esid &= ~SLB_ESID_V;
 110             /* XXX: given the fact that segment size is 256 MB or 1TB,
 111              *      and we still don't have a tlb_flush_mask(env, n, mask)
 112              *      in QEMU, we just invalidate all TLBs
 113              */
 114             env->tlb_need_flush = 1;
 115         }
 116     }
 117 }
 118
 119 void helper_slbie(CPUPPCState *env, target_ulong addr)
 120 {
 121     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 122     ppc_slb_t *slb;
 123
 124     slb = slb_lookup(cpu, addr);
 125     if (!slb) {
 126         return;
 127     }
 128
 129     if (slb->esid & SLB_ESID_V) {
 130         slb->esid &= ~SLB_ESID_V;
 131
 132         /* XXX: given the fact that segment size is 256 MB or 1TB,
 133          *      and we still don't have a tlb_flush_mask(env, n, mask)
 134          *      in QEMU, we just invalidate all TLBs
 135          */
 136         env->tlb_need_flush = 1;
 137     }
 138 }
 139
 140 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
 141                   target_ulong esid, target_ulong vsid)
 142 {
 143     CPUPPCState *env = &cpu->env;
 144     ppc_slb_t *slb = &env->slb[slot];
 145     const struct ppc_one_seg_page_size *sps = NULL;
 146     int i;
 147
 148     if (slot >= env->slb_nr) {
 149         return -1; /* Bad slot number */
 150     }
 151     if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
 152         return -1; /* Reserved bits set */
 153     }
 154     if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 155         return -1; /* Bad segment size */
 156     }
 157     if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 158         return -1; /* 1T segment on MMU that doesn't support it */
 159     }
 160
 161     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 162         const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
 163
 164         if (!sps1->page_shift) {
 165             break;
 166         }
 167
 168         if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
 169             sps = sps1;
 170             break;
 171         }
 172     }
 173
 174     if (!sps) {
 175         error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
 176                      " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
 177                      slot, esid, vsid);
 178         return -1;
 179     }
 180
 181     slb->esid = esid;
 182     slb->vsid = vsid;
 183     slb->sps = sps;
 184
 185     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 186             " %016" PRIx64 "\n", __func__, slot, esid, vsid,
 187             slb->esid, slb->vsid);
 188
 189     return 0;
 190 }
 191
 192 static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
 193                              target_ulong *rt)
 194 {
 195     CPUPPCState *env = &cpu->env;
 196     int slot = rb & 0xfff;
 197     ppc_slb_t *slb = &env->slb[slot];
 198
 199     if (slot >= env->slb_nr) {
 200         return -1;
 201     }
 202
 203     *rt = slb->esid;
 204     return 0;
 205 }
 206
 207 static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
 208                              target_ulong *rt)
 209 {
 210     CPUPPCState *env = &cpu->env;
 211     int slot = rb & 0xfff;
 212     ppc_slb_t *slb = &env->slb[slot];
 213
 214     if (slot >= env->slb_nr) {
 215         return -1;
 216     }
 217
 218     *rt = slb->vsid;
 219     return 0;
 220 }
 221
 222 static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
 223                              target_ulong *rt)
 224 {
 225     CPUPPCState *env = &cpu->env;
 226     ppc_slb_t *slb;
 227
 228     if (!msr_is_64bit(env, env->msr)) {
 229         rb &= 0xffffffff;
 230     }
 231     slb = slb_lookup(cpu, rb);
 232     if (slb == NULL) {
 233         *rt = (target_ulong)-1ul;
 234     } else {
 235         *rt = slb->vsid;
 236     }
 237     return 0;
 238 }
 239
 240 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 241 {
 242     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 243
 244     if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
 245         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 246                                    POWERPC_EXCP_INVAL);
 247     }
 248 }
 249
 250 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 251 {
 252     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 253     target_ulong rt = 0;
 254
 255     if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
 256         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 257                                    POWERPC_EXCP_INVAL);
 258     }
 259     return rt;
 260 }
 261
 262 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
 263 {
 264     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 265     target_ulong rt = 0;
 266
 267     if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
 268         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 269                                    POWERPC_EXCP_INVAL);
 270     }
 271     return rt;
 272 }
 273
 274 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 275 {
 276     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 277     target_ulong rt = 0;
 278
 279     if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
 280         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 281                                    POWERPC_EXCP_INVAL);
 282     }
 283     return rt;
 284 }
 285
 286 /*
 287  * 64-bit hash table MMU handling
 288  */
 289 void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
 290                          Error **errp)
 291 {
 292     CPUPPCState *env = &cpu->env;
 293     target_ulong htabsize = value & SDR_64_HTABSIZE;
 294
 295     env->spr[SPR_SDR1] = value;
 296     if (htabsize > 28) {
 297         error_setg(errp,
 298                    "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
 299                    htabsize);
 300         htabsize = 28;
 301     }
 302     env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
 303     env->htab_base = value & SDR_64_HTABORG;
 304 }
 305
 306 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
 307                                  Error **errp)
 308 {
 309     CPUPPCState *env = &cpu->env;
 310     Error *local_err = NULL;
 311
 312     if (hpt) {
 313         env->external_htab = hpt;
 314     } else {
 315         env->external_htab = MMU_HASH64_KVM_MANAGED_HPT;
 316     }
 317     ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
 318                         &local_err);
 319     if (local_err) {
 320         error_propagate(errp, local_err);
 321         return;
 322     }
 323
 324     /* Not strictly necessary, but makes it clearer that an external
 325      * htab is in use when debugging */
 326     env->htab_base = -1;
 327
 328     if (kvm_enabled()) {
 329         if (kvmppc_put_books_sregs(cpu) < 0) {
 330             error_setg(errp, "Unable to update SDR1 in KVM");
 331         }
 332     }
 333 }
 334
 335 static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
 336                                ppc_slb_t *slb, ppc_hash_pte64_t pte)
 337 {
 338     CPUPPCState *env = &cpu->env;
 339     unsigned pp, key;
 340     /* Some pp bit combinations have undefined behaviour, so default
 341      * to no access in those cases */
 342     int prot = 0;
 343
 344     key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 345              : (slb->vsid & SLB_VSID_KS));
 346     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 347
 348     if (key == 0) {
 349         switch (pp) {
 350         case 0x0:
 351         case 0x1:
 352         case 0x2:
 353             prot = PAGE_READ | PAGE_WRITE;
 354             break;
 355
 356         case 0x3:
 357         case 0x6:
 358             prot = PAGE_READ;
 359             break;
 360         }
 361     } else {
 362         switch (pp) {
 363         case 0x0:
 364         case 0x6:
 365             prot = 0;
 366             break;
 367
 368         case 0x1:
 369         case 0x3:
 370             prot = PAGE_READ;
 371             break;
 372
 373         case 0x2:
 374             prot = PAGE_READ | PAGE_WRITE;
 375             break;
 376         }
 377     }
 378
 379     /* No execute if either noexec or guarded bits set */
 380     if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
 381         || (slb->vsid & SLB_VSID_N)) {
 382         prot |= PAGE_EXEC;
 383     }
 384
 385     return prot;
 386 }
 387
 388 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
 389 {
 390     CPUPPCState *env = &cpu->env;
 391     int key, amrbits;
 392     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 393
 394     /* Only recent MMUs implement Virtual Page Class Key Protection */
 395     if (!(env->mmu_model & POWERPC_MMU_AMR)) {
 396         return prot;
 397     }
 398
 399     key = HPTE64_R_KEY(pte.pte1);
 400     amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
 401
 402     /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
 403     /*         env->spr[SPR_AMR]); */
 404
 405     /*
 406      * A store is permitted if the AMR bit is 0. Remove write
 407      * protection if it is set.
 408      */
 409     if (amrbits & 0x2) {
 410         prot &= ~PAGE_WRITE;
 411     }
 412     /*
 413      * A load is permitted if the AMR bit is 0. Remove read
 414      * protection if it is set.
 415      */
 416     if (amrbits & 0x1) {
 417         prot &= ~PAGE_READ;
 418     }
 419
 420     return prot;
 421 }
 422
 423 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
 424 {
 425     uint64_t token = 0;
 426     hwaddr pte_offset;
 427
 428     pte_offset = pte_index * HASH_PTE_SIZE_64;
 429     if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 430         /*
 431          * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
 432          */
 433         token = kvmppc_hash64_read_pteg(cpu, pte_index);
 434     } else if (cpu->env.external_htab) {
 435         /*
 436          * HTAB is controlled by QEMU. Just point to the internally
 437          * accessible PTEG.
 438          */
 439         token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
 440     } else if (cpu->env.htab_base) {
 441         token = cpu->env.htab_base + pte_offset;
 442     }
 443     return token;
 444 }
 445
 446 void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token)
 447 {
 448     if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 449         kvmppc_hash64_free_pteg(token);
 450     }
 451 }
 452
 453 /* Returns the effective page shift or 0. MPSS isn't supported yet so
 454  * this will always be the slb_pshift or 0
 455  */
 456 static uint32_t ppc_hash64_pte_size_decode(uint64_t pte1, uint32_t slb_pshift)
 457 {
 458     switch (slb_pshift) {
 459     case 12:
 460         return 12;
 461     case 16:
 462         if ((pte1 & 0xf000) == 0x1000) {
 463             return 16;
 464         }
 465         return 0;
 466     case 24:
 467         if ((pte1 & 0xff000) == 0) {
 468             return 24;
 469         }
 470         return 0;
 471     }
 472     return 0;
 473 }
 474
 475 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
 476                                      uint32_t slb_pshift, bool secondary,
 477                                      target_ulong ptem, ppc_hash_pte64_t *pte)
 478 {
 479     CPUPPCState *env = &cpu->env;
 480     int i;
 481     uint64_t token;
 482     target_ulong pte0, pte1;
 483     target_ulong pte_index;
 484
 485     pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
 486     token = ppc_hash64_start_access(cpu, pte_index);
 487     if (!token) {
 488         return -1;
 489     }
 490     for (i = 0; i < HPTES_PER_GROUP; i++) {
 491         pte0 = ppc_hash64_load_hpte0(cpu, token, i);
 492         pte1 = ppc_hash64_load_hpte1(cpu, token, i);
 493
 494         if ((pte0 & HPTE64_V_VALID)
 495             && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
 496             && HPTE64_V_COMPARE(pte0, ptem)) {
 497             uint32_t pshift = ppc_hash64_pte_size_decode(pte1, slb_pshift);
 498             if (pshift == 0) {
 499                 continue;
 500             }
 501             /* We don't do anything with pshift yet as qemu TLB only deals
 502              * with 4K pages anyway
 503              */
 504             pte->pte0 = pte0;
 505             pte->pte1 = pte1;
 506             ppc_hash64_stop_access(cpu, token);
 507             return (pte_index + i) * HASH_PTE_SIZE_64;
 508         }
 509     }
 510     ppc_hash64_stop_access(cpu, token);
 511     /*
 512      * We didn't find a valid entry.
 513      */
 514     return -1;
 515 }
 516
 517 static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
 518                                      ppc_slb_t *slb, target_ulong eaddr,
 519                                      ppc_hash_pte64_t *pte)
 520 {
 521     CPUPPCState *env = &cpu->env;
 522     hwaddr pte_offset;
 523     hwaddr hash;
 524     uint64_t vsid, epnmask, epn, ptem;
 525
 526     /* The SLB store path should prevent any bad page size encodings
 527      * getting in there, so: */
 528     assert(slb->sps);
 529
 530     epnmask = ~((1ULL << slb->sps->page_shift) - 1);
 531
 532     if (slb->vsid & SLB_VSID_B) {
 533         /* 1TB segment */
 534         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 535         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 536         hash = vsid ^ (vsid << 25) ^ (epn >> slb->sps->page_shift);
 537     } else {
 538         /* 256M segment */
 539         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 540         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 541         hash = vsid ^ (epn >> slb->sps->page_shift);
 542     }
 543     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 544
 545     /* Page address translation */
 546     qemu_log_mask(CPU_LOG_MMU,
 547             "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 548             " hash " TARGET_FMT_plx "\n",
 549             env->htab_base, env->htab_mask, hash);
 550
 551     /* Primary PTEG lookup */
 552     qemu_log_mask(CPU_LOG_MMU,
 553             "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 554             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 555             " hash=" TARGET_FMT_plx "\n",
 556             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 557     pte_offset = ppc_hash64_pteg_search(cpu, hash, slb->sps->page_shift,
 558                                         0, ptem, pte);
 559
 560     if (pte_offset == -1) {
 561         /* Secondary PTEG lookup */
 562         qemu_log_mask(CPU_LOG_MMU,
 563                 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 564                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 565                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 566                 env->htab_mask, vsid, ptem, ~hash);
 567
 568         pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb->sps->page_shift, 1,
 569                                             ptem, pte);
 570     }
 571
 572     return pte_offset;
 573 }
 574
 575 static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
 576     uint64_t pte0, uint64_t pte1)
 577 {
 578     int i;
 579
 580     if (!(pte0 & HPTE64_V_LARGE)) {
 581         if (sps->page_shift != 12) {
 582             /* 4kiB page in a non 4kiB segment */
 583             return 0;
 584         }
 585         /* Normal 4kiB page */
 586         return 12;
 587     }
 588
 589     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 590         const struct ppc_one_page_size *ps = &sps->enc[i];
 591         uint64_t mask;
 592
 593         if (!ps->page_shift) {
 594             break;
 595         }
 596
 597         if (ps->page_shift == 12) {
 598             /* L bit is set so this can't be a 4kiB page */
 599             continue;
 600         }
 601
 602         mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
 603
 604         if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
 605             return ps->page_shift;
 606         }
 607     }
 608
 609     return 0; /* Bad page size encoding */
 610 }
 611
 612 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
 613                                           uint64_t pte0, uint64_t pte1,
 614                                           unsigned *seg_page_shift)
 615 {
 616     CPUPPCState *env = &cpu->env;
 617     int i;
 618
 619     if (!(pte0 & HPTE64_V_LARGE)) {
 620         *seg_page_shift = 12;
 621         return 12;
 622     }
 623
 624     /*
 625      * The encodings in env->sps need to be carefully chosen so that
 626      * this gives an unambiguous result.
 627      */
 628     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 629         const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
 630         unsigned shift;
 631
 632         if (!sps->page_shift) {
 633             break;
 634         }
 635
 636         shift = hpte_page_shift(sps, pte0, pte1);
 637         if (shift) {
 638             *seg_page_shift = sps->page_shift;
 639             return shift;
 640         }
 641     }
 642
 643     *seg_page_shift = 0;
 644     return 0;
 645 }
 646
 647 static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
 648                                uint64_t error_code)
 649 {
 650     bool vpm;
 651
 652     if (msr_ir) {
 653         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
 654     } else {
 655         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
 656     }
 657     if (vpm && !msr_hv) {
 658         cs->exception_index = POWERPC_EXCP_HISI;
 659     } else {
 660         cs->exception_index = POWERPC_EXCP_ISI;
 661     }
 662     env->error_code = error_code;
 663 }
 664
 665 static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
 666                                uint64_t dsisr)
 667 {
 668     bool vpm;
 669
 670     if (msr_dr) {
 671         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
 672     } else {
 673         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
 674     }
 675     if (vpm && !msr_hv) {
 676         cs->exception_index = POWERPC_EXCP_HDSI;
 677         env->spr[SPR_HDAR] = dar;
 678         env->spr[SPR_HDSISR] = dsisr;
 679     } else {
 680         cs->exception_index = POWERPC_EXCP_DSI;
 681         env->spr[SPR_DAR] = dar;
 682         env->spr[SPR_DSISR] = dsisr;
 683    }
 684     env->error_code = 0;
 685 }
 686
 687
 688 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
 689                                 int rwx, int mmu_idx)
 690 {
 691     CPUState *cs = CPU(cpu);
 692     CPUPPCState *env = &cpu->env;
 693     ppc_slb_t *slb;
 694     unsigned apshift;
 695     hwaddr pte_offset;
 696     ppc_hash_pte64_t pte;
 697     int pp_prot, amr_prot, prot;
 698     uint64_t new_pte1, dsisr;
 699     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 700     hwaddr raddr;
 701
 702     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 703
 704     /* 1. Handle real mode accesses */
 705     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 706         /* Translation is off */
 707         /* In real mode the top 4 effective address bits are ignored */
 708         raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 709         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 710                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 711                      TARGET_PAGE_SIZE);
 712         return 0;
 713     }
 714
 715     /* 2. Translation is on, so look up the SLB */
 716     slb = slb_lookup(cpu, eaddr);
 717
 718     if (!slb) {
 719         if (rwx == 2) {
 720             cs->exception_index = POWERPC_EXCP_ISEG;
 721             env->error_code = 0;
 722         } else {
 723             cs->exception_index = POWERPC_EXCP_DSEG;
 724             env->error_code = 0;
 725             env->spr[SPR_DAR] = eaddr;
 726         }
 727         return 1;
 728     }
 729
 730     /* 3. Check for segment level no-execute violation */
 731     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 732         ppc_hash64_set_isi(cs, env, 0x10000000);
 733         return 1;
 734     }
 735
 736     /* 4. Locate the PTE in the hash table */
 737     pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
 738     if (pte_offset == -1) {
 739         dsisr = 0x40000000;
 740         if (rwx == 2) {
 741             ppc_hash64_set_isi(cs, env, dsisr);
 742         } else {
 743             if (rwx == 1) {
 744                 dsisr |= 0x02000000;
 745             }
 746             ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 747         }
 748         return 1;
 749     }
 750     qemu_log_mask(CPU_LOG_MMU,
 751                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 752
 753     /* Validate page size encoding */
 754     apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
 755     if (!apshift) {
 756         error_report("Bad page size encoding in HPTE 0x%"PRIx64" - 0x%"PRIx64
 757                      " @ 0x%"HWADDR_PRIx, pte.pte0, pte.pte1, pte_offset);
 758         /* Not entirely sure what the right action here, but machine
 759          * check seems reasonable */
 760         cs->exception_index = POWERPC_EXCP_MCHECK;
 761         env->error_code = 0;
 762         return 1;
 763     }
 764
 765     /* 5. Check access permissions */
 766
 767     pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
 768     amr_prot = ppc_hash64_amr_prot(cpu, pte);
 769     prot = pp_prot & amr_prot;
 770
 771     if ((need_prot[rwx] & ~prot) != 0) {
 772         /* Access right violation */
 773         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 774         if (rwx == 2) {
 775             ppc_hash64_set_isi(cs, env, 0x08000000);
 776         } else {
 777             dsisr = 0;
 778             if (need_prot[rwx] & ~pp_prot) {
 779                 dsisr |= 0x08000000;
 780             }
 781             if (rwx == 1) {
 782                 dsisr |= 0x02000000;
 783             }
 784             if (need_prot[rwx] & ~amr_prot) {
 785                 dsisr |= 0x00200000;
 786             }
 787             ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 788         }
 789         return 1;
 790     }
 791
 792     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 793
 794     /* 6. Update PTE referenced and changed bits if necessary */
 795
 796     new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
 797     if (rwx == 1) {
 798         new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
 799     } else {
 800         /* Treat the page as read-only for now, so that a later write
 801          * will pass through this function again to set the C bit */
 802         prot &= ~PAGE_WRITE;
 803     }
 804
 805     if (new_pte1 != pte.pte1) {
 806         ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
 807                               pte.pte0, new_pte1);
 808     }
 809
 810     /* 7. Determine the real address from the PTE */
 811
 812     raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
 813
 814     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 815                  prot, mmu_idx, 1ULL << apshift);
 816
 817     return 0;
 818 }
 819
 820 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
 821 {
 822     CPUPPCState *env = &cpu->env;
 823     ppc_slb_t *slb;
 824     hwaddr pte_offset;
 825     ppc_hash_pte64_t pte;
 826     unsigned apshift;
 827
 828     if (msr_dr == 0) {
 829         /* In real mode the top 4 effective address bits are ignored */
 830         return addr & 0x0FFFFFFFFFFFFFFFULL;
 831     }
 832
 833     slb = slb_lookup(cpu, addr);
 834     if (!slb) {
 835         return -1;
 836     }
 837
 838     pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte);
 839     if (pte_offset == -1) {
 840         return -1;
 841     }
 842
 843     apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
 844     if (!apshift) {
 845         return -1;
 846     }
 847
 848     return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
 849         & TARGET_PAGE_MASK;
 850 }
 851
 852 void ppc_hash64_store_hpte(PowerPCCPU *cpu,
 853                            target_ulong pte_index,
 854                            target_ulong pte0, target_ulong pte1)
 855 {
 856     CPUPPCState *env = &cpu->env;
 857
 858     if (env->external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 859         kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
 860         return;
 861     }
 862
 863     pte_index *= HASH_PTE_SIZE_64;
 864     if (env->external_htab) {
 865         stq_p(env->external_htab + pte_index, pte0);
 866         stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
 867     } else {
 868         stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
 869         stq_phys(CPU(cpu)->as,
 870                  env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
 871     }
 872 }
 873
 874 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
 875                                target_ulong pte_index,
 876                                target_ulong pte0, target_ulong pte1)
 877 {
 878     /*
 879      * XXX: given the fact that there are too many segments to
 880      * invalidate, and we still don't have a tlb_flush_mask(env, n,
 881      * mask) in QEMU, we just invalidate all TLBs
 882      */
 883     tlb_flush(CPU(cpu), 1);
 884 }
 885
 886 void helper_store_lpcr(CPUPPCState *env, target_ulong val)
 887 {
 888     uint64_t lpcr = 0;
 889
 890     /* Filter out bits */
 891     switch (env->mmu_model) {
 892     case POWERPC_MMU_64B: /* 970 */
 893         if (val & 0x40) {
 894             lpcr |= LPCR_LPES0;
 895         }
 896         if (val & 0x8000000000000000ull) {
 897             lpcr |= LPCR_LPES1;
 898         }
 899         if (val & 0x20) {
 900             lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
 901         }
 902         if (val & 0x4000000000000000ull) {
 903             lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
 904         }
 905         if (val & 0x2000000000000000ull) {
 906             lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
 907         }
 908         env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
 909
 910         /* XXX We could also write LPID from HID4 here
 911          * but since we don't tag any translation on it
 912          * it doesn't actually matter
 913          */
 914         /* XXX For proper emulation of 970 we also need
 915          * to dig HRMOR out of HID5
 916          */
 917         break;
 918     case POWERPC_MMU_2_03: /* P5p */
 919         lpcr = val & (LPCR_RMLS | LPCR_ILE |
 920                       LPCR_LPES0 | LPCR_LPES1 |
 921                       LPCR_RMI | LPCR_HDICE);
 922         break;
 923     case POWERPC_MMU_2_06: /* P7 */
 924         lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
 925                       LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
 926                       LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
 927                       LPCR_MER | LPCR_TC |
 928                       LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
 929         break;
 930     case POWERPC_MMU_2_07: /* P8 */
 931         lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
 932                       LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
 933                       LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
 934                       LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
 935                       LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
 936         break;
 937     default:
 938         ;
 939     }
 940     env->spr[SPR_LPCR] = lpcr;
 941 }