target-lm32/translate.c

   1 /*
   2  *  LatticeMico32 main translation routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <assert.h>
  26
  27 #include "cpu.h"
  28 #include "exec-all.h"
  29 #include "disas.h"
  30 #include "helper.h"
  31 #include "tcg-op.h"
  32 #include "qemu-common.h"
  33
  34 #include "hw/lm32_pic.h"
  35
  36 #define GEN_HELPER 1
  37 #include "helper.h"
  38
  39 #define DISAS_LM32 1
  40 #if DISAS_LM32
  41 #  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
  42 #else
  43 #  define LOG_DIS(...) do { } while (0)
  44 #endif
  45
  46 #define EXTRACT_FIELD(src, start, end) \
  47             (((src) >> start) & ((1 << (end - start + 1)) - 1))
  48
  49 #define MEM_INDEX 0
  50
  51 static TCGv_ptr cpu_env;
  52 static TCGv cpu_R[32];
  53 static TCGv cpu_pc;
  54 static TCGv cpu_ie;
  55 static TCGv cpu_icc;
  56 static TCGv cpu_dcc;
  57 static TCGv cpu_cc;
  58 static TCGv cpu_cfg;
  59 static TCGv cpu_eba;
  60 static TCGv cpu_dc;
  61 static TCGv cpu_deba;
  62 static TCGv cpu_bp[4];
  63 static TCGv cpu_wp[4];
  64
  65 #include "gen-icount.h"
  66
  67 enum {
  68     OP_FMT_RI,
  69     OP_FMT_RR,
  70     OP_FMT_CR,
  71     OP_FMT_I
  72 };
  73
  74 /* This is the state at translation time.  */
  75 typedef struct DisasContext {
  76     CPUState *env;
  77     target_ulong pc;
  78
  79     /* Decoder.  */
  80     int format;
  81     uint32_t ir;
  82     uint8_t opcode;
  83     uint8_t r0, r1, r2, csr;
  84     uint16_t imm5;
  85     uint16_t imm16;
  86     uint32_t imm26;
  87
  88     unsigned int delayed_branch;
  89     unsigned int tb_flags, synced_flags; /* tb dependent flags.  */
  90     int is_jmp;
  91
  92     int nr_nops;
  93     struct TranslationBlock *tb;
  94     int singlestep_enabled;
  95 } DisasContext;
  96
  97 static const char *regnames[] = {
  98     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  99     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 100     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 101     "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
 102     "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
 103     "wp1", "wp2", "wp3"
 104 };
 105
 106 static inline int zero_extend(unsigned int val, int width)
 107 {
 108     return val & ((1 << width) - 1);
 109 }
 110
 111 static inline int sign_extend(unsigned int val, int width)
 112 {
 113     int sval;
 114
 115     /* LSL.  */
 116     val <<= 32 - width;
 117     sval = val;
 118     /* ASR.  */
 119     sval >>= 32 - width;
 120
 121     return sval;
 122 }
 123
 124 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
 125 {
 126     TCGv_i32 tmp = tcg_const_i32(index);
 127
 128     gen_helper_raise_exception(tmp);
 129     tcg_temp_free_i32(tmp);
 130 }
 131
 132 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
 133 {
 134     TranslationBlock *tb;
 135
 136     tb = dc->tb;
 137     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 138             likely(!dc->singlestep_enabled)) {
 139         tcg_gen_goto_tb(n);
 140         tcg_gen_movi_tl(cpu_pc, dest);
 141         tcg_gen_exit_tb((tcg_target_long)tb + n);
 142     } else {
 143         tcg_gen_movi_tl(cpu_pc, dest);
 144         if (dc->singlestep_enabled) {
 145             t_gen_raise_exception(dc, EXCP_DEBUG);
 146         }
 147         tcg_gen_exit_tb(0);
 148     }
 149 }
 150
 151 static void dec_add(DisasContext *dc)
 152 {
 153     if (dc->format == OP_FMT_RI) {
 154         if (dc->r0 == R_R0) {
 155             if (dc->r1 == R_R0 && dc->imm16 == 0) {
 156                 LOG_DIS("nop\n");
 157             } else {
 158                 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
 159             }
 160         } else {
 161             LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
 162                     sign_extend(dc->imm16, 16));
 163         }
 164     } else {
 165         LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 166     }
 167
 168     if (dc->format == OP_FMT_RI) {
 169         tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 170                 sign_extend(dc->imm16, 16));
 171     } else {
 172         tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 173     }
 174 }
 175
 176 static void dec_and(DisasContext *dc)
 177 {
 178     if (dc->format == OP_FMT_RI) {
 179         LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
 180                 zero_extend(dc->imm16, 16));
 181     } else {
 182         LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 183     }
 184
 185     if (dc->format == OP_FMT_RI) {
 186         tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 187                 zero_extend(dc->imm16, 16));
 188     } else  {
 189         if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
 190             tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 191             gen_helper_hlt();
 192         } else {
 193             tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 194         }
 195     }
 196 }
 197
 198 static void dec_andhi(DisasContext *dc)
 199 {
 200     LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
 201
 202     tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 203 }
 204
 205 static void dec_b(DisasContext *dc)
 206 {
 207     if (dc->r0 == R_RA) {
 208         LOG_DIS("ret\n");
 209     } else if (dc->r0 == R_EA) {
 210         LOG_DIS("eret\n");
 211     } else if (dc->r0 == R_BA) {
 212         LOG_DIS("bret\n");
 213     } else {
 214         LOG_DIS("b r%d\n", dc->r0);
 215     }
 216
 217     /* restore IE.IE in case of an eret */
 218     if (dc->r0 == R_EA) {
 219         TCGv t0 = tcg_temp_new();
 220         int l1 = gen_new_label();
 221         tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
 222         tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
 223         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
 224         tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
 225         gen_set_label(l1);
 226         tcg_temp_free(t0);
 227     } else if (dc->r0 == R_BA) {
 228         TCGv t0 = tcg_temp_new();
 229         int l1 = gen_new_label();
 230         tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
 231         tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
 232         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
 233         tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
 234         gen_set_label(l1);
 235         tcg_temp_free(t0);
 236     }
 237     tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
 238
 239     dc->is_jmp = DISAS_JUMP;
 240 }
 241
 242 static void dec_bi(DisasContext *dc)
 243 {
 244     LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
 245
 246     gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
 247
 248     dc->is_jmp = DISAS_TB_JUMP;
 249 }
 250
 251 static inline void gen_cond_branch(DisasContext *dc, int cond)
 252 {
 253     int l1;
 254
 255     l1 = gen_new_label();
 256     tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
 257     gen_goto_tb(dc, 0, dc->pc + 4);
 258     gen_set_label(l1);
 259     gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
 260     dc->is_jmp = DISAS_TB_JUMP;
 261 }
 262
 263 static void dec_be(DisasContext *dc)
 264 {
 265     LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
 266             sign_extend(dc->imm16, 16) * 4);
 267
 268     gen_cond_branch(dc, TCG_COND_EQ);
 269 }
 270
 271 static void dec_bg(DisasContext *dc)
 272 {
 273     LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
 274             sign_extend(dc->imm16, 16 * 4));
 275
 276     gen_cond_branch(dc, TCG_COND_GT);
 277 }
 278
 279 static void dec_bge(DisasContext *dc)
 280 {
 281     LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
 282             sign_extend(dc->imm16, 16) * 4);
 283
 284     gen_cond_branch(dc, TCG_COND_GE);
 285 }
 286
 287 static void dec_bgeu(DisasContext *dc)
 288 {
 289     LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
 290             sign_extend(dc->imm16, 16) * 4);
 291
 292     gen_cond_branch(dc, TCG_COND_GEU);
 293 }
 294
 295 static void dec_bgu(DisasContext *dc)
 296 {
 297     LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
 298             sign_extend(dc->imm16, 16) * 4);
 299
 300     gen_cond_branch(dc, TCG_COND_GTU);
 301 }
 302
 303 static void dec_bne(DisasContext *dc)
 304 {
 305     LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
 306             sign_extend(dc->imm16, 16) * 4);
 307
 308     gen_cond_branch(dc, TCG_COND_NE);
 309 }
 310
 311 static void dec_call(DisasContext *dc)
 312 {
 313     LOG_DIS("call r%d\n", dc->r0);
 314
 315     tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
 316     tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
 317
 318     dc->is_jmp = DISAS_JUMP;
 319 }
 320
 321 static void dec_calli(DisasContext *dc)
 322 {
 323     LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
 324
 325     tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
 326     gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
 327
 328     dc->is_jmp = DISAS_TB_JUMP;
 329 }
 330
 331 static inline void gen_compare(DisasContext *dc, int cond)
 332 {
 333     int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
 334     int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
 335     int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
 336
 337     if (dc->format == OP_FMT_RI) {
 338         tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY],
 339                 sign_extend(dc->imm16, 16));
 340     } else {
 341         tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
 342     }
 343 }
 344
 345 static void dec_cmpe(DisasContext *dc)
 346 {
 347     if (dc->format == OP_FMT_RI) {
 348         LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
 349                 sign_extend(dc->imm16, 16));
 350     } else {
 351         LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 352     }
 353
 354     gen_compare(dc, TCG_COND_EQ);
 355 }
 356
 357 static void dec_cmpg(DisasContext *dc)
 358 {
 359     if (dc->format == OP_FMT_RI) {
 360         LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
 361                 sign_extend(dc->imm16, 16));
 362     } else {
 363         LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 364     }
 365
 366     gen_compare(dc, TCG_COND_GT);
 367 }
 368
 369 static void dec_cmpge(DisasContext *dc)
 370 {
 371     if (dc->format == OP_FMT_RI) {
 372         LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
 373                 sign_extend(dc->imm16, 16));
 374     } else {
 375         LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 376     }
 377
 378     gen_compare(dc, TCG_COND_GE);
 379 }
 380
 381 static void dec_cmpgeu(DisasContext *dc)
 382 {
 383     if (dc->format == OP_FMT_RI) {
 384         LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
 385                 sign_extend(dc->imm16, 16));
 386     } else {
 387         LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 388     }
 389
 390     gen_compare(dc, TCG_COND_GEU);
 391 }
 392
 393 static void dec_cmpgu(DisasContext *dc)
 394 {
 395     if (dc->format == OP_FMT_RI) {
 396         LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
 397                 sign_extend(dc->imm16, 16));
 398     } else {
 399         LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 400     }
 401
 402     gen_compare(dc, TCG_COND_GTU);
 403 }
 404
 405 static void dec_cmpne(DisasContext *dc)
 406 {
 407     if (dc->format == OP_FMT_RI) {
 408         LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
 409                 sign_extend(dc->imm16, 16));
 410     } else {
 411         LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 412     }
 413
 414     gen_compare(dc, TCG_COND_NE);
 415 }
 416
 417 static void dec_divu(DisasContext *dc)
 418 {
 419     int l1;
 420
 421     LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 422
 423     if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
 424         cpu_abort(dc->env, "hardware divider is not available\n");
 425     }
 426
 427     l1 = gen_new_label();
 428     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
 429     tcg_gen_movi_tl(cpu_pc, dc->pc);
 430     t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
 431     gen_set_label(l1);
 432     tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 433 }
 434
 435 static void dec_lb(DisasContext *dc)
 436 {
 437     TCGv t0;
 438
 439     LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 440
 441     t0 = tcg_temp_new();
 442     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 443     tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
 444     tcg_temp_free(t0);
 445 }
 446
 447 static void dec_lbu(DisasContext *dc)
 448 {
 449     TCGv t0;
 450
 451     LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 452
 453     t0 = tcg_temp_new();
 454     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 455     tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
 456     tcg_temp_free(t0);
 457 }
 458
 459 static void dec_lh(DisasContext *dc)
 460 {
 461     TCGv t0;
 462
 463     LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 464
 465     t0 = tcg_temp_new();
 466     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 467     tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
 468     tcg_temp_free(t0);
 469 }
 470
 471 static void dec_lhu(DisasContext *dc)
 472 {
 473     TCGv t0;
 474
 475     LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 476
 477     t0 = tcg_temp_new();
 478     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 479     tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
 480     tcg_temp_free(t0);
 481 }
 482
 483 static void dec_lw(DisasContext *dc)
 484 {
 485     TCGv t0;
 486
 487     LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
 488
 489     t0 = tcg_temp_new();
 490     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 491     tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
 492     tcg_temp_free(t0);
 493 }
 494
 495 static void dec_modu(DisasContext *dc)
 496 {
 497     int l1;
 498
 499     LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
 500
 501     if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
 502         cpu_abort(dc->env, "hardware divider is not available\n");
 503     }
 504
 505     l1 = gen_new_label();
 506     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
 507     tcg_gen_movi_tl(cpu_pc, dc->pc);
 508     t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
 509     gen_set_label(l1);
 510     tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 511 }
 512
 513 static void dec_mul(DisasContext *dc)
 514 {
 515     if (dc->format == OP_FMT_RI) {
 516         LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
 517                 sign_extend(dc->imm16, 16));
 518     } else {
 519         LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 520     }
 521
 522     if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
 523         cpu_abort(dc->env, "hardware multiplier is not available\n");
 524     }
 525
 526     if (dc->format == OP_FMT_RI) {
 527         tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 528                 sign_extend(dc->imm16, 16));
 529     } else {
 530         tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 531     }
 532 }
 533
 534 static void dec_nor(DisasContext *dc)
 535 {
 536     if (dc->format == OP_FMT_RI) {
 537         LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
 538                 zero_extend(dc->imm16, 16));
 539     } else {
 540         LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 541     }
 542
 543     if (dc->format == OP_FMT_RI) {
 544         TCGv t0 = tcg_temp_new();
 545         tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
 546         tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
 547         tcg_temp_free(t0);
 548     } else {
 549         tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 550     }
 551 }
 552
 553 static void dec_or(DisasContext *dc)
 554 {
 555     if (dc->format == OP_FMT_RI) {
 556         LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
 557                 zero_extend(dc->imm16, 16));
 558     } else {
 559         if (dc->r1 == R_R0) {
 560             LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
 561         } else {
 562             LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 563         }
 564     }
 565
 566     if (dc->format == OP_FMT_RI) {
 567         tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 568                 zero_extend(dc->imm16, 16));
 569     } else {
 570         tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 571     }
 572 }
 573
 574 static void dec_orhi(DisasContext *dc)
 575 {
 576     if (dc->r0 == R_R0) {
 577         LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
 578     } else {
 579         LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
 580     }
 581
 582     tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 583 }
 584
 585 static void dec_scall(DisasContext *dc)
 586 {
 587     TCGv t0;
 588     int l1;
 589
 590     if (dc->imm5 == 7) {
 591         LOG_DIS("scall\n");
 592     } else if (dc->imm5 == 2) {
 593         LOG_DIS("break\n");
 594     } else {
 595         cpu_abort(dc->env, "invalid opcode\n");
 596     }
 597
 598     t0 = tcg_temp_new();
 599     l1 = gen_new_label();
 600
 601     if (dc->imm5 == 7) {
 602         tcg_gen_movi_tl(cpu_pc, dc->pc);
 603         t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
 604     } else {
 605         tcg_gen_movi_tl(cpu_pc, dc->pc);
 606         t_gen_raise_exception(dc, EXCP_BREAKPOINT);
 607     }
 608 }
 609
 610 static void dec_rcsr(DisasContext *dc)
 611 {
 612     LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
 613
 614     switch (dc->csr) {
 615     case CSR_IE:
 616         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
 617         break;
 618     case CSR_IM:
 619         gen_helper_rcsr_im(cpu_R[dc->r2]);
 620         break;
 621     case CSR_IP:
 622         gen_helper_rcsr_ip(cpu_R[dc->r2]);
 623         break;
 624     case CSR_CC:
 625         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
 626         break;
 627     case CSR_CFG:
 628         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
 629         break;
 630     case CSR_EBA:
 631         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
 632         break;
 633     case CSR_DC:
 634         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
 635         break;
 636     case CSR_DEBA:
 637         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
 638         break;
 639     case CSR_JTX:
 640         gen_helper_rcsr_jtx(cpu_R[dc->r2]);
 641         break;
 642     case CSR_JRX:
 643         gen_helper_rcsr_jrx(cpu_R[dc->r2]);
 644         break;
 645     case CSR_ICC:
 646     case CSR_DCC:
 647     case CSR_BP0:
 648     case CSR_BP1:
 649     case CSR_BP2:
 650     case CSR_BP3:
 651     case CSR_WP0:
 652     case CSR_WP1:
 653     case CSR_WP2:
 654     case CSR_WP3:
 655         cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
 656         break;
 657     default:
 658         cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
 659         break;
 660     }
 661 }
 662
 663 static void dec_sb(DisasContext *dc)
 664 {
 665     TCGv t0;
 666
 667     LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
 668
 669     t0 = tcg_temp_new();
 670     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 671     tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
 672     tcg_temp_free(t0);
 673 }
 674
 675 static void dec_sextb(DisasContext *dc)
 676 {
 677     LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
 678
 679     if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
 680         cpu_abort(dc->env, "hardware sign extender is not available\n");
 681     }
 682
 683     tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
 684 }
 685
 686 static void dec_sexth(DisasContext *dc)
 687 {
 688     LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
 689
 690     if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
 691         cpu_abort(dc->env, "hardware sign extender is not available\n");
 692     }
 693
 694     tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
 695 }
 696
 697 static void dec_sh(DisasContext *dc)
 698 {
 699     TCGv t0;
 700
 701     LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
 702
 703     t0 = tcg_temp_new();
 704     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 705     tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
 706     tcg_temp_free(t0);
 707 }
 708
 709 static void dec_sl(DisasContext *dc)
 710 {
 711     if (dc->format == OP_FMT_RI) {
 712         LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 713     } else {
 714         LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 715     }
 716
 717     if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
 718         cpu_abort(dc->env, "hardware shifter is not available\n");
 719     }
 720
 721     if (dc->format == OP_FMT_RI) {
 722         tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 723     } else {
 724         TCGv t0 = tcg_temp_new();
 725         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 726         tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 727         tcg_temp_free(t0);
 728     }
 729 }
 730
 731 static void dec_sr(DisasContext *dc)
 732 {
 733     if (dc->format == OP_FMT_RI) {
 734         LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 735     } else {
 736         LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 737     }
 738
 739     if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
 740         if (dc->format == OP_FMT_RI) {
 741             /* TODO: check r1 == 1 during runtime */
 742         } else {
 743             if (dc->imm5 != 1) {
 744                 cpu_abort(dc->env, "hardware shifter is not available\n");
 745             }
 746         }
 747     }
 748
 749     if (dc->format == OP_FMT_RI) {
 750         tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 751     } else {
 752         TCGv t0 = tcg_temp_new();
 753         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 754         tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 755         tcg_temp_free(t0);
 756     }
 757 }
 758
 759 static void dec_sru(DisasContext *dc)
 760 {
 761     if (dc->format == OP_FMT_RI) {
 762         LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 763     } else {
 764         LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 765     }
 766
 767     if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
 768         if (dc->format == OP_FMT_RI) {
 769             /* TODO: check r1 == 1 during runtime */
 770         } else {
 771             if (dc->imm5 != 1) {
 772                 cpu_abort(dc->env, "hardware shifter is not available\n");
 773             }
 774         }
 775     }
 776
 777     if (dc->format == OP_FMT_RI) {
 778         tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 779     } else {
 780         TCGv t0 = tcg_temp_new();
 781         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 782         tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 783         tcg_temp_free(t0);
 784     }
 785 }
 786
 787 static void dec_sub(DisasContext *dc)
 788 {
 789     LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 790
 791     tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 792 }
 793
 794 static void dec_sw(DisasContext *dc)
 795 {
 796     TCGv t0;
 797
 798     LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
 799
 800     t0 = tcg_temp_new();
 801     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 802     tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
 803     tcg_temp_free(t0);
 804 }
 805
 806 static void dec_user(DisasContext *dc)
 807 {
 808     LOG_DIS("user");
 809
 810     cpu_abort(dc->env, "user insn undefined\n");
 811 }
 812
 813 static void dec_wcsr(DisasContext *dc)
 814 {
 815     int no;
 816
 817     LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
 818
 819     switch (dc->csr) {
 820     case CSR_IE:
 821         tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
 822         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 823         dc->is_jmp = DISAS_UPDATE;
 824         break;
 825     case CSR_IM:
 826         /* mark as an io operation because it could cause an interrupt */
 827         if (use_icount) {
 828             gen_io_start();
 829         }
 830         gen_helper_wcsr_im(cpu_R[dc->r1]);
 831         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 832         if (use_icount) {
 833             gen_io_end();
 834         }
 835         dc->is_jmp = DISAS_UPDATE;
 836         break;
 837     case CSR_IP:
 838         /* mark as an io operation because it could cause an interrupt */
 839         if (use_icount) {
 840             gen_io_start();
 841         }
 842         gen_helper_wcsr_ip(cpu_R[dc->r1]);
 843         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 844         if (use_icount) {
 845             gen_io_end();
 846         }
 847         dc->is_jmp = DISAS_UPDATE;
 848         break;
 849     case CSR_ICC:
 850         /* TODO */
 851         break;
 852     case CSR_DCC:
 853         /* TODO */
 854         break;
 855     case CSR_EBA:
 856         tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
 857         break;
 858     case CSR_DEBA:
 859         tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
 860         break;
 861     case CSR_JTX:
 862         gen_helper_wcsr_jtx(cpu_R[dc->r1]);
 863         break;
 864     case CSR_JRX:
 865         gen_helper_wcsr_jrx(cpu_R[dc->r1]);
 866         break;
 867     case CSR_DC:
 868         tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
 869         break;
 870     case CSR_BP0:
 871     case CSR_BP1:
 872     case CSR_BP2:
 873     case CSR_BP3:
 874         no = dc->csr - CSR_BP0;
 875         if (dc->env->num_bps <= no) {
 876             cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
 877         }
 878         tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
 879         break;
 880     case CSR_WP0:
 881     case CSR_WP1:
 882     case CSR_WP2:
 883     case CSR_WP3:
 884         no = dc->csr - CSR_WP0;
 885         if (dc->env->num_wps <= no) {
 886             cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
 887         }
 888         tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
 889         break;
 890     case CSR_CC:
 891     case CSR_CFG:
 892         cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
 893         break;
 894     default:
 895         cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
 896         break;
 897     }
 898 }
 899
 900 static void dec_xnor(DisasContext *dc)
 901 {
 902     if (dc->format == OP_FMT_RI) {
 903         LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
 904                 zero_extend(dc->imm16, 16));
 905     } else {
 906         if (dc->r1 == R_R0) {
 907             LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
 908         } else {
 909             LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 910         }
 911     }
 912
 913     if (dc->format == OP_FMT_RI) {
 914         tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 915                 zero_extend(dc->imm16, 16));
 916         tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
 917     } else {
 918         tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 919     }
 920 }
 921
 922 static void dec_xor(DisasContext *dc)
 923 {
 924     if (dc->format == OP_FMT_RI) {
 925         LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
 926                 zero_extend(dc->imm16, 16));
 927     } else {
 928         LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 929     }
 930
 931     if (dc->format == OP_FMT_RI) {
 932         tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 933                 zero_extend(dc->imm16, 16));
 934     } else {
 935         tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 936     }
 937 }
 938
 939 static void dec_ill(DisasContext *dc)
 940 {
 941     cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
 942 }
 943
 944 typedef void (*DecoderInfo)(DisasContext *dc);
 945 static const DecoderInfo decinfo[] = {
 946     dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
 947     dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
 948     dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
 949     dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
 950     dec_cmpne,
 951     dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
 952     dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
 953     dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
 954     dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
 955     dec_cmpne
 956 };
 957
 958 static inline void decode(DisasContext *dc)
 959 {
 960     uint32_t ir;
 961
 962     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
 963         tcg_gen_debug_insn_start(dc->pc);
 964     }
 965
 966     dc->ir = ir = ldl_code(dc->pc);
 967     LOG_DIS("%8.8x\t", dc->ir);
 968
 969     /* try guessing 'empty' instruction memory, although it may be a valid
 970      * instruction sequence (eg. srui r0, r0, 0) */
 971     if (dc->ir) {
 972         dc->nr_nops = 0;
 973     } else {
 974         LOG_DIS("nr_nops=%d\t", dc->nr_nops);
 975         dc->nr_nops++;
 976         if (dc->nr_nops > 4) {
 977             cpu_abort(dc->env, "fetching nop sequence\n");
 978         }
 979     }
 980
 981     dc->opcode = EXTRACT_FIELD(ir, 26, 31);
 982
 983     dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
 984     dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
 985     dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
 986
 987     dc->csr = EXTRACT_FIELD(ir, 21, 25);
 988     dc->r0 = EXTRACT_FIELD(ir, 21, 25);
 989     dc->r1 = EXTRACT_FIELD(ir, 16, 20);
 990     dc->r2 = EXTRACT_FIELD(ir, 11, 15);
 991
 992     /* bit 31 seems to indicate insn type.  */
 993     if (ir & (1 << 31)) {
 994         dc->format = OP_FMT_RR;
 995     } else {
 996         dc->format = OP_FMT_RI;
 997     }
 998
 999     assert(ARRAY_SIZE(decinfo) == 64);
1000     assert(dc->opcode < 64);
1001
1002     decinfo[dc->opcode](dc);
1003 }
1004
1005 static void check_breakpoint(CPUState *env, DisasContext *dc)
1006 {
1007     CPUBreakpoint *bp;
1008
1009     if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1010         QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1011             if (bp->pc == dc->pc) {
1012                 tcg_gen_movi_tl(cpu_pc, dc->pc);
1013                 t_gen_raise_exception(dc, EXCP_DEBUG);
1014                 dc->is_jmp = DISAS_UPDATE;
1015              }
1016         }
1017     }
1018 }
1019
1020 /* generate intermediate code for basic block 'tb'.  */
1021 static void gen_intermediate_code_internal(CPUState *env,
1022         TranslationBlock *tb, int search_pc)
1023 {
1024     struct DisasContext ctx, *dc = &ctx;
1025     uint16_t *gen_opc_end;
1026     uint32_t pc_start;
1027     int j, lj;
1028     uint32_t next_page_start;
1029     int num_insns;
1030     int max_insns;
1031
1032     qemu_log_try_set_file(stderr);
1033
1034     pc_start = tb->pc;
1035     dc->env = env;
1036     dc->tb = tb;
1037
1038     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1039
1040     dc->is_jmp = DISAS_NEXT;
1041     dc->pc = pc_start;
1042     dc->singlestep_enabled = env->singlestep_enabled;
1043     dc->nr_nops = 0;
1044
1045     if (pc_start & 3) {
1046         cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
1047     }
1048
1049     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1050         qemu_log("-----------------------------------------\n");
1051         log_cpu_state(env, 0);
1052     }
1053
1054     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1055     lj = -1;
1056     num_insns = 0;
1057     max_insns = tb->cflags & CF_COUNT_MASK;
1058     if (max_insns == 0) {
1059         max_insns = CF_COUNT_MASK;
1060     }
1061
1062     gen_icount_start();
1063     do {
1064         check_breakpoint(env, dc);
1065
1066         if (search_pc) {
1067             j = gen_opc_ptr - gen_opc_buf;
1068             if (lj < j) {
1069                 lj++;
1070                 while (lj < j) {
1071                     gen_opc_instr_start[lj++] = 0;
1072                 }
1073             }
1074             gen_opc_pc[lj] = dc->pc;
1075             gen_opc_instr_start[lj] = 1;
1076             gen_opc_icount[lj] = num_insns;
1077         }
1078
1079         /* Pretty disas.  */
1080         LOG_DIS("%8.8x:\t", dc->pc);
1081
1082         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1083             gen_io_start();
1084         }
1085
1086         decode(dc);
1087         dc->pc += 4;
1088         num_insns++;
1089
1090     } while (!dc->is_jmp
1091          && gen_opc_ptr < gen_opc_end
1092          && !env->singlestep_enabled
1093          && !singlestep
1094          && (dc->pc < next_page_start)
1095          && num_insns < max_insns);
1096
1097     if (tb->cflags & CF_LAST_IO) {
1098         gen_io_end();
1099     }
1100
1101     if (unlikely(env->singlestep_enabled)) {
1102         if (dc->is_jmp == DISAS_NEXT) {
1103             tcg_gen_movi_tl(cpu_pc, dc->pc);
1104         }
1105         t_gen_raise_exception(dc, EXCP_DEBUG);
1106     } else {
1107         switch (dc->is_jmp) {
1108         case DISAS_NEXT:
1109             gen_goto_tb(dc, 1, dc->pc);
1110             break;
1111         default:
1112         case DISAS_JUMP:
1113         case DISAS_UPDATE:
1114             /* indicate that the hash table must be used
1115                to find the next TB */
1116             tcg_gen_exit_tb(0);
1117             break;
1118         case DISAS_TB_JUMP:
1119             /* nothing more to generate */
1120             break;
1121         }
1122     }
1123
1124     gen_icount_end(tb, num_insns);
1125     *gen_opc_ptr = INDEX_op_end;
1126     if (search_pc) {
1127         j = gen_opc_ptr - gen_opc_buf;
1128         lj++;
1129         while (lj <= j) {
1130             gen_opc_instr_start[lj++] = 0;
1131         }
1132     } else {
1133         tb->size = dc->pc - pc_start;
1134         tb->icount = num_insns;
1135     }
1136
1137 #ifdef DEBUG_DISAS
1138     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1139         qemu_log("\n");
1140         log_target_disas(pc_start, dc->pc - pc_start, 0);
1141         qemu_log("\nisize=%d osize=%zd\n",
1142             dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1143     }
1144 #endif
1145 }
1146
1147 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb)
1148 {
1149     gen_intermediate_code_internal(env, tb, 0);
1150 }
1151
1152 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb)
1153 {
1154     gen_intermediate_code_internal(env, tb, 1);
1155 }
1156
1157 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1158                      int flags)
1159 {
1160     int i;
1161
1162     if (!env || !f) {
1163         return;
1164     }
1165
1166     cpu_fprintf(f, "IN: PC=%x %s\n",
1167                 env->pc, lookup_symbol(env->pc));
1168
1169     cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1170              env->ie,
1171              (env->ie & IE_IE) ? 1 : 0,
1172              (env->ie & IE_EIE) ? 1 : 0,
1173              (env->ie & IE_BIE) ? 1 : 0,
1174              lm32_pic_get_im(env->pic_state),
1175              lm32_pic_get_ip(env->pic_state));
1176     cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1177              env->eba,
1178              env->deba);
1179
1180     for (i = 0; i < 32; i++) {
1181         cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1182         if ((i + 1) % 4 == 0) {
1183             cpu_fprintf(f, "\n");
1184         }
1185     }
1186     cpu_fprintf(f, "\n\n");
1187 }
1188
1189 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
1190 {
1191     env->pc = gen_opc_pc[pc_pos];
1192 }
1193
1194 void lm32_translate_init(void)
1195 {
1196     int i;
1197
1198     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1199
1200     for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1201         cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1202                           offsetof(CPUState, regs[i]),
1203                           regnames[i]);
1204     }
1205
1206     for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1207         cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
1208                           offsetof(CPUState, bp[i]),
1209                           regnames[32+i]);
1210     }
1211
1212     for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1213         cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
1214                           offsetof(CPUState, wp[i]),
1215                           regnames[36+i]);
1216     }
1217
1218     cpu_pc = tcg_global_mem_new(TCG_AREG0,
1219                     offsetof(CPUState, pc),
1220                     "pc");
1221     cpu_ie = tcg_global_mem_new(TCG_AREG0,
1222                     offsetof(CPUState, ie),
1223                     "ie");
1224     cpu_icc = tcg_global_mem_new(TCG_AREG0,
1225                     offsetof(CPUState, icc),
1226                     "icc");
1227     cpu_dcc = tcg_global_mem_new(TCG_AREG0,
1228                     offsetof(CPUState, dcc),
1229                     "dcc");
1230     cpu_cc = tcg_global_mem_new(TCG_AREG0,
1231                     offsetof(CPUState, cc),
1232                     "cc");
1233     cpu_cfg = tcg_global_mem_new(TCG_AREG0,
1234                     offsetof(CPUState, cfg),
1235                     "cfg");
1236     cpu_eba = tcg_global_mem_new(TCG_AREG0,
1237                     offsetof(CPUState, eba),
1238                     "eba");
1239     cpu_dc = tcg_global_mem_new(TCG_AREG0,
1240                     offsetof(CPUState, dc),
1241                     "dc");
1242     cpu_deba = tcg_global_mem_new(TCG_AREG0,
1243                     offsetof(CPUState, deba),
1244                     "deba");
1245 }
1246