target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #ifndef CONFIG_USER_ONLY
  26 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  27 #endif
  28
  29 /*****************************************************************************/
  30 /* Exceptions processing helpers */
  31
  32 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  33                                                         uint32_t exception,
  34                                                         int error_code,
  35                                                         uintptr_t pc)
  36 {
  37     CPUState *cs = CPU(mips_env_get_cpu(env));
  38
  39     if (exception < EXCP_SC) {
  40         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  41     }
  42     cs->exception_index = exception;
  43     env->error_code = error_code;
  44
  45     if (pc) {
  46         /* now we have a real cpu fault */
  47         cpu_restore_state(cs, pc);
  48     }
  49
  50     cpu_loop_exit(cs);
  51 }
  52
  53 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  54                                                     uint32_t exception,
  55                                                     uintptr_t pc)
  56 {
  57     do_raise_exception_err(env, exception, 0, pc);
  58 }
  59
  60 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  61                                 int error_code)
  62 {
  63     do_raise_exception_err(env, exception, error_code, 0);
  64 }
  65
  66 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  67 {
  68     do_raise_exception(env, exception, 0);
  69 }
  70
  71 #if defined(CONFIG_USER_ONLY)
  72 #define HELPER_LD(name, insn, type)                                     \
  73 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  74                              int mem_idx)                               \
  75 {                                                                       \
  76     return (type) insn##_raw(addr);                                     \
  77 }
  78 #else
  79 #define HELPER_LD(name, insn, type)                                     \
  80 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  81                              int mem_idx)                               \
  82 {                                                                       \
  83     switch (mem_idx)                                                    \
  84     {                                                                   \
  85     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  86     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  87     default:                                                            \
  88     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  89     }                                                                   \
  90 }
  91 #endif
  92 HELPER_LD(lbu, ldub, uint8_t)
  93 HELPER_LD(lw, ldl, int32_t)
  94 #ifdef TARGET_MIPS64
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     insn##_raw(addr, val);                                              \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #ifdef TARGET_MIPS64
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 #ifndef CONFIG_USER_ONLY
 269
 270 static inline hwaddr do_translate_address(CPUMIPSState *env,
 271                                                       target_ulong address,
 272                                                       int rw)
 273 {
 274     hwaddr lladdr;
 275
 276     lladdr = cpu_mips_translate_address(env, address, rw);
 277
 278     if (lladdr == -1LL) {
 279         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 280     } else {
 281         return lladdr;
 282     }
 283 }
 284
 285 #define HELPER_LD_ATOMIC(name, insn)                                          \
 286 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 287 {                                                                             \
 288     env->lladdr = do_translate_address(env, arg, 0);                          \
 289     env->llval = do_##insn(env, arg, mem_idx);                                \
 290     return env->llval;                                                        \
 291 }
 292 HELPER_LD_ATOMIC(ll, lw)
 293 #ifdef TARGET_MIPS64
 294 HELPER_LD_ATOMIC(lld, ld)
 295 #endif
 296 #undef HELPER_LD_ATOMIC
 297
 298 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 299 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 300                            target_ulong arg2, int mem_idx)                    \
 301 {                                                                             \
 302     target_long tmp;                                                          \
 303                                                                               \
 304     if (arg2 & almask) {                                                      \
 305         env->CP0_BadVAddr = arg2;                                             \
 306         helper_raise_exception(env, EXCP_AdES);                               \
 307     }                                                                         \
 308     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 309         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 310         if (tmp == env->llval) {                                              \
 311             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 312             return 1;                                                         \
 313         }                                                                     \
 314     }                                                                         \
 315     return 0;                                                                 \
 316 }
 317 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 318 #ifdef TARGET_MIPS64
 319 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 320 #endif
 321 #undef HELPER_ST_ATOMIC
 322 #endif
 323
 324 #ifdef TARGET_WORDS_BIGENDIAN
 325 #define GET_LMASK(v) ((v) & 3)
 326 #define GET_OFFSET(addr, offset) (addr + (offset))
 327 #else
 328 #define GET_LMASK(v) (((v) & 3) ^ 3)
 329 #define GET_OFFSET(addr, offset) (addr - (offset))
 330 #endif
 331
 332 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 333                 int mem_idx)
 334 {
 335     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 336
 337     if (GET_LMASK(arg2) <= 2)
 338         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 339
 340     if (GET_LMASK(arg2) <= 1)
 341         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 342
 343     if (GET_LMASK(arg2) == 0)
 344         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 345 }
 346
 347 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 348                 int mem_idx)
 349 {
 350     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 351
 352     if (GET_LMASK(arg2) >= 1)
 353         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 354
 355     if (GET_LMASK(arg2) >= 2)
 356         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 357
 358     if (GET_LMASK(arg2) == 3)
 359         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 360 }
 361
 362 #if defined(TARGET_MIPS64)
 363 /* "half" load and stores.  We must do the memory access inline,
 364    or fault handling won't work.  */
 365
 366 #ifdef TARGET_WORDS_BIGENDIAN
 367 #define GET_LMASK64(v) ((v) & 7)
 368 #else
 369 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 370 #endif
 371
 372 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 373                 int mem_idx)
 374 {
 375     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 376
 377     if (GET_LMASK64(arg2) <= 6)
 378         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 379
 380     if (GET_LMASK64(arg2) <= 5)
 381         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 382
 383     if (GET_LMASK64(arg2) <= 4)
 384         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 385
 386     if (GET_LMASK64(arg2) <= 3)
 387         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 388
 389     if (GET_LMASK64(arg2) <= 2)
 390         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 391
 392     if (GET_LMASK64(arg2) <= 1)
 393         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 394
 395     if (GET_LMASK64(arg2) <= 0)
 396         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 397 }
 398
 399 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 400                 int mem_idx)
 401 {
 402     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 403
 404     if (GET_LMASK64(arg2) >= 1)
 405         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 406
 407     if (GET_LMASK64(arg2) >= 2)
 408         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 409
 410     if (GET_LMASK64(arg2) >= 3)
 411         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 412
 413     if (GET_LMASK64(arg2) >= 4)
 414         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 415
 416     if (GET_LMASK64(arg2) >= 5)
 417         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 418
 419     if (GET_LMASK64(arg2) >= 6)
 420         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 421
 422     if (GET_LMASK64(arg2) == 7)
 423         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 424 }
 425 #endif /* TARGET_MIPS64 */
 426
 427 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 428
 429 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 430                 uint32_t mem_idx)
 431 {
 432     target_ulong base_reglist = reglist & 0xf;
 433     target_ulong do_r31 = reglist & 0x10;
 434
 435     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 436         target_ulong i;
 437
 438         for (i = 0; i < base_reglist; i++) {
 439             env->active_tc.gpr[multiple_regs[i]] =
 440                 (target_long)do_lw(env, addr, mem_idx);
 441             addr += 4;
 442         }
 443     }
 444
 445     if (do_r31) {
 446         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 447     }
 448 }
 449
 450 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 451                 uint32_t mem_idx)
 452 {
 453     target_ulong base_reglist = reglist & 0xf;
 454     target_ulong do_r31 = reglist & 0x10;
 455
 456     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 457         target_ulong i;
 458
 459         for (i = 0; i < base_reglist; i++) {
 460             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 461             addr += 4;
 462         }
 463     }
 464
 465     if (do_r31) {
 466         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 467     }
 468 }
 469
 470 #if defined(TARGET_MIPS64)
 471 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 472                 uint32_t mem_idx)
 473 {
 474     target_ulong base_reglist = reglist & 0xf;
 475     target_ulong do_r31 = reglist & 0x10;
 476
 477     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 478         target_ulong i;
 479
 480         for (i = 0; i < base_reglist; i++) {
 481             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 482             addr += 8;
 483         }
 484     }
 485
 486     if (do_r31) {
 487         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 488     }
 489 }
 490
 491 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 492                 uint32_t mem_idx)
 493 {
 494     target_ulong base_reglist = reglist & 0xf;
 495     target_ulong do_r31 = reglist & 0x10;
 496
 497     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 498         target_ulong i;
 499
 500         for (i = 0; i < base_reglist; i++) {
 501             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 502             addr += 8;
 503         }
 504     }
 505
 506     if (do_r31) {
 507         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 508     }
 509 }
 510 #endif
 511
 512 #ifndef CONFIG_USER_ONLY
 513 /* SMP helpers.  */
 514 static bool mips_vpe_is_wfi(MIPSCPU *c)
 515 {
 516     CPUState *cpu = CPU(c);
 517     CPUMIPSState *env = &c->env;
 518
 519     /* If the VPE is halted but otherwise active, it means it's waiting for
 520        an interrupt.  */
 521     return cpu->halted && mips_vpe_active(env);
 522 }
 523
 524 static inline void mips_vpe_wake(MIPSCPU *c)
 525 {
 526     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 527        because there might be other conditions that state that c should
 528        be sleeping.  */
 529     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 530 }
 531
 532 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 533 {
 534     CPUState *cs = CPU(cpu);
 535
 536     /* The VPE was shut off, really go to bed.
 537        Reset any old _WAKE requests.  */
 538     cs->halted = 1;
 539     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 540 }
 541
 542 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 543 {
 544     CPUMIPSState *c = &cpu->env;
 545
 546     /* FIXME: TC reschedule.  */
 547     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 548         mips_vpe_wake(cpu);
 549     }
 550 }
 551
 552 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 553 {
 554     CPUMIPSState *c = &cpu->env;
 555
 556     /* FIXME: TC reschedule.  */
 557     if (!mips_vpe_active(c)) {
 558         mips_vpe_sleep(cpu);
 559     }
 560 }
 561
 562 /**
 563  * mips_cpu_map_tc:
 564  * @env: CPU from which mapping is performed.
 565  * @tc: Should point to an int with the value of the global TC index.
 566  *
 567  * This function will transform @tc into a local index within the
 568  * returned #CPUMIPSState.
 569  */
 570 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 571           which depends on runtime setup. Can probably be fixed by
 572           walking the list of CPUMIPSStates.  */
 573 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 574 {
 575     MIPSCPU *cpu;
 576     CPUState *cs;
 577     CPUState *other_cs;
 578     int vpe_idx;
 579     int tc_idx = *tc;
 580
 581     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 582         /* Not allowed to address other CPUs.  */
 583         *tc = env->current_tc;
 584         return env;
 585     }
 586
 587     cs = CPU(mips_env_get_cpu(env));
 588     vpe_idx = tc_idx / cs->nr_threads;
 589     *tc = tc_idx % cs->nr_threads;
 590     other_cs = qemu_get_cpu(vpe_idx);
 591     if (other_cs == NULL) {
 592         return env;
 593     }
 594     cpu = MIPS_CPU(other_cs);
 595     return &cpu->env;
 596 }
 597
 598 /* The per VPE CP0_Status register shares some fields with the per TC
 599    CP0_TCStatus registers. These fields are wired to the same registers,
 600    so changes to either of them should be reflected on both registers.
 601
 602    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 603
 604    These helper call synchronizes the regs for a given cpu.  */
 605
 606 /* Called for updates to CP0_Status.  */
 607 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 608 {
 609     int32_t tcstatus, *tcst;
 610     uint32_t v = cpu->CP0_Status;
 611     uint32_t cu, mx, asid, ksu;
 612     uint32_t mask = ((1 << CP0TCSt_TCU3)
 613                        | (1 << CP0TCSt_TCU2)
 614                        | (1 << CP0TCSt_TCU1)
 615                        | (1 << CP0TCSt_TCU0)
 616                        | (1 << CP0TCSt_TMX)
 617                        | (3 << CP0TCSt_TKSU)
 618                        | (0xff << CP0TCSt_TASID));
 619
 620     cu = (v >> CP0St_CU0) & 0xf;
 621     mx = (v >> CP0St_MX) & 0x1;
 622     ksu = (v >> CP0St_KSU) & 0x3;
 623     asid = env->CP0_EntryHi & 0xff;
 624
 625     tcstatus = cu << CP0TCSt_TCU0;
 626     tcstatus |= mx << CP0TCSt_TMX;
 627     tcstatus |= ksu << CP0TCSt_TKSU;
 628     tcstatus |= asid;
 629
 630     if (tc == cpu->current_tc) {
 631         tcst = &cpu->active_tc.CP0_TCStatus;
 632     } else {
 633         tcst = &cpu->tcs[tc].CP0_TCStatus;
 634     }
 635
 636     *tcst &= ~mask;
 637     *tcst |= tcstatus;
 638     compute_hflags(cpu);
 639 }
 640
 641 /* Called for updates to CP0_TCStatus.  */
 642 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 643                              target_ulong v)
 644 {
 645     uint32_t status;
 646     uint32_t tcu, tmx, tasid, tksu;
 647     uint32_t mask = ((1U << CP0St_CU3)
 648                        | (1 << CP0St_CU2)
 649                        | (1 << CP0St_CU1)
 650                        | (1 << CP0St_CU0)
 651                        | (1 << CP0St_MX)
 652                        | (3 << CP0St_KSU));
 653
 654     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 655     tmx = (v >> CP0TCSt_TMX) & 0x1;
 656     tasid = v & 0xff;
 657     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 658
 659     status = tcu << CP0St_CU0;
 660     status |= tmx << CP0St_MX;
 661     status |= tksu << CP0St_KSU;
 662
 663     cpu->CP0_Status &= ~mask;
 664     cpu->CP0_Status |= status;
 665
 666     /* Sync the TASID with EntryHi.  */
 667     cpu->CP0_EntryHi &= ~0xff;
 668     cpu->CP0_EntryHi = tasid;
 669
 670     compute_hflags(cpu);
 671 }
 672
 673 /* Called for updates to CP0_EntryHi.  */
 674 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 675 {
 676     int32_t *tcst;
 677     uint32_t asid, v = cpu->CP0_EntryHi;
 678
 679     asid = v & 0xff;
 680
 681     if (tc == cpu->current_tc) {
 682         tcst = &cpu->active_tc.CP0_TCStatus;
 683     } else {
 684         tcst = &cpu->tcs[tc].CP0_TCStatus;
 685     }
 686
 687     *tcst &= ~0xff;
 688     *tcst |= asid;
 689 }
 690
 691 /* CP0 helpers */
 692 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 693 {
 694     return env->mvp->CP0_MVPControl;
 695 }
 696
 697 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 698 {
 699     return env->mvp->CP0_MVPConf0;
 700 }
 701
 702 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 703 {
 704     return env->mvp->CP0_MVPConf1;
 705 }
 706
 707 target_ulong helper_mfc0_random(CPUMIPSState *env)
 708 {
 709     return (int32_t)cpu_mips_get_random(env);
 710 }
 711
 712 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 713 {
 714     return env->active_tc.CP0_TCStatus;
 715 }
 716
 717 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 718 {
 719     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 720     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 721
 722     if (other_tc == other->current_tc)
 723         return other->active_tc.CP0_TCStatus;
 724     else
 725         return other->tcs[other_tc].CP0_TCStatus;
 726 }
 727
 728 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 729 {
 730     return env->active_tc.CP0_TCBind;
 731 }
 732
 733 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 734 {
 735     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 736     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 737
 738     if (other_tc == other->current_tc)
 739         return other->active_tc.CP0_TCBind;
 740     else
 741         return other->tcs[other_tc].CP0_TCBind;
 742 }
 743
 744 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 745 {
 746     return env->active_tc.PC;
 747 }
 748
 749 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 750 {
 751     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 752     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 753
 754     if (other_tc == other->current_tc)
 755         return other->active_tc.PC;
 756     else
 757         return other->tcs[other_tc].PC;
 758 }
 759
 760 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 761 {
 762     return env->active_tc.CP0_TCHalt;
 763 }
 764
 765 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 766 {
 767     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 768     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 769
 770     if (other_tc == other->current_tc)
 771         return other->active_tc.CP0_TCHalt;
 772     else
 773         return other->tcs[other_tc].CP0_TCHalt;
 774 }
 775
 776 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 777 {
 778     return env->active_tc.CP0_TCContext;
 779 }
 780
 781 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 782 {
 783     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 784     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 785
 786     if (other_tc == other->current_tc)
 787         return other->active_tc.CP0_TCContext;
 788     else
 789         return other->tcs[other_tc].CP0_TCContext;
 790 }
 791
 792 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 793 {
 794     return env->active_tc.CP0_TCSchedule;
 795 }
 796
 797 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 798 {
 799     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 800     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 801
 802     if (other_tc == other->current_tc)
 803         return other->active_tc.CP0_TCSchedule;
 804     else
 805         return other->tcs[other_tc].CP0_TCSchedule;
 806 }
 807
 808 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 809 {
 810     return env->active_tc.CP0_TCScheFBack;
 811 }
 812
 813 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 814 {
 815     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 816     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 817
 818     if (other_tc == other->current_tc)
 819         return other->active_tc.CP0_TCScheFBack;
 820     else
 821         return other->tcs[other_tc].CP0_TCScheFBack;
 822 }
 823
 824 target_ulong helper_mfc0_count(CPUMIPSState *env)
 825 {
 826     return (int32_t)cpu_mips_get_count(env);
 827 }
 828
 829 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 830 {
 831     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 832     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 833
 834     return other->CP0_EntryHi;
 835 }
 836
 837 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 838 {
 839     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 840     int32_t tccause;
 841     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 842
 843     if (other_tc == other->current_tc) {
 844         tccause = other->CP0_Cause;
 845     } else {
 846         tccause = other->CP0_Cause;
 847     }
 848
 849     return tccause;
 850 }
 851
 852 target_ulong helper_mftc0_status(CPUMIPSState *env)
 853 {
 854     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 855     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 856
 857     return other->CP0_Status;
 858 }
 859
 860 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 861 {
 862     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 863 }
 864
 865 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 866 {
 867     return (int32_t)env->CP0_WatchLo[sel];
 868 }
 869
 870 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 871 {
 872     return env->CP0_WatchHi[sel];
 873 }
 874
 875 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 876 {
 877     target_ulong t0 = env->CP0_Debug;
 878     if (env->hflags & MIPS_HFLAG_DM)
 879         t0 |= 1 << CP0DB_DM;
 880
 881     return t0;
 882 }
 883
 884 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 885 {
 886     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 887     int32_t tcstatus;
 888     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 889
 890     if (other_tc == other->current_tc)
 891         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 892     else
 893         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 894
 895     /* XXX: Might be wrong, check with EJTAG spec. */
 896     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 897             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 898 }
 899
 900 #if defined(TARGET_MIPS64)
 901 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 902 {
 903     return env->active_tc.PC;
 904 }
 905
 906 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 907 {
 908     return env->active_tc.CP0_TCHalt;
 909 }
 910
 911 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 912 {
 913     return env->active_tc.CP0_TCContext;
 914 }
 915
 916 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 917 {
 918     return env->active_tc.CP0_TCSchedule;
 919 }
 920
 921 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 922 {
 923     return env->active_tc.CP0_TCScheFBack;
 924 }
 925
 926 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 927 {
 928     return env->lladdr >> env->CP0_LLAddr_shift;
 929 }
 930
 931 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 932 {
 933     return env->CP0_WatchLo[sel];
 934 }
 935 #endif /* TARGET_MIPS64 */
 936
 937 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 938 {
 939     int num = 1;
 940     unsigned int tmp = env->tlb->nb_tlb;
 941
 942     do {
 943         tmp >>= 1;
 944         num <<= 1;
 945     } while (tmp);
 946     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 947 }
 948
 949 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 950 {
 951     uint32_t mask = 0;
 952     uint32_t newval;
 953
 954     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 955         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 956                 (1 << CP0MVPCo_EVP);
 957     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 958         mask |= (1 << CP0MVPCo_STLB);
 959     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 960
 961     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 962
 963     env->mvp->CP0_MVPControl = newval;
 964 }
 965
 966 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 967 {
 968     uint32_t mask;
 969     uint32_t newval;
 970
 971     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 972            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 973     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 974
 975     /* Yield scheduler intercept not implemented. */
 976     /* Gating storage scheduler intercept not implemented. */
 977
 978     // TODO: Enable/disable TCs.
 979
 980     env->CP0_VPEControl = newval;
 981 }
 982
 983 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 984 {
 985     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 986     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 987     uint32_t mask;
 988     uint32_t newval;
 989
 990     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 991            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 992     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 993
 994     /* TODO: Enable/disable TCs.  */
 995
 996     other->CP0_VPEControl = newval;
 997 }
 998
 999 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1000 {
1001     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1002     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1003     /* FIXME: Mask away return zero on read bits.  */
1004     return other->CP0_VPEControl;
1005 }
1006
1007 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1008 {
1009     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1010     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011
1012     return other->CP0_VPEConf0;
1013 }
1014
1015 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1016 {
1017     uint32_t mask = 0;
1018     uint32_t newval;
1019
1020     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1021         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1022             mask |= (0xff << CP0VPEC0_XTC);
1023         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1024     }
1025     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1026
1027     // TODO: TC exclusive handling due to ERL/EXL.
1028
1029     env->CP0_VPEConf0 = newval;
1030 }
1031
1032 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1033 {
1034     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1035     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1036     uint32_t mask = 0;
1037     uint32_t newval;
1038
1039     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1040     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1041
1042     /* TODO: TC exclusive handling due to ERL/EXL.  */
1043     other->CP0_VPEConf0 = newval;
1044 }
1045
1046 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1047 {
1048     uint32_t mask = 0;
1049     uint32_t newval;
1050
1051     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1052         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1053                 (0xff << CP0VPEC1_NCP1);
1054     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1055
1056     /* UDI not implemented. */
1057     /* CP2 not implemented. */
1058
1059     // TODO: Handle FPU (CP1) binding.
1060
1061     env->CP0_VPEConf1 = newval;
1062 }
1063
1064 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1065 {
1066     /* Yield qualifier inputs not implemented. */
1067     env->CP0_YQMask = 0x00000000;
1068 }
1069
1070 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1071 {
1072     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1073 }
1074
1075 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1076 {
1077     /* Large physaddr (PABITS) not implemented */
1078     /* 1k pages not implemented */
1079     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1080 }
1081
1082 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1083 {
1084     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1085     uint32_t newval;
1086
1087     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1088
1089     env->active_tc.CP0_TCStatus = newval;
1090     sync_c0_tcstatus(env, env->current_tc, newval);
1091 }
1092
1093 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1094 {
1095     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1096     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1097
1098     if (other_tc == other->current_tc)
1099         other->active_tc.CP0_TCStatus = arg1;
1100     else
1101         other->tcs[other_tc].CP0_TCStatus = arg1;
1102     sync_c0_tcstatus(other, other_tc, arg1);
1103 }
1104
1105 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1106 {
1107     uint32_t mask = (1 << CP0TCBd_TBE);
1108     uint32_t newval;
1109
1110     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1111         mask |= (1 << CP0TCBd_CurVPE);
1112     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1113     env->active_tc.CP0_TCBind = newval;
1114 }
1115
1116 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1117 {
1118     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1119     uint32_t mask = (1 << CP0TCBd_TBE);
1120     uint32_t newval;
1121     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1122
1123     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1124         mask |= (1 << CP0TCBd_CurVPE);
1125     if (other_tc == other->current_tc) {
1126         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1127         other->active_tc.CP0_TCBind = newval;
1128     } else {
1129         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1130         other->tcs[other_tc].CP0_TCBind = newval;
1131     }
1132 }
1133
1134 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1135 {
1136     env->active_tc.PC = arg1;
1137     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1138     env->lladdr = 0ULL;
1139     /* MIPS16 not implemented. */
1140 }
1141
1142 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1143 {
1144     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1145     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1146
1147     if (other_tc == other->current_tc) {
1148         other->active_tc.PC = arg1;
1149         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1150         other->lladdr = 0ULL;
1151         /* MIPS16 not implemented. */
1152     } else {
1153         other->tcs[other_tc].PC = arg1;
1154         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1155         other->lladdr = 0ULL;
1156         /* MIPS16 not implemented. */
1157     }
1158 }
1159
1160 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1161 {
1162     MIPSCPU *cpu = mips_env_get_cpu(env);
1163
1164     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1165
1166     // TODO: Halt TC / Restart (if allocated+active) TC.
1167     if (env->active_tc.CP0_TCHalt & 1) {
1168         mips_tc_sleep(cpu, env->current_tc);
1169     } else {
1170         mips_tc_wake(cpu, env->current_tc);
1171     }
1172 }
1173
1174 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1175 {
1176     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1177     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1178     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1179
1180     // TODO: Halt TC / Restart (if allocated+active) TC.
1181
1182     if (other_tc == other->current_tc)
1183         other->active_tc.CP0_TCHalt = arg1;
1184     else
1185         other->tcs[other_tc].CP0_TCHalt = arg1;
1186
1187     if (arg1 & 1) {
1188         mips_tc_sleep(other_cpu, other_tc);
1189     } else {
1190         mips_tc_wake(other_cpu, other_tc);
1191     }
1192 }
1193
1194 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1195 {
1196     env->active_tc.CP0_TCContext = arg1;
1197 }
1198
1199 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1200 {
1201     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1202     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1203
1204     if (other_tc == other->current_tc)
1205         other->active_tc.CP0_TCContext = arg1;
1206     else
1207         other->tcs[other_tc].CP0_TCContext = arg1;
1208 }
1209
1210 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1211 {
1212     env->active_tc.CP0_TCSchedule = arg1;
1213 }
1214
1215 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1216 {
1217     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1218     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1219
1220     if (other_tc == other->current_tc)
1221         other->active_tc.CP0_TCSchedule = arg1;
1222     else
1223         other->tcs[other_tc].CP0_TCSchedule = arg1;
1224 }
1225
1226 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1227 {
1228     env->active_tc.CP0_TCScheFBack = arg1;
1229 }
1230
1231 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1232 {
1233     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235
1236     if (other_tc == other->current_tc)
1237         other->active_tc.CP0_TCScheFBack = arg1;
1238     else
1239         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1240 }
1241
1242 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1243 {
1244     /* Large physaddr (PABITS) not implemented */
1245     /* 1k pages not implemented */
1246     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1247 }
1248
1249 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1250 {
1251     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1252 }
1253
1254 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1255 {
1256     /* 1k pages not implemented */
1257     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1258 }
1259
1260 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1261 {
1262     /* SmartMIPS not implemented */
1263     /* Large physaddr (PABITS) not implemented */
1264     /* 1k pages not implemented */
1265     env->CP0_PageGrain = 0;
1266 }
1267
1268 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1269 {
1270     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1271 }
1272
1273 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1274 {
1275     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1276 }
1277
1278 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1279 {
1280     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1281 }
1282
1283 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1284 {
1285     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1286 }
1287
1288 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1289 {
1290     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1291 }
1292
1293 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1294 {
1295     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1296 }
1297
1298 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1299 {
1300     uint32_t mask = 0x0000000F;
1301
1302     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1303         mask |= (1 << 29);
1304
1305         if (arg1 & (1 << 29)) {
1306             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1307         } else {
1308             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1309         }
1310     }
1311
1312     env->CP0_HWREna = arg1 & mask;
1313 }
1314
1315 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1316 {
1317     cpu_mips_store_count(env, arg1);
1318 }
1319
1320 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1321 {
1322     target_ulong old, val;
1323
1324     /* 1k pages not implemented */
1325     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1326 #if defined(TARGET_MIPS64)
1327     val &= env->SEGMask;
1328 #endif
1329     old = env->CP0_EntryHi;
1330     env->CP0_EntryHi = val;
1331     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1332         sync_c0_entryhi(env, env->current_tc);
1333     }
1334     /* If the ASID changes, flush qemu's TLB.  */
1335     if ((old & 0xFF) != (val & 0xFF))
1336         cpu_mips_tlb_flush(env, 1);
1337 }
1338
1339 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1340 {
1341     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1342     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1343
1344     other->CP0_EntryHi = arg1;
1345     sync_c0_entryhi(other, other_tc);
1346 }
1347
1348 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1349 {
1350     cpu_mips_store_compare(env, arg1);
1351 }
1352
1353 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1354 {
1355     MIPSCPU *cpu = mips_env_get_cpu(env);
1356     uint32_t val, old;
1357     uint32_t mask = env->CP0_Status_rw_bitmask;
1358
1359     val = arg1 & mask;
1360     old = env->CP0_Status;
1361     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1362     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1363         sync_c0_status(env, env, env->current_tc);
1364     } else {
1365         compute_hflags(env);
1366     }
1367
1368     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1369         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1370                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1371                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1372                 env->CP0_Cause);
1373         switch (env->hflags & MIPS_HFLAG_KSU) {
1374         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1375         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1376         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1377         default:
1378             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1379             break;
1380         }
1381     }
1382 }
1383
1384 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1385 {
1386     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1387     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1388
1389     other->CP0_Status = arg1 & ~0xf1000018;
1390     sync_c0_status(env, other, other_tc);
1391 }
1392
1393 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1394 {
1395     /* vectored interrupts not implemented, no performance counters. */
1396     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1397 }
1398
1399 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1400 {
1401     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1402     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1403 }
1404
1405 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1406 {
1407     uint32_t mask = 0x00C00300;
1408     uint32_t old = cpu->CP0_Cause;
1409     int i;
1410
1411     if (cpu->insn_flags & ISA_MIPS32R2) {
1412         mask |= 1 << CP0Ca_DC;
1413     }
1414
1415     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1416
1417     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1418         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1419             cpu_mips_stop_count(cpu);
1420         } else {
1421             cpu_mips_start_count(cpu);
1422         }
1423     }
1424
1425     /* Set/reset software interrupts */
1426     for (i = 0 ; i < 2 ; i++) {
1427         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1428             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1429         }
1430     }
1431 }
1432
1433 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1434 {
1435     mtc0_cause(env, arg1);
1436 }
1437
1438 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1439 {
1440     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1441     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1442
1443     mtc0_cause(other, arg1);
1444 }
1445
1446 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1447 {
1448     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1449     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1450
1451     return other->CP0_EPC;
1452 }
1453
1454 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1455 {
1456     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1457     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1458
1459     return other->CP0_EBase;
1460 }
1461
1462 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1463 {
1464     /* vectored interrupts not implemented */
1465     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1466 }
1467
1468 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1469 {
1470     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1471     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1472     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1473 }
1474
1475 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1476 {
1477     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1478     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1479
1480     switch (idx) {
1481     case 0: return other->CP0_Config0;
1482     case 1: return other->CP0_Config1;
1483     case 2: return other->CP0_Config2;
1484     case 3: return other->CP0_Config3;
1485     /* 4 and 5 are reserved.  */
1486     case 6: return other->CP0_Config6;
1487     case 7: return other->CP0_Config7;
1488     default:
1489         break;
1490     }
1491     return 0;
1492 }
1493
1494 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1495 {
1496     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1497 }
1498
1499 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1500 {
1501     /* tertiary/secondary caches not implemented */
1502     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1503 }
1504
1505 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1506 {
1507     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1508                        (arg1 & env->CP0_Config4_rw_bitmask);
1509 }
1510
1511 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1512 {
1513     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1514                        (arg1 & env->CP0_Config5_rw_bitmask);
1515 }
1516
1517 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1518 {
1519     target_long mask = env->CP0_LLAddr_rw_bitmask;
1520     arg1 = arg1 << env->CP0_LLAddr_shift;
1521     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1522 }
1523
1524 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1525 {
1526     /* Watch exceptions for instructions, data loads, data stores
1527        not implemented. */
1528     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1529 }
1530
1531 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1532 {
1533     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1534     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1535 }
1536
1537 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1538 {
1539     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1540     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1541 }
1542
1543 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1544 {
1545     env->CP0_Framemask = arg1; /* XXX */
1546 }
1547
1548 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1549 {
1550     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1551     if (arg1 & (1 << CP0DB_DM))
1552         env->hflags |= MIPS_HFLAG_DM;
1553     else
1554         env->hflags &= ~MIPS_HFLAG_DM;
1555 }
1556
1557 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1558 {
1559     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1560     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1561     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1562
1563     /* XXX: Might be wrong, check with EJTAG spec. */
1564     if (other_tc == other->current_tc)
1565         other->active_tc.CP0_Debug_tcstatus = val;
1566     else
1567         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1568     other->CP0_Debug = (other->CP0_Debug &
1569                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1570                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1571 }
1572
1573 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1574 {
1575     env->CP0_Performance0 = arg1 & 0x000007ff;
1576 }
1577
1578 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1579 {
1580     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1581 }
1582
1583 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1584 {
1585     env->CP0_DataLo = arg1; /* XXX */
1586 }
1587
1588 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1589 {
1590     env->CP0_TagHi = arg1; /* XXX */
1591 }
1592
1593 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1594 {
1595     env->CP0_DataHi = arg1; /* XXX */
1596 }
1597
1598 /* MIPS MT functions */
1599 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1600 {
1601     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1602     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1603
1604     if (other_tc == other->current_tc)
1605         return other->active_tc.gpr[sel];
1606     else
1607         return other->tcs[other_tc].gpr[sel];
1608 }
1609
1610 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1611 {
1612     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1613     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1614
1615     if (other_tc == other->current_tc)
1616         return other->active_tc.LO[sel];
1617     else
1618         return other->tcs[other_tc].LO[sel];
1619 }
1620
1621 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1622 {
1623     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1624     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1625
1626     if (other_tc == other->current_tc)
1627         return other->active_tc.HI[sel];
1628     else
1629         return other->tcs[other_tc].HI[sel];
1630 }
1631
1632 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1633 {
1634     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1635     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1636
1637     if (other_tc == other->current_tc)
1638         return other->active_tc.ACX[sel];
1639     else
1640         return other->tcs[other_tc].ACX[sel];
1641 }
1642
1643 target_ulong helper_mftdsp(CPUMIPSState *env)
1644 {
1645     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1646     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1647
1648     if (other_tc == other->current_tc)
1649         return other->active_tc.DSPControl;
1650     else
1651         return other->tcs[other_tc].DSPControl;
1652 }
1653
1654 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1655 {
1656     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1657     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1658
1659     if (other_tc == other->current_tc)
1660         other->active_tc.gpr[sel] = arg1;
1661     else
1662         other->tcs[other_tc].gpr[sel] = arg1;
1663 }
1664
1665 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1666 {
1667     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1668     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1669
1670     if (other_tc == other->current_tc)
1671         other->active_tc.LO[sel] = arg1;
1672     else
1673         other->tcs[other_tc].LO[sel] = arg1;
1674 }
1675
1676 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1677 {
1678     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1679     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1680
1681     if (other_tc == other->current_tc)
1682         other->active_tc.HI[sel] = arg1;
1683     else
1684         other->tcs[other_tc].HI[sel] = arg1;
1685 }
1686
1687 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1688 {
1689     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1690     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1691
1692     if (other_tc == other->current_tc)
1693         other->active_tc.ACX[sel] = arg1;
1694     else
1695         other->tcs[other_tc].ACX[sel] = arg1;
1696 }
1697
1698 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1699 {
1700     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1701     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1702
1703     if (other_tc == other->current_tc)
1704         other->active_tc.DSPControl = arg1;
1705     else
1706         other->tcs[other_tc].DSPControl = arg1;
1707 }
1708
1709 /* MIPS MT functions */
1710 target_ulong helper_dmt(void)
1711 {
1712     // TODO
1713      return 0;
1714 }
1715
1716 target_ulong helper_emt(void)
1717 {
1718     // TODO
1719     return 0;
1720 }
1721
1722 target_ulong helper_dvpe(CPUMIPSState *env)
1723 {
1724     CPUState *other_cs = first_cpu;
1725     target_ulong prev = env->mvp->CP0_MVPControl;
1726
1727     CPU_FOREACH(other_cs) {
1728         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1729         /* Turn off all VPEs except the one executing the dvpe.  */
1730         if (&other_cpu->env != env) {
1731             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1732             mips_vpe_sleep(other_cpu);
1733         }
1734     }
1735     return prev;
1736 }
1737
1738 target_ulong helper_evpe(CPUMIPSState *env)
1739 {
1740     CPUState *other_cs = first_cpu;
1741     target_ulong prev = env->mvp->CP0_MVPControl;
1742
1743     CPU_FOREACH(other_cs) {
1744         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1745
1746         if (&other_cpu->env != env
1747             /* If the VPE is WFI, don't disturb its sleep.  */
1748             && !mips_vpe_is_wfi(other_cpu)) {
1749             /* Enable the VPE.  */
1750             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1751             mips_vpe_wake(other_cpu); /* And wake it up.  */
1752         }
1753     }
1754     return prev;
1755 }
1756 #endif /* !CONFIG_USER_ONLY */
1757
1758 void helper_fork(target_ulong arg1, target_ulong arg2)
1759 {
1760     // arg1 = rt, arg2 = rs
1761     // TODO: store to TC register
1762 }
1763
1764 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1765 {
1766     target_long arg1 = arg;
1767
1768     if (arg1 < 0) {
1769         /* No scheduling policy implemented. */
1770         if (arg1 != -2) {
1771             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1772                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1773                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1774                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1775                 helper_raise_exception(env, EXCP_THREAD);
1776             }
1777         }
1778     } else if (arg1 == 0) {
1779         if (0 /* TODO: TC underflow */) {
1780             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1781             helper_raise_exception(env, EXCP_THREAD);
1782         } else {
1783             // TODO: Deallocate TC
1784         }
1785     } else if (arg1 > 0) {
1786         /* Yield qualifier inputs not implemented. */
1787         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1788         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1789         helper_raise_exception(env, EXCP_THREAD);
1790     }
1791     return env->CP0_YQMask;
1792 }
1793
1794 #ifndef CONFIG_USER_ONLY
1795 /* TLB management */
1796 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1797 {
1798     MIPSCPU *cpu = mips_env_get_cpu(env);
1799
1800     /* Flush qemu's TLB and discard all shadowed entries.  */
1801     tlb_flush(CPU(cpu), flush_global);
1802     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1803 }
1804
1805 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1806 {
1807     /* Discard entries from env->tlb[first] onwards.  */
1808     while (env->tlb->tlb_in_use > first) {
1809         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1810     }
1811 }
1812
1813 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1814 {
1815     r4k_tlb_t *tlb;
1816
1817     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1818     tlb = &env->tlb->mmu.r4k.tlb[idx];
1819     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1820 #if defined(TARGET_MIPS64)
1821     tlb->VPN &= env->SEGMask;
1822 #endif
1823     tlb->ASID = env->CP0_EntryHi & 0xFF;
1824     tlb->PageMask = env->CP0_PageMask;
1825     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1826     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1827     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1828     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1829     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1830     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1831     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1832     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1833     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1834 }
1835
1836 void r4k_helper_tlbwi(CPUMIPSState *env)
1837 {
1838     r4k_tlb_t *tlb;
1839     int idx;
1840     target_ulong VPN;
1841     uint8_t ASID;
1842     bool G, V0, D0, V1, D1;
1843
1844     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1845     tlb = &env->tlb->mmu.r4k.tlb[idx];
1846     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1847 #if defined(TARGET_MIPS64)
1848     VPN &= env->SEGMask;
1849 #endif
1850     ASID = env->CP0_EntryHi & 0xff;
1851     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1852     V0 = (env->CP0_EntryLo0 & 2) != 0;
1853     D0 = (env->CP0_EntryLo0 & 4) != 0;
1854     V1 = (env->CP0_EntryLo1 & 2) != 0;
1855     D1 = (env->CP0_EntryLo1 & 4) != 0;
1856
1857     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1858        permissions on the current entry. */
1859     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1860         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1861         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1862         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1863     }
1864
1865     r4k_invalidate_tlb(env, idx, 0);
1866     r4k_fill_tlb(env, idx);
1867 }
1868
1869 void r4k_helper_tlbwr(CPUMIPSState *env)
1870 {
1871     int r = cpu_mips_get_random(env);
1872
1873     r4k_invalidate_tlb(env, r, 1);
1874     r4k_fill_tlb(env, r);
1875 }
1876
1877 void r4k_helper_tlbp(CPUMIPSState *env)
1878 {
1879     r4k_tlb_t *tlb;
1880     target_ulong mask;
1881     target_ulong tag;
1882     target_ulong VPN;
1883     uint8_t ASID;
1884     int i;
1885
1886     ASID = env->CP0_EntryHi & 0xFF;
1887     for (i = 0; i < env->tlb->nb_tlb; i++) {
1888         tlb = &env->tlb->mmu.r4k.tlb[i];
1889         /* 1k pages are not supported. */
1890         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1891         tag = env->CP0_EntryHi & ~mask;
1892         VPN = tlb->VPN & ~mask;
1893 #if defined(TARGET_MIPS64)
1894         tag &= env->SEGMask;
1895 #endif
1896         /* Check ASID, virtual page number & size */
1897         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1898             /* TLB match */
1899             env->CP0_Index = i;
1900             break;
1901         }
1902     }
1903     if (i == env->tlb->nb_tlb) {
1904         /* No match.  Discard any shadow entries, if any of them match.  */
1905         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1906             tlb = &env->tlb->mmu.r4k.tlb[i];
1907             /* 1k pages are not supported. */
1908             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1909             tag = env->CP0_EntryHi & ~mask;
1910             VPN = tlb->VPN & ~mask;
1911 #if defined(TARGET_MIPS64)
1912             tag &= env->SEGMask;
1913 #endif
1914             /* Check ASID, virtual page number & size */
1915             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1916                 r4k_mips_tlb_flush_extra (env, i);
1917                 break;
1918             }
1919         }
1920
1921         env->CP0_Index |= 0x80000000;
1922     }
1923 }
1924
1925 void r4k_helper_tlbr(CPUMIPSState *env)
1926 {
1927     r4k_tlb_t *tlb;
1928     uint8_t ASID;
1929     int idx;
1930
1931     ASID = env->CP0_EntryHi & 0xFF;
1932     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1933     tlb = &env->tlb->mmu.r4k.tlb[idx];
1934
1935     /* If this will change the current ASID, flush qemu's TLB.  */
1936     if (ASID != tlb->ASID)
1937         cpu_mips_tlb_flush (env, 1);
1938
1939     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1940
1941     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1942     env->CP0_PageMask = tlb->PageMask;
1943     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1944                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1945     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1946                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1947 }
1948
1949 void helper_tlbwi(CPUMIPSState *env)
1950 {
1951     env->tlb->helper_tlbwi(env);
1952 }
1953
1954 void helper_tlbwr(CPUMIPSState *env)
1955 {
1956     env->tlb->helper_tlbwr(env);
1957 }
1958
1959 void helper_tlbp(CPUMIPSState *env)
1960 {
1961     env->tlb->helper_tlbp(env);
1962 }
1963
1964 void helper_tlbr(CPUMIPSState *env)
1965 {
1966     env->tlb->helper_tlbr(env);
1967 }
1968
1969 /* Specials */
1970 target_ulong helper_di(CPUMIPSState *env)
1971 {
1972     target_ulong t0 = env->CP0_Status;
1973
1974     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1975     return t0;
1976 }
1977
1978 target_ulong helper_ei(CPUMIPSState *env)
1979 {
1980     target_ulong t0 = env->CP0_Status;
1981
1982     env->CP0_Status = t0 | (1 << CP0St_IE);
1983     return t0;
1984 }
1985
1986 static void debug_pre_eret(CPUMIPSState *env)
1987 {
1988     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1989         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1990                 env->active_tc.PC, env->CP0_EPC);
1991         if (env->CP0_Status & (1 << CP0St_ERL))
1992             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1993         if (env->hflags & MIPS_HFLAG_DM)
1994             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1995         qemu_log("\n");
1996     }
1997 }
1998
1999 static void debug_post_eret(CPUMIPSState *env)
2000 {
2001     MIPSCPU *cpu = mips_env_get_cpu(env);
2002
2003     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2004         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2005                 env->active_tc.PC, env->CP0_EPC);
2006         if (env->CP0_Status & (1 << CP0St_ERL))
2007             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2008         if (env->hflags & MIPS_HFLAG_DM)
2009             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2010         switch (env->hflags & MIPS_HFLAG_KSU) {
2011         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2012         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2013         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2014         default:
2015             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2016             break;
2017         }
2018     }
2019 }
2020
2021 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2022 {
2023     env->active_tc.PC = error_pc & ~(target_ulong)1;
2024     if (error_pc & 1) {
2025         env->hflags |= MIPS_HFLAG_M16;
2026     } else {
2027         env->hflags &= ~(MIPS_HFLAG_M16);
2028     }
2029 }
2030
2031 void helper_eret(CPUMIPSState *env)
2032 {
2033     debug_pre_eret(env);
2034     if (env->CP0_Status & (1 << CP0St_ERL)) {
2035         set_pc(env, env->CP0_ErrorEPC);
2036         env->CP0_Status &= ~(1 << CP0St_ERL);
2037     } else {
2038         set_pc(env, env->CP0_EPC);
2039         env->CP0_Status &= ~(1 << CP0St_EXL);
2040     }
2041     compute_hflags(env);
2042     debug_post_eret(env);
2043     env->lladdr = 1;
2044 }
2045
2046 void helper_deret(CPUMIPSState *env)
2047 {
2048     debug_pre_eret(env);
2049     set_pc(env, env->CP0_DEPC);
2050
2051     env->hflags &= MIPS_HFLAG_DM;
2052     compute_hflags(env);
2053     debug_post_eret(env);
2054     env->lladdr = 1;
2055 }
2056 #endif /* !CONFIG_USER_ONLY */
2057
2058 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2059 {
2060     if ((env->hflags & MIPS_HFLAG_CP0) ||
2061         (env->CP0_HWREna & (1 << 0)))
2062         return env->CP0_EBase & 0x3ff;
2063     else
2064         helper_raise_exception(env, EXCP_RI);
2065
2066     return 0;
2067 }
2068
2069 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2070 {
2071     if ((env->hflags & MIPS_HFLAG_CP0) ||
2072         (env->CP0_HWREna & (1 << 1)))
2073         return env->SYNCI_Step;
2074     else
2075         helper_raise_exception(env, EXCP_RI);
2076
2077     return 0;
2078 }
2079
2080 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2081 {
2082     if ((env->hflags & MIPS_HFLAG_CP0) ||
2083         (env->CP0_HWREna & (1 << 2)))
2084         return env->CP0_Count;
2085     else
2086         helper_raise_exception(env, EXCP_RI);
2087
2088     return 0;
2089 }
2090
2091 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2092 {
2093     if ((env->hflags & MIPS_HFLAG_CP0) ||
2094         (env->CP0_HWREna & (1 << 3)))
2095         return env->CCRes;
2096     else
2097         helper_raise_exception(env, EXCP_RI);
2098
2099     return 0;
2100 }
2101
2102 void helper_pmon(CPUMIPSState *env, int function)
2103 {
2104     function /= 2;
2105     switch (function) {
2106     case 2: /* TODO: char inbyte(int waitflag); */
2107         if (env->active_tc.gpr[4] == 0)
2108             env->active_tc.gpr[2] = -1;
2109         /* Fall through */
2110     case 11: /* TODO: char inbyte (void); */
2111         env->active_tc.gpr[2] = -1;
2112         break;
2113     case 3:
2114     case 12:
2115         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2116         break;
2117     case 17:
2118         break;
2119     case 158:
2120         {
2121             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2122             printf("%s", fmt);
2123         }
2124         break;
2125     }
2126 }
2127
2128 void helper_wait(CPUMIPSState *env)
2129 {
2130     CPUState *cs = CPU(mips_env_get_cpu(env));
2131
2132     cs->halted = 1;
2133     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2134     helper_raise_exception(env, EXCP_HLT);
2135 }
2136
2137 #if !defined(CONFIG_USER_ONLY)
2138
2139 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2140                                   int is_write, int is_user, uintptr_t retaddr)
2141 {
2142     MIPSCPU *cpu = MIPS_CPU(cs);
2143     CPUMIPSState *env = &cpu->env;
2144
2145     env->CP0_BadVAddr = addr;
2146     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2147 }
2148
2149 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2150               uintptr_t retaddr)
2151 {
2152     int ret;
2153
2154     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2155     if (ret) {
2156         MIPSCPU *cpu = MIPS_CPU(cs);
2157         CPUMIPSState *env = &cpu->env;
2158
2159         do_raise_exception_err(env, cs->exception_index,
2160                                env->error_code, retaddr);
2161     }
2162 }
2163
2164 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2165                                 bool is_write, bool is_exec, int unused,
2166                                 unsigned size)
2167 {
2168     MIPSCPU *cpu = MIPS_CPU(cs);
2169     CPUMIPSState *env = &cpu->env;
2170
2171     if (is_exec) {
2172         helper_raise_exception(env, EXCP_IBE);
2173     } else {
2174         helper_raise_exception(env, EXCP_DBE);
2175     }
2176 }
2177 #endif /* !CONFIG_USER_ONLY */
2178
2179 /* Complex FPU operations which may need stack space. */
2180
2181 #define FLOAT_TWO32 make_float32(1 << 30)
2182 #define FLOAT_TWO64 make_float64(1ULL << 62)
2183 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2184 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2185
2186 /* convert MIPS rounding mode in FCR31 to IEEE library */
2187 static unsigned int ieee_rm[] = {
2188     float_round_nearest_even,
2189     float_round_to_zero,
2190     float_round_up,
2191     float_round_down
2192 };
2193
2194 static inline void restore_rounding_mode(CPUMIPSState *env)
2195 {
2196     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2197                             &env->active_fpu.fp_status);
2198 }
2199
2200 static inline void restore_flush_mode(CPUMIPSState *env)
2201 {
2202     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2203                       &env->active_fpu.fp_status);
2204 }
2205
2206 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2207 {
2208     target_ulong arg1 = 0;
2209
2210     switch (reg) {
2211     case 0:
2212         arg1 = (int32_t)env->active_fpu.fcr0;
2213         break;
2214     case 1:
2215         /* UFR Support - Read Status FR */
2216         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2217             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2218                 arg1 = (int32_t)
2219                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2220             } else {
2221                 helper_raise_exception(env, EXCP_RI);
2222             }
2223         }
2224         break;
2225     case 25:
2226         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2227         break;
2228     case 26:
2229         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2230         break;
2231     case 28:
2232         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2233         break;
2234     default:
2235         arg1 = (int32_t)env->active_fpu.fcr31;
2236         break;
2237     }
2238
2239     return arg1;
2240 }
2241
2242 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2243 {
2244     switch (fs) {
2245     case 1:
2246         /* UFR Alias - Reset Status FR */
2247         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2248             return;
2249         }
2250         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2251             env->CP0_Status &= ~(1 << CP0St_FR);
2252             compute_hflags(env);
2253         } else {
2254             helper_raise_exception(env, EXCP_RI);
2255         }
2256         break;
2257     case 4:
2258         /* UNFR Alias - Set Status FR */
2259         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2260             return;
2261         }
2262         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2263             env->CP0_Status |= (1 << CP0St_FR);
2264             compute_hflags(env);
2265         } else {
2266             helper_raise_exception(env, EXCP_RI);
2267         }
2268         break;
2269     case 25:
2270         if (arg1 & 0xffffff00)
2271             return;
2272         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2273                      ((arg1 & 0x1) << 23);
2274         break;
2275     case 26:
2276         if (arg1 & 0x007c0000)
2277             return;
2278         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2279         break;
2280     case 28:
2281         if (arg1 & 0x007c0000)
2282             return;
2283         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2284                      ((arg1 & 0x4) << 22);
2285         break;
2286     case 31:
2287         if (arg1 & 0x007c0000)
2288             return;
2289         env->active_fpu.fcr31 = arg1;
2290         break;
2291     default:
2292         return;
2293     }
2294     /* set rounding mode */
2295     restore_rounding_mode(env);
2296     /* set flush-to-zero mode */
2297     restore_flush_mode(env);
2298     set_float_exception_flags(0, &env->active_fpu.fp_status);
2299     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2300         do_raise_exception(env, EXCP_FPE, GETPC());
2301 }
2302
2303 static inline int ieee_ex_to_mips(int xcpt)
2304 {
2305     int ret = 0;
2306     if (xcpt) {
2307         if (xcpt & float_flag_invalid) {
2308             ret |= FP_INVALID;
2309         }
2310         if (xcpt & float_flag_overflow) {
2311             ret |= FP_OVERFLOW;
2312         }
2313         if (xcpt & float_flag_underflow) {
2314             ret |= FP_UNDERFLOW;
2315         }
2316         if (xcpt & float_flag_divbyzero) {
2317             ret |= FP_DIV0;
2318         }
2319         if (xcpt & float_flag_inexact) {
2320             ret |= FP_INEXACT;
2321         }
2322     }
2323     return ret;
2324 }
2325
2326 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2327 {
2328     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2329
2330     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2331
2332     if (tmp) {
2333         set_float_exception_flags(0, &env->active_fpu.fp_status);
2334
2335         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2336             do_raise_exception(env, EXCP_FPE, pc);
2337         } else {
2338             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2339         }
2340     }
2341 }
2342
2343 /* Float support.
2344    Single precition routines have a "s" suffix, double precision a
2345    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2346    paired single lower "pl", paired single upper "pu".  */
2347
2348 /* unary operations, modifying fp status  */
2349 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2350 {
2351     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2352     update_fcr31(env, GETPC());
2353     return fdt0;
2354 }
2355
2356 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2357 {
2358     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2359     update_fcr31(env, GETPC());
2360     return fst0;
2361 }
2362
2363 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2364 {
2365     uint64_t fdt2;
2366
2367     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2368     update_fcr31(env, GETPC());
2369     return fdt2;
2370 }
2371
2372 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2373 {
2374     uint64_t fdt2;
2375
2376     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2377     update_fcr31(env, GETPC());
2378     return fdt2;
2379 }
2380
2381 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2382 {
2383     uint64_t fdt2;
2384
2385     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2386     update_fcr31(env, GETPC());
2387     return fdt2;
2388 }
2389
2390 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2391 {
2392     uint64_t dt2;
2393
2394     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2395     if (get_float_exception_flags(&env->active_fpu.fp_status)
2396         & (float_flag_invalid | float_flag_overflow)) {
2397         dt2 = FP_TO_INT64_OVERFLOW;
2398     }
2399     update_fcr31(env, GETPC());
2400     return dt2;
2401 }
2402
2403 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2404 {
2405     uint64_t dt2;
2406
2407     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2408     if (get_float_exception_flags(&env->active_fpu.fp_status)
2409         & (float_flag_invalid | float_flag_overflow)) {
2410         dt2 = FP_TO_INT64_OVERFLOW;
2411     }
2412     update_fcr31(env, GETPC());
2413     return dt2;
2414 }
2415
2416 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2417 {
2418     uint32_t fst2;
2419     uint32_t fsth2;
2420
2421     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2422     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2423     update_fcr31(env, GETPC());
2424     return ((uint64_t)fsth2 << 32) | fst2;
2425 }
2426
2427 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2428 {
2429     uint32_t wt2;
2430     uint32_t wth2;
2431     int excp, excph;
2432
2433     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2434     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2435     if (excp & (float_flag_overflow | float_flag_invalid)) {
2436         wt2 = FP_TO_INT32_OVERFLOW;
2437     }
2438
2439     set_float_exception_flags(0, &env->active_fpu.fp_status);
2440     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2441     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2442     if (excph & (float_flag_overflow | float_flag_invalid)) {
2443         wth2 = FP_TO_INT32_OVERFLOW;
2444     }
2445
2446     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2447     update_fcr31(env, GETPC());
2448
2449     return ((uint64_t)wth2 << 32) | wt2;
2450 }
2451
2452 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2453 {
2454     uint32_t fst2;
2455
2456     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2457     update_fcr31(env, GETPC());
2458     return fst2;
2459 }
2460
2461 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2462 {
2463     uint32_t fst2;
2464
2465     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2466     update_fcr31(env, GETPC());
2467     return fst2;
2468 }
2469
2470 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2471 {
2472     uint32_t fst2;
2473
2474     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2475     update_fcr31(env, GETPC());
2476     return fst2;
2477 }
2478
2479 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2480 {
2481     uint32_t wt2;
2482
2483     wt2 = wt0;
2484     update_fcr31(env, GETPC());
2485     return wt2;
2486 }
2487
2488 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2489 {
2490     uint32_t wt2;
2491
2492     wt2 = wth0;
2493     update_fcr31(env, GETPC());
2494     return wt2;
2495 }
2496
2497 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2498 {
2499     uint32_t wt2;
2500
2501     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2502     update_fcr31(env, GETPC());
2503     if (get_float_exception_flags(&env->active_fpu.fp_status)
2504         & (float_flag_invalid | float_flag_overflow)) {
2505         wt2 = FP_TO_INT32_OVERFLOW;
2506     }
2507     return wt2;
2508 }
2509
2510 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2511 {
2512     uint32_t wt2;
2513
2514     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2515     if (get_float_exception_flags(&env->active_fpu.fp_status)
2516         & (float_flag_invalid | float_flag_overflow)) {
2517         wt2 = FP_TO_INT32_OVERFLOW;
2518     }
2519     update_fcr31(env, GETPC());
2520     return wt2;
2521 }
2522
2523 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2524 {
2525     uint64_t dt2;
2526
2527     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2528     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2529     restore_rounding_mode(env);
2530     if (get_float_exception_flags(&env->active_fpu.fp_status)
2531         & (float_flag_invalid | float_flag_overflow)) {
2532         dt2 = FP_TO_INT64_OVERFLOW;
2533     }
2534     update_fcr31(env, GETPC());
2535     return dt2;
2536 }
2537
2538 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2539 {
2540     uint64_t dt2;
2541
2542     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2543     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2544     restore_rounding_mode(env);
2545     if (get_float_exception_flags(&env->active_fpu.fp_status)
2546         & (float_flag_invalid | float_flag_overflow)) {
2547         dt2 = FP_TO_INT64_OVERFLOW;
2548     }
2549     update_fcr31(env, GETPC());
2550     return dt2;
2551 }
2552
2553 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2554 {
2555     uint32_t wt2;
2556
2557     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2558     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2559     restore_rounding_mode(env);
2560     if (get_float_exception_flags(&env->active_fpu.fp_status)
2561         & (float_flag_invalid | float_flag_overflow)) {
2562         wt2 = FP_TO_INT32_OVERFLOW;
2563     }
2564     update_fcr31(env, GETPC());
2565     return wt2;
2566 }
2567
2568 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2569 {
2570     uint32_t wt2;
2571
2572     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2573     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2574     restore_rounding_mode(env);
2575     if (get_float_exception_flags(&env->active_fpu.fp_status)
2576         & (float_flag_invalid | float_flag_overflow)) {
2577         wt2 = FP_TO_INT32_OVERFLOW;
2578     }
2579     update_fcr31(env, GETPC());
2580     return wt2;
2581 }
2582
2583 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2584 {
2585     uint64_t dt2;
2586
2587     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2588     if (get_float_exception_flags(&env->active_fpu.fp_status)
2589         & (float_flag_invalid | float_flag_overflow)) {
2590         dt2 = FP_TO_INT64_OVERFLOW;
2591     }
2592     update_fcr31(env, GETPC());
2593     return dt2;
2594 }
2595
2596 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2597 {
2598     uint64_t dt2;
2599
2600     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2601     if (get_float_exception_flags(&env->active_fpu.fp_status)
2602         & (float_flag_invalid | float_flag_overflow)) {
2603         dt2 = FP_TO_INT64_OVERFLOW;
2604     }
2605     update_fcr31(env, GETPC());
2606     return dt2;
2607 }
2608
2609 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2610 {
2611     uint32_t wt2;
2612
2613     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2614     if (get_float_exception_flags(&env->active_fpu.fp_status)
2615         & (float_flag_invalid | float_flag_overflow)) {
2616         wt2 = FP_TO_INT32_OVERFLOW;
2617     }
2618     update_fcr31(env, GETPC());
2619     return wt2;
2620 }
2621
2622 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2623 {
2624     uint32_t wt2;
2625
2626     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2627     if (get_float_exception_flags(&env->active_fpu.fp_status)
2628         & (float_flag_invalid | float_flag_overflow)) {
2629         wt2 = FP_TO_INT32_OVERFLOW;
2630     }
2631     update_fcr31(env, GETPC());
2632     return wt2;
2633 }
2634
2635 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2636 {
2637     uint64_t dt2;
2638
2639     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2640     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2641     restore_rounding_mode(env);
2642     if (get_float_exception_flags(&env->active_fpu.fp_status)
2643         & (float_flag_invalid | float_flag_overflow)) {
2644         dt2 = FP_TO_INT64_OVERFLOW;
2645     }
2646     update_fcr31(env, GETPC());
2647     return dt2;
2648 }
2649
2650 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2651 {
2652     uint64_t dt2;
2653
2654     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2655     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2656     restore_rounding_mode(env);
2657     if (get_float_exception_flags(&env->active_fpu.fp_status)
2658         & (float_flag_invalid | float_flag_overflow)) {
2659         dt2 = FP_TO_INT64_OVERFLOW;
2660     }
2661     update_fcr31(env, GETPC());
2662     return dt2;
2663 }
2664
2665 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2666 {
2667     uint32_t wt2;
2668
2669     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2670     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2671     restore_rounding_mode(env);
2672     if (get_float_exception_flags(&env->active_fpu.fp_status)
2673         & (float_flag_invalid | float_flag_overflow)) {
2674         wt2 = FP_TO_INT32_OVERFLOW;
2675     }
2676     update_fcr31(env, GETPC());
2677     return wt2;
2678 }
2679
2680 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2681 {
2682     uint32_t wt2;
2683
2684     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2685     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2686     restore_rounding_mode(env);
2687     if (get_float_exception_flags(&env->active_fpu.fp_status)
2688         & (float_flag_invalid | float_flag_overflow)) {
2689         wt2 = FP_TO_INT32_OVERFLOW;
2690     }
2691     update_fcr31(env, GETPC());
2692     return wt2;
2693 }
2694
2695 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2696 {
2697     uint64_t dt2;
2698
2699     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2700     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2701     restore_rounding_mode(env);
2702     if (get_float_exception_flags(&env->active_fpu.fp_status)
2703         & (float_flag_invalid | float_flag_overflow)) {
2704         dt2 = FP_TO_INT64_OVERFLOW;
2705     }
2706     update_fcr31(env, GETPC());
2707     return dt2;
2708 }
2709
2710 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2711 {
2712     uint64_t dt2;
2713
2714     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2715     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2716     restore_rounding_mode(env);
2717     if (get_float_exception_flags(&env->active_fpu.fp_status)
2718         & (float_flag_invalid | float_flag_overflow)) {
2719         dt2 = FP_TO_INT64_OVERFLOW;
2720     }
2721     update_fcr31(env, GETPC());
2722     return dt2;
2723 }
2724
2725 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2726 {
2727     uint32_t wt2;
2728
2729     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2730     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2731     restore_rounding_mode(env);
2732     if (get_float_exception_flags(&env->active_fpu.fp_status)
2733         & (float_flag_invalid | float_flag_overflow)) {
2734         wt2 = FP_TO_INT32_OVERFLOW;
2735     }
2736     update_fcr31(env, GETPC());
2737     return wt2;
2738 }
2739
2740 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2741 {
2742     uint32_t wt2;
2743
2744     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2745     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2746     restore_rounding_mode(env);
2747     if (get_float_exception_flags(&env->active_fpu.fp_status)
2748         & (float_flag_invalid | float_flag_overflow)) {
2749         wt2 = FP_TO_INT32_OVERFLOW;
2750     }
2751     update_fcr31(env, GETPC());
2752     return wt2;
2753 }
2754
2755 /* unary operations, not modifying fp status  */
2756 #define FLOAT_UNOP(name)                                       \
2757 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2758 {                                                              \
2759     return float64_ ## name(fdt0);                             \
2760 }                                                              \
2761 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2762 {                                                              \
2763     return float32_ ## name(fst0);                             \
2764 }                                                              \
2765 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2766 {                                                              \
2767     uint32_t wt0;                                              \
2768     uint32_t wth0;                                             \
2769                                                                \
2770     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2771     wth0 = float32_ ## name(fdt0 >> 32);                       \
2772     return ((uint64_t)wth0 << 32) | wt0;                       \
2773 }
2774 FLOAT_UNOP(abs)
2775 FLOAT_UNOP(chs)
2776 #undef FLOAT_UNOP
2777
2778 /* MIPS specific unary operations */
2779 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2780 {
2781     uint64_t fdt2;
2782
2783     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2784     update_fcr31(env, GETPC());
2785     return fdt2;
2786 }
2787
2788 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2789 {
2790     uint32_t fst2;
2791
2792     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2793     update_fcr31(env, GETPC());
2794     return fst2;
2795 }
2796
2797 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2798 {
2799     uint64_t fdt2;
2800
2801     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2802     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2803     update_fcr31(env, GETPC());
2804     return fdt2;
2805 }
2806
2807 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2808 {
2809     uint32_t fst2;
2810
2811     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2812     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2813     update_fcr31(env, GETPC());
2814     return fst2;
2815 }
2816
2817 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2818 {
2819     uint64_t fdt2;
2820
2821     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2822     update_fcr31(env, GETPC());
2823     return fdt2;
2824 }
2825
2826 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2827 {
2828     uint32_t fst2;
2829
2830     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2831     update_fcr31(env, GETPC());
2832     return fst2;
2833 }
2834
2835 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2836 {
2837     uint32_t fst2;
2838     uint32_t fsth2;
2839
2840     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2841     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2842     update_fcr31(env, GETPC());
2843     return ((uint64_t)fsth2 << 32) | fst2;
2844 }
2845
2846 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2847 {
2848     uint64_t fdt2;
2849
2850     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2851     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2852     update_fcr31(env, GETPC());
2853     return fdt2;
2854 }
2855
2856 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2857 {
2858     uint32_t fst2;
2859
2860     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2861     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2862     update_fcr31(env, GETPC());
2863     return fst2;
2864 }
2865
2866 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2867 {
2868     uint32_t fst2;
2869     uint32_t fsth2;
2870
2871     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2872     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2873     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2874     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2875     update_fcr31(env, GETPC());
2876     return ((uint64_t)fsth2 << 32) | fst2;
2877 }
2878
2879 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2880
2881 /* binary operations */
2882 #define FLOAT_BINOP(name)                                          \
2883 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2884                                      uint64_t fdt0, uint64_t fdt1) \
2885 {                                                                  \
2886     uint64_t dt2;                                                  \
2887                                                                    \
2888     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2889     update_fcr31(env, GETPC());                                    \
2890     return dt2;                                                    \
2891 }                                                                  \
2892                                                                    \
2893 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2894                                      uint32_t fst0, uint32_t fst1) \
2895 {                                                                  \
2896     uint32_t wt2;                                                  \
2897                                                                    \
2898     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2899     update_fcr31(env, GETPC());                                    \
2900     return wt2;                                                    \
2901 }                                                                  \
2902                                                                    \
2903 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2904                                       uint64_t fdt0,               \
2905                                       uint64_t fdt1)               \
2906 {                                                                  \
2907     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2908     uint32_t fsth0 = fdt0 >> 32;                                   \
2909     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2910     uint32_t fsth1 = fdt1 >> 32;                                   \
2911     uint32_t wt2;                                                  \
2912     uint32_t wth2;                                                 \
2913                                                                    \
2914     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2915     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2916     update_fcr31(env, GETPC());                                    \
2917     return ((uint64_t)wth2 << 32) | wt2;                           \
2918 }
2919
2920 FLOAT_BINOP(add)
2921 FLOAT_BINOP(sub)
2922 FLOAT_BINOP(mul)
2923 FLOAT_BINOP(div)
2924 #undef FLOAT_BINOP
2925
2926 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
2927 {                                                                    \
2928     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
2929     if ((flags) & float_muladd_negate_c) {                           \
2930         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
2931     } else {                                                         \
2932         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
2933     }                                                                \
2934     if ((flags) & float_muladd_negate_result) {                      \
2935         a = prefix##_chs(a);                                         \
2936     }                                                                \
2937 }
2938
2939 /* FMA based operations */
2940 #define FLOAT_FMA(name, type)                                        \
2941 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2942                                      uint64_t fdt0, uint64_t fdt1,   \
2943                                      uint64_t fdt2)                  \
2944 {                                                                    \
2945     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
2946     update_fcr31(env, GETPC());                                      \
2947     return fdt0;                                                     \
2948 }                                                                    \
2949                                                                      \
2950 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2951                                      uint32_t fst0, uint32_t fst1,   \
2952                                      uint32_t fst2)                  \
2953 {                                                                    \
2954     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2955     update_fcr31(env, GETPC());                                      \
2956     return fst0;                                                     \
2957 }                                                                    \
2958                                                                      \
2959 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2960                                       uint64_t fdt0, uint64_t fdt1,  \
2961                                       uint64_t fdt2)                 \
2962 {                                                                    \
2963     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2964     uint32_t fsth0 = fdt0 >> 32;                                     \
2965     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2966     uint32_t fsth1 = fdt1 >> 32;                                     \
2967     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2968     uint32_t fsth2 = fdt2 >> 32;                                     \
2969                                                                      \
2970     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2971     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
2972     update_fcr31(env, GETPC());                                      \
2973     return ((uint64_t)fsth0 << 32) | fst0;                           \
2974 }
2975 FLOAT_FMA(madd, 0)
2976 FLOAT_FMA(msub, float_muladd_negate_c)
2977 FLOAT_FMA(nmadd, float_muladd_negate_result)
2978 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2979 #undef FLOAT_FMA
2980
2981 /* MIPS specific binary operations */
2982 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2983 {
2984     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2985     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2986     update_fcr31(env, GETPC());
2987     return fdt2;
2988 }
2989
2990 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2991 {
2992     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2993     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2994     update_fcr31(env, GETPC());
2995     return fst2;
2996 }
2997
2998 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2999 {
3000     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3001     uint32_t fsth0 = fdt0 >> 32;
3002     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3003     uint32_t fsth2 = fdt2 >> 32;
3004
3005     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3006     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3007     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3008     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3009     update_fcr31(env, GETPC());
3010     return ((uint64_t)fsth2 << 32) | fst2;
3011 }
3012
3013 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3014 {
3015     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3016     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3017     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3018     update_fcr31(env, GETPC());
3019     return fdt2;
3020 }
3021
3022 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3023 {
3024     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3025     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3026     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3027     update_fcr31(env, GETPC());
3028     return fst2;
3029 }
3030
3031 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3032 {
3033     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3034     uint32_t fsth0 = fdt0 >> 32;
3035     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3036     uint32_t fsth2 = fdt2 >> 32;
3037
3038     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3039     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3040     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3041     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3042     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3043     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3044     update_fcr31(env, GETPC());
3045     return ((uint64_t)fsth2 << 32) | fst2;
3046 }
3047
3048 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3049 {
3050     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3051     uint32_t fsth0 = fdt0 >> 32;
3052     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3053     uint32_t fsth1 = fdt1 >> 32;
3054     uint32_t fst2;
3055     uint32_t fsth2;
3056
3057     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3058     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3059     update_fcr31(env, GETPC());
3060     return ((uint64_t)fsth2 << 32) | fst2;
3061 }
3062
3063 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3064 {
3065     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3066     uint32_t fsth0 = fdt0 >> 32;
3067     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3068     uint32_t fsth1 = fdt1 >> 32;
3069     uint32_t fst2;
3070     uint32_t fsth2;
3071
3072     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3073     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3074     update_fcr31(env, GETPC());
3075     return ((uint64_t)fsth2 << 32) | fst2;
3076 }
3077
3078 /* compare operations */
3079 #define FOP_COND_D(op, cond)                                   \
3080 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3081                          uint64_t fdt1, int cc)                \
3082 {                                                              \
3083     int c;                                                     \
3084     c = cond;                                                  \
3085     update_fcr31(env, GETPC());                                \
3086     if (c)                                                     \
3087         SET_FP_COND(cc, env->active_fpu);                      \
3088     else                                                       \
3089         CLEAR_FP_COND(cc, env->active_fpu);                    \
3090 }                                                              \
3091 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3092                             uint64_t fdt1, int cc)             \
3093 {                                                              \
3094     int c;                                                     \
3095     fdt0 = float64_abs(fdt0);                                  \
3096     fdt1 = float64_abs(fdt1);                                  \
3097     c = cond;                                                  \
3098     update_fcr31(env, GETPC());                                \
3099     if (c)                                                     \
3100         SET_FP_COND(cc, env->active_fpu);                      \
3101     else                                                       \
3102         CLEAR_FP_COND(cc, env->active_fpu);                    \
3103 }
3104
3105 /* NOTE: the comma operator will make "cond" to eval to false,
3106  * but float64_unordered_quiet() is still called. */
3107 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3108 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3109 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3110 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3111 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3112 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3113 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3114 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3115 /* NOTE: the comma operator will make "cond" to eval to false,
3116  * but float64_unordered() is still called. */
3117 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3118 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3119 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3120 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3121 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3122 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3123 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3124 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3125
3126 #define FOP_COND_S(op, cond)                                   \
3127 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3128                          uint32_t fst1, int cc)                \
3129 {                                                              \
3130     int c;                                                     \
3131     c = cond;                                                  \
3132     update_fcr31(env, GETPC());                                \
3133     if (c)                                                     \
3134         SET_FP_COND(cc, env->active_fpu);                      \
3135     else                                                       \
3136         CLEAR_FP_COND(cc, env->active_fpu);                    \
3137 }                                                              \
3138 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3139                             uint32_t fst1, int cc)             \
3140 {                                                              \
3141     int c;                                                     \
3142     fst0 = float32_abs(fst0);                                  \
3143     fst1 = float32_abs(fst1);                                  \
3144     c = cond;                                                  \
3145     update_fcr31(env, GETPC());                                \
3146     if (c)                                                     \
3147         SET_FP_COND(cc, env->active_fpu);                      \
3148     else                                                       \
3149         CLEAR_FP_COND(cc, env->active_fpu);                    \
3150 }
3151
3152 /* NOTE: the comma operator will make "cond" to eval to false,
3153  * but float32_unordered_quiet() is still called. */
3154 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3155 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3156 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3157 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3158 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3159 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3160 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3161 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3162 /* NOTE: the comma operator will make "cond" to eval to false,
3163  * but float32_unordered() is still called. */
3164 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3165 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3166 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3167 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3168 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3169 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3170 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3171 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3172
3173 #define FOP_COND_PS(op, condl, condh)                           \
3174 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3175                           uint64_t fdt1, int cc)                \
3176 {                                                               \
3177     uint32_t fst0, fsth0, fst1, fsth1;                          \
3178     int ch, cl;                                                 \
3179     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3180     fsth0 = fdt0 >> 32;                                         \
3181     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3182     fsth1 = fdt1 >> 32;                                         \
3183     cl = condl;                                                 \
3184     ch = condh;                                                 \
3185     update_fcr31(env, GETPC());                                 \
3186     if (cl)                                                     \
3187         SET_FP_COND(cc, env->active_fpu);                       \
3188     else                                                        \
3189         CLEAR_FP_COND(cc, env->active_fpu);                     \
3190     if (ch)                                                     \
3191         SET_FP_COND(cc + 1, env->active_fpu);                   \
3192     else                                                        \
3193         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3194 }                                                               \
3195 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3196                              uint64_t fdt1, int cc)             \
3197 {                                                               \
3198     uint32_t fst0, fsth0, fst1, fsth1;                          \
3199     int ch, cl;                                                 \
3200     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3201     fsth0 = float32_abs(fdt0 >> 32);                            \
3202     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3203     fsth1 = float32_abs(fdt1 >> 32);                            \
3204     cl = condl;                                                 \
3205     ch = condh;                                                 \
3206     update_fcr31(env, GETPC());                                 \
3207     if (cl)                                                     \
3208         SET_FP_COND(cc, env->active_fpu);                       \
3209     else                                                        \
3210         CLEAR_FP_COND(cc, env->active_fpu);                     \
3211     if (ch)                                                     \
3212         SET_FP_COND(cc + 1, env->active_fpu);                   \
3213     else                                                        \
3214         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3215 }
3216
3217 /* NOTE: the comma operator will make "cond" to eval to false,
3218  * but float32_unordered_quiet() is still called. */
3219 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3220                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3221 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3222                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3223 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3224                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3225 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3226                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3227 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3228                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3229 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3230                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3231 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3232                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3233 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3234                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3235 /* NOTE: the comma operator will make "cond" to eval to false,
3236  * but float32_unordered() is still called. */
3237 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3238                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3239 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3240                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3241 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3242                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3243 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3244                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3245 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3246                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3247 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3248                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3249 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3250                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3251 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3252                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))