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iotests/223: Create socket in $SOCK_DIR
[qemu/ar7.git] / hw / mips / gt64xxx_pci.c
blobf325bd6c1c9825d23f6c430b42b9b8f721d64830
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * Copyright (c) 2006,2007 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/log.h"
28 #include "hw/mips/mips.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_host.h"
31 #include "migration/vmstate.h"
32 #include "hw/i386/pc.h"
33 #include "hw/irq.h"
34 #include "exec/address-spaces.h"
35 #include "trace.h"
36
37 #define GT_REGS (0x1000 >> 2)
38
39 /* CPU Configuration */
40 #define GT_CPU (0x000 >> 2)
41 #define GT_MULTI (0x120 >> 2)
42
43 /* CPU Address Decode */
44 #define GT_SCS10LD (0x008 >> 2)
45 #define GT_SCS10HD (0x010 >> 2)
46 #define GT_SCS32LD (0x018 >> 2)
47 #define GT_SCS32HD (0x020 >> 2)
48 #define GT_CS20LD (0x028 >> 2)
49 #define GT_CS20HD (0x030 >> 2)
50 #define GT_CS3BOOTLD (0x038 >> 2)
51 #define GT_CS3BOOTHD (0x040 >> 2)
52 #define GT_PCI0IOLD (0x048 >> 2)
53 #define GT_PCI0IOHD (0x050 >> 2)
54 #define GT_PCI0M0LD (0x058 >> 2)
55 #define GT_PCI0M0HD (0x060 >> 2)
56 #define GT_PCI0M1LD (0x080 >> 2)
57 #define GT_PCI0M1HD (0x088 >> 2)
58 #define GT_PCI1IOLD (0x090 >> 2)
59 #define GT_PCI1IOHD (0x098 >> 2)
60 #define GT_PCI1M0LD (0x0a0 >> 2)
61 #define GT_PCI1M0HD (0x0a8 >> 2)
62 #define GT_PCI1M1LD (0x0b0 >> 2)
63 #define GT_PCI1M1HD (0x0b8 >> 2)
64 #define GT_ISD (0x068 >> 2)
65
66 #define GT_SCS10AR (0x0d0 >> 2)
67 #define GT_SCS32AR (0x0d8 >> 2)
68 #define GT_CS20R (0x0e0 >> 2)
69 #define GT_CS3BOOTR (0x0e8 >> 2)
70
71 #define GT_PCI0IOREMAP (0x0f0 >> 2)
72 #define GT_PCI0M0REMAP (0x0f8 >> 2)
73 #define GT_PCI0M1REMAP (0x100 >> 2)
74 #define GT_PCI1IOREMAP (0x108 >> 2)
75 #define GT_PCI1M0REMAP (0x110 >> 2)
76 #define GT_PCI1M1REMAP (0x118 >> 2)
77
78 /* CPU Error Report */
79 #define GT_CPUERR_ADDRLO (0x070 >> 2)
80 #define GT_CPUERR_ADDRHI (0x078 >> 2)
81 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
82 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
83 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
84
85 /* CPU Sync Barrier */
86 #define GT_PCI0SYNC (0x0c0 >> 2)
87 #define GT_PCI1SYNC (0x0c8 >> 2)
88
89 /* SDRAM and Device Address Decode */
90 #define GT_SCS0LD (0x400 >> 2)
91 #define GT_SCS0HD (0x404 >> 2)
92 #define GT_SCS1LD (0x408 >> 2)
93 #define GT_SCS1HD (0x40c >> 2)
94 #define GT_SCS2LD (0x410 >> 2)
95 #define GT_SCS2HD (0x414 >> 2)
96 #define GT_SCS3LD (0x418 >> 2)
97 #define GT_SCS3HD (0x41c >> 2)
98 #define GT_CS0LD (0x420 >> 2)
99 #define GT_CS0HD (0x424 >> 2)
100 #define GT_CS1LD (0x428 >> 2)
101 #define GT_CS1HD (0x42c >> 2)
102 #define GT_CS2LD (0x430 >> 2)
103 #define GT_CS2HD (0x434 >> 2)
104 #define GT_CS3LD (0x438 >> 2)
105 #define GT_CS3HD (0x43c >> 2)
106 #define GT_BOOTLD (0x440 >> 2)
107 #define GT_BOOTHD (0x444 >> 2)
108 #define GT_ADERR (0x470 >> 2)
109
110 /* SDRAM Configuration */
111 #define GT_SDRAM_CFG (0x448 >> 2)
112 #define GT_SDRAM_OPMODE (0x474 >> 2)
113 #define GT_SDRAM_BM (0x478 >> 2)
114 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
115
116 /* SDRAM Parameters */
117 #define GT_SDRAM_B0 (0x44c >> 2)
118 #define GT_SDRAM_B1 (0x450 >> 2)
119 #define GT_SDRAM_B2 (0x454 >> 2)
120 #define GT_SDRAM_B3 (0x458 >> 2)
121
122 /* Device Parameters */
123 #define GT_DEV_B0 (0x45c >> 2)
124 #define GT_DEV_B1 (0x460 >> 2)
125 #define GT_DEV_B2 (0x464 >> 2)
126 #define GT_DEV_B3 (0x468 >> 2)
127 #define GT_DEV_BOOT (0x46c >> 2)
128
129 /* ECC */
130 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
131 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
132 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
133 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
134 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
135
136 /* DMA Record */
137 #define GT_DMA0_CNT (0x800 >> 2)
138 #define GT_DMA1_CNT (0x804 >> 2)
139 #define GT_DMA2_CNT (0x808 >> 2)
140 #define GT_DMA3_CNT (0x80c >> 2)
141 #define GT_DMA0_SA (0x810 >> 2)
142 #define GT_DMA1_SA (0x814 >> 2)
143 #define GT_DMA2_SA (0x818 >> 2)
144 #define GT_DMA3_SA (0x81c >> 2)
145 #define GT_DMA0_DA (0x820 >> 2)
146 #define GT_DMA1_DA (0x824 >> 2)
147 #define GT_DMA2_DA (0x828 >> 2)
148 #define GT_DMA3_DA (0x82c >> 2)
149 #define GT_DMA0_NEXT (0x830 >> 2)
150 #define GT_DMA1_NEXT (0x834 >> 2)
151 #define GT_DMA2_NEXT (0x838 >> 2)
152 #define GT_DMA3_NEXT (0x83c >> 2)
153 #define GT_DMA0_CUR (0x870 >> 2)
154 #define GT_DMA1_CUR (0x874 >> 2)
155 #define GT_DMA2_CUR (0x878 >> 2)
156 #define GT_DMA3_CUR (0x87c >> 2)
157
158 /* DMA Channel Control */
159 #define GT_DMA0_CTRL (0x840 >> 2)
160 #define GT_DMA1_CTRL (0x844 >> 2)
161 #define GT_DMA2_CTRL (0x848 >> 2)
162 #define GT_DMA3_CTRL (0x84c >> 2)
163
164 /* DMA Arbiter */
165 #define GT_DMA_ARB (0x860 >> 2)
166
167 /* Timer/Counter */
168 #define GT_TC0 (0x850 >> 2)
169 #define GT_TC1 (0x854 >> 2)
170 #define GT_TC2 (0x858 >> 2)
171 #define GT_TC3 (0x85c >> 2)
172 #define GT_TC_CONTROL (0x864 >> 2)
173
174 /* PCI Internal */
175 #define GT_PCI0_CMD (0xc00 >> 2)
176 #define GT_PCI0_TOR (0xc04 >> 2)
177 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
178 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
179 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
180 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
181 #define GT_PCI1_IACK (0xc30 >> 2)
182 #define GT_PCI0_IACK (0xc34 >> 2)
183 #define GT_PCI0_BARE (0xc3c >> 2)
184 #define GT_PCI0_PREFMBR (0xc40 >> 2)
185 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
186 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
187 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
188 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
189 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
190 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
191 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
192 #define GT_PCI1_CMD (0xc80 >> 2)
193 #define GT_PCI1_TOR (0xc84 >> 2)
194 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
195 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
196 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
197 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
198 #define GT_PCI1_BARE (0xcbc >> 2)
199 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
200 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
201 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
202 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
203 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
204 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
205 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
206 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
207 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
208 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
209 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
210 #define GT_PCI0_CFGDATA (0xcfc >> 2)
211
212 /* Interrupts */
213 #define GT_INTRCAUSE (0xc18 >> 2)
214 #define GT_INTRMASK (0xc1c >> 2)
215 #define GT_PCI0_ICMASK (0xc24 >> 2)
216 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
217 #define GT_CPU_INTSEL (0xc70 >> 2)
218 #define GT_PCI0_INTSEL (0xc74 >> 2)
219 #define GT_HINTRCAUSE (0xc98 >> 2)
220 #define GT_HINTRMASK (0xc9c >> 2)
221 #define GT_PCI0_HICMASK (0xca4 >> 2)
222 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
223
224 #define PCI_MAPPING_ENTRY(regname) \
225 hwaddr regname ##_start; \
226 hwaddr regname ##_length; \
227 MemoryRegion regname ##_mem
228
229 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
230
231 #define GT64120_PCI_HOST_BRIDGE(obj) \
232 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
233
234 typedef struct GT64120State {
235 PCIHostState parent_obj;
236
237 uint32_t regs[GT_REGS];
238 PCI_MAPPING_ENTRY(PCI0IO);
239 PCI_MAPPING_ENTRY(PCI0M0);
240 PCI_MAPPING_ENTRY(PCI0M1);
241 PCI_MAPPING_ENTRY(ISD);
242 MemoryRegion pci0_mem;
243 AddressSpace pci0_mem_as;
244 } GT64120State;
245
246 /* Adjust range to avoid touching space which isn't mappable via PCI */
247 /*
248 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
249 * 0x1fc00000 - 0x1fd00000
250 */
251 static void check_reserved_space(hwaddr *start, hwaddr *length)
252 {
253 hwaddr begin = *start;
254 hwaddr end = *start + *length;
255
256 if (end >= 0x1e000000LL && end < 0x1f100000LL) {
257 end = 0x1e000000LL;
258 }
259 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
260 begin = 0x1f100000LL;
261 }
262 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
263 end = 0x1fc00000LL;
264 }
265 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
266 begin = 0x1fd00000LL;
267 }
268 /* XXX: This is broken when a reserved range splits the requested range */
269 if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
270 end = 0x1e000000LL;
271 }
272 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
273 end = 0x1fc00000LL;
274 }
275
276 *start = begin;
277 *length = end - begin;
278 }
279
280 static void gt64120_isd_mapping(GT64120State *s)
281 {
282 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
283 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
284 hwaddr length = 0x1000;
285
286 if (s->ISD_length) {
287 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
288 }
289 check_reserved_space(&start, &length);
290 length = 0x1000;
291 /* Map new address */
292 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
293 s->ISD_start = start;
294 s->ISD_length = length;
295 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
296 }
297
298 static void gt64120_pci_mapping(GT64120State *s)
299 {
300 /* Update PCI0IO mapping */
301 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
302 /* Unmap old IO address */
303 if (s->PCI0IO_length) {
304 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
305 object_unparent(OBJECT(&s->PCI0IO_mem));
306 }
307 /* Map new IO address */
308 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
309 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
310 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
311 if (s->PCI0IO_length) {
312 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
313 get_system_io(), 0, s->PCI0IO_length);
314 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
315 &s->PCI0IO_mem);
316 }
317 }
318
319 /* Update PCI0M0 mapping */
320 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
321 /* Unmap old MEM address */
322 if (s->PCI0M0_length) {
323 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
324 object_unparent(OBJECT(&s->PCI0M0_mem));
325 }
326 /* Map new mem address */
327 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
328 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
329 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
330 if (s->PCI0M0_length) {
331 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
332 &s->pci0_mem, s->PCI0M0_start,
333 s->PCI0M0_length);
334 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
335 &s->PCI0M0_mem);
336 }
337 }
338
339 /* Update PCI0M1 mapping */
340 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
341 /* Unmap old MEM address */
342 if (s->PCI0M1_length) {
343 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
344 object_unparent(OBJECT(&s->PCI0M1_mem));
345 }
346 /* Map new mem address */
347 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
348 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
349 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
350 if (s->PCI0M1_length) {
351 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
352 &s->pci0_mem, s->PCI0M1_start,
353 s->PCI0M1_length);
354 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
355 &s->PCI0M1_mem);
356 }
357 }
358 }
359
360 static int gt64120_post_load(void *opaque, int version_id)
361 {
362 GT64120State *s = opaque;
363
364 gt64120_isd_mapping(s);
365 gt64120_pci_mapping(s);
366
367 return 0;
368 }
369
370 static const VMStateDescription vmstate_gt64120 = {
371 .name = "gt64120",
372 .version_id = 1,
373 .minimum_version_id = 1,
374 .post_load = gt64120_post_load,
375 .fields = (VMStateField[]) {
376 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
377 VMSTATE_END_OF_LIST()
378 }
379 };
380
381 static void gt64120_writel(void *opaque, hwaddr addr,
382 uint64_t val, unsigned size)
383 {
384 GT64120State *s = opaque;
385 PCIHostState *phb = PCI_HOST_BRIDGE(s);
386 uint32_t saddr;
387
388 if (!(s->regs[GT_CPU] & 0x00001000)) {
389 val = bswap32(val);
390 }
391
392 saddr = (addr & 0xfff) >> 2;
393 switch (saddr) {
394
395 /* CPU Configuration */
396 case GT_CPU:
397 s->regs[GT_CPU] = val;
398 break;
399 case GT_MULTI:
400 /* Read-only register as only one GT64xxx is present on the CPU bus */
401 break;
402
403 /* CPU Address Decode */
404 case GT_PCI0IOLD:
405 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
406 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
407 gt64120_pci_mapping(s);
408 break;
409 case GT_PCI0M0LD:
410 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
411 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
412 gt64120_pci_mapping(s);
413 break;
414 case GT_PCI0M1LD:
415 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
416 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
417 gt64120_pci_mapping(s);
418 break;
419 case GT_PCI1IOLD:
420 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
421 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
422 break;
423 case GT_PCI1M0LD:
424 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
425 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
426 break;
427 case GT_PCI1M1LD:
428 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
429 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
430 break;
431 case GT_PCI0M0HD:
432 case GT_PCI0M1HD:
433 case GT_PCI0IOHD:
434 s->regs[saddr] = val & 0x0000007f;
435 gt64120_pci_mapping(s);
436 break;
437 case GT_PCI1IOHD:
438 case GT_PCI1M0HD:
439 case GT_PCI1M1HD:
440 s->regs[saddr] = val & 0x0000007f;
441 break;
442 case GT_ISD:
443 s->regs[saddr] = val & 0x00007fff;
444 gt64120_isd_mapping(s);
445 break;
446
447 case GT_PCI0IOREMAP:
448 case GT_PCI0M0REMAP:
449 case GT_PCI0M1REMAP:
450 case GT_PCI1IOREMAP:
451 case GT_PCI1M0REMAP:
452 case GT_PCI1M1REMAP:
453 s->regs[saddr] = val & 0x000007ff;
454 break;
455
456 /* CPU Error Report */
457 case GT_CPUERR_ADDRLO:
458 case GT_CPUERR_ADDRHI:
459 case GT_CPUERR_DATALO:
460 case GT_CPUERR_DATAHI:
461 case GT_CPUERR_PARITY:
462 /* Read-only registers, do nothing */
463 qemu_log_mask(LOG_GUEST_ERROR,
464 "gt64120: Read-only register write "
465 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
466 saddr << 2, size, size << 1, val);
467 break;
468
469 /* CPU Sync Barrier */
470 case GT_PCI0SYNC:
471 case GT_PCI1SYNC:
472 /* Read-only registers, do nothing */
473 qemu_log_mask(LOG_GUEST_ERROR,
474 "gt64120: Read-only register write "
475 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
476 saddr << 2, size, size << 1, val);
477 break;
478
479 /* SDRAM and Device Address Decode */
480 case GT_SCS0LD:
481 case GT_SCS0HD:
482 case GT_SCS1LD:
483 case GT_SCS1HD:
484 case GT_SCS2LD:
485 case GT_SCS2HD:
486 case GT_SCS3LD:
487 case GT_SCS3HD:
488 case GT_CS0LD:
489 case GT_CS0HD:
490 case GT_CS1LD:
491 case GT_CS1HD:
492 case GT_CS2LD:
493 case GT_CS2HD:
494 case GT_CS3LD:
495 case GT_CS3HD:
496 case GT_BOOTLD:
497 case GT_BOOTHD:
498 case GT_ADERR:
499 /* SDRAM Configuration */
500 case GT_SDRAM_CFG:
501 case GT_SDRAM_OPMODE:
502 case GT_SDRAM_BM:
503 case GT_SDRAM_ADDRDECODE:
504 /* Accept and ignore SDRAM interleave configuration */
505 s->regs[saddr] = val;
506 break;
507
508 /* Device Parameters */
509 case GT_DEV_B0:
510 case GT_DEV_B1:
511 case GT_DEV_B2:
512 case GT_DEV_B3:
513 case GT_DEV_BOOT:
514 /* Not implemented */
515 qemu_log_mask(LOG_UNIMP,
516 "gt64120: Unimplemented device register write "
517 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
518 saddr << 2, size, size << 1, val);
519 break;
520
521 /* ECC */
522 case GT_ECC_ERRDATALO:
523 case GT_ECC_ERRDATAHI:
524 case GT_ECC_MEM:
525 case GT_ECC_CALC:
526 case GT_ECC_ERRADDR:
527 /* Read-only registers, do nothing */
528 qemu_log_mask(LOG_GUEST_ERROR,
529 "gt64120: Read-only register write "
530 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
531 saddr << 2, size, size << 1, val);
532 break;
533
534 /* DMA Record */
535 case GT_DMA0_CNT:
536 case GT_DMA1_CNT:
537 case GT_DMA2_CNT:
538 case GT_DMA3_CNT:
539 case GT_DMA0_SA:
540 case GT_DMA1_SA:
541 case GT_DMA2_SA:
542 case GT_DMA3_SA:
543 case GT_DMA0_DA:
544 case GT_DMA1_DA:
545 case GT_DMA2_DA:
546 case GT_DMA3_DA:
547 case GT_DMA0_NEXT:
548 case GT_DMA1_NEXT:
549 case GT_DMA2_NEXT:
550 case GT_DMA3_NEXT:
551 case GT_DMA0_CUR:
552 case GT_DMA1_CUR:
553 case GT_DMA2_CUR:
554 case GT_DMA3_CUR:
555
556 /* DMA Channel Control */
557 case GT_DMA0_CTRL:
558 case GT_DMA1_CTRL:
559 case GT_DMA2_CTRL:
560 case GT_DMA3_CTRL:
561
562 /* DMA Arbiter */
563 case GT_DMA_ARB:
564 /* Not implemented */
565 qemu_log_mask(LOG_UNIMP,
566 "gt64120: Unimplemented DMA register write "
567 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
568 saddr << 2, size, size << 1, val);
569 break;
570
571 /* Timer/Counter */
572 case GT_TC0:
573 case GT_TC1:
574 case GT_TC2:
575 case GT_TC3:
576 case GT_TC_CONTROL:
577 /* Not implemented */
578 qemu_log_mask(LOG_UNIMP,
579 "gt64120: Unimplemented timer register write "
580 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
581 saddr << 2, size, size << 1, val);
582 break;
583
584 /* PCI Internal */
585 case GT_PCI0_CMD:
586 case GT_PCI1_CMD:
587 s->regs[saddr] = val & 0x0401fc0f;
588 break;
589 case GT_PCI0_TOR:
590 case GT_PCI0_BS_SCS10:
591 case GT_PCI0_BS_SCS32:
592 case GT_PCI0_BS_CS20:
593 case GT_PCI0_BS_CS3BT:
594 case GT_PCI1_IACK:
595 case GT_PCI0_IACK:
596 case GT_PCI0_BARE:
597 case GT_PCI0_PREFMBR:
598 case GT_PCI0_SCS10_BAR:
599 case GT_PCI0_SCS32_BAR:
600 case GT_PCI0_CS20_BAR:
601 case GT_PCI0_CS3BT_BAR:
602 case GT_PCI0_SSCS10_BAR:
603 case GT_PCI0_SSCS32_BAR:
604 case GT_PCI0_SCS3BT_BAR:
605 case GT_PCI1_TOR:
606 case GT_PCI1_BS_SCS10:
607 case GT_PCI1_BS_SCS32:
608 case GT_PCI1_BS_CS20:
609 case GT_PCI1_BS_CS3BT:
610 case GT_PCI1_BARE:
611 case GT_PCI1_PREFMBR:
612 case GT_PCI1_SCS10_BAR:
613 case GT_PCI1_SCS32_BAR:
614 case GT_PCI1_CS20_BAR:
615 case GT_PCI1_CS3BT_BAR:
616 case GT_PCI1_SSCS10_BAR:
617 case GT_PCI1_SSCS32_BAR:
618 case GT_PCI1_SCS3BT_BAR:
619 case GT_PCI1_CFGADDR:
620 case GT_PCI1_CFGDATA:
621 /* not implemented */
622 qemu_log_mask(LOG_UNIMP,
623 "gt64120: Unimplemented timer register write "
624 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
625 saddr << 2, size, size << 1, val);
626 break;
627 case GT_PCI0_CFGADDR:
628 phb->config_reg = val & 0x80fffffc;
629 break;
630 case GT_PCI0_CFGDATA:
631 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
632 val = bswap32(val);
633 }
634 if (phb->config_reg & (1u << 31)) {
635 pci_data_write(phb->bus, phb->config_reg, val, 4);
636 }
637 break;
638
639 /* Interrupts */
640 case GT_INTRCAUSE:
641 /* not really implemented */
642 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
643 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
644 trace_gt64120_write("INTRCAUSE", size << 1, val);
645 break;
646 case GT_INTRMASK:
647 s->regs[saddr] = val & 0x3c3ffffe;
648 trace_gt64120_write("INTRMASK", size << 1, val);
649 break;
650 case GT_PCI0_ICMASK:
651 s->regs[saddr] = val & 0x03fffffe;
652 trace_gt64120_write("ICMASK", size << 1, val);
653 break;
654 case GT_PCI0_SERR0MASK:
655 s->regs[saddr] = val & 0x0000003f;
656 trace_gt64120_write("SERR0MASK", size << 1, val);
657 break;
658
659 /* Reserved when only PCI_0 is configured. */
660 case GT_HINTRCAUSE:
661 case GT_CPU_INTSEL:
662 case GT_PCI0_INTSEL:
663 case GT_HINTRMASK:
664 case GT_PCI0_HICMASK:
665 case GT_PCI1_SERR1MASK:
666 /* not implemented */
667 break;
668
669 /* SDRAM Parameters */
670 case GT_SDRAM_B0:
671 case GT_SDRAM_B1:
672 case GT_SDRAM_B2:
673 case GT_SDRAM_B3:
674 /*
675 * We don't simulate electrical parameters of the SDRAM.
676 * Accept, but ignore the values.
677 */
678 s->regs[saddr] = val;
679 break;
680
681 default:
682 qemu_log_mask(LOG_GUEST_ERROR,
683 "gt64120: Illegal register write "
684 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
685 saddr << 2, size, size << 1, val);
686 break;
687 }
688 }
689
690 static uint64_t gt64120_readl(void *opaque,
691 hwaddr addr, unsigned size)
692 {
693 GT64120State *s = opaque;
694 PCIHostState *phb = PCI_HOST_BRIDGE(s);
695 uint32_t val;
696 uint32_t saddr;
697
698 saddr = (addr & 0xfff) >> 2;
699 switch (saddr) {
700
701 /* CPU Configuration */
702 case GT_MULTI:
703 /*
704 * Only one GT64xxx is present on the CPU bus, return
705 * the initial value.
706 */
707 val = s->regs[saddr];
708 break;
709
710 /* CPU Error Report */
711 case GT_CPUERR_ADDRLO:
712 case GT_CPUERR_ADDRHI:
713 case GT_CPUERR_DATALO:
714 case GT_CPUERR_DATAHI:
715 case GT_CPUERR_PARITY:
716 /* Emulated memory has no error, always return the initial values. */
717 val = s->regs[saddr];
718 break;
719
720 /* CPU Sync Barrier */
721 case GT_PCI0SYNC:
722 case GT_PCI1SYNC:
723 /*
724 * Reading those register should empty all FIFO on the PCI
725 * bus, which are not emulated. The return value should be
726 * a random value that should be ignored.
727 */
728 val = 0xc000ffee;
729 break;
730
731 /* ECC */
732 case GT_ECC_ERRDATALO:
733 case GT_ECC_ERRDATAHI:
734 case GT_ECC_MEM:
735 case GT_ECC_CALC:
736 case GT_ECC_ERRADDR:
737 /* Emulated memory has no error, always return the initial values. */
738 val = s->regs[saddr];
739 break;
740
741 case GT_CPU:
742 case GT_SCS10LD:
743 case GT_SCS10HD:
744 case GT_SCS32LD:
745 case GT_SCS32HD:
746 case GT_CS20LD:
747 case GT_CS20HD:
748 case GT_CS3BOOTLD:
749 case GT_CS3BOOTHD:
750 case GT_SCS10AR:
751 case GT_SCS32AR:
752 case GT_CS20R:
753 case GT_CS3BOOTR:
754 case GT_PCI0IOLD:
755 case GT_PCI0M0LD:
756 case GT_PCI0M1LD:
757 case GT_PCI1IOLD:
758 case GT_PCI1M0LD:
759 case GT_PCI1M1LD:
760 case GT_PCI0IOHD:
761 case GT_PCI0M0HD:
762 case GT_PCI0M1HD:
763 case GT_PCI1IOHD:
764 case GT_PCI1M0HD:
765 case GT_PCI1M1HD:
766 case GT_PCI0IOREMAP:
767 case GT_PCI0M0REMAP:
768 case GT_PCI0M1REMAP:
769 case GT_PCI1IOREMAP:
770 case GT_PCI1M0REMAP:
771 case GT_PCI1M1REMAP:
772 case GT_ISD:
773 val = s->regs[saddr];
774 break;
775 case GT_PCI0_IACK:
776 /* Read the IRQ number */
777 val = pic_read_irq(isa_pic);
778 break;
779
780 /* SDRAM and Device Address Decode */
781 case GT_SCS0LD:
782 case GT_SCS0HD:
783 case GT_SCS1LD:
784 case GT_SCS1HD:
785 case GT_SCS2LD:
786 case GT_SCS2HD:
787 case GT_SCS3LD:
788 case GT_SCS3HD:
789 case GT_CS0LD:
790 case GT_CS0HD:
791 case GT_CS1LD:
792 case GT_CS1HD:
793 case GT_CS2LD:
794 case GT_CS2HD:
795 case GT_CS3LD:
796 case GT_CS3HD:
797 case GT_BOOTLD:
798 case GT_BOOTHD:
799 case GT_ADERR:
800 val = s->regs[saddr];
801 break;
802
803 /* SDRAM Configuration */
804 case GT_SDRAM_CFG:
805 case GT_SDRAM_OPMODE:
806 case GT_SDRAM_BM:
807 case GT_SDRAM_ADDRDECODE:
808 val = s->regs[saddr];
809 break;
810
811 /* SDRAM Parameters */
812 case GT_SDRAM_B0:
813 case GT_SDRAM_B1:
814 case GT_SDRAM_B2:
815 case GT_SDRAM_B3:
816 /*
817 * We don't simulate electrical parameters of the SDRAM.
818 * Just return the last written value.
819 */
820 val = s->regs[saddr];
821 break;
822
823 /* Device Parameters */
824 case GT_DEV_B0:
825 case GT_DEV_B1:
826 case GT_DEV_B2:
827 case GT_DEV_B3:
828 case GT_DEV_BOOT:
829 val = s->regs[saddr];
830 break;
831
832 /* DMA Record */
833 case GT_DMA0_CNT:
834 case GT_DMA1_CNT:
835 case GT_DMA2_CNT:
836 case GT_DMA3_CNT:
837 case GT_DMA0_SA:
838 case GT_DMA1_SA:
839 case GT_DMA2_SA:
840 case GT_DMA3_SA:
841 case GT_DMA0_DA:
842 case GT_DMA1_DA:
843 case GT_DMA2_DA:
844 case GT_DMA3_DA:
845 case GT_DMA0_NEXT:
846 case GT_DMA1_NEXT:
847 case GT_DMA2_NEXT:
848 case GT_DMA3_NEXT:
849 case GT_DMA0_CUR:
850 case GT_DMA1_CUR:
851 case GT_DMA2_CUR:
852 case GT_DMA3_CUR:
853 val = s->regs[saddr];
854 break;
855
856 /* DMA Channel Control */
857 case GT_DMA0_CTRL:
858 case GT_DMA1_CTRL:
859 case GT_DMA2_CTRL:
860 case GT_DMA3_CTRL:
861 val = s->regs[saddr];
862 break;
863
864 /* DMA Arbiter */
865 case GT_DMA_ARB:
866 val = s->regs[saddr];
867 break;
868
869 /* Timer/Counter */
870 case GT_TC0:
871 case GT_TC1:
872 case GT_TC2:
873 case GT_TC3:
874 case GT_TC_CONTROL:
875 val = s->regs[saddr];
876 break;
877
878 /* PCI Internal */
879 case GT_PCI0_CFGADDR:
880 val = phb->config_reg;
881 break;
882 case GT_PCI0_CFGDATA:
883 if (!(phb->config_reg & (1 << 31))) {
884 val = 0xffffffff;
885 } else {
886 val = pci_data_read(phb->bus, phb->config_reg, 4);
887 }
888 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
889 val = bswap32(val);
890 }
891 break;
892
893 case GT_PCI0_CMD:
894 case GT_PCI0_TOR:
895 case GT_PCI0_BS_SCS10:
896 case GT_PCI0_BS_SCS32:
897 case GT_PCI0_BS_CS20:
898 case GT_PCI0_BS_CS3BT:
899 case GT_PCI1_IACK:
900 case GT_PCI0_BARE:
901 case GT_PCI0_PREFMBR:
902 case GT_PCI0_SCS10_BAR:
903 case GT_PCI0_SCS32_BAR:
904 case GT_PCI0_CS20_BAR:
905 case GT_PCI0_CS3BT_BAR:
906 case GT_PCI0_SSCS10_BAR:
907 case GT_PCI0_SSCS32_BAR:
908 case GT_PCI0_SCS3BT_BAR:
909 case GT_PCI1_CMD:
910 case GT_PCI1_TOR:
911 case GT_PCI1_BS_SCS10:
912 case GT_PCI1_BS_SCS32:
913 case GT_PCI1_BS_CS20:
914 case GT_PCI1_BS_CS3BT:
915 case GT_PCI1_BARE:
916 case GT_PCI1_PREFMBR:
917 case GT_PCI1_SCS10_BAR:
918 case GT_PCI1_SCS32_BAR:
919 case GT_PCI1_CS20_BAR:
920 case GT_PCI1_CS3BT_BAR:
921 case GT_PCI1_SSCS10_BAR:
922 case GT_PCI1_SSCS32_BAR:
923 case GT_PCI1_SCS3BT_BAR:
924 case GT_PCI1_CFGADDR:
925 case GT_PCI1_CFGDATA:
926 val = s->regs[saddr];
927 break;
928
929 /* Interrupts */
930 case GT_INTRCAUSE:
931 val = s->regs[saddr];
932 trace_gt64120_read("INTRCAUSE", size << 1, val);
933 break;
934 case GT_INTRMASK:
935 val = s->regs[saddr];
936 trace_gt64120_read("INTRMASK", size << 1, val);
937 break;
938 case GT_PCI0_ICMASK:
939 val = s->regs[saddr];
940 trace_gt64120_read("ICMASK", size << 1, val);
941 break;
942 case GT_PCI0_SERR0MASK:
943 val = s->regs[saddr];
944 trace_gt64120_read("SERR0MASK", size << 1, val);
945 break;
946
947 /* Reserved when only PCI_0 is configured. */
948 case GT_HINTRCAUSE:
949 case GT_CPU_INTSEL:
950 case GT_PCI0_INTSEL:
951 case GT_HINTRMASK:
952 case GT_PCI0_HICMASK:
953 case GT_PCI1_SERR1MASK:
954 val = s->regs[saddr];
955 break;
956
957 default:
958 val = s->regs[saddr];
959 qemu_log_mask(LOG_GUEST_ERROR,
960 "gt64120: Illegal register read "
961 "reg:0x03%x size:%u value:0x%0*x\n",
962 saddr << 2, size, size << 1, val);
963 break;
964 }
965
966 if (!(s->regs[GT_CPU] & 0x00001000)) {
967 val = bswap32(val);
968 }
969
970 return val;
971 }
972
973 static const MemoryRegionOps isd_mem_ops = {
974 .read = gt64120_readl,
975 .write = gt64120_writel,
976 .endianness = DEVICE_NATIVE_ENDIAN,
977 };
978
979 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
980 {
981 int slot;
982
983 slot = (pci_dev->devfn >> 3);
984
985 switch (slot) {
986 /* PIIX4 USB */
987 case 10:
988 return 3;
989 /* AMD 79C973 Ethernet */
990 case 11:
991 return 1;
992 /* Crystal 4281 Sound */
993 case 12:
994 return 2;
995 /* PCI slot 1 to 4 */
996 case 18 ... 21:
997 return ((slot - 18) + irq_num) & 0x03;
998 /* Unknown device, don't do any translation */
999 default:
1000 return irq_num;
1001 }
1002 }
1003
1004 static int pci_irq_levels[4];
1005
1006 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
1007 {
1008 int i, pic_irq, pic_level;
1009 qemu_irq *pic = opaque;
1010
1011 pci_irq_levels[irq_num] = level;
1012
1013 /* now we change the pic irq level according to the piix irq mappings */
1014 /* XXX: optimize */
1015 pic_irq = piix4_dev->config[0x60 + irq_num];
1016 if (pic_irq < 16) {
1017 /* The pic level is the logical OR of all the PCI irqs mapped to it. */
1018 pic_level = 0;
1019 for (i = 0; i < 4; i++) {
1020 if (pic_irq == piix4_dev->config[0x60 + i]) {
1021 pic_level |= pci_irq_levels[i];
1022 }
1023 }
1024 qemu_set_irq(pic[pic_irq], pic_level);
1025 }
1026 }
1027
1028
1029 static void gt64120_reset(DeviceState *dev)
1030 {
1031 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1032
1033 /* FIXME: Malta specific hw assumptions ahead */
1034
1035 /* CPU Configuration */
1036 #ifdef TARGET_WORDS_BIGENDIAN
1037 s->regs[GT_CPU] = 0x00000000;
1038 #else
1039 s->regs[GT_CPU] = 0x00001000;
1040 #endif
1041 s->regs[GT_MULTI] = 0x00000003;
1042
1043 /* CPU Address decode */
1044 s->regs[GT_SCS10LD] = 0x00000000;
1045 s->regs[GT_SCS10HD] = 0x00000007;
1046 s->regs[GT_SCS32LD] = 0x00000008;
1047 s->regs[GT_SCS32HD] = 0x0000000f;
1048 s->regs[GT_CS20LD] = 0x000000e0;
1049 s->regs[GT_CS20HD] = 0x00000070;
1050 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1051 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1052
1053 s->regs[GT_PCI0IOLD] = 0x00000080;
1054 s->regs[GT_PCI0IOHD] = 0x0000000f;
1055 s->regs[GT_PCI0M0LD] = 0x00000090;
1056 s->regs[GT_PCI0M0HD] = 0x0000001f;
1057 s->regs[GT_ISD] = 0x000000a0;
1058 s->regs[GT_PCI0M1LD] = 0x00000790;
1059 s->regs[GT_PCI0M1HD] = 0x0000001f;
1060 s->regs[GT_PCI1IOLD] = 0x00000100;
1061 s->regs[GT_PCI1IOHD] = 0x0000000f;
1062 s->regs[GT_PCI1M0LD] = 0x00000110;
1063 s->regs[GT_PCI1M0HD] = 0x0000001f;
1064 s->regs[GT_PCI1M1LD] = 0x00000120;
1065 s->regs[GT_PCI1M1HD] = 0x0000002f;
1066
1067 s->regs[GT_SCS10AR] = 0x00000000;
1068 s->regs[GT_SCS32AR] = 0x00000008;
1069 s->regs[GT_CS20R] = 0x000000e0;
1070 s->regs[GT_CS3BOOTR] = 0x000000f8;
1071
1072 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1073 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1074 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1075 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1076 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1077 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1078
1079 /* CPU Error Report */
1080 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1081 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1082 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1083 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1084 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1085
1086 /* CPU Sync Barrier */
1087 s->regs[GT_PCI0SYNC] = 0x00000000;
1088 s->regs[GT_PCI1SYNC] = 0x00000000;
1089
1090 /* SDRAM and Device Address Decode */
1091 s->regs[GT_SCS0LD] = 0x00000000;
1092 s->regs[GT_SCS0HD] = 0x00000007;
1093 s->regs[GT_SCS1LD] = 0x00000008;
1094 s->regs[GT_SCS1HD] = 0x0000000f;
1095 s->regs[GT_SCS2LD] = 0x00000010;
1096 s->regs[GT_SCS2HD] = 0x00000017;
1097 s->regs[GT_SCS3LD] = 0x00000018;
1098 s->regs[GT_SCS3HD] = 0x0000001f;
1099 s->regs[GT_CS0LD] = 0x000000c0;
1100 s->regs[GT_CS0HD] = 0x000000c7;
1101 s->regs[GT_CS1LD] = 0x000000c8;
1102 s->regs[GT_CS1HD] = 0x000000cf;
1103 s->regs[GT_CS2LD] = 0x000000d0;
1104 s->regs[GT_CS2HD] = 0x000000df;
1105 s->regs[GT_CS3LD] = 0x000000f0;
1106 s->regs[GT_CS3HD] = 0x000000fb;
1107 s->regs[GT_BOOTLD] = 0x000000fc;
1108 s->regs[GT_BOOTHD] = 0x000000ff;
1109 s->regs[GT_ADERR] = 0xffffffff;
1110
1111 /* SDRAM Configuration */
1112 s->regs[GT_SDRAM_CFG] = 0x00000200;
1113 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1114 s->regs[GT_SDRAM_BM] = 0x00000007;
1115 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1116
1117 /* SDRAM Parameters */
1118 s->regs[GT_SDRAM_B0] = 0x00000005;
1119 s->regs[GT_SDRAM_B1] = 0x00000005;
1120 s->regs[GT_SDRAM_B2] = 0x00000005;
1121 s->regs[GT_SDRAM_B3] = 0x00000005;
1122
1123 /* ECC */
1124 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1125 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1126 s->regs[GT_ECC_MEM] = 0x00000000;
1127 s->regs[GT_ECC_CALC] = 0x00000000;
1128 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1129
1130 /* Device Parameters */
1131 s->regs[GT_DEV_B0] = 0x386fffff;
1132 s->regs[GT_DEV_B1] = 0x386fffff;
1133 s->regs[GT_DEV_B2] = 0x386fffff;
1134 s->regs[GT_DEV_B3] = 0x386fffff;
1135 s->regs[GT_DEV_BOOT] = 0x146fffff;
1136
1137 /* DMA registers are all zeroed at reset */
1138
1139 /* Timer/Counter */
1140 s->regs[GT_TC0] = 0xffffffff;
1141 s->regs[GT_TC1] = 0x00ffffff;
1142 s->regs[GT_TC2] = 0x00ffffff;
1143 s->regs[GT_TC3] = 0x00ffffff;
1144 s->regs[GT_TC_CONTROL] = 0x00000000;
1145
1146 /* PCI Internal */
1147 #ifdef TARGET_WORDS_BIGENDIAN
1148 s->regs[GT_PCI0_CMD] = 0x00000000;
1149 #else
1150 s->regs[GT_PCI0_CMD] = 0x00010001;
1151 #endif
1152 s->regs[GT_PCI0_TOR] = 0x0000070f;
1153 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1154 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1155 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1156 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1157 s->regs[GT_PCI1_IACK] = 0x00000000;
1158 s->regs[GT_PCI0_IACK] = 0x00000000;
1159 s->regs[GT_PCI0_BARE] = 0x0000000f;
1160 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1161 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1162 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1163 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1164 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1165 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1166 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1167 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1168 #ifdef TARGET_WORDS_BIGENDIAN
1169 s->regs[GT_PCI1_CMD] = 0x00000000;
1170 #else
1171 s->regs[GT_PCI1_CMD] = 0x00010001;
1172 #endif
1173 s->regs[GT_PCI1_TOR] = 0x0000070f;
1174 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1175 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1176 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1177 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1178 s->regs[GT_PCI1_BARE] = 0x0000000f;
1179 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1180 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1181 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1182 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1183 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1184 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1185 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1186 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1187 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1188 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1189 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1190
1191 /* Interrupt registers are all zeroed at reset */
1192
1193 gt64120_isd_mapping(s);
1194 gt64120_pci_mapping(s);
1195 }
1196
1197 PCIBus *gt64120_register(qemu_irq *pic)
1198 {
1199 GT64120State *d;
1200 PCIHostState *phb;
1201 DeviceState *dev;
1202
1203 dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1204 d = GT64120_PCI_HOST_BRIDGE(dev);
1205 phb = PCI_HOST_BRIDGE(dev);
1206 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1207 address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1208 phb->bus = pci_register_root_bus(dev, "pci",
1209 gt64120_pci_set_irq, gt64120_pci_map_irq,
1210 pic,
1211 &d->pci0_mem,
1212 get_system_io(),
1213 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1214 qdev_init_nofail(dev);
1215 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
1216 "isd-mem", 0x1000);
1217
1218 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1219 return phb->bus;
1220 }
1221
1222 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1223 {
1224 /* FIXME: Malta specific hw assumptions ahead */
1225 pci_set_word(d->config + PCI_COMMAND, 0);
1226 pci_set_word(d->config + PCI_STATUS,
1227 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1228 pci_config_set_prog_interface(d->config, 0);
1229 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1230 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1231 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1232 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1233 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1234 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1235 pci_set_byte(d->config + 0x3d, 0x01);
1236 }
1237
1238 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1239 {
1240 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1241 DeviceClass *dc = DEVICE_CLASS(klass);
1242
1243 k->realize = gt64120_pci_realize;
1244 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1245 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1246 k->revision = 0x10;
1247 k->class_id = PCI_CLASS_BRIDGE_HOST;
1248 /*
1249 * PCI-facing part of the host bridge, not usable without the
1250 * host-facing part, which can't be device_add'ed, yet.
1251 */
1252 dc->user_creatable = false;
1253 }
1254
1255 static const TypeInfo gt64120_pci_info = {
1256 .name = "gt64120_pci",
1257 .parent = TYPE_PCI_DEVICE,
1258 .instance_size = sizeof(PCIDevice),
1259 .class_init = gt64120_pci_class_init,
1260 .interfaces = (InterfaceInfo[]) {
1261 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1262 { },
1263 },
1264 };
1265
1266 static void gt64120_class_init(ObjectClass *klass, void *data)
1267 {
1268 DeviceClass *dc = DEVICE_CLASS(klass);
1269
1270 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1271 dc->reset = gt64120_reset;
1272 dc->vmsd = &vmstate_gt64120;
1273 }
1274
1275 static const TypeInfo gt64120_info = {
1276 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1277 .parent = TYPE_PCI_HOST_BRIDGE,
1278 .instance_size = sizeof(GT64120State),
1279 .class_init = gt64120_class_init,
1280 };
1281
1282 static void gt64120_pci_register_types(void)
1283 {
1284 type_register_static(&gt64120_info);
1285 type_register_static(&gt64120_pci_info);
1286 }
1287
1288 type_init(gt64120_pci_register_types)
AR7 emulation for QEMU