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target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
[qemu/ar7.git] / target / mips / fpu_helper.c
blobbdb65065ee7b3b96f70f89f4b66615f8fda1fc2e
1 /*
2 * Helpers for emulation of FPU-related MIPS instructions.
3 *
4 * Copyright (C) 2004-2005 Jocelyn Mayer
5 * Copyright (C) 2020 Wave Computing, Inc.
6 * Copyright (C) 2020 Aleksandar Markovic <amarkovic@wavecomp.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23 #include "qemu/osdep.h"
24 #include "cpu.h"
25 #include "internal.h"
26 #include "exec/helper-proto.h"
27 #include "exec/exec-all.h"
28 #include "exec/cpu_ldst.h"
29 #include "fpu/softfloat.h"
30
31
32 /* Complex FPU operations which may need stack space. */
33
34 #define FLOAT_TWO32 make_float32(1 << 30)
35 #define FLOAT_TWO64 make_float64(1ULL << 62)
36
37 #define FP_TO_INT32_OVERFLOW 0x7fffffff
38 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
39
40 /* convert MIPS rounding mode in FCR31 to IEEE library */
41 const FloatRoundMode ieee_rm[4] = {
42 float_round_nearest_even,
43 float_round_to_zero,
44 float_round_up,
45 float_round_down
46 };
47
48 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
49 {
50 target_ulong arg1 = 0;
51
52 switch (reg) {
53 case 0:
54 arg1 = (int32_t)env->active_fpu.fcr0;
55 break;
56 case 1:
57 /* UFR Support - Read Status FR */
58 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
59 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
60 arg1 = (int32_t)
61 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
62 } else {
63 do_raise_exception(env, EXCP_RI, GETPC());
64 }
65 }
66 break;
67 case 5:
68 /* FRE Support - read Config5.FRE bit */
69 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
70 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
71 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
72 } else {
73 helper_raise_exception(env, EXCP_RI);
74 }
75 }
76 break;
77 case 25:
78 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) |
79 ((env->active_fpu.fcr31 >> 23) & 0x1);
80 break;
81 case 26:
82 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
83 break;
84 case 28:
85 arg1 = (env->active_fpu.fcr31 & 0x00000f83) |
86 ((env->active_fpu.fcr31 >> 22) & 0x4);
87 break;
88 default:
89 arg1 = (int32_t)env->active_fpu.fcr31;
90 break;
91 }
92
93 return arg1;
94 }
95
96 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
97 {
98 switch (fs) {
99 case 1:
100 /* UFR Alias - Reset Status FR */
101 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
102 return;
103 }
104 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
105 env->CP0_Status &= ~(1 << CP0St_FR);
106 compute_hflags(env);
107 } else {
108 do_raise_exception(env, EXCP_RI, GETPC());
109 }
110 break;
111 case 4:
112 /* UNFR Alias - Set Status FR */
113 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
114 return;
115 }
116 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
117 env->CP0_Status |= (1 << CP0St_FR);
118 compute_hflags(env);
119 } else {
120 do_raise_exception(env, EXCP_RI, GETPC());
121 }
122 break;
123 case 5:
124 /* FRE Support - clear Config5.FRE bit */
125 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
126 return;
127 }
128 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
129 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
130 compute_hflags(env);
131 } else {
132 helper_raise_exception(env, EXCP_RI);
133 }
134 break;
135 case 6:
136 /* FRE Support - set Config5.FRE bit */
137 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
138 return;
139 }
140 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
141 env->CP0_Config5 |= (1 << CP0C5_FRE);
142 compute_hflags(env);
143 } else {
144 helper_raise_exception(env, EXCP_RI);
145 }
146 break;
147 case 25:
148 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
149 return;
150 }
151 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
152 ((arg1 & 0xfe) << 24) |
153 ((arg1 & 0x1) << 23);
154 break;
155 case 26:
156 if (arg1 & 0x007c0000) {
157 return;
158 }
159 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) |
160 (arg1 & 0x0003f07c);
161 break;
162 case 28:
163 if (arg1 & 0x007c0000) {
164 return;
165 }
166 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) |
167 (arg1 & 0x00000f83) |
168 ((arg1 & 0x4) << 22);
169 break;
170 case 31:
171 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
172 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
173 break;
174 default:
175 if (env->insn_flags & ISA_MIPS32R6) {
176 do_raise_exception(env, EXCP_RI, GETPC());
177 }
178 return;
179 }
180 restore_fp_status(env);
181 set_float_exception_flags(0, &env->active_fpu.fp_status);
182 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
183 GET_FP_CAUSE(env->active_fpu.fcr31)) {
184 do_raise_exception(env, EXCP_FPE, GETPC());
185 }
186 }
187
188 static inline int ieee_to_mips_xcpt(int ieee_xcpt)
189 {
190 int mips_xcpt = 0;
191
192 if (ieee_xcpt & float_flag_invalid) {
193 mips_xcpt |= FP_INVALID;
194 }
195 if (ieee_xcpt & float_flag_overflow) {
196 mips_xcpt |= FP_OVERFLOW;
197 }
198 if (ieee_xcpt & float_flag_underflow) {
199 mips_xcpt |= FP_UNDERFLOW;
200 }
201 if (ieee_xcpt & float_flag_divbyzero) {
202 mips_xcpt |= FP_DIV0;
203 }
204 if (ieee_xcpt & float_flag_inexact) {
205 mips_xcpt |= FP_INEXACT;
206 }
207
208 return mips_xcpt;
209 }
210
211 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
212 {
213 int ieee_exception_flags = get_float_exception_flags(
214 &env->active_fpu.fp_status);
215 int mips_exception_flags = 0;
216
217 if (ieee_exception_flags) {
218 mips_exception_flags = ieee_to_mips_xcpt(ieee_exception_flags);
219 }
220
221 SET_FP_CAUSE(env->active_fpu.fcr31, mips_exception_flags);
222
223 if (mips_exception_flags) {
224 set_float_exception_flags(0, &env->active_fpu.fp_status);
225
226 if (GET_FP_ENABLE(env->active_fpu.fcr31) & mips_exception_flags) {
227 do_raise_exception(env, EXCP_FPE, pc);
228 } else {
229 UPDATE_FP_FLAGS(env->active_fpu.fcr31, mips_exception_flags);
230 }
231 }
232 }
233
234 /*
235 * Float support.
236 * Single precition routines have a "s" suffix, double precision a
237 * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
238 * paired single lower "pl", paired single upper "pu".
239 */
240
241 /* unary operations, modifying fp status */
242 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
243 {
244 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
245 update_fcr31(env, GETPC());
246 return fdt0;
247 }
248
249 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
250 {
251 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
252 update_fcr31(env, GETPC());
253 return fst0;
254 }
255
256 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
257 {
258 uint64_t fdt2;
259
260 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
261 update_fcr31(env, GETPC());
262 return fdt2;
263 }
264
265 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
266 {
267 uint64_t fdt2;
268
269 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
270 update_fcr31(env, GETPC());
271 return fdt2;
272 }
273
274 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
275 {
276 uint64_t fdt2;
277
278 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
279 update_fcr31(env, GETPC());
280 return fdt2;
281 }
282
283 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
284 {
285 uint64_t dt2;
286
287 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
288 if (get_float_exception_flags(&env->active_fpu.fp_status)
289 & (float_flag_invalid | float_flag_overflow)) {
290 dt2 = FP_TO_INT64_OVERFLOW;
291 }
292 update_fcr31(env, GETPC());
293 return dt2;
294 }
295
296 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
297 {
298 uint64_t dt2;
299
300 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
301 if (get_float_exception_flags(&env->active_fpu.fp_status)
302 & (float_flag_invalid | float_flag_overflow)) {
303 dt2 = FP_TO_INT64_OVERFLOW;
304 }
305 update_fcr31(env, GETPC());
306 return dt2;
307 }
308
309 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
310 {
311 uint32_t fst2;
312 uint32_t fsth2;
313
314 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
315 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
316 update_fcr31(env, GETPC());
317 return ((uint64_t)fsth2 << 32) | fst2;
318 }
319
320 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
321 {
322 uint32_t wt2;
323 uint32_t wth2;
324 int excp, excph;
325
326 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
327 excp = get_float_exception_flags(&env->active_fpu.fp_status);
328 if (excp & (float_flag_overflow | float_flag_invalid)) {
329 wt2 = FP_TO_INT32_OVERFLOW;
330 }
331
332 set_float_exception_flags(0, &env->active_fpu.fp_status);
333 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
334 excph = get_float_exception_flags(&env->active_fpu.fp_status);
335 if (excph & (float_flag_overflow | float_flag_invalid)) {
336 wth2 = FP_TO_INT32_OVERFLOW;
337 }
338
339 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
340 update_fcr31(env, GETPC());
341
342 return ((uint64_t)wth2 << 32) | wt2;
343 }
344
345 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
346 {
347 uint32_t fst2;
348
349 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
350 update_fcr31(env, GETPC());
351 return fst2;
352 }
353
354 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
355 {
356 uint32_t fst2;
357
358 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
359 update_fcr31(env, GETPC());
360 return fst2;
361 }
362
363 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
364 {
365 uint32_t fst2;
366
367 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
368 update_fcr31(env, GETPC());
369 return fst2;
370 }
371
372 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
373 {
374 uint32_t wt2;
375
376 wt2 = wt0;
377 update_fcr31(env, GETPC());
378 return wt2;
379 }
380
381 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
382 {
383 uint32_t wt2;
384
385 wt2 = wth0;
386 update_fcr31(env, GETPC());
387 return wt2;
388 }
389
390 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
391 {
392 uint32_t wt2;
393
394 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
395 if (get_float_exception_flags(&env->active_fpu.fp_status)
396 & (float_flag_invalid | float_flag_overflow)) {
397 wt2 = FP_TO_INT32_OVERFLOW;
398 }
399 update_fcr31(env, GETPC());
400 return wt2;
401 }
402
403 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
404 {
405 uint32_t wt2;
406
407 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
408 if (get_float_exception_flags(&env->active_fpu.fp_status)
409 & (float_flag_invalid | float_flag_overflow)) {
410 wt2 = FP_TO_INT32_OVERFLOW;
411 }
412 update_fcr31(env, GETPC());
413 return wt2;
414 }
415
416 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
417 {
418 uint64_t dt2;
419
420 set_float_rounding_mode(float_round_nearest_even,
421 &env->active_fpu.fp_status);
422 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
423 restore_rounding_mode(env);
424 if (get_float_exception_flags(&env->active_fpu.fp_status)
425 & (float_flag_invalid | float_flag_overflow)) {
426 dt2 = FP_TO_INT64_OVERFLOW;
427 }
428 update_fcr31(env, GETPC());
429 return dt2;
430 }
431
432 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
433 {
434 uint64_t dt2;
435
436 set_float_rounding_mode(float_round_nearest_even,
437 &env->active_fpu.fp_status);
438 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
439 restore_rounding_mode(env);
440 if (get_float_exception_flags(&env->active_fpu.fp_status)
441 & (float_flag_invalid | float_flag_overflow)) {
442 dt2 = FP_TO_INT64_OVERFLOW;
443 }
444 update_fcr31(env, GETPC());
445 return dt2;
446 }
447
448 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
449 {
450 uint32_t wt2;
451
452 set_float_rounding_mode(float_round_nearest_even,
453 &env->active_fpu.fp_status);
454 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
455 restore_rounding_mode(env);
456 if (get_float_exception_flags(&env->active_fpu.fp_status)
457 & (float_flag_invalid | float_flag_overflow)) {
458 wt2 = FP_TO_INT32_OVERFLOW;
459 }
460 update_fcr31(env, GETPC());
461 return wt2;
462 }
463
464 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
465 {
466 uint32_t wt2;
467
468 set_float_rounding_mode(float_round_nearest_even,
469 &env->active_fpu.fp_status);
470 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
471 restore_rounding_mode(env);
472 if (get_float_exception_flags(&env->active_fpu.fp_status)
473 & (float_flag_invalid | float_flag_overflow)) {
474 wt2 = FP_TO_INT32_OVERFLOW;
475 }
476 update_fcr31(env, GETPC());
477 return wt2;
478 }
479
480 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
481 {
482 uint64_t dt2;
483
484 dt2 = float64_to_int64_round_to_zero(fdt0,
485 &env->active_fpu.fp_status);
486 if (get_float_exception_flags(&env->active_fpu.fp_status)
487 & (float_flag_invalid | float_flag_overflow)) {
488 dt2 = FP_TO_INT64_OVERFLOW;
489 }
490 update_fcr31(env, GETPC());
491 return dt2;
492 }
493
494 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
495 {
496 uint64_t dt2;
497
498 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
499 if (get_float_exception_flags(&env->active_fpu.fp_status)
500 & (float_flag_invalid | float_flag_overflow)) {
501 dt2 = FP_TO_INT64_OVERFLOW;
502 }
503 update_fcr31(env, GETPC());
504 return dt2;
505 }
506
507 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
508 {
509 uint32_t wt2;
510
511 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
512 if (get_float_exception_flags(&env->active_fpu.fp_status)
513 & (float_flag_invalid | float_flag_overflow)) {
514 wt2 = FP_TO_INT32_OVERFLOW;
515 }
516 update_fcr31(env, GETPC());
517 return wt2;
518 }
519
520 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
521 {
522 uint32_t wt2;
523
524 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
525 if (get_float_exception_flags(&env->active_fpu.fp_status)
526 & (float_flag_invalid | float_flag_overflow)) {
527 wt2 = FP_TO_INT32_OVERFLOW;
528 }
529 update_fcr31(env, GETPC());
530 return wt2;
531 }
532
533 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
534 {
535 uint64_t dt2;
536
537 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
538 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
539 restore_rounding_mode(env);
540 if (get_float_exception_flags(&env->active_fpu.fp_status)
541 & (float_flag_invalid | float_flag_overflow)) {
542 dt2 = FP_TO_INT64_OVERFLOW;
543 }
544 update_fcr31(env, GETPC());
545 return dt2;
546 }
547
548 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
549 {
550 uint64_t dt2;
551
552 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
553 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
554 restore_rounding_mode(env);
555 if (get_float_exception_flags(&env->active_fpu.fp_status)
556 & (float_flag_invalid | float_flag_overflow)) {
557 dt2 = FP_TO_INT64_OVERFLOW;
558 }
559 update_fcr31(env, GETPC());
560 return dt2;
561 }
562
563 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
564 {
565 uint32_t wt2;
566
567 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
568 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
569 restore_rounding_mode(env);
570 if (get_float_exception_flags(&env->active_fpu.fp_status)
571 & (float_flag_invalid | float_flag_overflow)) {
572 wt2 = FP_TO_INT32_OVERFLOW;
573 }
574 update_fcr31(env, GETPC());
575 return wt2;
576 }
577
578 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
579 {
580 uint32_t wt2;
581
582 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
583 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
584 restore_rounding_mode(env);
585 if (get_float_exception_flags(&env->active_fpu.fp_status)
586 & (float_flag_invalid | float_flag_overflow)) {
587 wt2 = FP_TO_INT32_OVERFLOW;
588 }
589 update_fcr31(env, GETPC());
590 return wt2;
591 }
592
593 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
594 {
595 uint64_t dt2;
596
597 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
598 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
599 restore_rounding_mode(env);
600 if (get_float_exception_flags(&env->active_fpu.fp_status)
601 & (float_flag_invalid | float_flag_overflow)) {
602 dt2 = FP_TO_INT64_OVERFLOW;
603 }
604 update_fcr31(env, GETPC());
605 return dt2;
606 }
607
608 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
609 {
610 uint64_t dt2;
611
612 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
613 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
614 restore_rounding_mode(env);
615 if (get_float_exception_flags(&env->active_fpu.fp_status)
616 & (float_flag_invalid | float_flag_overflow)) {
617 dt2 = FP_TO_INT64_OVERFLOW;
618 }
619 update_fcr31(env, GETPC());
620 return dt2;
621 }
622
623 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
624 {
625 uint32_t wt2;
626
627 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
628 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
629 restore_rounding_mode(env);
630 if (get_float_exception_flags(&env->active_fpu.fp_status)
631 & (float_flag_invalid | float_flag_overflow)) {
632 wt2 = FP_TO_INT32_OVERFLOW;
633 }
634 update_fcr31(env, GETPC());
635 return wt2;
636 }
637
638 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
639 {
640 uint32_t wt2;
641
642 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
643 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
644 restore_rounding_mode(env);
645 if (get_float_exception_flags(&env->active_fpu.fp_status)
646 & (float_flag_invalid | float_flag_overflow)) {
647 wt2 = FP_TO_INT32_OVERFLOW;
648 }
649 update_fcr31(env, GETPC());
650 return wt2;
651 }
652
653 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
654 {
655 uint64_t dt2;
656
657 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
658 if (get_float_exception_flags(&env->active_fpu.fp_status)
659 & float_flag_invalid) {
660 if (float64_is_any_nan(fdt0)) {
661 dt2 = 0;
662 }
663 }
664 update_fcr31(env, GETPC());
665 return dt2;
666 }
667
668 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
669 {
670 uint64_t dt2;
671
672 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
673 if (get_float_exception_flags(&env->active_fpu.fp_status)
674 & float_flag_invalid) {
675 if (float32_is_any_nan(fst0)) {
676 dt2 = 0;
677 }
678 }
679 update_fcr31(env, GETPC());
680 return dt2;
681 }
682
683 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
684 {
685 uint32_t wt2;
686
687 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
688 if (get_float_exception_flags(&env->active_fpu.fp_status)
689 & float_flag_invalid) {
690 if (float64_is_any_nan(fdt0)) {
691 wt2 = 0;
692 }
693 }
694 update_fcr31(env, GETPC());
695 return wt2;
696 }
697
698 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
699 {
700 uint32_t wt2;
701
702 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
703 if (get_float_exception_flags(&env->active_fpu.fp_status)
704 & float_flag_invalid) {
705 if (float32_is_any_nan(fst0)) {
706 wt2 = 0;
707 }
708 }
709 update_fcr31(env, GETPC());
710 return wt2;
711 }
712
713 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
714 {
715 uint64_t dt2;
716
717 set_float_rounding_mode(float_round_nearest_even,
718 &env->active_fpu.fp_status);
719 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
720 restore_rounding_mode(env);
721 if (get_float_exception_flags(&env->active_fpu.fp_status)
722 & float_flag_invalid) {
723 if (float64_is_any_nan(fdt0)) {
724 dt2 = 0;
725 }
726 }
727 update_fcr31(env, GETPC());
728 return dt2;
729 }
730
731 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
732 {
733 uint64_t dt2;
734
735 set_float_rounding_mode(float_round_nearest_even,
736 &env->active_fpu.fp_status);
737 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
738 restore_rounding_mode(env);
739 if (get_float_exception_flags(&env->active_fpu.fp_status)
740 & float_flag_invalid) {
741 if (float32_is_any_nan(fst0)) {
742 dt2 = 0;
743 }
744 }
745 update_fcr31(env, GETPC());
746 return dt2;
747 }
748
749 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
750 {
751 uint32_t wt2;
752
753 set_float_rounding_mode(float_round_nearest_even,
754 &env->active_fpu.fp_status);
755 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
756 restore_rounding_mode(env);
757 if (get_float_exception_flags(&env->active_fpu.fp_status)
758 & float_flag_invalid) {
759 if (float64_is_any_nan(fdt0)) {
760 wt2 = 0;
761 }
762 }
763 update_fcr31(env, GETPC());
764 return wt2;
765 }
766
767 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
768 {
769 uint32_t wt2;
770
771 set_float_rounding_mode(float_round_nearest_even,
772 &env->active_fpu.fp_status);
773 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
774 restore_rounding_mode(env);
775 if (get_float_exception_flags(&env->active_fpu.fp_status)
776 & float_flag_invalid) {
777 if (float32_is_any_nan(fst0)) {
778 wt2 = 0;
779 }
780 }
781 update_fcr31(env, GETPC());
782 return wt2;
783 }
784
785 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
786 {
787 uint64_t dt2;
788
789 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
790 if (get_float_exception_flags(&env->active_fpu.fp_status)
791 & float_flag_invalid) {
792 if (float64_is_any_nan(fdt0)) {
793 dt2 = 0;
794 }
795 }
796 update_fcr31(env, GETPC());
797 return dt2;
798 }
799
800 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
801 {
802 uint64_t dt2;
803
804 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
805 if (get_float_exception_flags(&env->active_fpu.fp_status)
806 & float_flag_invalid) {
807 if (float32_is_any_nan(fst0)) {
808 dt2 = 0;
809 }
810 }
811 update_fcr31(env, GETPC());
812 return dt2;
813 }
814
815 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
816 {
817 uint32_t wt2;
818
819 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
820 if (get_float_exception_flags(&env->active_fpu.fp_status)
821 & float_flag_invalid) {
822 if (float64_is_any_nan(fdt0)) {
823 wt2 = 0;
824 }
825 }
826 update_fcr31(env, GETPC());
827 return wt2;
828 }
829
830 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
831 {
832 uint32_t wt2;
833
834 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
835 if (get_float_exception_flags(&env->active_fpu.fp_status)
836 & float_flag_invalid) {
837 if (float32_is_any_nan(fst0)) {
838 wt2 = 0;
839 }
840 }
841 update_fcr31(env, GETPC());
842 return wt2;
843 }
844
845 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
846 {
847 uint64_t dt2;
848
849 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
850 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
851 restore_rounding_mode(env);
852 if (get_float_exception_flags(&env->active_fpu.fp_status)
853 & float_flag_invalid) {
854 if (float64_is_any_nan(fdt0)) {
855 dt2 = 0;
856 }
857 }
858 update_fcr31(env, GETPC());
859 return dt2;
860 }
861
862 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
863 {
864 uint64_t dt2;
865
866 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
867 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
868 restore_rounding_mode(env);
869 if (get_float_exception_flags(&env->active_fpu.fp_status)
870 & float_flag_invalid) {
871 if (float32_is_any_nan(fst0)) {
872 dt2 = 0;
873 }
874 }
875 update_fcr31(env, GETPC());
876 return dt2;
877 }
878
879 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
880 {
881 uint32_t wt2;
882
883 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
884 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
885 restore_rounding_mode(env);
886 if (get_float_exception_flags(&env->active_fpu.fp_status)
887 & float_flag_invalid) {
888 if (float64_is_any_nan(fdt0)) {
889 wt2 = 0;
890 }
891 }
892 update_fcr31(env, GETPC());
893 return wt2;
894 }
895
896 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
897 {
898 uint32_t wt2;
899
900 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
901 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
902 restore_rounding_mode(env);
903 if (get_float_exception_flags(&env->active_fpu.fp_status)
904 & float_flag_invalid) {
905 if (float32_is_any_nan(fst0)) {
906 wt2 = 0;
907 }
908 }
909 update_fcr31(env, GETPC());
910 return wt2;
911 }
912
913 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
914 {
915 uint64_t dt2;
916
917 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
918 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
919 restore_rounding_mode(env);
920 if (get_float_exception_flags(&env->active_fpu.fp_status)
921 & float_flag_invalid) {
922 if (float64_is_any_nan(fdt0)) {
923 dt2 = 0;
924 }
925 }
926 update_fcr31(env, GETPC());
927 return dt2;
928 }
929
930 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
931 {
932 uint64_t dt2;
933
934 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
935 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
936 restore_rounding_mode(env);
937 if (get_float_exception_flags(&env->active_fpu.fp_status)
938 & float_flag_invalid) {
939 if (float32_is_any_nan(fst0)) {
940 dt2 = 0;
941 }
942 }
943 update_fcr31(env, GETPC());
944 return dt2;
945 }
946
947 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
948 {
949 uint32_t wt2;
950
951 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
952 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
953 restore_rounding_mode(env);
954 if (get_float_exception_flags(&env->active_fpu.fp_status)
955 & float_flag_invalid) {
956 if (float64_is_any_nan(fdt0)) {
957 wt2 = 0;
958 }
959 }
960 update_fcr31(env, GETPC());
961 return wt2;
962 }
963
964 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
965 {
966 uint32_t wt2;
967
968 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
969 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
970 restore_rounding_mode(env);
971 if (get_float_exception_flags(&env->active_fpu.fp_status)
972 & float_flag_invalid) {
973 if (float32_is_any_nan(fst0)) {
974 wt2 = 0;
975 }
976 }
977 update_fcr31(env, GETPC());
978 return wt2;
979 }
980
981 /* unary operations, not modifying fp status */
982
983 uint64_t helper_float_abs_d(uint64_t fdt0)
984 {
985 return float64_abs(fdt0);
986 }
987
988 uint32_t helper_float_abs_s(uint32_t fst0)
989 {
990 return float32_abs(fst0);
991 }
992
993 uint64_t helper_float_abs_ps(uint64_t fdt0)
994 {
995 uint32_t wt0;
996 uint32_t wth0;
997
998 wt0 = float32_abs(fdt0 & 0XFFFFFFFF);
999 wth0 = float32_abs(fdt0 >> 32);
1000 return ((uint64_t)wth0 << 32) | wt0;
1001 }
1002
1003 uint64_t helper_float_chs_d(uint64_t fdt0)
1004 {
1005 return float64_chs(fdt0);
1006 }
1007
1008 uint32_t helper_float_chs_s(uint32_t fst0)
1009 {
1010 return float32_chs(fst0);
1011 }
1012
1013 uint64_t helper_float_chs_ps(uint64_t fdt0)
1014 {
1015 uint32_t wt0;
1016 uint32_t wth0;
1017
1018 wt0 = float32_chs(fdt0 & 0XFFFFFFFF);
1019 wth0 = float32_chs(fdt0 >> 32);
1020 return ((uint64_t)wth0 << 32) | wt0;
1021 }
1022
1023 /* MIPS specific unary operations */
1024 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
1025 {
1026 uint64_t fdt2;
1027
1028 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
1029 update_fcr31(env, GETPC());
1030 return fdt2;
1031 }
1032
1033 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
1034 {
1035 uint32_t fst2;
1036
1037 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
1038 update_fcr31(env, GETPC());
1039 return fst2;
1040 }
1041
1042 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
1043 {
1044 uint64_t fdt2;
1045
1046 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
1047 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
1048 update_fcr31(env, GETPC());
1049 return fdt2;
1050 }
1051
1052 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
1053 {
1054 uint32_t fst2;
1055
1056 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
1057 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1058 update_fcr31(env, GETPC());
1059 return fst2;
1060 }
1061
1062 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
1063 {
1064 uint64_t fdt2;
1065
1066 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
1067 update_fcr31(env, GETPC());
1068 return fdt2;
1069 }
1070
1071 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
1072 {
1073 uint32_t fst2;
1074
1075 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
1076 update_fcr31(env, GETPC());
1077 return fst2;
1078 }
1079
1080 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
1081 {
1082 uint32_t fstl2;
1083 uint32_t fsth2;
1084
1085 fstl2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
1086 &env->active_fpu.fp_status);
1087 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
1088 update_fcr31(env, GETPC());
1089 return ((uint64_t)fsth2 << 32) | fstl2;
1090 }
1091
1092 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
1093 {
1094 uint64_t fdt2;
1095
1096 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
1097 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
1098 update_fcr31(env, GETPC());
1099 return fdt2;
1100 }
1101
1102 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
1103 {
1104 uint32_t fst2;
1105
1106 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
1107 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1108 update_fcr31(env, GETPC());
1109 return fst2;
1110 }
1111
1112 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
1113 {
1114 uint32_t fstl2;
1115 uint32_t fsth2;
1116
1117 fstl2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
1118 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
1119 fstl2 = float32_div(float32_one, fstl2, &env->active_fpu.fp_status);
1120 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
1121 update_fcr31(env, GETPC());
1122 return ((uint64_t)fsth2 << 32) | fstl2;
1123 }
1124
1125 uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
1126 {
1127 uint64_t fdret;
1128
1129 fdret = float64_round_to_int(fs, &env->active_fpu.fp_status);
1130 update_fcr31(env, GETPC());
1131 return fdret;
1132 }
1133
1134 uint32_t helper_float_rint_s(CPUMIPSState *env, uint32_t fs)
1135 {
1136 uint32_t fdret;
1137
1138 fdret = float32_round_to_int(fs, &env->active_fpu.fp_status);
1139 update_fcr31(env, GETPC());
1140 return fdret;
1141 }
1142
1143 #define FLOAT_CLASS_SIGNALING_NAN 0x001
1144 #define FLOAT_CLASS_QUIET_NAN 0x002
1145 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
1146 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
1147 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
1148 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
1149 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
1150 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
1151 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
1152 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
1153
1154 uint64_t float_class_d(uint64_t arg, float_status *status)
1155 {
1156 if (float64_is_signaling_nan(arg, status)) {
1157 return FLOAT_CLASS_SIGNALING_NAN;
1158 } else if (float64_is_quiet_nan(arg, status)) {
1159 return FLOAT_CLASS_QUIET_NAN;
1160 } else if (float64_is_neg(arg)) {
1161 if (float64_is_infinity(arg)) {
1162 return FLOAT_CLASS_NEGATIVE_INFINITY;
1163 } else if (float64_is_zero(arg)) {
1164 return FLOAT_CLASS_NEGATIVE_ZERO;
1165 } else if (float64_is_zero_or_denormal(arg)) {
1166 return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
1167 } else {
1168 return FLOAT_CLASS_NEGATIVE_NORMAL;
1169 }
1170 } else {
1171 if (float64_is_infinity(arg)) {
1172 return FLOAT_CLASS_POSITIVE_INFINITY;
1173 } else if (float64_is_zero(arg)) {
1174 return FLOAT_CLASS_POSITIVE_ZERO;
1175 } else if (float64_is_zero_or_denormal(arg)) {
1176 return FLOAT_CLASS_POSITIVE_SUBNORMAL;
1177 } else {
1178 return FLOAT_CLASS_POSITIVE_NORMAL;
1179 }
1180 }
1181 }
1182
1183 uint64_t helper_float_class_d(CPUMIPSState *env, uint64_t arg)
1184 {
1185 return float_class_d(arg, &env->active_fpu.fp_status);
1186 }
1187
1188 uint32_t float_class_s(uint32_t arg, float_status *status)
1189 {
1190 if (float32_is_signaling_nan(arg, status)) {
1191 return FLOAT_CLASS_SIGNALING_NAN;
1192 } else if (float32_is_quiet_nan(arg, status)) {
1193 return FLOAT_CLASS_QUIET_NAN;
1194 } else if (float32_is_neg(arg)) {
1195 if (float32_is_infinity(arg)) {
1196 return FLOAT_CLASS_NEGATIVE_INFINITY;
1197 } else if (float32_is_zero(arg)) {
1198 return FLOAT_CLASS_NEGATIVE_ZERO;
1199 } else if (float32_is_zero_or_denormal(arg)) {
1200 return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
1201 } else {
1202 return FLOAT_CLASS_NEGATIVE_NORMAL;
1203 }
1204 } else {
1205 if (float32_is_infinity(arg)) {
1206 return FLOAT_CLASS_POSITIVE_INFINITY;
1207 } else if (float32_is_zero(arg)) {
1208 return FLOAT_CLASS_POSITIVE_ZERO;
1209 } else if (float32_is_zero_or_denormal(arg)) {
1210 return FLOAT_CLASS_POSITIVE_SUBNORMAL;
1211 } else {
1212 return FLOAT_CLASS_POSITIVE_NORMAL;
1213 }
1214 }
1215 }
1216
1217 uint32_t helper_float_class_s(CPUMIPSState *env, uint32_t arg)
1218 {
1219 return float_class_s(arg, &env->active_fpu.fp_status);
1220 }
1221
1222 /* binary operations */
1223
1224 uint64_t helper_float_add_d(CPUMIPSState *env,
1225 uint64_t fdt0, uint64_t fdt1)
1226 {
1227 uint64_t dt2;
1228
1229 dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status);
1230 update_fcr31(env, GETPC());
1231 return dt2;
1232 }
1233
1234 uint32_t helper_float_add_s(CPUMIPSState *env,
1235 uint32_t fst0, uint32_t fst1)
1236 {
1237 uint32_t wt2;
1238
1239 wt2 = float32_add(fst0, fst1, &env->active_fpu.fp_status);
1240 update_fcr31(env, GETPC());
1241 return wt2;
1242 }
1243
1244 uint64_t helper_float_add_ps(CPUMIPSState *env,
1245 uint64_t fdt0, uint64_t fdt1)
1246 {
1247 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1248 uint32_t fsth0 = fdt0 >> 32;
1249 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1250 uint32_t fsth1 = fdt1 >> 32;
1251 uint32_t wtl2;
1252 uint32_t wth2;
1253
1254 wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status);
1255 wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status);
1256 update_fcr31(env, GETPC());
1257 return ((uint64_t)wth2 << 32) | wtl2;
1258 }
1259
1260 uint64_t helper_float_sub_d(CPUMIPSState *env,
1261 uint64_t fdt0, uint64_t fdt1)
1262 {
1263 uint64_t dt2;
1264
1265 dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status);
1266 update_fcr31(env, GETPC());
1267 return dt2;
1268 }
1269
1270 uint32_t helper_float_sub_s(CPUMIPSState *env,
1271 uint32_t fst0, uint32_t fst1)
1272 {
1273 uint32_t wt2;
1274
1275 wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
1276 update_fcr31(env, GETPC());
1277 return wt2;
1278 }
1279
1280 uint64_t helper_float_sub_ps(CPUMIPSState *env,
1281 uint64_t fdt0, uint64_t fdt1)
1282 {
1283 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1284 uint32_t fsth0 = fdt0 >> 32;
1285 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1286 uint32_t fsth1 = fdt1 >> 32;
1287 uint32_t wtl2;
1288 uint32_t wth2;
1289
1290 wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status);
1291 wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status);
1292 update_fcr31(env, GETPC());
1293 return ((uint64_t)wth2 << 32) | wtl2;
1294 }
1295
1296 uint64_t helper_float_mul_d(CPUMIPSState *env,
1297 uint64_t fdt0, uint64_t fdt1)
1298 {
1299 uint64_t dt2;
1300
1301 dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status);
1302 update_fcr31(env, GETPC());
1303 return dt2;
1304 }
1305
1306 uint32_t helper_float_mul_s(CPUMIPSState *env,
1307 uint32_t fst0, uint32_t fst1)
1308 {
1309 uint32_t wt2;
1310
1311 wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1312 update_fcr31(env, GETPC());
1313 return wt2;
1314 }
1315
1316 uint64_t helper_float_mul_ps(CPUMIPSState *env,
1317 uint64_t fdt0, uint64_t fdt1)
1318 {
1319 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1320 uint32_t fsth0 = fdt0 >> 32;
1321 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1322 uint32_t fsth1 = fdt1 >> 32;
1323 uint32_t wtl2;
1324 uint32_t wth2;
1325
1326 wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1327 wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1328 update_fcr31(env, GETPC());
1329 return ((uint64_t)wth2 << 32) | wtl2;
1330 }
1331
1332 uint64_t helper_float_div_d(CPUMIPSState *env,
1333 uint64_t fdt0, uint64_t fdt1)
1334 {
1335 uint64_t dt2;
1336
1337 dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status);
1338 update_fcr31(env, GETPC());
1339 return dt2;
1340 }
1341
1342 uint32_t helper_float_div_s(CPUMIPSState *env,
1343 uint32_t fst0, uint32_t fst1)
1344 {
1345 uint32_t wt2;
1346
1347 wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status);
1348 update_fcr31(env, GETPC());
1349 return wt2;
1350 }
1351
1352 uint64_t helper_float_div_ps(CPUMIPSState *env,
1353 uint64_t fdt0, uint64_t fdt1)
1354 {
1355 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1356 uint32_t fsth0 = fdt0 >> 32;
1357 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1358 uint32_t fsth1 = fdt1 >> 32;
1359 uint32_t wtl2;
1360 uint32_t wth2;
1361
1362 wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status);
1363 wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status);
1364 update_fcr31(env, GETPC());
1365 return ((uint64_t)wth2 << 32) | wtl2;
1366 }
1367
1368
1369 /* MIPS specific binary operations */
1370 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1371 {
1372 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
1373 fdt2 = float64_chs(float64_sub(fdt2, float64_one,
1374 &env->active_fpu.fp_status));
1375 update_fcr31(env, GETPC());
1376 return fdt2;
1377 }
1378
1379 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
1380 {
1381 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1382 fst2 = float32_chs(float32_sub(fst2, float32_one,
1383 &env->active_fpu.fp_status));
1384 update_fcr31(env, GETPC());
1385 return fst2;
1386 }
1387
1388 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1389 {
1390 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1391 uint32_t fsth0 = fdt0 >> 32;
1392 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1393 uint32_t fsth2 = fdt2 >> 32;
1394
1395 fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
1396 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
1397 fstl2 = float32_chs(float32_sub(fstl2, float32_one,
1398 &env->active_fpu.fp_status));
1399 fsth2 = float32_chs(float32_sub(fsth2, float32_one,
1400 &env->active_fpu.fp_status));
1401 update_fcr31(env, GETPC());
1402 return ((uint64_t)fsth2 << 32) | fstl2;
1403 }
1404
1405 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1406 {
1407 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
1408 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
1409 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64,
1410 &env->active_fpu.fp_status));
1411 update_fcr31(env, GETPC());
1412 return fdt2;
1413 }
1414
1415 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
1416 {
1417 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1418 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
1419 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
1420 &env->active_fpu.fp_status));
1421 update_fcr31(env, GETPC());
1422 return fst2;
1423 }
1424
1425 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1426 {
1427 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1428 uint32_t fsth0 = fdt0 >> 32;
1429 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1430 uint32_t fsth2 = fdt2 >> 32;
1431
1432 fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
1433 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
1434 fstl2 = float32_sub(fstl2, float32_one, &env->active_fpu.fp_status);
1435 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
1436 fstl2 = float32_chs(float32_div(fstl2, FLOAT_TWO32,
1437 &env->active_fpu.fp_status));
1438 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
1439 &env->active_fpu.fp_status));
1440 update_fcr31(env, GETPC());
1441 return ((uint64_t)fsth2 << 32) | fstl2;
1442 }
1443
1444 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
1445 {
1446 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1447 uint32_t fsth0 = fdt0 >> 32;
1448 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1449 uint32_t fsth1 = fdt1 >> 32;
1450 uint32_t fstl2;
1451 uint32_t fsth2;
1452
1453 fstl2 = float32_add(fstl0, fsth0, &env->active_fpu.fp_status);
1454 fsth2 = float32_add(fstl1, fsth1, &env->active_fpu.fp_status);
1455 update_fcr31(env, GETPC());
1456 return ((uint64_t)fsth2 << 32) | fstl2;
1457 }
1458
1459 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
1460 {
1461 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1462 uint32_t fsth0 = fdt0 >> 32;
1463 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1464 uint32_t fsth1 = fdt1 >> 32;
1465 uint32_t fstl2;
1466 uint32_t fsth2;
1467
1468 fstl2 = float32_mul(fstl0, fsth0, &env->active_fpu.fp_status);
1469 fsth2 = float32_mul(fstl1, fsth1, &env->active_fpu.fp_status);
1470 update_fcr31(env, GETPC());
1471 return ((uint64_t)fsth2 << 32) | fstl2;
1472 }
1473
1474
1475 uint32_t helper_float_max_s(CPUMIPSState *env, uint32_t fs, uint32_t ft)
1476 {
1477 uint32_t fdret;
1478
1479 fdret = float32_maxnum(fs, ft, &env->active_fpu.fp_status);
1480
1481 update_fcr31(env, GETPC());
1482 return fdret;
1483 }
1484
1485 uint64_t helper_float_max_d(CPUMIPSState *env, uint64_t fs, uint64_t ft)
1486 {
1487 uint64_t fdret;
1488
1489 fdret = float64_maxnum(fs, ft, &env->active_fpu.fp_status);
1490
1491 update_fcr31(env, GETPC());
1492 return fdret;
1493 }
1494
1495 uint32_t helper_float_maxa_s(CPUMIPSState *env, uint32_t fs, uint32_t ft)
1496 {
1497 uint32_t fdret;
1498
1499 fdret = float32_maxnummag(fs, ft, &env->active_fpu.fp_status);
1500
1501 update_fcr31(env, GETPC());
1502 return fdret;
1503 }
1504
1505 uint64_t helper_float_maxa_d(CPUMIPSState *env, uint64_t fs, uint64_t ft)
1506 {
1507 uint64_t fdret;
1508
1509 fdret = float64_maxnummag(fs, ft, &env->active_fpu.fp_status);
1510
1511 update_fcr31(env, GETPC());
1512 return fdret;
1513 }
1514
1515 uint32_t helper_float_min_s(CPUMIPSState *env, uint32_t fs, uint32_t ft)
1516 {
1517 uint32_t fdret;
1518
1519 fdret = float32_minnum(fs, ft, &env->active_fpu.fp_status);
1520
1521 update_fcr31(env, GETPC());
1522 return fdret;
1523 }
1524
1525 uint64_t helper_float_min_d(CPUMIPSState *env, uint64_t fs, uint64_t ft)
1526 {
1527 uint64_t fdret;
1528
1529 fdret = float64_minnum(fs, ft, &env->active_fpu.fp_status);
1530
1531 update_fcr31(env, GETPC());
1532 return fdret;
1533 }
1534
1535 uint32_t helper_float_mina_s(CPUMIPSState *env, uint32_t fs, uint32_t ft)
1536 {
1537 uint32_t fdret;
1538
1539 fdret = float32_minnummag(fs, ft, &env->active_fpu.fp_status);
1540
1541 update_fcr31(env, GETPC());
1542 return fdret;
1543 }
1544
1545 uint64_t helper_float_mina_d(CPUMIPSState *env, uint64_t fs, uint64_t ft)
1546 {
1547 uint64_t fdret;
1548
1549 fdret = float64_minnummag(fs, ft, &env->active_fpu.fp_status);
1550
1551 update_fcr31(env, GETPC());
1552 return fdret;
1553 }
1554
1555
1556 /* ternary operations */
1557
1558 uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
1559 uint64_t fst1, uint64_t fst2)
1560 {
1561 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1562 fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
1563
1564 update_fcr31(env, GETPC());
1565 return fst0;
1566 }
1567
1568 uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0,
1569 uint32_t fst1, uint32_t fst2)
1570 {
1571 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1572 fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
1573
1574 update_fcr31(env, GETPC());
1575 return fst0;
1576 }
1577
1578 uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
1579 uint64_t fdt1, uint64_t fdt2)
1580 {
1581 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1582 uint32_t fsth0 = fdt0 >> 32;
1583 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1584 uint32_t fsth1 = fdt1 >> 32;
1585 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1586 uint32_t fsth2 = fdt2 >> 32;
1587
1588 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1589 fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
1590 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1591 fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
1592
1593 update_fcr31(env, GETPC());
1594 return ((uint64_t)fsth0 << 32) | fstl0;
1595 }
1596
1597 uint64_t helper_float_msub_d(CPUMIPSState *env, uint64_t fst0,
1598 uint64_t fst1, uint64_t fst2)
1599 {
1600 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1601 fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
1602
1603 update_fcr31(env, GETPC());
1604 return fst0;
1605 }
1606
1607 uint32_t helper_float_msub_s(CPUMIPSState *env, uint32_t fst0,
1608 uint32_t fst1, uint32_t fst2)
1609 {
1610 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1611 fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
1612
1613 update_fcr31(env, GETPC());
1614 return fst0;
1615 }
1616
1617 uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
1618 uint64_t fdt1, uint64_t fdt2)
1619 {
1620 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1621 uint32_t fsth0 = fdt0 >> 32;
1622 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1623 uint32_t fsth1 = fdt1 >> 32;
1624 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1625 uint32_t fsth2 = fdt2 >> 32;
1626
1627 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1628 fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
1629 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1630 fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
1631
1632 update_fcr31(env, GETPC());
1633 return ((uint64_t)fsth0 << 32) | fstl0;
1634 }
1635
1636 uint64_t helper_float_nmadd_d(CPUMIPSState *env, uint64_t fst0,
1637 uint64_t fst1, uint64_t fst2)
1638 {
1639 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1640 fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
1641 fst0 = float64_chs(fst0);
1642
1643 update_fcr31(env, GETPC());
1644 return fst0;
1645 }
1646
1647 uint32_t helper_float_nmadd_s(CPUMIPSState *env, uint32_t fst0,
1648 uint32_t fst1, uint32_t fst2)
1649 {
1650 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1651 fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
1652 fst0 = float32_chs(fst0);
1653
1654 update_fcr31(env, GETPC());
1655 return fst0;
1656 }
1657
1658 uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
1659 uint64_t fdt1, uint64_t fdt2)
1660 {
1661 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1662 uint32_t fsth0 = fdt0 >> 32;
1663 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1664 uint32_t fsth1 = fdt1 >> 32;
1665 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1666 uint32_t fsth2 = fdt2 >> 32;
1667
1668 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1669 fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
1670 fstl0 = float32_chs(fstl0);
1671 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1672 fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
1673 fsth0 = float32_chs(fsth0);
1674
1675 update_fcr31(env, GETPC());
1676 return ((uint64_t)fsth0 << 32) | fstl0;
1677 }
1678
1679 uint64_t helper_float_nmsub_d(CPUMIPSState *env, uint64_t fst0,
1680 uint64_t fst1, uint64_t fst2)
1681 {
1682 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1683 fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
1684 fst0 = float64_chs(fst0);
1685
1686 update_fcr31(env, GETPC());
1687 return fst0;
1688 }
1689
1690 uint32_t helper_float_nmsub_s(CPUMIPSState *env, uint32_t fst0,
1691 uint32_t fst1, uint32_t fst2)
1692 {
1693 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1694 fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
1695 fst0 = float32_chs(fst0);
1696
1697 update_fcr31(env, GETPC());
1698 return fst0;
1699 }
1700
1701 uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0,
1702 uint64_t fdt1, uint64_t fdt2)
1703 {
1704 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1705 uint32_t fsth0 = fdt0 >> 32;
1706 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1707 uint32_t fsth1 = fdt1 >> 32;
1708 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1709 uint32_t fsth2 = fdt2 >> 32;
1710
1711 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1712 fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
1713 fstl0 = float32_chs(fstl0);
1714 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1715 fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
1716 fsth0 = float32_chs(fsth0);
1717
1718 update_fcr31(env, GETPC());
1719 return ((uint64_t)fsth0 << 32) | fstl0;
1720 }
1721
1722
1723 uint32_t helper_float_maddf_s(CPUMIPSState *env, uint32_t fs,
1724 uint32_t ft, uint32_t fd)
1725 {
1726 uint32_t fdret;
1727
1728 fdret = float32_muladd(fs, ft, fd, 0,
1729 &env->active_fpu.fp_status);
1730
1731 update_fcr31(env, GETPC());
1732 return fdret;
1733 }
1734
1735 uint64_t helper_float_maddf_d(CPUMIPSState *env, uint64_t fs,
1736 uint64_t ft, uint64_t fd)
1737 {
1738 uint64_t fdret;
1739
1740 fdret = float64_muladd(fs, ft, fd, 0,
1741 &env->active_fpu.fp_status);
1742
1743 update_fcr31(env, GETPC());
1744 return fdret;
1745 }
1746
1747 uint32_t helper_float_msubf_s(CPUMIPSState *env, uint32_t fs,
1748 uint32_t ft, uint32_t fd)
1749 {
1750 uint32_t fdret;
1751
1752 fdret = float32_muladd(fs, ft, fd, float_muladd_negate_product,
1753 &env->active_fpu.fp_status);
1754
1755 update_fcr31(env, GETPC());
1756 return fdret;
1757 }
1758
1759 uint64_t helper_float_msubf_d(CPUMIPSState *env, uint64_t fs,
1760 uint64_t ft, uint64_t fd)
1761 {
1762 uint64_t fdret;
1763
1764 fdret = float64_muladd(fs, ft, fd, float_muladd_negate_product,
1765 &env->active_fpu.fp_status);
1766
1767 update_fcr31(env, GETPC());
1768 return fdret;
1769 }
1770
1771
1772 /* compare operations */
1773 #define FOP_COND_D(op, cond) \
1774 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1775 uint64_t fdt1, int cc) \
1776 { \
1777 int c; \
1778 c = cond; \
1779 update_fcr31(env, GETPC()); \
1780 if (c) \
1781 SET_FP_COND(cc, env->active_fpu); \
1782 else \
1783 CLEAR_FP_COND(cc, env->active_fpu); \
1784 } \
1785 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1786 uint64_t fdt1, int cc) \
1787 { \
1788 int c; \
1789 fdt0 = float64_abs(fdt0); \
1790 fdt1 = float64_abs(fdt1); \
1791 c = cond; \
1792 update_fcr31(env, GETPC()); \
1793 if (c) \
1794 SET_FP_COND(cc, env->active_fpu); \
1795 else \
1796 CLEAR_FP_COND(cc, env->active_fpu); \
1797 }
1798
1799 /*
1800 * NOTE: the comma operator will make "cond" to eval to false,
1801 * but float64_unordered_quiet() is still called.
1802 */
1803 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0,
1804 &env->active_fpu.fp_status), 0))
1805 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0,
1806 &env->active_fpu.fp_status))
1807 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1,
1808 &env->active_fpu.fp_status))
1809 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0,
1810 &env->active_fpu.fp_status)
1811 || float64_eq_quiet(fdt0, fdt1,
1812 &env->active_fpu.fp_status))
1813 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1,
1814 &env->active_fpu.fp_status))
1815 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0,
1816 &env->active_fpu.fp_status)
1817 || float64_lt_quiet(fdt0, fdt1,
1818 &env->active_fpu.fp_status))
1819 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1,
1820 &env->active_fpu.fp_status))
1821 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0,
1822 &env->active_fpu.fp_status)
1823 || float64_le_quiet(fdt0, fdt1,
1824 &env->active_fpu.fp_status))
1825 /*
1826 * NOTE: the comma operator will make "cond" to eval to false,
1827 * but float64_unordered() is still called.
1828 */
1829 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0,
1830 &env->active_fpu.fp_status), 0))
1831 FOP_COND_D(ngle, float64_unordered(fdt1, fdt0,
1832 &env->active_fpu.fp_status))
1833 FOP_COND_D(seq, float64_eq(fdt0, fdt1,
1834 &env->active_fpu.fp_status))
1835 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0,
1836 &env->active_fpu.fp_status)
1837 || float64_eq(fdt0, fdt1,
1838 &env->active_fpu.fp_status))
1839 FOP_COND_D(lt, float64_lt(fdt0, fdt1,
1840 &env->active_fpu.fp_status))
1841 FOP_COND_D(nge, float64_unordered(fdt1, fdt0,
1842 &env->active_fpu.fp_status)
1843 || float64_lt(fdt0, fdt1,
1844 &env->active_fpu.fp_status))
1845 FOP_COND_D(le, float64_le(fdt0, fdt1,
1846 &env->active_fpu.fp_status))
1847 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0,
1848 &env->active_fpu.fp_status)
1849 || float64_le(fdt0, fdt1,
1850 &env->active_fpu.fp_status))
1851
1852 #define FOP_COND_S(op, cond) \
1853 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1854 uint32_t fst1, int cc) \
1855 { \
1856 int c; \
1857 c = cond; \
1858 update_fcr31(env, GETPC()); \
1859 if (c) \
1860 SET_FP_COND(cc, env->active_fpu); \
1861 else \
1862 CLEAR_FP_COND(cc, env->active_fpu); \
1863 } \
1864 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1865 uint32_t fst1, int cc) \
1866 { \
1867 int c; \
1868 fst0 = float32_abs(fst0); \
1869 fst1 = float32_abs(fst1); \
1870 c = cond; \
1871 update_fcr31(env, GETPC()); \
1872 if (c) \
1873 SET_FP_COND(cc, env->active_fpu); \
1874 else \
1875 CLEAR_FP_COND(cc, env->active_fpu); \
1876 }
1877
1878 /*
1879 * NOTE: the comma operator will make "cond" to eval to false,
1880 * but float32_unordered_quiet() is still called.
1881 */
1882 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0,
1883 &env->active_fpu.fp_status), 0))
1884 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0,
1885 &env->active_fpu.fp_status))
1886 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1,
1887 &env->active_fpu.fp_status))
1888 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0,
1889 &env->active_fpu.fp_status)
1890 || float32_eq_quiet(fst0, fst1,
1891 &env->active_fpu.fp_status))
1892 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1,
1893 &env->active_fpu.fp_status))
1894 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0,
1895 &env->active_fpu.fp_status)
1896 || float32_lt_quiet(fst0, fst1,
1897 &env->active_fpu.fp_status))
1898 FOP_COND_S(ole, float32_le_quiet(fst0, fst1,
1899 &env->active_fpu.fp_status))
1900 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0,
1901 &env->active_fpu.fp_status)
1902 || float32_le_quiet(fst0, fst1,
1903 &env->active_fpu.fp_status))
1904 /*
1905 * NOTE: the comma operator will make "cond" to eval to false,
1906 * but float32_unordered() is still called.
1907 */
1908 FOP_COND_S(sf, (float32_unordered(fst1, fst0,
1909 &env->active_fpu.fp_status), 0))
1910 FOP_COND_S(ngle, float32_unordered(fst1, fst0,
1911 &env->active_fpu.fp_status))
1912 FOP_COND_S(seq, float32_eq(fst0, fst1,
1913 &env->active_fpu.fp_status))
1914 FOP_COND_S(ngl, float32_unordered(fst1, fst0,
1915 &env->active_fpu.fp_status)
1916 || float32_eq(fst0, fst1,
1917 &env->active_fpu.fp_status))
1918 FOP_COND_S(lt, float32_lt(fst0, fst1,
1919 &env->active_fpu.fp_status))
1920 FOP_COND_S(nge, float32_unordered(fst1, fst0,
1921 &env->active_fpu.fp_status)
1922 || float32_lt(fst0, fst1,
1923 &env->active_fpu.fp_status))
1924 FOP_COND_S(le, float32_le(fst0, fst1,
1925 &env->active_fpu.fp_status))
1926 FOP_COND_S(ngt, float32_unordered(fst1, fst0,
1927 &env->active_fpu.fp_status)
1928 || float32_le(fst0, fst1,
1929 &env->active_fpu.fp_status))
1930
1931 #define FOP_COND_PS(op, condl, condh) \
1932 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1933 uint64_t fdt1, int cc) \
1934 { \
1935 uint32_t fst0, fsth0, fst1, fsth1; \
1936 int ch, cl; \
1937 fst0 = fdt0 & 0XFFFFFFFF; \
1938 fsth0 = fdt0 >> 32; \
1939 fst1 = fdt1 & 0XFFFFFFFF; \
1940 fsth1 = fdt1 >> 32; \
1941 cl = condl; \
1942 ch = condh; \
1943 update_fcr31(env, GETPC()); \
1944 if (cl) \
1945 SET_FP_COND(cc, env->active_fpu); \
1946 else \
1947 CLEAR_FP_COND(cc, env->active_fpu); \
1948 if (ch) \
1949 SET_FP_COND(cc + 1, env->active_fpu); \
1950 else \
1951 CLEAR_FP_COND(cc + 1, env->active_fpu); \
1952 } \
1953 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1954 uint64_t fdt1, int cc) \
1955 { \
1956 uint32_t fst0, fsth0, fst1, fsth1; \
1957 int ch, cl; \
1958 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
1959 fsth0 = float32_abs(fdt0 >> 32); \
1960 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
1961 fsth1 = float32_abs(fdt1 >> 32); \
1962 cl = condl; \
1963 ch = condh; \
1964 update_fcr31(env, GETPC()); \
1965 if (cl) \
1966 SET_FP_COND(cc, env->active_fpu); \
1967 else \
1968 CLEAR_FP_COND(cc, env->active_fpu); \
1969 if (ch) \
1970 SET_FP_COND(cc + 1, env->active_fpu); \
1971 else \
1972 CLEAR_FP_COND(cc + 1, env->active_fpu); \
1973 }
1974
1975 /*
1976 * NOTE: the comma operator will make "cond" to eval to false,
1977 * but float32_unordered_quiet() is still called.
1978 */
1979 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0,
1980 &env->active_fpu.fp_status), 0),
1981 (float32_unordered_quiet(fsth1, fsth0,
1982 &env->active_fpu.fp_status), 0))
1983 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0,
1984 &env->active_fpu.fp_status),
1985 float32_unordered_quiet(fsth1, fsth0,
1986 &env->active_fpu.fp_status))
1987 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1,
1988 &env->active_fpu.fp_status),
1989 float32_eq_quiet(fsth0, fsth1,
1990 &env->active_fpu.fp_status))
1991 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0,
1992 &env->active_fpu.fp_status)
1993 || float32_eq_quiet(fst0, fst1,
1994 &env->active_fpu.fp_status),
1995 float32_unordered_quiet(fsth1, fsth0,
1996 &env->active_fpu.fp_status)
1997 || float32_eq_quiet(fsth0, fsth1,
1998 &env->active_fpu.fp_status))
1999 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1,
2000 &env->active_fpu.fp_status),
2001 float32_lt_quiet(fsth0, fsth1,
2002 &env->active_fpu.fp_status))
2003 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0,
2004 &env->active_fpu.fp_status)
2005 || float32_lt_quiet(fst0, fst1,
2006 &env->active_fpu.fp_status),
2007 float32_unordered_quiet(fsth1, fsth0,
2008 &env->active_fpu.fp_status)
2009 || float32_lt_quiet(fsth0, fsth1,
2010 &env->active_fpu.fp_status))
2011 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1,
2012 &env->active_fpu.fp_status),
2013 float32_le_quiet(fsth0, fsth1,
2014 &env->active_fpu.fp_status))
2015 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0,
2016 &env->active_fpu.fp_status)
2017 || float32_le_quiet(fst0, fst1,
2018 &env->active_fpu.fp_status),
2019 float32_unordered_quiet(fsth1, fsth0,
2020 &env->active_fpu.fp_status)
2021 || float32_le_quiet(fsth0, fsth1,
2022 &env->active_fpu.fp_status))
2023 /*
2024 * NOTE: the comma operator will make "cond" to eval to false,
2025 * but float32_unordered() is still called.
2026 */
2027 FOP_COND_PS(sf, (float32_unordered(fst1, fst0,
2028 &env->active_fpu.fp_status), 0),
2029 (float32_unordered(fsth1, fsth0,
2030 &env->active_fpu.fp_status), 0))
2031 FOP_COND_PS(ngle, float32_unordered(fst1, fst0,
2032 &env->active_fpu.fp_status),
2033 float32_unordered(fsth1, fsth0,
2034 &env->active_fpu.fp_status))
2035 FOP_COND_PS(seq, float32_eq(fst0, fst1,
2036 &env->active_fpu.fp_status),
2037 float32_eq(fsth0, fsth1,
2038 &env->active_fpu.fp_status))
2039 FOP_COND_PS(ngl, float32_unordered(fst1, fst0,
2040 &env->active_fpu.fp_status)
2041 || float32_eq(fst0, fst1,
2042 &env->active_fpu.fp_status),
2043 float32_unordered(fsth1, fsth0,
2044 &env->active_fpu.fp_status)
2045 || float32_eq(fsth0, fsth1,
2046 &env->active_fpu.fp_status))
2047 FOP_COND_PS(lt, float32_lt(fst0, fst1,
2048 &env->active_fpu.fp_status),
2049 float32_lt(fsth0, fsth1,
2050 &env->active_fpu.fp_status))
2051 FOP_COND_PS(nge, float32_unordered(fst1, fst0,
2052 &env->active_fpu.fp_status)
2053 || float32_lt(fst0, fst1,
2054 &env->active_fpu.fp_status),
2055 float32_unordered(fsth1, fsth0,
2056 &env->active_fpu.fp_status)
2057 || float32_lt(fsth0, fsth1,
2058 &env->active_fpu.fp_status))
2059 FOP_COND_PS(le, float32_le(fst0, fst1,
2060 &env->active_fpu.fp_status),
2061 float32_le(fsth0, fsth1,
2062 &env->active_fpu.fp_status))
2063 FOP_COND_PS(ngt, float32_unordered(fst1, fst0,
2064 &env->active_fpu.fp_status)
2065 || float32_le(fst0, fst1,
2066 &env->active_fpu.fp_status),
2067 float32_unordered(fsth1, fsth0,
2068 &env->active_fpu.fp_status)
2069 || float32_le(fsth0, fsth1,
2070 &env->active_fpu.fp_status))
2071
2072 /* R6 compare operations */
2073 #define FOP_CONDN_D(op, cond) \
2074 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
2075 uint64_t fdt1) \
2076 { \
2077 uint64_t c; \
2078 c = cond; \
2079 update_fcr31(env, GETPC()); \
2080 if (c) { \
2081 return -1; \
2082 } else { \
2083 return 0; \
2084 } \
2085 }
2086
2087 /*
2088 * NOTE: the comma operator will make "cond" to eval to false,
2089 * but float64_unordered_quiet() is still called.
2090 */
2091 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0,
2092 &env->active_fpu.fp_status), 0))
2093 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0,
2094 &env->active_fpu.fp_status)))
2095 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1,
2096 &env->active_fpu.fp_status)))
2097 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0,
2098 &env->active_fpu.fp_status)
2099 || float64_eq_quiet(fdt0, fdt1,
2100 &env->active_fpu.fp_status)))
2101 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1,
2102 &env->active_fpu.fp_status)))
2103 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0,
2104 &env->active_fpu.fp_status)
2105 || float64_lt_quiet(fdt0, fdt1,
2106 &env->active_fpu.fp_status)))
2107 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1,
2108 &env->active_fpu.fp_status)))
2109 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0,
2110 &env->active_fpu.fp_status)
2111 || float64_le_quiet(fdt0, fdt1,
2112 &env->active_fpu.fp_status)))
2113 /*
2114 * NOTE: the comma operator will make "cond" to eval to false,
2115 * but float64_unordered() is still called.\
2116 */
2117 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0,
2118 &env->active_fpu.fp_status), 0))
2119 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0,
2120 &env->active_fpu.fp_status)))
2121 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1,
2122 &env->active_fpu.fp_status)))
2123 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0,
2124 &env->active_fpu.fp_status)
2125 || float64_eq(fdt0, fdt1,
2126 &env->active_fpu.fp_status)))
2127 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1,
2128 &env->active_fpu.fp_status)))
2129 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0,
2130 &env->active_fpu.fp_status)
2131 || float64_lt(fdt0, fdt1,
2132 &env->active_fpu.fp_status)))
2133 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1,
2134 &env->active_fpu.fp_status)))
2135 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0,
2136 &env->active_fpu.fp_status)
2137 || float64_le(fdt0, fdt1,
2138 &env->active_fpu.fp_status)))
2139 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0,
2140 &env->active_fpu.fp_status)
2141 || float64_le_quiet(fdt0, fdt1,
2142 &env->active_fpu.fp_status)))
2143 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0,
2144 &env->active_fpu.fp_status)
2145 || float64_lt_quiet(fdt1, fdt0,
2146 &env->active_fpu.fp_status)
2147 || float64_lt_quiet(fdt0, fdt1,
2148 &env->active_fpu.fp_status)))
2149 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0,
2150 &env->active_fpu.fp_status)
2151 || float64_lt_quiet(fdt0, fdt1,
2152 &env->active_fpu.fp_status)))
2153 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0,
2154 &env->active_fpu.fp_status)
2155 || float64_le(fdt0, fdt1,
2156 &env->active_fpu.fp_status)))
2157 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0,
2158 &env->active_fpu.fp_status)
2159 || float64_lt(fdt1, fdt0,
2160 &env->active_fpu.fp_status)
2161 || float64_lt(fdt0, fdt1,
2162 &env->active_fpu.fp_status)))
2163 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0,
2164 &env->active_fpu.fp_status)
2165 || float64_lt(fdt0, fdt1,
2166 &env->active_fpu.fp_status)))
2167
2168 #define FOP_CONDN_S(op, cond) \
2169 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
2170 uint32_t fst1) \
2171 { \
2172 uint64_t c; \
2173 c = cond; \
2174 update_fcr31(env, GETPC()); \
2175 if (c) { \
2176 return -1; \
2177 } else { \
2178 return 0; \
2179 } \
2180 }
2181
2182 /*
2183 * NOTE: the comma operator will make "cond" to eval to false,
2184 * but float32_unordered_quiet() is still called.
2185 */
2186 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0,
2187 &env->active_fpu.fp_status), 0))
2188 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0,
2189 &env->active_fpu.fp_status)))
2190 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1,
2191 &env->active_fpu.fp_status)))
2192 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0,
2193 &env->active_fpu.fp_status)
2194 || float32_eq_quiet(fst0, fst1,
2195 &env->active_fpu.fp_status)))
2196 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1,
2197 &env->active_fpu.fp_status)))
2198 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0,
2199 &env->active_fpu.fp_status)
2200 || float32_lt_quiet(fst0, fst1,
2201 &env->active_fpu.fp_status)))
2202 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1,
2203 &env->active_fpu.fp_status)))
2204 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0,
2205 &env->active_fpu.fp_status)
2206 || float32_le_quiet(fst0, fst1,
2207 &env->active_fpu.fp_status)))
2208 /*
2209 * NOTE: the comma operator will make "cond" to eval to false,
2210 * but float32_unordered() is still called.
2211 */
2212 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0,
2213 &env->active_fpu.fp_status), 0))
2214 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0,
2215 &env->active_fpu.fp_status)))
2216 FOP_CONDN_S(seq, (float32_eq(fst0, fst1,
2217 &env->active_fpu.fp_status)))
2218 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0,
2219 &env->active_fpu.fp_status)
2220 || float32_eq(fst0, fst1,
2221 &env->active_fpu.fp_status)))
2222 FOP_CONDN_S(slt, (float32_lt(fst0, fst1,
2223 &env->active_fpu.fp_status)))
2224 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0,
2225 &env->active_fpu.fp_status)
2226 || float32_lt(fst0, fst1,
2227 &env->active_fpu.fp_status)))
2228 FOP_CONDN_S(sle, (float32_le(fst0, fst1,
2229 &env->active_fpu.fp_status)))
2230 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0,
2231 &env->active_fpu.fp_status)
2232 || float32_le(fst0, fst1,
2233 &env->active_fpu.fp_status)))
2234 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0,
2235 &env->active_fpu.fp_status)
2236 || float32_le_quiet(fst0, fst1,
2237 &env->active_fpu.fp_status)))
2238 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0,
2239 &env->active_fpu.fp_status)
2240 || float32_lt_quiet(fst1, fst0,
2241 &env->active_fpu.fp_status)
2242 || float32_lt_quiet(fst0, fst1,
2243 &env->active_fpu.fp_status)))
2244 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0,
2245 &env->active_fpu.fp_status)
2246 || float32_lt_quiet(fst0, fst1,
2247 &env->active_fpu.fp_status)))
2248 FOP_CONDN_S(sor, (float32_le(fst1, fst0,
2249 &env->active_fpu.fp_status)
2250 || float32_le(fst0, fst1,
2251 &env->active_fpu.fp_status)))
2252 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0,
2253 &env->active_fpu.fp_status)
2254 || float32_lt(fst1, fst0,
2255 &env->active_fpu.fp_status)
2256 || float32_lt(fst0, fst1,
2257 &env->active_fpu.fp_status)))
2258 FOP_CONDN_S(sne, (float32_lt(fst1, fst0,
2259 &env->active_fpu.fp_status)
2260 || float32_lt(fst0, fst1,
2261 &env->active_fpu.fp_status)))
AR7 emulation for QEMU