2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o BIOS work to boot from USB storage
28 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/module.h"
32 #include "qemu/timer.h"
34 #include "migration/vmstate.h"
35 #include "hw/sysbus.h"
36 #include "hw/qdev-dma.h"
37 #include "hw/qdev-properties.h"
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
44 #define ED_LINK_LIMIT 32
46 static int64_t usb_frame_time
;
47 static int64_t usb_bit_time
;
49 /* Host Controller Communications Area */
55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
59 #define ED_WBACK_SIZE 4
61 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
);
63 /* Bitfields for the first word of an Endpoint Desciptor. */
64 #define OHCI_ED_FA_SHIFT 0
65 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
66 #define OHCI_ED_EN_SHIFT 7
67 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
68 #define OHCI_ED_D_SHIFT 11
69 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
70 #define OHCI_ED_S (1<<13)
71 #define OHCI_ED_K (1<<14)
72 #define OHCI_ED_F (1<<15)
73 #define OHCI_ED_MPS_SHIFT 16
74 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
76 /* Flags in the head field of an Endpoint Desciptor. */
80 /* Bitfields for the first word of a Transfer Desciptor. */
81 #define OHCI_TD_R (1<<18)
82 #define OHCI_TD_DP_SHIFT 19
83 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
84 #define OHCI_TD_DI_SHIFT 21
85 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
86 #define OHCI_TD_T0 (1<<24)
87 #define OHCI_TD_T1 (1<<25)
88 #define OHCI_TD_EC_SHIFT 26
89 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
90 #define OHCI_TD_CC_SHIFT 28
91 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
93 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
94 /* CC & DI - same as in the General Transfer Desciptor */
95 #define OHCI_TD_SF_SHIFT 0
96 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
97 #define OHCI_TD_FC_SHIFT 24
98 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
100 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
101 #define OHCI_TD_PSW_CC_SHIFT 12
102 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
103 #define OHCI_TD_PSW_SIZE_SHIFT 0
104 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
106 #define OHCI_PAGE_MASK 0xfffff000
107 #define OHCI_OFFSET_MASK 0xfff
109 #define OHCI_DPTR_MASK 0xfffffff0
111 #define OHCI_BM(val, field) \
112 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
114 #define OHCI_SET_BM(val, field, newval) do { \
115 val &= ~OHCI_##field##_MASK; \
116 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
119 /* endpoint descriptor */
127 /* General transfer descriptor */
135 /* Isochronous transfer descriptor */
144 #define USB_HZ 12000000
146 /* OHCI Local stuff */
147 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
148 #define OHCI_CTL_PLE (1<<2)
149 #define OHCI_CTL_IE (1<<3)
150 #define OHCI_CTL_CLE (1<<4)
151 #define OHCI_CTL_BLE (1<<5)
152 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
153 #define OHCI_USB_RESET 0x00
154 #define OHCI_USB_RESUME 0x40
155 #define OHCI_USB_OPERATIONAL 0x80
156 #define OHCI_USB_SUSPEND 0xc0
157 #define OHCI_CTL_IR (1<<8)
158 #define OHCI_CTL_RWC (1<<9)
159 #define OHCI_CTL_RWE (1<<10)
161 #define OHCI_STATUS_HCR (1<<0)
162 #define OHCI_STATUS_CLF (1<<1)
163 #define OHCI_STATUS_BLF (1<<2)
164 #define OHCI_STATUS_OCR (1<<3)
165 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
167 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
168 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
169 #define OHCI_INTR_SF (1U<<2) /* Start of frame */
170 #define OHCI_INTR_RD (1U<<3) /* Resume detect */
171 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
172 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
173 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
174 #define OHCI_INTR_OC (1U<<30) /* Ownership change */
175 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
177 #define OHCI_HCCA_SIZE 0x100
178 #define OHCI_HCCA_MASK 0xffffff00
180 #define OHCI_EDPTR_MASK 0xfffffff0
182 #define OHCI_FMI_FI 0x00003fff
183 #define OHCI_FMI_FSMPS 0xffff0000
184 #define OHCI_FMI_FIT 0x80000000
186 #define OHCI_FR_RT (1U<<31)
188 #define OHCI_LS_THRESH 0x628
190 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
191 #define OHCI_RHA_PSM (1<<8)
192 #define OHCI_RHA_NPS (1<<9)
193 #define OHCI_RHA_DT (1<<10)
194 #define OHCI_RHA_OCPM (1<<11)
195 #define OHCI_RHA_NOCP (1<<12)
196 #define OHCI_RHA_POTPGT_MASK 0xff000000
198 #define OHCI_RHS_LPS (1U<<0)
199 #define OHCI_RHS_OCI (1U<<1)
200 #define OHCI_RHS_DRWE (1U<<15)
201 #define OHCI_RHS_LPSC (1U<<16)
202 #define OHCI_RHS_OCIC (1U<<17)
203 #define OHCI_RHS_CRWE (1U<<31)
205 #define OHCI_PORT_CCS (1<<0)
206 #define OHCI_PORT_PES (1<<1)
207 #define OHCI_PORT_PSS (1<<2)
208 #define OHCI_PORT_POCI (1<<3)
209 #define OHCI_PORT_PRS (1<<4)
210 #define OHCI_PORT_PPS (1<<8)
211 #define OHCI_PORT_LSDA (1<<9)
212 #define OHCI_PORT_CSC (1<<16)
213 #define OHCI_PORT_PESC (1<<17)
214 #define OHCI_PORT_PSSC (1<<18)
215 #define OHCI_PORT_OCIC (1<<19)
216 #define OHCI_PORT_PRSC (1<<20)
217 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
218 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
220 #define OHCI_TD_DIR_SETUP 0x0
221 #define OHCI_TD_DIR_OUT 0x1
222 #define OHCI_TD_DIR_IN 0x2
223 #define OHCI_TD_DIR_RESERVED 0x3
225 #define OHCI_CC_NOERROR 0x0
226 #define OHCI_CC_CRC 0x1
227 #define OHCI_CC_BITSTUFFING 0x2
228 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
229 #define OHCI_CC_STALL 0x4
230 #define OHCI_CC_DEVICENOTRESPONDING 0x5
231 #define OHCI_CC_PIDCHECKFAILURE 0x6
232 #define OHCI_CC_UNDEXPETEDPID 0x7
233 #define OHCI_CC_DATAOVERRUN 0x8
234 #define OHCI_CC_DATAUNDERRUN 0x9
235 #define OHCI_CC_BUFFEROVERRUN 0xc
236 #define OHCI_CC_BUFFERUNDERRUN 0xd
238 #define OHCI_HRESET_FSBIR (1 << 0)
240 static void ohci_die(OHCIState
*ohci
)
242 ohci
->ohci_die(ohci
);
245 /* Update IRQ levels */
246 static inline void ohci_intr_update(OHCIState
*ohci
)
250 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
251 (ohci
->intr_status
& ohci
->intr
))
254 qemu_set_irq(ohci
->irq
, level
);
257 /* Set an interrupt */
258 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
260 ohci
->intr_status
|= intr
;
261 ohci_intr_update(ohci
);
264 /* Attach or detach a device on a root hub port. */
265 static void ohci_attach(USBPort
*port1
)
267 OHCIState
*s
= port1
->opaque
;
268 OHCIPort
*port
= &s
->rhport
[port1
->index
];
269 uint32_t old_state
= port
->ctrl
;
271 /* set connect status */
272 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
275 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
276 port
->ctrl
|= OHCI_PORT_LSDA
;
278 port
->ctrl
&= ~OHCI_PORT_LSDA
;
281 /* notify of remote-wakeup */
282 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
283 ohci_set_interrupt(s
, OHCI_INTR_RD
);
286 trace_usb_ohci_port_attach(port1
->index
);
288 if (old_state
!= port
->ctrl
) {
289 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
293 static void ohci_detach(USBPort
*port1
)
295 OHCIState
*s
= port1
->opaque
;
296 OHCIPort
*port
= &s
->rhport
[port1
->index
];
297 uint32_t old_state
= port
->ctrl
;
299 ohci_async_cancel_device(s
, port1
->dev
);
301 /* set connect status */
302 if (port
->ctrl
& OHCI_PORT_CCS
) {
303 port
->ctrl
&= ~OHCI_PORT_CCS
;
304 port
->ctrl
|= OHCI_PORT_CSC
;
307 if (port
->ctrl
& OHCI_PORT_PES
) {
308 port
->ctrl
&= ~OHCI_PORT_PES
;
309 port
->ctrl
|= OHCI_PORT_PESC
;
311 trace_usb_ohci_port_detach(port1
->index
);
313 if (old_state
!= port
->ctrl
) {
314 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
318 static void ohci_wakeup(USBPort
*port1
)
320 OHCIState
*s
= port1
->opaque
;
321 OHCIPort
*port
= &s
->rhport
[port1
->index
];
323 if (port
->ctrl
& OHCI_PORT_PSS
) {
324 trace_usb_ohci_port_wakeup(port1
->index
);
325 port
->ctrl
|= OHCI_PORT_PSSC
;
326 port
->ctrl
&= ~OHCI_PORT_PSS
;
327 intr
= OHCI_INTR_RHSC
;
329 /* Note that the controller can be suspended even if this port is not */
330 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
331 trace_usb_ohci_remote_wakeup(s
->name
);
332 /* This is the one state transition the controller can do by itself */
333 s
->ctl
&= ~OHCI_CTL_HCFS
;
334 s
->ctl
|= OHCI_USB_RESUME
;
335 /* In suspend mode only ResumeDetected is possible, not RHSC:
336 * see the OHCI spec 5.1.2.3.
340 ohci_set_interrupt(s
, intr
);
343 static void ohci_child_detach(USBPort
*port1
, USBDevice
*child
)
345 OHCIState
*s
= port1
->opaque
;
347 ohci_async_cancel_device(s
, child
);
350 static USBDevice
*ohci_find_device(OHCIState
*ohci
, uint8_t addr
)
355 for (i
= 0; i
< ohci
->num_ports
; i
++) {
356 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0) {
359 dev
= usb_find_device(&ohci
->rhport
[i
].port
, addr
);
367 void ohci_stop_endpoints(OHCIState
*ohci
)
372 for (i
= 0; i
< ohci
->num_ports
; i
++) {
373 dev
= ohci
->rhport
[i
].port
.dev
;
374 if (dev
&& dev
->attached
) {
375 usb_device_ep_stopped(dev
, &dev
->ep_ctl
);
376 for (j
= 0; j
< USB_MAX_ENDPOINTS
; j
++) {
377 usb_device_ep_stopped(dev
, &dev
->ep_in
[j
]);
378 usb_device_ep_stopped(dev
, &dev
->ep_out
[j
]);
384 static void ohci_roothub_reset(OHCIState
*ohci
)
390 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
391 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
394 for (i
= 0; i
< ohci
->num_ports
; i
++) {
395 port
= &ohci
->rhport
[i
];
397 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
398 usb_port_reset(&port
->port
);
401 if (ohci
->async_td
) {
402 usb_cancel_packet(&ohci
->usb_packet
);
405 ohci_stop_endpoints(ohci
);
408 /* Reset the controller */
409 static void ohci_soft_reset(OHCIState
*ohci
)
411 trace_usb_ohci_reset(ohci
->name
);
414 ohci
->ctl
= (ohci
->ctl
& OHCI_CTL_IR
) | OHCI_USB_SUSPEND
;
417 ohci
->intr_status
= 0;
418 ohci
->intr
= OHCI_INTR_MIE
;
421 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
422 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
425 ohci
->done_count
= 7;
427 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
428 * I took the value linux sets ...
430 ohci
->fsmps
= 0x2778;
434 ohci
->frame_number
= 0;
436 ohci
->lst
= OHCI_LS_THRESH
;
439 void ohci_hard_reset(OHCIState
*ohci
)
441 ohci_soft_reset(ohci
);
443 ohci_roothub_reset(ohci
);
446 /* Get an array of dwords from main memory */
447 static inline int get_dwords(OHCIState
*ohci
,
448 dma_addr_t addr
, uint32_t *buf
, int num
)
452 addr
+= ohci
->localmem_base
;
454 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
455 if (dma_memory_read(ohci
->as
, addr
, buf
, sizeof(*buf
))) {
458 *buf
= le32_to_cpu(*buf
);
464 /* Put an array of dwords in to main memory */
465 static inline int put_dwords(OHCIState
*ohci
,
466 dma_addr_t addr
, uint32_t *buf
, int num
)
470 addr
+= ohci
->localmem_base
;
472 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
473 uint32_t tmp
= cpu_to_le32(*buf
);
474 if (dma_memory_write(ohci
->as
, addr
, &tmp
, sizeof(tmp
))) {
482 /* Get an array of words from main memory */
483 static inline int get_words(OHCIState
*ohci
,
484 dma_addr_t addr
, uint16_t *buf
, int num
)
488 addr
+= ohci
->localmem_base
;
490 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
491 if (dma_memory_read(ohci
->as
, addr
, buf
, sizeof(*buf
))) {
494 *buf
= le16_to_cpu(*buf
);
500 /* Put an array of words in to main memory */
501 static inline int put_words(OHCIState
*ohci
,
502 dma_addr_t addr
, uint16_t *buf
, int num
)
506 addr
+= ohci
->localmem_base
;
508 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
509 uint16_t tmp
= cpu_to_le16(*buf
);
510 if (dma_memory_write(ohci
->as
, addr
, &tmp
, sizeof(tmp
))) {
518 static inline int ohci_read_ed(OHCIState
*ohci
,
519 dma_addr_t addr
, struct ohci_ed
*ed
)
521 return get_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
524 static inline int ohci_read_td(OHCIState
*ohci
,
525 dma_addr_t addr
, struct ohci_td
*td
)
527 return get_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
530 static inline int ohci_read_iso_td(OHCIState
*ohci
,
531 dma_addr_t addr
, struct ohci_iso_td
*td
)
533 return get_dwords(ohci
, addr
, (uint32_t *)td
, 4) ||
534 get_words(ohci
, addr
+ 16, td
->offset
, 8);
537 static inline int ohci_read_hcca(OHCIState
*ohci
,
538 dma_addr_t addr
, struct ohci_hcca
*hcca
)
540 return dma_memory_read(ohci
->as
, addr
+ ohci
->localmem_base
,
541 hcca
, sizeof(*hcca
));
544 static inline int ohci_put_ed(OHCIState
*ohci
,
545 dma_addr_t addr
, struct ohci_ed
*ed
)
547 /* ed->tail is under control of the HCD.
548 * Since just ed->head is changed by HC, just write back this
551 return put_dwords(ohci
, addr
+ ED_WBACK_OFFSET
,
552 (uint32_t *)((char *)ed
+ ED_WBACK_OFFSET
),
556 static inline int ohci_put_td(OHCIState
*ohci
,
557 dma_addr_t addr
, struct ohci_td
*td
)
559 return put_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
562 static inline int ohci_put_iso_td(OHCIState
*ohci
,
563 dma_addr_t addr
, struct ohci_iso_td
*td
)
565 return put_dwords(ohci
, addr
, (uint32_t *)td
, 4) ||
566 put_words(ohci
, addr
+ 16, td
->offset
, 8);
569 static inline int ohci_put_hcca(OHCIState
*ohci
,
570 dma_addr_t addr
, struct ohci_hcca
*hcca
)
572 return dma_memory_write(ohci
->as
,
573 addr
+ ohci
->localmem_base
+ HCCA_WRITEBACK_OFFSET
,
574 (char *)hcca
+ HCCA_WRITEBACK_OFFSET
,
575 HCCA_WRITEBACK_SIZE
);
578 /* Read/Write the contents of a TD from/to main memory. */
579 static int ohci_copy_td(OHCIState
*ohci
, struct ohci_td
*td
,
580 uint8_t *buf
, int len
, DMADirection dir
)
585 n
= 0x1000 - (ptr
& 0xfff);
589 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
, n
, dir
)) {
595 ptr
= td
->be
& ~0xfffu
;
597 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
,
604 /* Read/Write the contents of an ISO TD from/to main memory. */
605 static int ohci_copy_iso_td(OHCIState
*ohci
,
606 uint32_t start_addr
, uint32_t end_addr
,
607 uint8_t *buf
, int len
, DMADirection dir
)
612 n
= 0x1000 - (ptr
& 0xfff);
616 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
, n
, dir
)) {
622 ptr
= end_addr
& ~0xfffu
;
624 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
,
631 static void ohci_process_lists(OHCIState
*ohci
, int completion
);
633 static void ohci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
635 OHCIState
*ohci
= container_of(packet
, OHCIState
, usb_packet
);
637 trace_usb_ohci_async_complete();
638 ohci
->async_complete
= true;
639 ohci_process_lists(ohci
, 1);
642 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
644 static int ohci_service_iso_td(OHCIState
*ohci
, struct ohci_ed
*ed
,
649 const char *str
= NULL
;
655 struct ohci_iso_td iso_td
;
657 uint16_t starting_frame
;
658 int16_t relative_frame_number
;
660 uint32_t start_offset
, next_offset
, end_offset
= 0;
661 uint32_t start_addr
, end_addr
;
663 addr
= ed
->head
& OHCI_DPTR_MASK
;
665 if (ohci_read_iso_td(ohci
, addr
, &iso_td
)) {
666 trace_usb_ohci_iso_td_read_failed(addr
);
671 starting_frame
= OHCI_BM(iso_td
.flags
, TD_SF
);
672 frame_count
= OHCI_BM(iso_td
.flags
, TD_FC
);
673 relative_frame_number
= USUB(ohci
->frame_number
, starting_frame
);
675 trace_usb_ohci_iso_td_head(
676 ed
->head
& OHCI_DPTR_MASK
, ed
->tail
& OHCI_DPTR_MASK
,
677 iso_td
.flags
, iso_td
.bp
, iso_td
.next
, iso_td
.be
,
678 ohci
->frame_number
, starting_frame
,
679 frame_count
, relative_frame_number
);
680 trace_usb_ohci_iso_td_head_offset(
681 iso_td
.offset
[0], iso_td
.offset
[1],
682 iso_td
.offset
[2], iso_td
.offset
[3],
683 iso_td
.offset
[4], iso_td
.offset
[5],
684 iso_td
.offset
[6], iso_td
.offset
[7]);
686 if (relative_frame_number
< 0) {
687 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number
);
689 } else if (relative_frame_number
> frame_count
) {
690 /* ISO TD expired - retire the TD to the Done Queue and continue with
691 the next ISO TD of the same ED */
692 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number
,
694 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
695 ed
->head
&= ~OHCI_DPTR_MASK
;
696 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
697 iso_td
.next
= ohci
->done
;
699 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
700 if (i
< ohci
->done_count
)
701 ohci
->done_count
= i
;
702 if (ohci_put_iso_td(ohci
, addr
, &iso_td
)) {
709 dir
= OHCI_BM(ed
->flags
, ED_D
);
715 case OHCI_TD_DIR_OUT
:
719 case OHCI_TD_DIR_SETUP
:
721 pid
= USB_TOKEN_SETUP
;
724 trace_usb_ohci_iso_td_bad_direction(dir
);
728 if (!iso_td
.bp
|| !iso_td
.be
) {
729 trace_usb_ohci_iso_td_bad_bp_be(iso_td
.bp
, iso_td
.be
);
733 start_offset
= iso_td
.offset
[relative_frame_number
];
734 if (relative_frame_number
< frame_count
) {
735 next_offset
= iso_td
.offset
[relative_frame_number
+ 1];
737 next_offset
= iso_td
.be
;
740 if (!(OHCI_BM(start_offset
, TD_PSW_CC
) & 0xe) ||
741 ((relative_frame_number
< frame_count
) &&
742 !(OHCI_BM(next_offset
, TD_PSW_CC
) & 0xe))) {
743 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset
, next_offset
);
747 if ((relative_frame_number
< frame_count
) && (start_offset
> next_offset
)) {
748 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset
, next_offset
);
752 if ((start_offset
& 0x1000) == 0) {
753 start_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
754 (start_offset
& OHCI_OFFSET_MASK
);
756 start_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
757 (start_offset
& OHCI_OFFSET_MASK
);
760 if (relative_frame_number
< frame_count
) {
761 end_offset
= next_offset
- 1;
762 if ((end_offset
& 0x1000) == 0) {
763 end_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
764 (end_offset
& OHCI_OFFSET_MASK
);
766 end_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
767 (end_offset
& OHCI_OFFSET_MASK
);
770 /* Last packet in the ISO TD */
771 end_addr
= next_offset
;
774 if (start_addr
> end_addr
) {
775 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr
, end_addr
);
779 if ((start_addr
& OHCI_PAGE_MASK
) != (end_addr
& OHCI_PAGE_MASK
)) {
780 len
= (end_addr
& OHCI_OFFSET_MASK
) + 0x1001
781 - (start_addr
& OHCI_OFFSET_MASK
);
783 len
= end_addr
- start_addr
+ 1;
785 if (len
> sizeof(ohci
->usb_buf
)) {
786 len
= sizeof(ohci
->usb_buf
);
789 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
790 if (ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, len
,
791 DMA_DIRECTION_TO_DEVICE
)) {
798 bool int_req
= relative_frame_number
== frame_count
&&
799 OHCI_BM(iso_td
.flags
, TD_DI
) == 0;
800 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
802 trace_usb_ohci_td_dev_error();
805 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
806 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
, 0, addr
, false, int_req
);
807 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, len
);
808 usb_handle_packet(dev
, &ohci
->usb_packet
);
809 if (ohci
->usb_packet
.status
== USB_RET_ASYNC
) {
810 usb_device_flush_ep_queue(dev
, ep
);
814 if (ohci
->usb_packet
.status
== USB_RET_SUCCESS
) {
815 ret
= ohci
->usb_packet
.actual_length
;
817 ret
= ohci
->usb_packet
.status
;
820 trace_usb_ohci_iso_td_so(start_offset
, end_offset
, start_addr
, end_addr
,
824 if (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && ret
<= len
) {
825 /* IN transfer succeeded */
826 if (ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, ret
,
827 DMA_DIRECTION_FROM_DEVICE
)) {
831 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
833 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, ret
);
834 } else if (dir
== OHCI_TD_DIR_OUT
&& ret
== len
) {
835 /* OUT transfer succeeded */
836 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
838 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, 0);
840 if (ret
> (ssize_t
) len
) {
841 trace_usb_ohci_iso_td_data_overrun(ret
, len
);
842 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
843 OHCI_CC_DATAOVERRUN
);
844 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
846 } else if (ret
>= 0) {
847 trace_usb_ohci_iso_td_data_underrun(ret
);
848 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
849 OHCI_CC_DATAUNDERRUN
);
852 case USB_RET_IOERROR
:
854 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
855 OHCI_CC_DEVICENOTRESPONDING
);
856 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
861 trace_usb_ohci_iso_td_nak(ret
);
862 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
864 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
868 trace_usb_ohci_iso_td_bad_response(ret
);
869 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
870 OHCI_CC_UNDEXPETEDPID
);
876 if (relative_frame_number
== frame_count
) {
877 /* Last data packet of ISO TD - retire the TD to the Done Queue */
878 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
879 ed
->head
&= ~OHCI_DPTR_MASK
;
880 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
881 iso_td
.next
= ohci
->done
;
883 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
884 if (i
< ohci
->done_count
)
885 ohci
->done_count
= i
;
887 if (ohci_put_iso_td(ohci
, addr
, &iso_td
)) {
893 static void ohci_td_pkt(const char *msg
, const uint8_t *buf
, size_t len
)
897 const int width
= 16;
899 char tmp
[3 * width
+ 1];
902 print16
= !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT
);
903 printall
= !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL
);
905 if (!printall
&& !print16
) {
910 if (i
&& (!(i
% width
) || (i
== len
))) {
912 trace_usb_ohci_td_pkt_short(msg
, tmp
);
915 trace_usb_ohci_td_pkt_full(msg
, tmp
);
923 p
+= sprintf(p
, " %.2x", buf
[i
]);
927 /* Service a transport descriptor.
928 Returns nonzero to terminate processing of this endpoint. */
930 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
933 size_t len
= 0, pktlen
= 0;
934 const char *str
= NULL
;
945 addr
= ed
->head
& OHCI_DPTR_MASK
;
946 /* See if this TD has already been submitted to the device. */
947 completion
= (addr
== ohci
->async_td
);
948 if (completion
&& !ohci
->async_complete
) {
949 trace_usb_ohci_td_skip_async();
952 if (ohci_read_td(ohci
, addr
, &td
)) {
953 trace_usb_ohci_td_read_error(addr
);
958 dir
= OHCI_BM(ed
->flags
, ED_D
);
960 case OHCI_TD_DIR_OUT
:
965 dir
= OHCI_BM(td
.flags
, TD_DP
);
974 case OHCI_TD_DIR_OUT
:
978 case OHCI_TD_DIR_SETUP
:
980 pid
= USB_TOKEN_SETUP
;
983 trace_usb_ohci_td_bad_direction(dir
);
986 if (td
.cbp
&& td
.be
) {
987 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
988 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
990 if (td
.cbp
> td
.be
) {
991 trace_usb_ohci_iso_td_bad_cc_overrun(td
.cbp
, td
.be
);
995 len
= (td
.be
- td
.cbp
) + 1;
997 if (len
> sizeof(ohci
->usb_buf
)) {
998 len
= sizeof(ohci
->usb_buf
);
1002 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
1003 /* The endpoint may not allow us to transfer it all now */
1004 pktlen
= (ed
->flags
& OHCI_ED_MPS_MASK
) >> OHCI_ED_MPS_SHIFT
;
1009 if (ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, pktlen
,
1010 DMA_DIRECTION_TO_DEVICE
)) {
1017 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
1018 trace_usb_ohci_td_pkt_hdr(addr
, (int64_t)pktlen
, (int64_t)len
, str
,
1019 flag_r
, td
.cbp
, td
.be
);
1020 ohci_td_pkt("OUT", ohci
->usb_buf
, pktlen
);
1024 ohci
->async_complete
= false;
1026 if (ohci
->async_td
) {
1027 /* ??? The hardware should allow one active packet per
1028 endpoint. We only allow one active packet per controller.
1029 This should be sufficient as long as devices respond in a
1032 trace_usb_ohci_td_too_many_pending();
1035 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
1037 trace_usb_ohci_td_dev_error();
1040 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
1041 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
, 0, addr
, !flag_r
,
1042 OHCI_BM(td
.flags
, TD_DI
) == 0);
1043 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, pktlen
);
1044 usb_handle_packet(dev
, &ohci
->usb_packet
);
1045 trace_usb_ohci_td_packet_status(ohci
->usb_packet
.status
);
1047 if (ohci
->usb_packet
.status
== USB_RET_ASYNC
) {
1048 usb_device_flush_ep_queue(dev
, ep
);
1049 ohci
->async_td
= addr
;
1053 if (ohci
->usb_packet
.status
== USB_RET_SUCCESS
) {
1054 ret
= ohci
->usb_packet
.actual_length
;
1056 ret
= ohci
->usb_packet
.status
;
1060 if (dir
== OHCI_TD_DIR_IN
) {
1061 if (ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, ret
,
1062 DMA_DIRECTION_FROM_DEVICE
)) {
1065 ohci_td_pkt("IN", ohci
->usb_buf
, pktlen
);
1072 if (ret
== pktlen
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
1073 /* Transmission succeeded. */
1077 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
1078 td
.cbp
= (td
.be
& ~0xfff) + ((td
.cbp
+ ret
) & 0xfff);
1083 td
.flags
|= OHCI_TD_T1
;
1084 td
.flags
^= OHCI_TD_T0
;
1085 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
1086 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
1088 if ((dir
!= OHCI_TD_DIR_IN
) && (ret
!= len
)) {
1089 /* Partial packet transfer: TD not ready to retire yet */
1090 goto exit_no_retire
;
1093 /* Setting ED_C is part of the TD retirement process */
1094 ed
->head
&= ~OHCI_ED_C
;
1095 if (td
.flags
& OHCI_TD_T0
)
1096 ed
->head
|= OHCI_ED_C
;
1099 trace_usb_ohci_td_underrun();
1100 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
1103 case USB_RET_IOERROR
:
1105 trace_usb_ohci_td_dev_error();
1106 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
1109 trace_usb_ohci_td_nak();
1112 trace_usb_ohci_td_stall();
1113 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
1115 case USB_RET_BABBLE
:
1116 trace_usb_ohci_td_babble();
1117 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
1120 trace_usb_ohci_td_bad_device_response(ret
);
1121 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
1122 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
1125 /* An error occured so we have to clear the interrupt counter. See
1126 * spec at 6.4.4 on page 104 */
1127 ohci
->done_count
= 0;
1129 ed
->head
|= OHCI_ED_H
;
1132 /* Retire this TD */
1133 ed
->head
&= ~OHCI_DPTR_MASK
;
1134 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
1135 td
.next
= ohci
->done
;
1137 i
= OHCI_BM(td
.flags
, TD_DI
);
1138 if (i
< ohci
->done_count
)
1139 ohci
->done_count
= i
;
1141 if (ohci_put_td(ohci
, addr
, &td
)) {
1145 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
1148 /* Service an endpoint list. Returns nonzero if active TD were found. */
1149 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
, int completion
)
1155 uint32_t link_cnt
= 0;
1161 for (cur
= head
; cur
&& link_cnt
++ < ED_LINK_LIMIT
; cur
= next_ed
) {
1162 if (ohci_read_ed(ohci
, cur
, &ed
)) {
1163 trace_usb_ohci_ed_read_error(cur
);
1168 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
1170 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
1172 /* Cancel pending packets for ED that have been paused. */
1173 addr
= ed
.head
& OHCI_DPTR_MASK
;
1174 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
1175 usb_cancel_packet(&ohci
->usb_packet
);
1177 usb_device_ep_stopped(ohci
->usb_packet
.ep
->dev
,
1178 ohci
->usb_packet
.ep
);
1183 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
1184 trace_usb_ohci_ed_pkt(cur
, (ed
.head
& OHCI_ED_H
) != 0,
1185 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
1186 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
1187 trace_usb_ohci_ed_pkt_flags(
1188 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
1189 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
1190 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
1191 OHCI_BM(ed
.flags
, ED_MPS
));
1195 if ((ed
.flags
& OHCI_ED_F
) == 0) {
1196 if (ohci_service_td(ohci
, &ed
))
1199 /* Handle isochronous endpoints */
1200 if (ohci_service_iso_td(ohci
, &ed
, completion
))
1205 if (ohci_put_ed(ohci
, cur
, &ed
)) {
1214 /* set a timer for EOF */
1215 static void ohci_eof_timer(OHCIState
*ohci
)
1217 timer_mod(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
1219 /* Set a timer for EOF and generate a SOF event */
1220 static void ohci_sof(OHCIState
*ohci
)
1222 ohci
->sof_time
+= usb_frame_time
;
1223 ohci_eof_timer(ohci
);
1224 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
1227 /* Process Control and Bulk lists. */
1228 static void ohci_process_lists(OHCIState
*ohci
, int completion
)
1230 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
1231 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
) {
1232 trace_usb_ohci_process_lists(ohci
->ctrl_head
, ohci
->ctrl_cur
);
1234 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
, completion
)) {
1236 ohci
->status
&= ~OHCI_STATUS_CLF
;
1240 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
1241 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
, completion
)) {
1243 ohci
->status
&= ~OHCI_STATUS_BLF
;
1248 /* Do frame processing on frame boundary */
1249 static void ohci_frame_boundary(void *opaque
)
1251 OHCIState
*ohci
= opaque
;
1252 struct ohci_hcca hcca
;
1254 if (ohci_read_hcca(ohci
, ohci
->hcca
, &hcca
)) {
1255 trace_usb_ohci_hcca_read_error(ohci
->hcca
);
1260 /* Process all the lists at the end of the frame */
1261 if (ohci
->ctl
& OHCI_CTL_PLE
) {
1264 n
= ohci
->frame_number
& 0x1f;
1265 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]), 0);
1268 /* Cancel all pending packets if either of the lists has been disabled. */
1269 if (ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
1270 if (ohci
->async_td
) {
1271 usb_cancel_packet(&ohci
->usb_packet
);
1274 ohci_stop_endpoints(ohci
);
1276 ohci
->old_ctl
= ohci
->ctl
;
1277 ohci_process_lists(ohci
, 0);
1279 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1280 if (ohci
->intr_status
& OHCI_INTR_UE
) {
1284 /* Frame boundary, so do EOF stuf here */
1285 ohci
->frt
= ohci
->fit
;
1287 /* Increment frame number and take care of endianness. */
1288 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
1289 hcca
.frame
= cpu_to_le16(ohci
->frame_number
);
1291 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
1294 if (ohci
->intr
& ohci
->intr_status
)
1296 hcca
.done
= cpu_to_le32(ohci
->done
);
1298 ohci
->done_count
= 7;
1299 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
1302 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
1305 /* Do SOF stuff here */
1308 /* Writeback HCCA */
1309 if (ohci_put_hcca(ohci
, ohci
->hcca
, &hcca
)) {
1314 /* Start sending SOF tokens across the USB bus, lists are processed in
1317 static int ohci_bus_start(OHCIState
*ohci
)
1319 trace_usb_ohci_start(ohci
->name
);
1321 /* Delay the first SOF event by one frame time as
1322 * linux driver is not ready to receive it and
1323 * can meet some race conditions
1326 ohci
->sof_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1327 ohci_eof_timer(ohci
);
1332 /* Stop sending SOF tokens on the bus */
1333 void ohci_bus_stop(OHCIState
*ohci
)
1335 trace_usb_ohci_stop(ohci
->name
);
1336 timer_del(ohci
->eof_timer
);
1339 /* Sets a flag in a port status register but only set it if the port is
1340 * connected, if not set ConnectStatusChange flag. If flag is enabled
1343 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
1347 /* writing a 0 has no effect */
1351 /* If CurrentConnectStatus is cleared we set
1352 * ConnectStatusChange
1354 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
1355 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
1356 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
1357 /* TODO: CSC is a wakeup event */
1362 if (ohci
->rhport
[i
].ctrl
& val
)
1366 ohci
->rhport
[i
].ctrl
|= val
;
1371 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1372 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
1376 if (val
!= ohci
->fi
) {
1377 trace_usb_ohci_set_frame_interval(ohci
->name
, ohci
->fi
, ohci
->fi
);
1383 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
1386 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
1388 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
1395 /* Set HcControlRegister */
1396 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
1401 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1403 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1405 /* no state change */
1406 if (old_state
== new_state
)
1409 trace_usb_ohci_set_ctl(ohci
->name
, new_state
);
1410 switch (new_state
) {
1411 case OHCI_USB_OPERATIONAL
:
1412 ohci_bus_start(ohci
);
1414 case OHCI_USB_SUSPEND
:
1415 ohci_bus_stop(ohci
);
1416 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1417 ohci
->intr_status
&= ~OHCI_INTR_SF
;
1418 ohci_intr_update(ohci
);
1420 case OHCI_USB_RESUME
:
1421 trace_usb_ohci_resume(ohci
->name
);
1423 case OHCI_USB_RESET
:
1424 ohci_roothub_reset(ohci
);
1429 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
1434 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
1435 return (ohci
->frt
<< 31);
1437 /* Being in USB operational state guarnatees sof_time was
1440 tks
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - ohci
->sof_time
;
1445 /* avoid muldiv if possible */
1446 if (tks
>= usb_frame_time
)
1447 return (ohci
->frt
<< 31);
1449 tks
= tks
/ usb_bit_time
;
1450 fr
= (uint16_t)(ohci
->fi
- tks
);
1452 return (ohci
->frt
<< 31) | fr
;
1456 /* Set root hub status */
1457 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
1461 old_state
= ohci
->rhstatus
;
1463 /* write 1 to clear OCIC */
1464 if (val
& OHCI_RHS_OCIC
)
1465 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
1467 if (val
& OHCI_RHS_LPS
) {
1470 for (i
= 0; i
< ohci
->num_ports
; i
++)
1471 ohci_port_power(ohci
, i
, 0);
1472 trace_usb_ohci_hub_power_down();
1475 if (val
& OHCI_RHS_LPSC
) {
1478 for (i
= 0; i
< ohci
->num_ports
; i
++)
1479 ohci_port_power(ohci
, i
, 1);
1480 trace_usb_ohci_hub_power_up();
1483 if (val
& OHCI_RHS_DRWE
)
1484 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
1486 if (val
& OHCI_RHS_CRWE
)
1487 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
1489 if (old_state
!= ohci
->rhstatus
)
1490 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1493 /* Set root hub port status */
1494 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
1499 port
= &ohci
->rhport
[portnum
];
1500 old_state
= port
->ctrl
;
1502 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1503 if (val
& OHCI_PORT_WTC
)
1504 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1506 if (val
& OHCI_PORT_CCS
)
1507 port
->ctrl
&= ~OHCI_PORT_PES
;
1509 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1511 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
)) {
1512 trace_usb_ohci_port_suspend(portnum
);
1515 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1516 trace_usb_ohci_port_reset(portnum
);
1517 usb_device_reset(port
->port
.dev
);
1518 port
->ctrl
&= ~OHCI_PORT_PRS
;
1519 /* ??? Should this also set OHCI_PORT_PESC. */
1520 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1523 /* Invert order here to ensure in ambiguous case, device is
1526 if (val
& OHCI_PORT_LSDA
)
1527 ohci_port_power(ohci
, portnum
, 0);
1528 if (val
& OHCI_PORT_PPS
)
1529 ohci_port_power(ohci
, portnum
, 1);
1531 if (old_state
!= port
->ctrl
)
1532 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1535 static uint64_t ohci_mem_read(void *opaque
,
1539 OHCIState
*ohci
= opaque
;
1542 /* Only aligned reads are allowed on OHCI */
1544 trace_usb_ohci_mem_read_unaligned(addr
);
1546 } else if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1547 /* HcRhPortStatus */
1548 retval
= ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1550 switch (addr
>> 2) {
1551 case 0: /* HcRevision */
1555 case 1: /* HcControl */
1559 case 2: /* HcCommandStatus */
1560 retval
= ohci
->status
;
1563 case 3: /* HcInterruptStatus */
1564 retval
= ohci
->intr_status
;
1567 case 4: /* HcInterruptEnable */
1568 case 5: /* HcInterruptDisable */
1569 retval
= ohci
->intr
;
1572 case 6: /* HcHCCA */
1573 retval
= ohci
->hcca
;
1576 case 7: /* HcPeriodCurrentED */
1577 retval
= ohci
->per_cur
;
1580 case 8: /* HcControlHeadED */
1581 retval
= ohci
->ctrl_head
;
1584 case 9: /* HcControlCurrentED */
1585 retval
= ohci
->ctrl_cur
;
1588 case 10: /* HcBulkHeadED */
1589 retval
= ohci
->bulk_head
;
1592 case 11: /* HcBulkCurrentED */
1593 retval
= ohci
->bulk_cur
;
1596 case 12: /* HcDoneHead */
1597 retval
= ohci
->done
;
1600 case 13: /* HcFmInterretval */
1601 retval
= (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1604 case 14: /* HcFmRemaining */
1605 retval
= ohci_get_frame_remaining(ohci
);
1608 case 15: /* HcFmNumber */
1609 retval
= ohci
->frame_number
;
1612 case 16: /* HcPeriodicStart */
1613 retval
= ohci
->pstart
;
1616 case 17: /* HcLSThreshold */
1620 case 18: /* HcRhDescriptorA */
1621 retval
= ohci
->rhdesc_a
;
1624 case 19: /* HcRhDescriptorB */
1625 retval
= ohci
->rhdesc_b
;
1628 case 20: /* HcRhStatus */
1629 retval
= ohci
->rhstatus
;
1632 /* PXA27x specific registers */
1633 case 24: /* HcStatus */
1634 retval
= ohci
->hstatus
& ohci
->hmask
;
1637 case 25: /* HcHReset */
1638 retval
= ohci
->hreset
;
1641 case 26: /* HcHInterruptEnable */
1642 retval
= ohci
->hmask
;
1645 case 27: /* HcHInterruptTest */
1646 retval
= ohci
->htest
;
1650 trace_usb_ohci_mem_read_bad_offset(addr
);
1651 retval
= 0xffffffff;
1658 static void ohci_mem_write(void *opaque
,
1663 OHCIState
*ohci
= opaque
;
1665 /* Only aligned reads are allowed on OHCI */
1667 trace_usb_ohci_mem_write_unaligned(addr
);
1671 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1672 /* HcRhPortStatus */
1673 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1677 switch (addr
>> 2) {
1678 case 1: /* HcControl */
1679 ohci_set_ctl(ohci
, val
);
1682 case 2: /* HcCommandStatus */
1683 /* SOC is read-only */
1684 val
= (val
& ~OHCI_STATUS_SOC
);
1686 /* Bits written as '0' remain unchanged in the register */
1687 ohci
->status
|= val
;
1689 if (ohci
->status
& OHCI_STATUS_HCR
)
1690 ohci_soft_reset(ohci
);
1693 case 3: /* HcInterruptStatus */
1694 ohci
->intr_status
&= ~val
;
1695 ohci_intr_update(ohci
);
1698 case 4: /* HcInterruptEnable */
1700 ohci_intr_update(ohci
);
1703 case 5: /* HcInterruptDisable */
1705 ohci_intr_update(ohci
);
1708 case 6: /* HcHCCA */
1709 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1712 case 7: /* HcPeriodCurrentED */
1713 /* Ignore writes to this read-only register, Linux does them */
1716 case 8: /* HcControlHeadED */
1717 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1720 case 9: /* HcControlCurrentED */
1721 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1724 case 10: /* HcBulkHeadED */
1725 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1728 case 11: /* HcBulkCurrentED */
1729 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1732 case 13: /* HcFmInterval */
1733 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1734 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1735 ohci_set_frame_interval(ohci
, val
);
1738 case 15: /* HcFmNumber */
1741 case 16: /* HcPeriodicStart */
1742 ohci
->pstart
= val
& 0xffff;
1745 case 17: /* HcLSThreshold */
1746 ohci
->lst
= val
& 0xffff;
1749 case 18: /* HcRhDescriptorA */
1750 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1751 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1754 case 19: /* HcRhDescriptorB */
1757 case 20: /* HcRhStatus */
1758 ohci_set_hub_status(ohci
, val
);
1761 /* PXA27x specific registers */
1762 case 24: /* HcStatus */
1763 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1766 case 25: /* HcHReset */
1767 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1768 if (val
& OHCI_HRESET_FSBIR
)
1769 ohci_hard_reset(ohci
);
1772 case 26: /* HcHInterruptEnable */
1776 case 27: /* HcHInterruptTest */
1781 trace_usb_ohci_mem_write_bad_offset(addr
);
1786 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
)
1788 if (ohci
->async_td
&&
1789 usb_packet_is_inflight(&ohci
->usb_packet
) &&
1790 ohci
->usb_packet
.ep
->dev
== dev
) {
1791 usb_cancel_packet(&ohci
->usb_packet
);
1796 static const MemoryRegionOps ohci_mem_ops
= {
1797 .read
= ohci_mem_read
,
1798 .write
= ohci_mem_write
,
1799 .endianness
= DEVICE_LITTLE_ENDIAN
,
1802 static USBPortOps ohci_port_ops
= {
1803 .attach
= ohci_attach
,
1804 .detach
= ohci_detach
,
1805 .child_detach
= ohci_child_detach
,
1806 .wakeup
= ohci_wakeup
,
1807 .complete
= ohci_async_complete_packet
,
1810 static USBBusOps ohci_bus_ops
= {
1813 void usb_ohci_init(OHCIState
*ohci
, DeviceState
*dev
, uint32_t num_ports
,
1814 dma_addr_t localmem_base
, char *masterbus
,
1815 uint32_t firstport
, AddressSpace
*as
,
1816 void (*ohci_die_fn
)(struct OHCIState
*), Error
**errp
)
1822 ohci
->ohci_die
= ohci_die_fn
;
1824 if (num_ports
> OHCI_MAX_PORTS
) {
1825 error_setg(errp
, "OHCI num-ports=%u is too big (limit is %u ports)",
1826 num_ports
, OHCI_MAX_PORTS
);
1830 if (usb_frame_time
== 0) {
1831 #ifdef OHCI_TIME_WARP
1832 usb_frame_time
= NANOSECONDS_PER_SECOND
;
1833 usb_bit_time
= NANOSECONDS_PER_SECOND
/ (USB_HZ
/ 1000);
1835 usb_frame_time
= NANOSECONDS_PER_SECOND
/ 1000;
1836 if (NANOSECONDS_PER_SECOND
>= USB_HZ
) {
1837 usb_bit_time
= NANOSECONDS_PER_SECOND
/ USB_HZ
;
1842 trace_usb_ohci_init_time(usb_frame_time
, usb_bit_time
);
1845 ohci
->num_ports
= num_ports
;
1847 USBPort
*ports
[OHCI_MAX_PORTS
];
1848 for(i
= 0; i
< num_ports
; i
++) {
1849 ports
[i
] = &ohci
->rhport
[i
].port
;
1851 usb_register_companion(masterbus
, ports
, num_ports
,
1852 firstport
, ohci
, &ohci_port_ops
,
1853 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
,
1856 error_propagate(errp
, err
);
1860 usb_bus_new(&ohci
->bus
, sizeof(ohci
->bus
), &ohci_bus_ops
, dev
);
1861 for (i
= 0; i
< num_ports
; i
++) {
1862 usb_register_port(&ohci
->bus
, &ohci
->rhport
[i
].port
,
1863 ohci
, i
, &ohci_port_ops
,
1864 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1868 memory_region_init_io(&ohci
->mem
, OBJECT(dev
), &ohci_mem_ops
,
1870 ohci
->localmem_base
= localmem_base
;
1872 ohci
->name
= object_get_typename(OBJECT(dev
));
1873 usb_packet_init(&ohci
->usb_packet
);
1877 ohci
->eof_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
1878 ohci_frame_boundary
, ohci
);
1882 * A typical OHCI will stop operating and set itself into error state
1883 * (which can be queried by MMIO) to signal that it got an error.
1885 void ohci_sysbus_die(struct OHCIState
*ohci
)
1887 trace_usb_ohci_die();
1889 ohci_set_interrupt(ohci
, OHCI_INTR_UE
);
1890 ohci_bus_stop(ohci
);
1893 static void ohci_realize_pxa(DeviceState
*dev
, Error
**errp
)
1895 OHCISysBusState
*s
= SYSBUS_OHCI(dev
);
1896 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1899 usb_ohci_init(&s
->ohci
, dev
, s
->num_ports
, s
->dma_offset
,
1900 s
->masterbus
, s
->firstport
,
1901 &address_space_memory
, ohci_sysbus_die
, &err
);
1903 error_propagate(errp
, err
);
1906 sysbus_init_irq(sbd
, &s
->ohci
.irq
);
1907 sysbus_init_mmio(sbd
, &s
->ohci
.mem
);
1910 static void usb_ohci_reset_sysbus(DeviceState
*dev
)
1912 OHCISysBusState
*s
= SYSBUS_OHCI(dev
);
1913 OHCIState
*ohci
= &s
->ohci
;
1915 ohci_hard_reset(ohci
);
1918 static const VMStateDescription vmstate_ohci_state_port
= {
1919 .name
= "ohci-core/port",
1921 .minimum_version_id
= 1,
1922 .fields
= (VMStateField
[]) {
1923 VMSTATE_UINT32(ctrl
, OHCIPort
),
1924 VMSTATE_END_OF_LIST()
1928 static bool ohci_eof_timer_needed(void *opaque
)
1930 OHCIState
*ohci
= opaque
;
1932 return timer_pending(ohci
->eof_timer
);
1935 static const VMStateDescription vmstate_ohci_eof_timer
= {
1936 .name
= "ohci-core/eof-timer",
1938 .minimum_version_id
= 1,
1939 .needed
= ohci_eof_timer_needed
,
1940 .fields
= (VMStateField
[]) {
1941 VMSTATE_TIMER_PTR(eof_timer
, OHCIState
),
1942 VMSTATE_END_OF_LIST()
1946 const VMStateDescription vmstate_ohci_state
= {
1947 .name
= "ohci-core",
1949 .minimum_version_id
= 1,
1950 .fields
= (VMStateField
[]) {
1951 VMSTATE_INT64(sof_time
, OHCIState
),
1952 VMSTATE_UINT32(ctl
, OHCIState
),
1953 VMSTATE_UINT32(status
, OHCIState
),
1954 VMSTATE_UINT32(intr_status
, OHCIState
),
1955 VMSTATE_UINT32(intr
, OHCIState
),
1956 VMSTATE_UINT32(hcca
, OHCIState
),
1957 VMSTATE_UINT32(ctrl_head
, OHCIState
),
1958 VMSTATE_UINT32(ctrl_cur
, OHCIState
),
1959 VMSTATE_UINT32(bulk_head
, OHCIState
),
1960 VMSTATE_UINT32(bulk_cur
, OHCIState
),
1961 VMSTATE_UINT32(per_cur
, OHCIState
),
1962 VMSTATE_UINT32(done
, OHCIState
),
1963 VMSTATE_INT32(done_count
, OHCIState
),
1964 VMSTATE_UINT16(fsmps
, OHCIState
),
1965 VMSTATE_UINT8(fit
, OHCIState
),
1966 VMSTATE_UINT16(fi
, OHCIState
),
1967 VMSTATE_UINT8(frt
, OHCIState
),
1968 VMSTATE_UINT16(frame_number
, OHCIState
),
1969 VMSTATE_UINT16(padding
, OHCIState
),
1970 VMSTATE_UINT32(pstart
, OHCIState
),
1971 VMSTATE_UINT32(lst
, OHCIState
),
1972 VMSTATE_UINT32(rhdesc_a
, OHCIState
),
1973 VMSTATE_UINT32(rhdesc_b
, OHCIState
),
1974 VMSTATE_UINT32(rhstatus
, OHCIState
),
1975 VMSTATE_STRUCT_ARRAY(rhport
, OHCIState
, OHCI_MAX_PORTS
, 0,
1976 vmstate_ohci_state_port
, OHCIPort
),
1977 VMSTATE_UINT32(hstatus
, OHCIState
),
1978 VMSTATE_UINT32(hmask
, OHCIState
),
1979 VMSTATE_UINT32(hreset
, OHCIState
),
1980 VMSTATE_UINT32(htest
, OHCIState
),
1981 VMSTATE_UINT32(old_ctl
, OHCIState
),
1982 VMSTATE_UINT8_ARRAY(usb_buf
, OHCIState
, 8192),
1983 VMSTATE_UINT32(async_td
, OHCIState
),
1984 VMSTATE_BOOL(async_complete
, OHCIState
),
1985 VMSTATE_END_OF_LIST()
1987 .subsections
= (const VMStateDescription
*[]) {
1988 &vmstate_ohci_eof_timer
,
1993 static Property ohci_sysbus_properties
[] = {
1994 DEFINE_PROP_STRING("masterbus", OHCISysBusState
, masterbus
),
1995 DEFINE_PROP_UINT32("num-ports", OHCISysBusState
, num_ports
, 3),
1996 DEFINE_PROP_UINT32("firstport", OHCISysBusState
, firstport
, 0),
1997 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState
, dma_offset
, 0),
1998 DEFINE_PROP_END_OF_LIST(),
2001 static void ohci_sysbus_class_init(ObjectClass
*klass
, void *data
)
2003 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2005 dc
->realize
= ohci_realize_pxa
;
2006 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
2007 dc
->desc
= "OHCI USB Controller";
2008 device_class_set_props(dc
, ohci_sysbus_properties
);
2009 dc
->reset
= usb_ohci_reset_sysbus
;
2012 static const TypeInfo ohci_sysbus_info
= {
2013 .name
= TYPE_SYSBUS_OHCI
,
2014 .parent
= TYPE_SYS_BUS_DEVICE
,
2015 .instance_size
= sizeof(OHCISysBusState
),
2016 .class_init
= ohci_sysbus_class_init
,
2019 static void ohci_register_types(void)
2021 type_register_static(&ohci_sysbus_info
);
2024 type_init(ohci_register_types
)