target/mips/cpu.h

   1 #ifndef MIPS_CPU_H
   2 #define MIPS_CPU_H
   3
   4 #define ALIGNED_ONLY
   5
   6 #include "cpu-qom.h"
   7 #include "exec/cpu-defs.h"
   8 #include "fpu/softfloat.h"
   9 #include "mips-defs.h"
  10
  11 #define TCG_GUEST_DEFAULT_MO (0)
  12
  13 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  14
  15 /* MSA Context */
  16 #define MSA_WRLEN (128)
  17
  18 typedef union wr_t wr_t;
  19 union wr_t {
  20     int8_t  b[MSA_WRLEN / 8];
  21     int16_t h[MSA_WRLEN / 16];
  22     int32_t w[MSA_WRLEN / 32];
  23     int64_t d[MSA_WRLEN / 64];
  24 };
  25
  26 typedef union fpr_t fpr_t;
  27 union fpr_t {
  28     float64  fd;   /* ieee double precision */
  29     float32  fs[2];/* ieee single precision */
  30     uint64_t d;    /* binary double fixed-point */
  31     uint32_t w[2]; /* binary single fixed-point */
  32 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  33     wr_t     wr;   /* vector data */
  34 };
  35 /*
  36  *define FP_ENDIAN_IDX to access the same location
  37  * in the fpr_t union regardless of the host endianness
  38  */
  39 #if defined(HOST_WORDS_BIGENDIAN)
  40 #  define FP_ENDIAN_IDX 1
  41 #else
  42 #  define FP_ENDIAN_IDX 0
  43 #endif
  44
  45 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  46 struct CPUMIPSFPUContext {
  47     /* Floating point registers */
  48     fpr_t fpr[32];
  49     float_status fp_status;
  50     /* fpu implementation/revision register (fir) */
  51     uint32_t fcr0;
  52 #define FCR0_FREP 29
  53 #define FCR0_UFRP 28
  54 #define FCR0_HAS2008 23
  55 #define FCR0_F64 22
  56 #define FCR0_L 21
  57 #define FCR0_W 20
  58 #define FCR0_3D 19
  59 #define FCR0_PS 18
  60 #define FCR0_D 17
  61 #define FCR0_S 16
  62 #define FCR0_PRID 8
  63 #define FCR0_REV 0
  64     /* fcsr */
  65     uint32_t fcr31_rw_bitmask;
  66     uint32_t fcr31;
  67 #define FCR31_FS 24
  68 #define FCR31_ABS2008 19
  69 #define FCR31_NAN2008 18
  70 #define SET_FP_COND(num, env)     do { ((env).fcr31) |=                 \
  71                                        ((num) ? (1 << ((num) + 24)) :   \
  72                                                 (1 << 23));             \
  73                                      } while (0)
  74 #define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &=                 \
  75                                        ~((num) ? (1 << ((num) + 24)) :  \
  76                                                  (1 << 23));            \
  77                                      } while (0)
  78 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) |        \
  79                                  (((env).fcr31 >> 23) & 0x1))
  80 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  81 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  82 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  83 #define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | \
  84                                                ((v & 0x3f) << 12);       \
  85                                      } while (0)
  86 #define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | \
  87                                                ((v & 0x1f) << 7);        \
  88                                      } while (0)
  89 #define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | \
  90                                                ((v & 0x1f) << 2);        \
  91                                      } while (0)
  92 #define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
  93 #define FP_INEXACT        1
  94 #define FP_UNDERFLOW      2
  95 #define FP_OVERFLOW       4
  96 #define FP_DIV0           8
  97 #define FP_INVALID        16
  98 #define FP_UNIMPLEMENTED  32
  99 };
 100
 101 #define TARGET_INSN_START_EXTRA_WORDS 2
 102
 103 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 104 struct CPUMIPSMVPContext {
 105     int32_t CP0_MVPControl;
 106 #define CP0MVPCo_CPA    3
 107 #define CP0MVPCo_STLB   2
 108 #define CP0MVPCo_VPC    1
 109 #define CP0MVPCo_EVP    0
 110     int32_t CP0_MVPConf0;
 111 #define CP0MVPC0_M      31
 112 #define CP0MVPC0_TLBS   29
 113 #define CP0MVPC0_GS     28
 114 #define CP0MVPC0_PCP    27
 115 #define CP0MVPC0_PTLBE  16
 116 #define CP0MVPC0_TCA    15
 117 #define CP0MVPC0_PVPE   10
 118 #define CP0MVPC0_PTC    0
 119     int32_t CP0_MVPConf1;
 120 #define CP0MVPC1_CIM    31
 121 #define CP0MVPC1_CIF    30
 122 #define CP0MVPC1_PCX    20
 123 #define CP0MVPC1_PCP2   10
 124 #define CP0MVPC1_PCP1   0
 125 };
 126
 127 typedef struct mips_def_t mips_def_t;
 128
 129 #define MIPS_SHADOW_SET_MAX 16
 130 #define MIPS_TC_MAX 5
 131 #define MIPS_FPU_MAX 1
 132 #define MIPS_DSP_ACC 4
 133 #define MIPS_KSCRATCH_NUM 6
 134 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 135
 136
 137 /*
 138  *     Summary of CP0 registers
 139  *     ========================
 140  *
 141  *
 142  *     Register 0        Register 1        Register 2        Register 3
 143  *     ----------        ----------        ----------        ----------
 144  *
 145  * 0   Index             Random            EntryLo0          EntryLo1
 146  * 1   MVPControl        VPEControl        TCStatus          GlobalNumber
 147  * 2   MVPConf0          VPEConf0          TCBind
 148  * 3   MVPConf1          VPEConf1          TCRestart
 149  * 4   VPControl         YQMask            TCHalt
 150  * 5                     VPESchedule       TCContext
 151  * 6                     VPEScheFBack      TCSchedule
 152  * 7                     VPEOpt            TCScheFBack       TCOpt
 153  *
 154  *
 155  *     Register 4        Register 5        Register 6        Register 7
 156  *     ----------        ----------        ----------        ----------
 157  *
 158  * 0   Context           PageMask          Wired             HWREna
 159  * 1   ContextConfig     PageGrain         SRSConf0
 160  * 2   UserLocal         SegCtl0           SRSConf1
 161  * 3   XContextConfig    SegCtl1           SRSConf2
 162  * 4   DebugContextID    SegCtl2           SRSConf3
 163  * 5   MemoryMapID       PWBase            SRSConf4
 164  * 6                     PWField           PWCtl
 165  * 7                     PWSize
 166  *
 167  *
 168  *     Register 8        Register 9        Register 10       Register 11
 169  *     ----------        ----------        -----------       -----------
 170  *
 171  * 0   BadVAddr          Count             EntryHi           Compare
 172  * 1   BadInstr
 173  * 2   BadInstrP
 174  * 3   BadInstrX
 175  * 4                                       GuestCtl1         GuestCtl0Ext
 176  * 5                                       GuestCtl2
 177  * 6                     SAARI             GuestCtl3
 178  * 7                     SAAR
 179  *
 180  *
 181  *     Register 12       Register 13       Register 14       Register 15
 182  *     -----------       -----------       -----------       -----------
 183  *
 184  * 0   Status            Cause             EPC               PRId
 185  * 1   IntCtl                                                EBase
 186  * 2   SRSCtl                              NestedEPC         CDMMBase
 187  * 3   SRSMap                                                CMGCRBase
 188  * 4   View_IPL          View_RIPL                           BEVVA
 189  * 5   SRSMap2           NestedExc
 190  * 6   GuestCtl0
 191  * 7   GTOffset
 192  *
 193  *
 194  *     Register 16       Register 17       Register 18       Register 19
 195  *     -----------       -----------       -----------       -----------
 196  *
 197  * 0   Config            LLAddr            WatchLo           WatchHi
 198  * 1   Config1           MAAR              WatchLo           WatchHi
 199  * 2   Config2           MAARI             WatchLo           WatchHi
 200  * 3   Config3                             WatchLo           WatchHi
 201  * 4   Config4                             WatchLo           WatchHi
 202  * 5   Config5                             WatchLo           WatchHi
 203  * 6                                       WatchLo           WatchHi
 204  * 7                                       WatchLo           WatchHi
 205  *
 206  *
 207  *     Register 20       Register 21       Register 22       Register 23
 208  *     -----------       -----------       -----------       -----------
 209  *
 210  * 0   XContext                                              Debug
 211  * 1                                                         TraceControl
 212  * 2                                                         TraceControl2
 213  * 3                                                         UserTraceData1
 214  * 4                                                         TraceIBPC
 215  * 5                                                         TraceDBPC
 216  * 6                                                         Debug2
 217  * 7
 218  *
 219  *
 220  *     Register 24       Register 25       Register 26       Register 27
 221  *     -----------       -----------       -----------       -----------
 222  *
 223  * 0   DEPC              PerfCnt            ErrCtl          CacheErr
 224  * 1                     PerfCnt
 225  * 2   TraceControl3     PerfCnt
 226  * 3   UserTraceData2    PerfCnt
 227  * 4                     PerfCnt
 228  * 5                     PerfCnt
 229  * 6                     PerfCnt
 230  * 7                     PerfCnt
 231  *
 232  *
 233  *     Register 28       Register 29       Register 30       Register 31
 234  *     -----------       -----------       -----------       -----------
 235  *
 236  * 0   DataLo            DataHi            ErrorEPC          DESAVE
 237  * 1   TagLo             TagHi
 238  * 2   DataLo            DataHi                              KScratch<n>
 239  * 3   TagLo             TagHi                               KScratch<n>
 240  * 4   DataLo            DataHi                              KScratch<n>
 241  * 5   TagLo             TagHi                               KScratch<n>
 242  * 6   DataLo            DataHi                              KScratch<n>
 243  * 7   TagLo             TagHi                               KScratch<n>
 244  *
 245  */
 246 #define CP0_REGISTER_00     0
 247 #define CP0_REGISTER_01     1
 248 #define CP0_REGISTER_02     2
 249 #define CP0_REGISTER_03     3
 250 #define CP0_REGISTER_04     4
 251 #define CP0_REGISTER_05     5
 252 #define CP0_REGISTER_06     6
 253 #define CP0_REGISTER_07     7
 254 #define CP0_REGISTER_08     8
 255 #define CP0_REGISTER_09     9
 256 #define CP0_REGISTER_10    10
 257 #define CP0_REGISTER_11    11
 258 #define CP0_REGISTER_12    12
 259 #define CP0_REGISTER_13    13
 260 #define CP0_REGISTER_14    14
 261 #define CP0_REGISTER_15    15
 262 #define CP0_REGISTER_16    16
 263 #define CP0_REGISTER_17    17
 264 #define CP0_REGISTER_18    18
 265 #define CP0_REGISTER_19    19
 266 #define CP0_REGISTER_20    20
 267 #define CP0_REGISTER_21    21
 268 #define CP0_REGISTER_22    22
 269 #define CP0_REGISTER_23    23
 270 #define CP0_REGISTER_24    24
 271 #define CP0_REGISTER_25    25
 272 #define CP0_REGISTER_26    26
 273 #define CP0_REGISTER_27    27
 274 #define CP0_REGISTER_28    28
 275 #define CP0_REGISTER_29    29
 276 #define CP0_REGISTER_30    30
 277 #define CP0_REGISTER_31    31
 278
 279
 280 /* CP0 Register 00 */
 281 #define CP0_REG00__INDEX           0
 282 #define CP0_REG00__VPCONTROL       4
 283 /* CP0 Register 01 */
 284 /* CP0 Register 02 */
 285 #define CP0_REG02__ENTRYLO0        0
 286 /* CP0 Register 03 */
 287 #define CP0_REG03__ENTRYLO1        0
 288 #define CP0_REG03__GLOBALNUM       1
 289 /* CP0 Register 04 */
 290 #define CP0_REG04__CONTEXT         0
 291 #define CP0_REG04__USERLOCAL       2
 292 #define CP0_REG04__DBGCONTEXTID    4
 293 #define CP0_REG00__MMID            5
 294 /* CP0 Register 05 */
 295 #define CP0_REG05__PAGEMASK        0
 296 #define CP0_REG05__PAGEGRAIN       1
 297 /* CP0 Register 06 */
 298 #define CP0_REG06__WIRED           0
 299 /* CP0 Register 07 */
 300 #define CP0_REG07__HWRENA          0
 301 /* CP0 Register 08 */
 302 #define CP0_REG08__BADVADDR        0
 303 #define CP0_REG08__BADINSTR        1
 304 #define CP0_REG08__BADINSTRP       2
 305 /* CP0 Register 09 */
 306 #define CP0_REG09__COUNT           0
 307 #define CP0_REG09__SAARI           6
 308 #define CP0_REG09__SAAR            7
 309 /* CP0 Register 10 */
 310 #define CP0_REG10__ENTRYHI         0
 311 #define CP0_REG10__GUESTCTL1       4
 312 #define CP0_REG10__GUESTCTL2       5
 313 /* CP0 Register 11 */
 314 #define CP0_REG11__COMPARE         0
 315 #define CP0_REG11__GUESTCTL0EXT    4
 316 /* CP0 Register 12 */
 317 #define CP0_REG12__STATUS          0
 318 #define CP0_REG12__INTCTL          1
 319 #define CP0_REG12__SRSCTL          2
 320 #define CP0_REG12__GUESTCTL0       6
 321 #define CP0_REG12__GTOFFSET        7
 322 /* CP0 Register 13 */
 323 #define CP0_REG13__CAUSE           0
 324 /* CP0 Register 14 */
 325 #define CP0_REG14__EPC             0
 326 /* CP0 Register 15 */
 327 #define CP0_REG15__PRID            0
 328 #define CP0_REG15__EBASE           1
 329 #define CP0_REG15__CDMMBASE        2
 330 #define CP0_REG15__CMGCRBASE       3
 331 /* CP0 Register 16 */
 332 #define CP0_REG16__CONFIG          0
 333 #define CP0_REG16__CONFIG1         1
 334 #define CP0_REG16__CONFIG2         2
 335 #define CP0_REG16__CONFIG3         3
 336 #define CP0_REG16__CONFIG4         4
 337 #define CP0_REG16__CONFIG5         5
 338 #define CP0_REG00__CONFIG7         7
 339 /* CP0 Register 17 */
 340 #define CP0_REG17__LLADDR          0
 341 #define CP0_REG17__MAAR            1
 342 #define CP0_REG17__MAARI           2
 343 /* CP0 Register 18 */
 344 #define CP0_REG18__WATCHLO0        0
 345 #define CP0_REG18__WATCHLO1        1
 346 #define CP0_REG18__WATCHLO2        2
 347 #define CP0_REG18__WATCHLO3        3
 348 /* CP0 Register 19 */
 349 #define CP0_REG19__WATCHHI0        0
 350 #define CP0_REG19__WATCHHI1        1
 351 #define CP0_REG19__WATCHHI2        2
 352 #define CP0_REG19__WATCHHI3        3
 353 /* CP0 Register 20 */
 354 #define CP0_REG20__XCONTEXT        0
 355 /* CP0 Register 21 */
 356 /* CP0 Register 22 */
 357 /* CP0 Register 23 */
 358 #define CP0_REG23__DEBUG           0
 359 /* CP0 Register 24 */
 360 #define CP0_REG24__DEPC            0
 361 /* CP0 Register 25 */
 362 #define CP0_REG25__PERFCTL0        0
 363 #define CP0_REG25__PERFCNT0        1
 364 #define CP0_REG25__PERFCTL1        2
 365 #define CP0_REG25__PERFCNT1        3
 366 #define CP0_REG25__PERFCTL2        4
 367 #define CP0_REG25__PERFCNT2        5
 368 #define CP0_REG25__PERFCTL3        6
 369 #define CP0_REG25__PERFCNT3        7
 370 /* CP0 Register 26 */
 371 #define CP0_REG00__ERRCTL          0
 372 /* CP0 Register 27 */
 373 #define CP0_REG27__CACHERR         0
 374 /* CP0 Register 28 */
 375 #define CP0_REG28__ITAGLO          0
 376 #define CP0_REG28__IDATALO         1
 377 #define CP0_REG28__DTAGLO          2
 378 #define CP0_REG28__DDATALO         3
 379 /* CP0 Register 29 */
 380 #define CP0_REG29__IDATAHI         1
 381 #define CP0_REG29__DDATAHI         3
 382 /* CP0 Register 30 */
 383 #define CP0_REG30__ERROREPC        0
 384 /* CP0 Register 31 */
 385 #define CP0_REG31__DESAVE          0
 386 #define CP0_REG31__KSCRATCH1       2
 387 #define CP0_REG31__KSCRATCH2       3
 388 #define CP0_REG31__KSCRATCH3       4
 389 #define CP0_REG31__KSCRATCH4       5
 390 #define CP0_REG31__KSCRATCH5       6
 391 #define CP0_REG31__KSCRATCH6       7
 392
 393
 394 typedef struct TCState TCState;
 395 struct TCState {
 396     target_ulong gpr[32];
 397     target_ulong PC;
 398     target_ulong HI[MIPS_DSP_ACC];
 399     target_ulong LO[MIPS_DSP_ACC];
 400     target_ulong ACX[MIPS_DSP_ACC];
 401     target_ulong DSPControl;
 402     int32_t CP0_TCStatus;
 403 #define CP0TCSt_TCU3    31
 404 #define CP0TCSt_TCU2    30
 405 #define CP0TCSt_TCU1    29
 406 #define CP0TCSt_TCU0    28
 407 #define CP0TCSt_TMX     27
 408 #define CP0TCSt_RNST    23
 409 #define CP0TCSt_TDS     21
 410 #define CP0TCSt_DT      20
 411 #define CP0TCSt_DA      15
 412 #define CP0TCSt_A       13
 413 #define CP0TCSt_TKSU    11
 414 #define CP0TCSt_IXMT    10
 415 #define CP0TCSt_TASID   0
 416     int32_t CP0_TCBind;
 417 #define CP0TCBd_CurTC   21
 418 #define CP0TCBd_TBE     17
 419 #define CP0TCBd_CurVPE  0
 420     target_ulong CP0_TCHalt;
 421     target_ulong CP0_TCContext;
 422     target_ulong CP0_TCSchedule;
 423     target_ulong CP0_TCScheFBack;
 424     int32_t CP0_Debug_tcstatus;
 425     target_ulong CP0_UserLocal;
 426
 427     int32_t msacsr;
 428
 429 #define MSACSR_FS       24
 430 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 431 #define MSACSR_NX       18
 432 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 433 #define MSACSR_CEF      2
 434 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 435 #define MSACSR_RM       0
 436 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 437 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 438         MSACSR_FS_MASK)
 439
 440     float_status msa_fp_status;
 441
 442     /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
 443     uint64_t mmr[32];
 444
 445 #define NUMBER_OF_MXU_REGISTERS 16
 446     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
 447     target_ulong mxu_cr;
 448 #define MXU_CR_LC       31
 449 #define MXU_CR_RC       30
 450 #define MXU_CR_BIAS     2
 451 #define MXU_CR_RD_EN    1
 452 #define MXU_CR_MXU_EN   0
 453
 454 };
 455
 456 struct MIPSITUState;
 457 typedef struct CPUMIPSState CPUMIPSState;
 458 struct CPUMIPSState {
 459     TCState active_tc;
 460     CPUMIPSFPUContext active_fpu;
 461
 462     uint32_t current_tc;
 463     uint32_t current_fpu;
 464
 465     uint32_t SEGBITS;
 466     uint32_t PABITS;
 467 #if defined(TARGET_MIPS64)
 468 # define PABITS_BASE 36
 469 #else
 470 # define PABITS_BASE 32
 471 #endif
 472     target_ulong SEGMask;
 473     uint64_t PAMask;
 474 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 475
 476     int32_t msair;
 477 #define MSAIR_ProcID    8
 478 #define MSAIR_Rev       0
 479
 480 /*
 481  * CP0 Register 0
 482  */
 483     int32_t CP0_Index;
 484     /* CP0_MVP* are per MVP registers. */
 485     int32_t CP0_VPControl;
 486 #define CP0VPCtl_DIS    0
 487 /*
 488  * CP0 Register 1
 489  */
 490     int32_t CP0_Random;
 491     int32_t CP0_VPEControl;
 492 #define CP0VPECo_YSI    21
 493 #define CP0VPECo_GSI    20
 494 #define CP0VPECo_EXCPT  16
 495 #define CP0VPECo_TE     15
 496 #define CP0VPECo_TargTC 0
 497     int32_t CP0_VPEConf0;
 498 #define CP0VPEC0_M      31
 499 #define CP0VPEC0_XTC    21
 500 #define CP0VPEC0_TCS    19
 501 #define CP0VPEC0_SCS    18
 502 #define CP0VPEC0_DSC    17
 503 #define CP0VPEC0_ICS    16
 504 #define CP0VPEC0_MVP    1
 505 #define CP0VPEC0_VPA    0
 506     int32_t CP0_VPEConf1;
 507 #define CP0VPEC1_NCX    20
 508 #define CP0VPEC1_NCP2   10
 509 #define CP0VPEC1_NCP1   0
 510     target_ulong CP0_YQMask;
 511     target_ulong CP0_VPESchedule;
 512     target_ulong CP0_VPEScheFBack;
 513     int32_t CP0_VPEOpt;
 514 #define CP0VPEOpt_IWX7  15
 515 #define CP0VPEOpt_IWX6  14
 516 #define CP0VPEOpt_IWX5  13
 517 #define CP0VPEOpt_IWX4  12
 518 #define CP0VPEOpt_IWX3  11
 519 #define CP0VPEOpt_IWX2  10
 520 #define CP0VPEOpt_IWX1  9
 521 #define CP0VPEOpt_IWX0  8
 522 #define CP0VPEOpt_DWX7  7
 523 #define CP0VPEOpt_DWX6  6
 524 #define CP0VPEOpt_DWX5  5
 525 #define CP0VPEOpt_DWX4  4
 526 #define CP0VPEOpt_DWX3  3
 527 #define CP0VPEOpt_DWX2  2
 528 #define CP0VPEOpt_DWX1  1
 529 #define CP0VPEOpt_DWX0  0
 530 /*
 531  * CP0 Register 2
 532  */
 533     uint64_t CP0_EntryLo0;
 534 /*
 535  * CP0 Register 3
 536  */
 537     uint64_t CP0_EntryLo1;
 538 #if defined(TARGET_MIPS64)
 539 # define CP0EnLo_RI 63
 540 # define CP0EnLo_XI 62
 541 #else
 542 # define CP0EnLo_RI 31
 543 # define CP0EnLo_XI 30
 544 #endif
 545     int32_t CP0_GlobalNumber;
 546 #define CP0GN_VPId 0
 547 /*
 548  * CP0 Register 4
 549  */
 550     target_ulong CP0_Context;
 551     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 552     int32_t CP0_MemoryMapID;
 553 /*
 554  * CP0 Register 5
 555  */
 556     int32_t CP0_PageMask;
 557     int32_t CP0_PageGrain_rw_bitmask;
 558     int32_t CP0_PageGrain;
 559 #define CP0PG_RIE 31
 560 #define CP0PG_XIE 30
 561 #define CP0PG_ELPA 29
 562 #define CP0PG_IEC 27
 563     target_ulong CP0_SegCtl0;
 564     target_ulong CP0_SegCtl1;
 565     target_ulong CP0_SegCtl2;
 566 #define CP0SC_PA        9
 567 #define CP0SC_PA_MASK   (0x7FULL << CP0SC_PA)
 568 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
 569 #define CP0SC_AM        4
 570 #define CP0SC_AM_MASK   (0x7ULL << CP0SC_AM)
 571 #define CP0SC_AM_UK     0ULL
 572 #define CP0SC_AM_MK     1ULL
 573 #define CP0SC_AM_MSK    2ULL
 574 #define CP0SC_AM_MUSK   3ULL
 575 #define CP0SC_AM_MUSUK  4ULL
 576 #define CP0SC_AM_USK    5ULL
 577 #define CP0SC_AM_UUSK   7ULL
 578 #define CP0SC_EU        3
 579 #define CP0SC_EU_MASK   (1ULL << CP0SC_EU)
 580 #define CP0SC_C         0
 581 #define CP0SC_C_MASK    (0x7ULL << CP0SC_C)
 582 #define CP0SC_MASK      (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 583                          CP0SC_PA_MASK)
 584 #define CP0SC_1GMASK    (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 585                          CP0SC_PA_1GMASK)
 586 #define CP0SC0_MASK     (CP0SC_MASK | (CP0SC_MASK << 16))
 587 #define CP0SC1_XAM      59
 588 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
 589 #define CP0SC1_MASK     (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
 590 #define CP0SC2_XR       56
 591 #define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)
 592 #define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
 593     target_ulong CP0_PWBase;
 594     target_ulong CP0_PWField;
 595 #if defined(TARGET_MIPS64)
 596 #define CP0PF_BDI  32    /* 37..32 */
 597 #define CP0PF_GDI  24    /* 29..24 */
 598 #define CP0PF_UDI  18    /* 23..18 */
 599 #define CP0PF_MDI  12    /* 17..12 */
 600 #define CP0PF_PTI  6     /* 11..6  */
 601 #define CP0PF_PTEI 0     /*  5..0  */
 602 #else
 603 #define CP0PF_GDW  24    /* 29..24 */
 604 #define CP0PF_UDW  18    /* 23..18 */
 605 #define CP0PF_MDW  12    /* 17..12 */
 606 #define CP0PF_PTW  6     /* 11..6  */
 607 #define CP0PF_PTEW 0     /*  5..0  */
 608 #endif
 609     target_ulong CP0_PWSize;
 610 #if defined(TARGET_MIPS64)
 611 #define CP0PS_BDW  32    /* 37..32 */
 612 #endif
 613 #define CP0PS_PS   30
 614 #define CP0PS_GDW  24    /* 29..24 */
 615 #define CP0PS_UDW  18    /* 23..18 */
 616 #define CP0PS_MDW  12    /* 17..12 */
 617 #define CP0PS_PTW  6     /* 11..6  */
 618 #define CP0PS_PTEW 0     /*  5..0  */
 619 /*
 620  * CP0 Register 6
 621  */
 622     int32_t CP0_Wired;
 623     int32_t CP0_PWCtl;
 624 #define CP0PC_PWEN      31
 625 #if defined(TARGET_MIPS64)
 626 #define CP0PC_PWDIREXT  30
 627 #define CP0PC_XK        28
 628 #define CP0PC_XS        27
 629 #define CP0PC_XU        26
 630 #endif
 631 #define CP0PC_DPH       7
 632 #define CP0PC_HUGEPG    6
 633 #define CP0PC_PSN       0     /*  5..0  */
 634     int32_t CP0_SRSConf0_rw_bitmask;
 635     int32_t CP0_SRSConf0;
 636 #define CP0SRSC0_M      31
 637 #define CP0SRSC0_SRS3   20
 638 #define CP0SRSC0_SRS2   10
 639 #define CP0SRSC0_SRS1   0
 640     int32_t CP0_SRSConf1_rw_bitmask;
 641     int32_t CP0_SRSConf1;
 642 #define CP0SRSC1_M      31
 643 #define CP0SRSC1_SRS6   20
 644 #define CP0SRSC1_SRS5   10
 645 #define CP0SRSC1_SRS4   0
 646     int32_t CP0_SRSConf2_rw_bitmask;
 647     int32_t CP0_SRSConf2;
 648 #define CP0SRSC2_M      31
 649 #define CP0SRSC2_SRS9   20
 650 #define CP0SRSC2_SRS8   10
 651 #define CP0SRSC2_SRS7   0
 652     int32_t CP0_SRSConf3_rw_bitmask;
 653     int32_t CP0_SRSConf3;
 654 #define CP0SRSC3_M      31
 655 #define CP0SRSC3_SRS12  20
 656 #define CP0SRSC3_SRS11  10
 657 #define CP0SRSC3_SRS10  0
 658     int32_t CP0_SRSConf4_rw_bitmask;
 659     int32_t CP0_SRSConf4;
 660 #define CP0SRSC4_SRS15  20
 661 #define CP0SRSC4_SRS14  10
 662 #define CP0SRSC4_SRS13  0
 663 /*
 664  * CP0 Register 7
 665  */
 666     int32_t CP0_HWREna;
 667 /*
 668  * CP0 Register 8
 669  */
 670     target_ulong CP0_BadVAddr;
 671     uint32_t CP0_BadInstr;
 672     uint32_t CP0_BadInstrP;
 673     uint32_t CP0_BadInstrX;
 674 /*
 675  * CP0 Register 9
 676  */
 677     int32_t CP0_Count;
 678     uint32_t CP0_SAARI;
 679 #define CP0SAARI_TARGET 0    /*  5..0  */
 680     uint64_t CP0_SAAR[2];
 681 #define CP0SAAR_BASE    12   /* 43..12 */
 682 #define CP0SAAR_SIZE    1    /*  5..1  */
 683 #define CP0SAAR_EN      0
 684 /*
 685  * CP0 Register 10
 686  */
 687     target_ulong CP0_EntryHi;
 688 #define CP0EnHi_EHINV 10
 689     target_ulong CP0_EntryHi_ASID_mask;
 690 /*
 691  * CP0 Register 11
 692  */
 693     int32_t CP0_Compare;
 694 /*
 695  * CP0 Register 12
 696  */
 697     int32_t CP0_Status;
 698 #define CP0St_CU3   31
 699 #define CP0St_CU2   30
 700 #define CP0St_CU1   29
 701 #define CP0St_CU0   28
 702 #define CP0St_RP    27
 703 #define CP0St_FR    26
 704 #define CP0St_RE    25
 705 #define CP0St_MX    24
 706 #define CP0St_PX    23
 707 #define CP0St_BEV   22
 708 #define CP0St_TS    21
 709 #define CP0St_SR    20
 710 #define CP0St_NMI   19
 711 #define CP0St_IM    8
 712 #define CP0St_KX    7
 713 #define CP0St_SX    6
 714 #define CP0St_UX    5
 715 #define CP0St_KSU   3
 716 #define CP0St_ERL   2
 717 #define CP0St_EXL   1
 718 #define CP0St_IE    0
 719     int32_t CP0_IntCtl;
 720 #define CP0IntCtl_IPTI 29
 721 #define CP0IntCtl_IPPCI 26
 722 #define CP0IntCtl_VS 5
 723     int32_t CP0_SRSCtl;
 724 #define CP0SRSCtl_HSS 26
 725 #define CP0SRSCtl_EICSS 18
 726 #define CP0SRSCtl_ESS 12
 727 #define CP0SRSCtl_PSS 6
 728 #define CP0SRSCtl_CSS 0
 729     int32_t CP0_SRSMap;
 730 #define CP0SRSMap_SSV7 28
 731 #define CP0SRSMap_SSV6 24
 732 #define CP0SRSMap_SSV5 20
 733 #define CP0SRSMap_SSV4 16
 734 #define CP0SRSMap_SSV3 12
 735 #define CP0SRSMap_SSV2 8
 736 #define CP0SRSMap_SSV1 4
 737 #define CP0SRSMap_SSV0 0
 738 /*
 739  * CP0 Register 13
 740  */
 741     int32_t CP0_Cause;
 742 #define CP0Ca_BD   31
 743 #define CP0Ca_TI   30
 744 #define CP0Ca_CE   28
 745 #define CP0Ca_DC   27
 746 #define CP0Ca_PCI  26
 747 #define CP0Ca_IV   23
 748 #define CP0Ca_WP   22
 749 #define CP0Ca_IP    8
 750 #define CP0Ca_IP_mask 0x0000FF00
 751 #define CP0Ca_EC    2
 752 /*
 753  * CP0 Register 14
 754  */
 755     target_ulong CP0_EPC;
 756 /*
 757  * CP0 Register 15
 758  */
 759     int32_t CP0_PRid;
 760     target_ulong CP0_EBase;
 761     target_ulong CP0_EBaseWG_rw_bitmask;
 762 #define CP0EBase_WG 11
 763     target_ulong CP0_CMGCRBase;
 764 /*
 765  * CP0 Register 16
 766  */
 767     int32_t CP0_Config0;
 768 #define CP0C0_M    31
 769 #define CP0C0_K23  28    /* 30..28 */
 770 #define CP0C0_KU   25    /* 27..25 */
 771 #define CP0C0_MDU  20
 772 #define CP0C0_MM   18
 773 #define CP0C0_BM   16
 774 #define CP0C0_Impl 16    /* 24..16 */
 775 #define CP0C0_BE   15
 776 #define CP0C0_AT   13    /* 14..13 */
 777 #define CP0C0_AR   10    /* 12..10 */
 778 #define CP0C0_MT   7     /*  9..7  */
 779 #define CP0C0_VI   3
 780 #define CP0C0_K0   0     /*  2..0  */
 781     int32_t CP0_Config1;
 782 #define CP0C1_M    31
 783 #define CP0C1_MMU  25    /* 30..25 */
 784 #define CP0C1_IS   22    /* 24..22 */
 785 #define CP0C1_IL   19    /* 21..19 */
 786 #define CP0C1_IA   16    /* 18..16 */
 787 #define CP0C1_DS   13    /* 15..13 */
 788 #define CP0C1_DL   10    /* 12..10 */
 789 #define CP0C1_DA   7     /*  9..7  */
 790 #define CP0C1_C2   6
 791 #define CP0C1_MD   5
 792 #define CP0C1_PC   4
 793 #define CP0C1_WR   3
 794 #define CP0C1_CA   2
 795 #define CP0C1_EP   1
 796 #define CP0C1_FP   0
 797     int32_t CP0_Config2;
 798 #define CP0C2_M    31
 799 #define CP0C2_TU   28    /* 30..28 */
 800 #define CP0C2_TS   24    /* 27..24 */
 801 #define CP0C2_TL   20    /* 23..20 */
 802 #define CP0C2_TA   16    /* 19..16 */
 803 #define CP0C2_SU   12    /* 15..12 */
 804 #define CP0C2_SS   8     /* 11..8  */
 805 #define CP0C2_SL   4     /*  7..4  */
 806 #define CP0C2_SA   0     /*  3..0  */
 807     int32_t CP0_Config3;
 808 #define CP0C3_M            31
 809 #define CP0C3_BPG          30
 810 #define CP0C3_CMGCR        29
 811 #define CP0C3_MSAP         28
 812 #define CP0C3_BP           27
 813 #define CP0C3_BI           26
 814 #define CP0C3_SC           25
 815 #define CP0C3_PW           24
 816 #define CP0C3_VZ           23
 817 #define CP0C3_IPLV         21    /* 22..21 */
 818 #define CP0C3_MMAR         18    /* 20..18 */
 819 #define CP0C3_MCU          17
 820 #define CP0C3_ISA_ON_EXC   16
 821 #define CP0C3_ISA          14    /* 15..14 */
 822 #define CP0C3_ULRI         13
 823 #define CP0C3_RXI          12
 824 #define CP0C3_DSP2P        11
 825 #define CP0C3_DSPP         10
 826 #define CP0C3_CTXTC        9
 827 #define CP0C3_ITL          8
 828 #define CP0C3_LPA          7
 829 #define CP0C3_VEIC         6
 830 #define CP0C3_VInt         5
 831 #define CP0C3_SP           4
 832 #define CP0C3_CDMM         3
 833 #define CP0C3_MT           2
 834 #define CP0C3_SM           1
 835 #define CP0C3_TL           0
 836     int32_t CP0_Config4;
 837     int32_t CP0_Config4_rw_bitmask;
 838 #define CP0C4_M            31
 839 #define CP0C4_IE           29    /* 30..29 */
 840 #define CP0C4_AE           28
 841 #define CP0C4_VTLBSizeExt  24    /* 27..24 */
 842 #define CP0C4_KScrExist    16
 843 #define CP0C4_MMUExtDef    14
 844 #define CP0C4_FTLBPageSize 8     /* 12..8  */
 845 /* bit layout if MMUExtDef=1 */
 846 #define CP0C4_MMUSizeExt   0     /*  7..0  */
 847 /* bit layout if MMUExtDef=2 */
 848 #define CP0C4_FTLBWays     4     /*  7..4  */
 849 #define CP0C4_FTLBSets     0     /*  3..0  */
 850     int32_t CP0_Config5;
 851     int32_t CP0_Config5_rw_bitmask;
 852 #define CP0C5_M            31
 853 #define CP0C5_K            30
 854 #define CP0C5_CV           29
 855 #define CP0C5_EVA          28
 856 #define CP0C5_MSAEn        27
 857 #define CP0C5_PMJ          23    /* 25..23 */
 858 #define CP0C5_WR2          22
 859 #define CP0C5_NMS          21
 860 #define CP0C5_ULS          20
 861 #define CP0C5_XPA          19
 862 #define CP0C5_CRCP         18
 863 #define CP0C5_MI           17
 864 #define CP0C5_GI           15    /* 16..15 */
 865 #define CP0C5_CA2          14
 866 #define CP0C5_XNP          13
 867 #define CP0C5_DEC          11
 868 #define CP0C5_L2C          10
 869 #define CP0C5_UFE          9
 870 #define CP0C5_FRE          8
 871 #define CP0C5_VP           7
 872 #define CP0C5_SBRI         6
 873 #define CP0C5_MVH          5
 874 #define CP0C5_LLB          4
 875 #define CP0C5_MRP          3
 876 #define CP0C5_UFR          2
 877 #define CP0C5_NFExists     0
 878     int32_t CP0_Config6;
 879     int32_t CP0_Config7;
 880     uint64_t CP0_LLAddr;
 881     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 882     int32_t CP0_MAARI;
 883     /* XXX: Maybe make LLAddr per-TC? */
 884 /*
 885  * CP0 Register 17
 886  */
 887     target_ulong lladdr; /* LL virtual address compared against SC */
 888     target_ulong llval;
 889     uint64_t llval_wp;
 890     uint32_t llnewval_wp;
 891     uint64_t CP0_LLAddr_rw_bitmask;
 892     int CP0_LLAddr_shift;
 893 /*
 894  * CP0 Register 18
 895  */
 896     target_ulong CP0_WatchLo[8];
 897 /*
 898  * CP0 Register 19
 899  */
 900     int32_t CP0_WatchHi[8];
 901 #define CP0WH_ASID 16
 902 /*
 903  * CP0 Register 20
 904  */
 905     target_ulong CP0_XContext;
 906     int32_t CP0_Framemask;
 907 /*
 908  * CP0 Register 23
 909  */
 910     int32_t CP0_Debug;
 911 #define CP0DB_DBD  31
 912 #define CP0DB_DM   30
 913 #define CP0DB_LSNM 28
 914 #define CP0DB_Doze 27
 915 #define CP0DB_Halt 26
 916 #define CP0DB_CNT  25
 917 #define CP0DB_IBEP 24
 918 #define CP0DB_DBEP 21
 919 #define CP0DB_IEXI 20
 920 #define CP0DB_VER  15
 921 #define CP0DB_DEC  10
 922 #define CP0DB_SSt  8
 923 #define CP0DB_DINT 5
 924 #define CP0DB_DIB  4
 925 #define CP0DB_DDBS 3
 926 #define CP0DB_DDBL 2
 927 #define CP0DB_DBp  1
 928 #define CP0DB_DSS  0
 929 /*
 930  * CP0 Register 24
 931  */
 932     target_ulong CP0_DEPC;
 933 /*
 934  * CP0 Register 25
 935  */
 936     int32_t CP0_Performance0;
 937 /*
 938  * CP0 Register 26
 939  */
 940     int32_t CP0_ErrCtl;
 941 #define CP0EC_WST 29
 942 #define CP0EC_SPR 28
 943 #define CP0EC_ITC 26
 944 /*
 945  * CP0 Register 28
 946  */
 947     uint64_t CP0_TagLo;
 948     int32_t CP0_DataLo;
 949 /*
 950  * CP0 Register 29
 951  */
 952     int32_t CP0_TagHi;
 953     int32_t CP0_DataHi;
 954 /*
 955  * CP0 Register 30
 956  */
 957     target_ulong CP0_ErrorEPC;
 958 /*
 959  * CP0 Register 31
 960  */
 961     int32_t CP0_DESAVE;
 962
 963     /* We waste some space so we can handle shadow registers like TCs. */
 964     TCState tcs[MIPS_SHADOW_SET_MAX];
 965     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 966     /* QEMU */
 967     int error_code;
 968 #define EXCP_TLB_NOMATCH   0x1
 969 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 970     uint32_t hflags;    /* CPU State */
 971     /* TMASK defines different execution modes */
 972 #define MIPS_HFLAG_TMASK  0x1F5807FF
 973 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 974     /*
 975      * The KSU flags must be the lowest bits in hflags. The flag order
 976      * must be the same as defined for CP0 Status. This allows to use
 977      * the bits as the value of mmu_idx.
 978      */
 979 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 980 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 981 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 982 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 983 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 984 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 985 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 986 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 987 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 988     /*
 989      * True if the MIPS IV COP1X instructions can be used.  This also
 990      * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 991      * and RSQRT.D.
 992      */
 993 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 994 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 995 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 996 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 997 #define MIPS_HFLAG_M16_SHIFT 10
 998     /*
 999      * If translation is interrupted between the branch instruction and
1000      * the delay slot, record what type of branch it is so that we can
1001      * resume translation properly.  It might be possible to reduce
1002      * this from three bits to two.
1003      */
1004 #define MIPS_HFLAG_BMASK_BASE  0x803800
1005 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
1006 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
1007 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
1008 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
1009     /* Extra flags about the current pending branch.  */
1010 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1011 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
1012 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
1013 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
1014 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
1015 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
1016 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1017     /* MIPS DSP resources access. */
1018 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
1019 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
1020 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1021     /* Extra flag about HWREna register. */
1022 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1023 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1024 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
1025 #define MIPS_HFLAG_MSA   0x1000000
1026 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
1027 #define MIPS_HFLAG_ELPA  0x4000000
1028 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
1029 #define MIPS_HFLAG_ERL   0x10000000 /* error level flag */
1030     target_ulong btarget;        /* Jump / branch target               */
1031     target_ulong bcond;          /* Branch condition (if needed)       */
1032
1033     int SYNCI_Step; /* Address step size for SYNCI */
1034     int CCRes; /* Cycle count resolution/divisor */
1035     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
1036     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
1037     uint64_t insn_flags; /* Supported instruction set */
1038     int saarp;
1039
1040     /* Fields up to this point are cleared by a CPU reset */
1041     struct {} end_reset_fields;
1042
1043     /* Fields from here on are preserved across CPU reset. */
1044     CPUMIPSMVPContext *mvp;
1045 #if !defined(CONFIG_USER_ONLY)
1046     CPUMIPSTLBContext *tlb;
1047 #endif
1048
1049     const mips_def_t *cpu_model;
1050     void *irq[8];
1051     QEMUTimer *timer; /* Internal timer */
1052     struct MIPSITUState *itu;
1053     MemoryRegion *itc_tag; /* ITC Configuration Tags */
1054     target_ulong exception_base; /* ExceptionBase input to the core */
1055 };
1056
1057 /**
1058  * MIPSCPU:
1059  * @env: #CPUMIPSState
1060  *
1061  * A MIPS CPU.
1062  */
1063 struct MIPSCPU {
1064     /*< private >*/
1065     CPUState parent_obj;
1066     /*< public >*/
1067
1068     CPUNegativeOffsetState neg;
1069     CPUMIPSState env;
1070 };
1071
1072
1073 void mips_cpu_list(void);
1074
1075 #define cpu_signal_handler cpu_mips_signal_handler
1076 #define cpu_list mips_cpu_list
1077
1078 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1079 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1080
1081 /*
1082  * MMU modes definitions. We carefully match the indices with our
1083  * hflags layout.
1084  */
1085 #define MMU_MODE0_SUFFIX _kernel
1086 #define MMU_MODE1_SUFFIX _super
1087 #define MMU_MODE2_SUFFIX _user
1088 #define MMU_MODE3_SUFFIX _error
1089 #define MMU_USER_IDX 2
1090
1091 static inline int hflags_mmu_index(uint32_t hflags)
1092 {
1093     if (hflags & MIPS_HFLAG_ERL) {
1094         return 3; /* ERL */
1095     } else {
1096         return hflags & MIPS_HFLAG_KSU;
1097     }
1098 }
1099
1100 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
1101 {
1102     return hflags_mmu_index(env->hflags);
1103 }
1104
1105 typedef CPUMIPSState CPUArchState;
1106 typedef MIPSCPU ArchCPU;
1107
1108 #include "exec/cpu-all.h"
1109
1110 /*
1111  * Memory access type :
1112  * may be needed for precise access rights control and precise exceptions.
1113  */
1114 enum {
1115     /* 1 bit to define user level / supervisor access */
1116     ACCESS_USER  = 0x00,
1117     ACCESS_SUPER = 0x01,
1118     /* 1 bit to indicate direction */
1119     ACCESS_STORE = 0x02,
1120     /* Type of instruction that generated the access */
1121     ACCESS_CODE  = 0x10, /* Code fetch access                */
1122     ACCESS_INT   = 0x20, /* Integer load/store access        */
1123     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1124 };
1125
1126 /* Exceptions */
1127 enum {
1128     EXCP_NONE          = -1,
1129     EXCP_RESET         = 0,
1130     EXCP_SRESET,
1131     EXCP_DSS,
1132     EXCP_DINT,
1133     EXCP_DDBL,
1134     EXCP_DDBS,
1135     EXCP_NMI,
1136     EXCP_MCHECK,
1137     EXCP_EXT_INTERRUPT, /* 8 */
1138     EXCP_DFWATCH,
1139     EXCP_DIB,
1140     EXCP_IWATCH,
1141     EXCP_AdEL,
1142     EXCP_AdES,
1143     EXCP_TLBF,
1144     EXCP_IBE,
1145     EXCP_DBp, /* 16 */
1146     EXCP_SYSCALL,
1147     EXCP_BREAK,
1148     EXCP_CpU,
1149     EXCP_RI,
1150     EXCP_OVERFLOW,
1151     EXCP_TRAP,
1152     EXCP_FPE,
1153     EXCP_DWATCH, /* 24 */
1154     EXCP_LTLBL,
1155     EXCP_TLBL,
1156     EXCP_TLBS,
1157     EXCP_DBE,
1158     EXCP_THREAD,
1159     EXCP_MDMX,
1160     EXCP_C2E,
1161     EXCP_CACHE, /* 32 */
1162     EXCP_DSPDIS,
1163     EXCP_MSADIS,
1164     EXCP_MSAFPE,
1165     EXCP_TLBXI,
1166     EXCP_TLBRI,
1167
1168     EXCP_LAST = EXCP_TLBRI,
1169 };
1170
1171 /*
1172  * This is an internally generated WAKE request line.
1173  * It is driven by the CPU itself. Raised when the MT
1174  * block wants to wake a VPE from an inactive state and
1175  * cleared when VPE goes from active to inactive.
1176  */
1177 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1178
1179 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1180
1181 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1182 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1183 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1184
1185 bool cpu_supports_cps_smp(const char *cpu_type);
1186 bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
1187 void cpu_set_exception_base(int vp_index, target_ulong address);
1188
1189 /* mips_int.c */
1190 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1191
1192 /* mips_itu.c */
1193 void itc_reconfigure(struct MIPSITUState *tag);
1194
1195 /* helper.c */
1196 target_ulong exception_resume_pc(CPUMIPSState *env);
1197
1198 static inline void restore_snan_bit_mode(CPUMIPSState *env)
1199 {
1200     set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
1201                         &env->active_fpu.fp_status);
1202 }
1203
1204 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1205                                         target_ulong *cs_base, uint32_t *flags)
1206 {
1207     *pc = env->active_tc.PC;
1208     *cs_base = 0;
1209     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1210                             MIPS_HFLAG_HWRENA_ULR);
1211 }
1212
1213 #endif /* MIPS_CPU_H */