include/hw/block/flash.h

   1 #ifndef HW_FLASH_H
   2 #define HW_FLASH_H
   3
   4 /* NOR flash devices */
   5
   6 #include "exec/memory.h"
   7
   8 /* pflash_cfi01.c */
   9
  10 #define TYPE_PFLASH_CFI01 "cfi.pflash01"
  11 #define PFLASH_CFI01(obj) \
  12     OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01)
  13
  14 typedef struct PFlashCFI01 PFlashCFI01;
  15
  16 PFlashCFI01 *pflash_cfi01_register(hwaddr base,
  17                                    const char *name,
  18                                    hwaddr size,
  19                                    BlockBackend *blk,
  20                                    uint32_t sector_len,
  21                                    int width,
  22                                    uint16_t id0, uint16_t id1,
  23                                    uint16_t id2, uint16_t id3,
  24                                    int be);
  25 BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
  26 MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
  27 void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo);
  28
  29 /* pflash_cfi02.c */
  30
  31 #define TYPE_PFLASH_CFI02 "cfi.pflash02"
  32 #define PFLASH_CFI02(obj) \
  33     OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02)
  34
  35 typedef struct PFlashCFI02 PFlashCFI02;
  36
  37 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
  38                                    const char *name,
  39                                    hwaddr size,
  40                                    BlockBackend *blk,
  41                                    uint32_t sector_len,
  42                                    int nb_mappings,
  43                                    int width,
  44                                    uint16_t id0, uint16_t id1,
  45                                    uint16_t id2, uint16_t id3,
  46                                    uint16_t unlock_addr0,
  47                                    uint16_t unlock_addr1,
  48                                    int be);
  49
  50 /* nand.c */
  51 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
  52 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  53                   uint8_t ce, uint8_t wp, uint8_t gnd);
  54 void nand_getpins(DeviceState *dev, int *rb);
  55 void nand_setio(DeviceState *dev, uint32_t value);
  56 uint32_t nand_getio(DeviceState *dev);
  57 uint32_t nand_getbuswidth(DeviceState *dev);
  58
  59 #define NAND_MFR_TOSHIBA        0x98
  60 #define NAND_MFR_SAMSUNG        0xec
  61 #define NAND_MFR_FUJITSU        0x04
  62 #define NAND_MFR_NATIONAL       0x8f
  63 #define NAND_MFR_RENESAS        0x07
  64 #define NAND_MFR_STMICRO        0x20
  65 #define NAND_MFR_HYNIX          0xad
  66 #define NAND_MFR_MICRON         0x2c
  67
  68 /* onenand.c */
  69 void *onenand_raw_otp(DeviceState *onenand_device);
  70
  71 /* ecc.c */
  72 typedef struct {
  73     uint8_t cp;         /* Column parity */
  74     uint16_t lp[2];     /* Line parity */
  75     uint16_t count;
  76 } ECCState;
  77
  78 uint8_t ecc_digest(ECCState *s, uint8_t sample);
  79 void ecc_reset(ECCState *s);
  80 extern VMStateDescription vmstate_ecc_state;
  81
  82 #endif