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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
[qemu/ar7.git] / hw / display / tc6393xb.c
blob0b7c59cde7d854688c846213ac8b3143390a325b
1 /*
2 * Toshiba TC6393XB I/O Controller.
3 * Found in Sharp Zaurus SL-6000 (tosa) or some
4 * Toshiba e-Series PDAs.
5 *
6 * Most features are currently unsupported!!!
7 *
8 * This code is licensed under the GNU GPL v2.
9 *
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
12 */
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu/host-utils.h"
16 #include "hw/hw.h"
17 #include "hw/display/tc6393xb.h"
18 #include "hw/block/flash.h"
19 #include "ui/console.h"
20 #include "ui/pixel_ops.h"
21 #include "sysemu/blockdev.h"
22
23 #define IRQ_TC6393_NAND 0
24 #define IRQ_TC6393_MMC 1
25 #define IRQ_TC6393_OHCI 2
26 #define IRQ_TC6393_SERIAL 3
27 #define IRQ_TC6393_FB 4
28
29 #define TC6393XB_NR_IRQS 8
30
31 #define TC6393XB_GPIOS 16
32
33 #define SCR_REVID 0x08 /* b Revision ID */
34 #define SCR_ISR 0x50 /* b Interrupt Status */
35 #define SCR_IMR 0x52 /* b Interrupt Mask */
36 #define SCR_IRR 0x54 /* b Interrupt Routing */
37 #define SCR_GPER 0x60 /* w GP Enable */
38 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
39 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
40 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
41 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
42 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
43 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
44 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
45 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
46 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
47 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
48 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
49 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
50 #define SCR_CCR 0x98 /* w Clock Control */
51 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
52 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
53 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
54 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
55 #define SCR_FER 0xe0 /* b Function Enable */
56 #define SCR_MCR 0xe4 /* w Mode Control */
57 #define SCR_CONFIG 0xfc /* b Configuration Control */
58 #define SCR_DEBUG 0xff /* b Debug */
59
60 #define NAND_CFG_COMMAND 0x04 /* w Command */
61 #define NAND_CFG_BASE 0x10 /* l Control Base Address */
62 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
63 #define NAND_CFG_INTE 0x48 /* b Int Enable */
64 #define NAND_CFG_EC 0x4a /* b Event Control */
65 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
66 #define NAND_CFG_ECCC 0x5b /* b ECC Control */
67 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
68 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
69 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
70 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
71
72 #define NAND_DATA 0x00 /* l Data */
73 #define NAND_MODE 0x04 /* b Mode */
74 #define NAND_STATUS 0x05 /* b Status */
75 #define NAND_ISR 0x06 /* b Interrupt Status */
76 #define NAND_IMR 0x07 /* b Interrupt Mask */
77
78 #define NAND_MODE_WP 0x80
79 #define NAND_MODE_CE 0x10
80 #define NAND_MODE_ALE 0x02
81 #define NAND_MODE_CLE 0x01
82 #define NAND_MODE_ECC_MASK 0x60
83 #define NAND_MODE_ECC_EN 0x20
84 #define NAND_MODE_ECC_READ 0x40
85 #define NAND_MODE_ECC_RST 0x60
86
87 struct TC6393xbState {
88 MemoryRegion iomem;
89 qemu_irq irq;
90 qemu_irq *sub_irqs;
91 struct {
92 uint8_t ISR;
93 uint8_t IMR;
94 uint8_t IRR;
95 uint16_t GPER;
96 uint8_t GPI_SR[3];
97 uint8_t GPI_IMR[3];
98 uint8_t GPI_EDER[3];
99 uint8_t GPI_LIR[3];
100 uint8_t GP_IARCR[3];
101 uint8_t GP_IARLCR[3];
102 uint8_t GPI_BCR[3];
103 uint16_t GPA_IARCR;
104 uint16_t GPA_IARLCR;
105 uint16_t CCR;
106 uint16_t PLL2CR;
107 uint32_t PLL1CR;
108 uint8_t DIARCR;
109 uint8_t DBOCR;
110 uint8_t FER;
111 uint16_t MCR;
112 uint8_t CONFIG;
113 uint8_t DEBUG;
114 } scr;
115 uint32_t gpio_dir;
116 uint32_t gpio_level;
117 uint32_t prev_level;
118 qemu_irq handler[TC6393XB_GPIOS];
119 qemu_irq *gpio_in;
120
121 struct {
122 uint8_t mode;
123 uint8_t isr;
124 uint8_t imr;
125 } nand;
126 int nand_enable;
127 uint32_t nand_phys;
128 DeviceState *flash;
129 ECCState ecc;
130
131 QemuConsole *con;
132 MemoryRegion vram;
133 uint16_t *vram_ptr;
134 uint32_t scr_width, scr_height; /* in pixels */
135 qemu_irq l3v;
136 unsigned blank : 1,
137 blanked : 1;
138 };
139
140 static void tc6393xb_gpio_set(void *opaque, int line, int level)
141 {
142 // TC6393xbState *s = opaque;
143
144 if (line > TC6393XB_GPIOS) {
145 printf("%s: No GPIO pin %i\n", __func__, line);
146 return;
147 }
148
149 // FIXME: how does the chip reflect the GPIO input level change?
150 }
151
152 static void tc6393xb_gpio_handler_update(TC6393xbState *s)
153 {
154 uint32_t level, diff;
155 int bit;
156
157 level = s->gpio_level & s->gpio_dir;
158 level &= MAKE_64BIT_MASK(0, TC6393XB_GPIOS);
159
160 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
161 bit = ctz32(diff);
162 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
163 }
164
165 s->prev_level = level;
166 }
167
168 qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
169 {
170 return s->l3v;
171 }
172
173 static void tc6393xb_l3v(void *opaque, int line, int level)
174 {
175 TC6393xbState *s = opaque;
176 s->blank = !level;
177 fprintf(stderr, "L3V: %d\n", level);
178 }
179
180 static void tc6393xb_sub_irq(void *opaque, int line, int level) {
181 TC6393xbState *s = opaque;
182 uint8_t isr = s->scr.ISR;
183 if (level)
184 isr |= 1 << line;
185 else
186 isr &= ~(1 << line);
187 s->scr.ISR = isr;
188 qemu_set_irq(s->irq, isr & s->scr.IMR);
189 }
190
191 #define SCR_REG_B(N) \
192 case SCR_ ##N: return s->scr.N
193 #define SCR_REG_W(N) \
194 case SCR_ ##N: return s->scr.N; \
195 case SCR_ ##N + 1: return s->scr.N >> 8;
196 #define SCR_REG_L(N) \
197 case SCR_ ##N: return s->scr.N; \
198 case SCR_ ##N + 1: return s->scr.N >> 8; \
199 case SCR_ ##N + 2: return s->scr.N >> 16; \
200 case SCR_ ##N + 3: return s->scr.N >> 24;
201 #define SCR_REG_A(N) \
202 case SCR_ ##N(0): return s->scr.N[0]; \
203 case SCR_ ##N(1): return s->scr.N[1]; \
204 case SCR_ ##N(2): return s->scr.N[2]
205
206 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
207 {
208 switch (addr) {
209 case SCR_REVID:
210 return 3;
211 case SCR_REVID+1:
212 return 0;
213 SCR_REG_B(ISR);
214 SCR_REG_B(IMR);
215 SCR_REG_B(IRR);
216 SCR_REG_W(GPER);
217 SCR_REG_A(GPI_SR);
218 SCR_REG_A(GPI_IMR);
219 SCR_REG_A(GPI_EDER);
220 SCR_REG_A(GPI_LIR);
221 case SCR_GPO_DSR(0):
222 case SCR_GPO_DSR(1):
223 case SCR_GPO_DSR(2):
224 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
225 case SCR_GPO_DOECR(0):
226 case SCR_GPO_DOECR(1):
227 case SCR_GPO_DOECR(2):
228 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
229 SCR_REG_A(GP_IARCR);
230 SCR_REG_A(GP_IARLCR);
231 SCR_REG_A(GPI_BCR);
232 SCR_REG_W(GPA_IARCR);
233 SCR_REG_W(GPA_IARLCR);
234 SCR_REG_W(CCR);
235 SCR_REG_W(PLL2CR);
236 SCR_REG_L(PLL1CR);
237 SCR_REG_B(DIARCR);
238 SCR_REG_B(DBOCR);
239 SCR_REG_B(FER);
240 SCR_REG_W(MCR);
241 SCR_REG_B(CONFIG);
242 SCR_REG_B(DEBUG);
243 }
244 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
245 return 0;
246 }
247 #undef SCR_REG_B
248 #undef SCR_REG_W
249 #undef SCR_REG_L
250 #undef SCR_REG_A
251
252 #define SCR_REG_B(N) \
253 case SCR_ ##N: s->scr.N = value; return;
254 #define SCR_REG_W(N) \
255 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
256 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
257 #define SCR_REG_L(N) \
258 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
259 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \
260 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \
261 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
262 #define SCR_REG_A(N) \
263 case SCR_ ##N(0): s->scr.N[0] = value; return; \
264 case SCR_ ##N(1): s->scr.N[1] = value; return; \
265 case SCR_ ##N(2): s->scr.N[2] = value; return
266
267 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
268 {
269 switch (addr) {
270 SCR_REG_B(ISR);
271 SCR_REG_B(IMR);
272 SCR_REG_B(IRR);
273 SCR_REG_W(GPER);
274 SCR_REG_A(GPI_SR);
275 SCR_REG_A(GPI_IMR);
276 SCR_REG_A(GPI_EDER);
277 SCR_REG_A(GPI_LIR);
278 case SCR_GPO_DSR(0):
279 case SCR_GPO_DSR(1):
280 case SCR_GPO_DSR(2):
281 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
282 tc6393xb_gpio_handler_update(s);
283 return;
284 case SCR_GPO_DOECR(0):
285 case SCR_GPO_DOECR(1):
286 case SCR_GPO_DOECR(2):
287 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
288 tc6393xb_gpio_handler_update(s);
289 return;
290 SCR_REG_A(GP_IARCR);
291 SCR_REG_A(GP_IARLCR);
292 SCR_REG_A(GPI_BCR);
293 SCR_REG_W(GPA_IARCR);
294 SCR_REG_W(GPA_IARLCR);
295 SCR_REG_W(CCR);
296 SCR_REG_W(PLL2CR);
297 SCR_REG_L(PLL1CR);
298 SCR_REG_B(DIARCR);
299 SCR_REG_B(DBOCR);
300 SCR_REG_B(FER);
301 SCR_REG_W(MCR);
302 SCR_REG_B(CONFIG);
303 SCR_REG_B(DEBUG);
304 }
305 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
306 (uint32_t) addr, value & 0xff);
307 }
308 #undef SCR_REG_B
309 #undef SCR_REG_W
310 #undef SCR_REG_L
311 #undef SCR_REG_A
312
313 static void tc6393xb_nand_irq(TC6393xbState *s) {
314 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
315 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
316 }
317
318 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
319 switch (addr) {
320 case NAND_CFG_COMMAND:
321 return s->nand_enable ? 2 : 0;
322 case NAND_CFG_BASE:
323 case NAND_CFG_BASE + 1:
324 case NAND_CFG_BASE + 2:
325 case NAND_CFG_BASE + 3:
326 return s->nand_phys >> (addr - NAND_CFG_BASE);
327 }
328 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
329 return 0;
330 }
331 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
332 switch (addr) {
333 case NAND_CFG_COMMAND:
334 s->nand_enable = (value & 0x2);
335 return;
336 case NAND_CFG_BASE:
337 case NAND_CFG_BASE + 1:
338 case NAND_CFG_BASE + 2:
339 case NAND_CFG_BASE + 3:
340 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
341 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
342 return;
343 }
344 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
345 (uint32_t) addr, value & 0xff);
346 }
347
348 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
349 switch (addr) {
350 case NAND_DATA + 0:
351 case NAND_DATA + 1:
352 case NAND_DATA + 2:
353 case NAND_DATA + 3:
354 return nand_getio(s->flash);
355 case NAND_MODE:
356 return s->nand.mode;
357 case NAND_STATUS:
358 return 0x14;
359 case NAND_ISR:
360 return s->nand.isr;
361 case NAND_IMR:
362 return s->nand.imr;
363 }
364 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
365 return 0;
366 }
367 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
368 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
369 // (uint32_t) addr, value & 0xff);
370 switch (addr) {
371 case NAND_DATA + 0:
372 case NAND_DATA + 1:
373 case NAND_DATA + 2:
374 case NAND_DATA + 3:
375 nand_setio(s->flash, value);
376 s->nand.isr |= 1;
377 tc6393xb_nand_irq(s);
378 return;
379 case NAND_MODE:
380 s->nand.mode = value;
381 nand_setpins(s->flash,
382 value & NAND_MODE_CLE,
383 value & NAND_MODE_ALE,
384 !(value & NAND_MODE_CE),
385 value & NAND_MODE_WP,
386 0); // FIXME: gnd
387 switch (value & NAND_MODE_ECC_MASK) {
388 case NAND_MODE_ECC_RST:
389 ecc_reset(&s->ecc);
390 break;
391 case NAND_MODE_ECC_READ:
392 // FIXME
393 break;
394 case NAND_MODE_ECC_EN:
395 ecc_reset(&s->ecc);
396 }
397 return;
398 case NAND_ISR:
399 s->nand.isr = value;
400 tc6393xb_nand_irq(s);
401 return;
402 case NAND_IMR:
403 s->nand.imr = value;
404 tc6393xb_nand_irq(s);
405 return;
406 }
407 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
408 (uint32_t) addr, value & 0xff);
409 }
410
411 #define BITS 8
412 #include "tc6393xb_template.h"
413 #define BITS 15
414 #include "tc6393xb_template.h"
415 #define BITS 16
416 #include "tc6393xb_template.h"
417 #define BITS 24
418 #include "tc6393xb_template.h"
419 #define BITS 32
420 #include "tc6393xb_template.h"
421
422 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
423 {
424 DisplaySurface *surface = qemu_console_surface(s->con);
425
426 switch (surface_bits_per_pixel(surface)) {
427 case 8:
428 tc6393xb_draw_graphic8(s);
429 break;
430 case 15:
431 tc6393xb_draw_graphic15(s);
432 break;
433 case 16:
434 tc6393xb_draw_graphic16(s);
435 break;
436 case 24:
437 tc6393xb_draw_graphic24(s);
438 break;
439 case 32:
440 tc6393xb_draw_graphic32(s);
441 break;
442 default:
443 printf("tc6393xb: unknown depth %d\n",
444 surface_bits_per_pixel(surface));
445 return;
446 }
447
448 dpy_gfx_update_full(s->con);
449 }
450
451 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
452 {
453 DisplaySurface *surface = qemu_console_surface(s->con);
454 int i, w;
455 uint8_t *d;
456
457 if (!full_update)
458 return;
459
460 w = s->scr_width * surface_bytes_per_pixel(surface);
461 d = surface_data(surface);
462 for(i = 0; i < s->scr_height; i++) {
463 memset(d, 0, w);
464 d += surface_stride(surface);
465 }
466
467 dpy_gfx_update_full(s->con);
468 }
469
470 static void tc6393xb_update_display(void *opaque)
471 {
472 TC6393xbState *s = opaque;
473 DisplaySurface *surface = qemu_console_surface(s->con);
474 int full_update;
475
476 if (s->scr_width == 0 || s->scr_height == 0)
477 return;
478
479 full_update = 0;
480 if (s->blanked != s->blank) {
481 s->blanked = s->blank;
482 full_update = 1;
483 }
484 if (s->scr_width != surface_width(surface) ||
485 s->scr_height != surface_height(surface)) {
486 qemu_console_resize(s->con, s->scr_width, s->scr_height);
487 full_update = 1;
488 }
489 if (s->blanked)
490 tc6393xb_draw_blank(s, full_update);
491 else
492 tc6393xb_draw_graphic(s, full_update);
493 }
494
495
496 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
497 unsigned size)
498 {
499 TC6393xbState *s = opaque;
500
501 switch (addr >> 8) {
502 case 0:
503 return tc6393xb_scr_readb(s, addr & 0xff);
504 case 1:
505 return tc6393xb_nand_cfg_readb(s, addr & 0xff);
506 };
507
508 if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
509 // return tc6393xb_nand_readb(s, addr & 0xff);
510 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
511 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
512 return d;
513 }
514
515 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
516 return 0;
517 }
518
519 static void tc6393xb_writeb(void *opaque, hwaddr addr,
520 uint64_t value, unsigned size) {
521 TC6393xbState *s = opaque;
522
523 switch (addr >> 8) {
524 case 0:
525 tc6393xb_scr_writeb(s, addr & 0xff, value);
526 return;
527 case 1:
528 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
529 return;
530 };
531
532 if ((addr &~0xff) == s->nand_phys && s->nand_enable)
533 tc6393xb_nand_writeb(s, addr & 0xff, value);
534 else
535 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
536 (uint32_t) addr, (int)value & 0xff);
537 }
538
539 static const GraphicHwOps tc6393xb_gfx_ops = {
540 .gfx_update = tc6393xb_update_display,
541 };
542
543 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
544 {
545 TC6393xbState *s;
546 DriveInfo *nand;
547 static const MemoryRegionOps tc6393xb_ops = {
548 .read = tc6393xb_readb,
549 .write = tc6393xb_writeb,
550 .endianness = DEVICE_NATIVE_ENDIAN,
551 .impl = {
552 .min_access_size = 1,
553 .max_access_size = 1,
554 },
555 };
556
557 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
558 s->irq = irq;
559 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
560
561 s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
562 s->blanked = 1;
563
564 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
565
566 nand = drive_get(IF_MTD, 0, 0);
567 s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
568 NAND_MFR_TOSHIBA, 0x76);
569
570 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
571 memory_region_add_subregion(sysmem, base, &s->iomem);
572
573 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000,
574 &error_fatal);
575 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
576 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
577 s->scr_width = 480;
578 s->scr_height = 640;
579 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s);
580
581 return s;
582 }
AR7 emulation for QEMU