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tcg: Add INDEX_op_qemu_{ld,st}_i128
[qemu/ar7.git] / target / riscv / cpu_helper.c
blob57d04385f113ed0e6f370c082bb4ed2ddcd4a563
1 /*
2 * RISC-V CPU helpers for qemu.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/main-loop.h"
23 #include "cpu.h"
24 #include "internals.h"
25 #include "pmu.h"
26 #include "exec/exec-all.h"
27 #include "instmap.h"
28 #include "tcg/tcg-op.h"
29 #include "trace.h"
30 #include "semihosting/common-semi.h"
31 #include "sysemu/cpu-timers.h"
32 #include "cpu_bits.h"
33 #include "debug.h"
34
35 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
36 {
37 #ifdef CONFIG_USER_ONLY
38 return 0;
39 #else
40 bool virt = env->virt_enabled;
41 int mode = env->priv;
42
43 /* All priv -> mmu_idx mapping are here */
44 if (!ifetch) {
45 uint64_t status = env->mstatus;
46
47 if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
48 mode = get_field(env->mstatus, MSTATUS_MPP);
49 virt = get_field(env->mstatus, MSTATUS_MPV);
50 if (virt) {
51 status = env->vsstatus;
52 }
53 }
54 if (mode == PRV_S && get_field(status, MSTATUS_SUM)) {
55 mode = MMUIdx_S_SUM;
56 }
57 }
58
59 return mode | (virt ? MMU_2STAGE_BIT : 0);
60 #endif
61 }
62
63 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
64 target_ulong *cs_base, uint32_t *pflags)
65 {
66 CPUState *cs = env_cpu(env);
67 RISCVCPU *cpu = RISCV_CPU(cs);
68 RISCVExtStatus fs, vs;
69 uint32_t flags = 0;
70
71 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
72 *cs_base = 0;
73
74 if (cpu->cfg.ext_zve32f) {
75 /*
76 * If env->vl equals to VLMAX, we can use generic vector operation
77 * expanders (GVEC) to accerlate the vector operations.
78 * However, as LMUL could be a fractional number. The maximum
79 * vector size can be operated might be less than 8 bytes,
80 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
81 * only when maxsz >= 8 bytes.
82 */
83 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
84 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
85 uint32_t maxsz = vlmax << sew;
86 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
87 (maxsz >= 8);
88 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
89 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
90 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
91 FIELD_EX64(env->vtype, VTYPE, VLMUL));
92 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
93 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
94 FIELD_EX64(env->vtype, VTYPE, VTA));
95 flags = FIELD_DP32(flags, TB_FLAGS, VMA,
96 FIELD_EX64(env->vtype, VTYPE, VMA));
97 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
98 } else {
99 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
100 }
101
102 #ifdef CONFIG_USER_ONLY
103 fs = EXT_STATUS_DIRTY;
104 vs = EXT_STATUS_DIRTY;
105 #else
106 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
107
108 flags |= cpu_mmu_index(env, 0);
109 fs = get_field(env->mstatus, MSTATUS_FS);
110 vs = get_field(env->mstatus, MSTATUS_VS);
111
112 if (env->virt_enabled) {
113 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
114 /*
115 * Merge DISABLED and !DIRTY states using MIN.
116 * We will set both fields when dirtying.
117 */
118 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
119 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
120 }
121
122 if (cpu->cfg.debug && !icount_enabled()) {
123 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
124 }
125 #endif
126
127 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
128 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
129 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
130 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
131 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
132 }
133 if (env->cur_pmbase != 0) {
134 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
135 }
136
137 *pflags = flags;
138 }
139
140 void riscv_cpu_update_mask(CPURISCVState *env)
141 {
142 target_ulong mask = -1, base = 0;
143 /*
144 * TODO: Current RVJ spec does not specify
145 * how the extension interacts with XLEN.
146 */
147 #ifndef CONFIG_USER_ONLY
148 if (riscv_has_ext(env, RVJ)) {
149 switch (env->priv) {
150 case PRV_M:
151 if (env->mmte & M_PM_ENABLE) {
152 mask = env->mpmmask;
153 base = env->mpmbase;
154 }
155 break;
156 case PRV_S:
157 if (env->mmte & S_PM_ENABLE) {
158 mask = env->spmmask;
159 base = env->spmbase;
160 }
161 break;
162 case PRV_U:
163 if (env->mmte & U_PM_ENABLE) {
164 mask = env->upmmask;
165 base = env->upmbase;
166 }
167 break;
168 default:
169 g_assert_not_reached();
170 }
171 }
172 #endif
173 if (env->xl == MXL_RV32) {
174 env->cur_pmmask = mask & UINT32_MAX;
175 env->cur_pmbase = base & UINT32_MAX;
176 } else {
177 env->cur_pmmask = mask;
178 env->cur_pmbase = base;
179 }
180 }
181
182 #ifndef CONFIG_USER_ONLY
183
184 /*
185 * The HS-mode is allowed to configure priority only for the
186 * following VS-mode local interrupts:
187 *
188 * 0 (Reserved interrupt, reads as zero)
189 * 1 Supervisor software interrupt
190 * 4 (Reserved interrupt, reads as zero)
191 * 5 Supervisor timer interrupt
192 * 8 (Reserved interrupt, reads as zero)
193 * 13 (Reserved interrupt)
194 * 14 "
195 * 15 "
196 * 16 "
197 * 17 "
198 * 18 "
199 * 19 "
200 * 20 "
201 * 21 "
202 * 22 "
203 * 23 "
204 */
205
206 static const int hviprio_index2irq[] = {
207 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
208 static const int hviprio_index2rdzero[] = {
209 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
210
211 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
212 {
213 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
214 return -EINVAL;
215 }
216
217 if (out_irq) {
218 *out_irq = hviprio_index2irq[index];
219 }
220
221 if (out_rdzero) {
222 *out_rdzero = hviprio_index2rdzero[index];
223 }
224
225 return 0;
226 }
227
228 /*
229 * Default priorities of local interrupts are defined in the
230 * RISC-V Advanced Interrupt Architecture specification.
231 *
232 * ----------------------------------------------------------------
233 * Default |
234 * Priority | Major Interrupt Numbers
235 * ----------------------------------------------------------------
236 * Highest | 47, 23, 46, 45, 22, 44,
237 * | 43, 21, 42, 41, 20, 40
238 * |
239 * | 11 (0b), 3 (03), 7 (07)
240 * | 9 (09), 1 (01), 5 (05)
241 * | 12 (0c)
242 * | 10 (0a), 2 (02), 6 (06)
243 * |
244 * | 39, 19, 38, 37, 18, 36,
245 * Lowest | 35, 17, 34, 33, 16, 32
246 * ----------------------------------------------------------------
247 */
248 static const uint8_t default_iprio[64] = {
249 /* Custom interrupts 48 to 63 */
250 [63] = IPRIO_MMAXIPRIO,
251 [62] = IPRIO_MMAXIPRIO,
252 [61] = IPRIO_MMAXIPRIO,
253 [60] = IPRIO_MMAXIPRIO,
254 [59] = IPRIO_MMAXIPRIO,
255 [58] = IPRIO_MMAXIPRIO,
256 [57] = IPRIO_MMAXIPRIO,
257 [56] = IPRIO_MMAXIPRIO,
258 [55] = IPRIO_MMAXIPRIO,
259 [54] = IPRIO_MMAXIPRIO,
260 [53] = IPRIO_MMAXIPRIO,
261 [52] = IPRIO_MMAXIPRIO,
262 [51] = IPRIO_MMAXIPRIO,
263 [50] = IPRIO_MMAXIPRIO,
264 [49] = IPRIO_MMAXIPRIO,
265 [48] = IPRIO_MMAXIPRIO,
266
267 /* Custom interrupts 24 to 31 */
268 [31] = IPRIO_MMAXIPRIO,
269 [30] = IPRIO_MMAXIPRIO,
270 [29] = IPRIO_MMAXIPRIO,
271 [28] = IPRIO_MMAXIPRIO,
272 [27] = IPRIO_MMAXIPRIO,
273 [26] = IPRIO_MMAXIPRIO,
274 [25] = IPRIO_MMAXIPRIO,
275 [24] = IPRIO_MMAXIPRIO,
276
277 [47] = IPRIO_DEFAULT_UPPER,
278 [23] = IPRIO_DEFAULT_UPPER + 1,
279 [46] = IPRIO_DEFAULT_UPPER + 2,
280 [45] = IPRIO_DEFAULT_UPPER + 3,
281 [22] = IPRIO_DEFAULT_UPPER + 4,
282 [44] = IPRIO_DEFAULT_UPPER + 5,
283
284 [43] = IPRIO_DEFAULT_UPPER + 6,
285 [21] = IPRIO_DEFAULT_UPPER + 7,
286 [42] = IPRIO_DEFAULT_UPPER + 8,
287 [41] = IPRIO_DEFAULT_UPPER + 9,
288 [20] = IPRIO_DEFAULT_UPPER + 10,
289 [40] = IPRIO_DEFAULT_UPPER + 11,
290
291 [11] = IPRIO_DEFAULT_M,
292 [3] = IPRIO_DEFAULT_M + 1,
293 [7] = IPRIO_DEFAULT_M + 2,
294
295 [9] = IPRIO_DEFAULT_S,
296 [1] = IPRIO_DEFAULT_S + 1,
297 [5] = IPRIO_DEFAULT_S + 2,
298
299 [12] = IPRIO_DEFAULT_SGEXT,
300
301 [10] = IPRIO_DEFAULT_VS,
302 [2] = IPRIO_DEFAULT_VS + 1,
303 [6] = IPRIO_DEFAULT_VS + 2,
304
305 [39] = IPRIO_DEFAULT_LOWER,
306 [19] = IPRIO_DEFAULT_LOWER + 1,
307 [38] = IPRIO_DEFAULT_LOWER + 2,
308 [37] = IPRIO_DEFAULT_LOWER + 3,
309 [18] = IPRIO_DEFAULT_LOWER + 4,
310 [36] = IPRIO_DEFAULT_LOWER + 5,
311
312 [35] = IPRIO_DEFAULT_LOWER + 6,
313 [17] = IPRIO_DEFAULT_LOWER + 7,
314 [34] = IPRIO_DEFAULT_LOWER + 8,
315 [33] = IPRIO_DEFAULT_LOWER + 9,
316 [16] = IPRIO_DEFAULT_LOWER + 10,
317 [32] = IPRIO_DEFAULT_LOWER + 11,
318 };
319
320 uint8_t riscv_cpu_default_priority(int irq)
321 {
322 if (irq < 0 || irq > 63) {
323 return IPRIO_MMAXIPRIO;
324 }
325
326 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
327 };
328
329 static int riscv_cpu_pending_to_irq(CPURISCVState *env,
330 int extirq, unsigned int extirq_def_prio,
331 uint64_t pending, uint8_t *iprio)
332 {
333 int irq, best_irq = RISCV_EXCP_NONE;
334 unsigned int prio, best_prio = UINT_MAX;
335
336 if (!pending) {
337 return RISCV_EXCP_NONE;
338 }
339
340 irq = ctz64(pending);
341 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
342 riscv_cpu_cfg(env)->ext_ssaia)) {
343 return irq;
344 }
345
346 pending = pending >> irq;
347 while (pending) {
348 prio = iprio[irq];
349 if (!prio) {
350 if (irq == extirq) {
351 prio = extirq_def_prio;
352 } else {
353 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
354 1 : IPRIO_MMAXIPRIO;
355 }
356 }
357 if ((pending & 0x1) && (prio <= best_prio)) {
358 best_irq = irq;
359 best_prio = prio;
360 }
361 irq++;
362 pending = pending >> 1;
363 }
364
365 return best_irq;
366 }
367
368 uint64_t riscv_cpu_all_pending(CPURISCVState *env)
369 {
370 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
371 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
372 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
373
374 return (env->mip | vsgein | vstip) & env->mie;
375 }
376
377 int riscv_cpu_mirq_pending(CPURISCVState *env)
378 {
379 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
380 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
381
382 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
383 irqs, env->miprio);
384 }
385
386 int riscv_cpu_sirq_pending(CPURISCVState *env)
387 {
388 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
389 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
390
391 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
392 irqs, env->siprio);
393 }
394
395 int riscv_cpu_vsirq_pending(CPURISCVState *env)
396 {
397 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
398 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
399
400 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
401 irqs >> 1, env->hviprio);
402 }
403
404 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
405 {
406 int virq;
407 uint64_t irqs, pending, mie, hsie, vsie;
408
409 /* Determine interrupt enable state of all privilege modes */
410 if (env->virt_enabled) {
411 mie = 1;
412 hsie = 1;
413 vsie = (env->priv < PRV_S) ||
414 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
415 } else {
416 mie = (env->priv < PRV_M) ||
417 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
418 hsie = (env->priv < PRV_S) ||
419 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
420 vsie = 0;
421 }
422
423 /* Determine all pending interrupts */
424 pending = riscv_cpu_all_pending(env);
425
426 /* Check M-mode interrupts */
427 irqs = pending & ~env->mideleg & -mie;
428 if (irqs) {
429 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
430 irqs, env->miprio);
431 }
432
433 /* Check HS-mode interrupts */
434 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
435 if (irqs) {
436 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
437 irqs, env->siprio);
438 }
439
440 /* Check VS-mode interrupts */
441 irqs = pending & env->mideleg & env->hideleg & -vsie;
442 if (irqs) {
443 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
444 irqs >> 1, env->hviprio);
445 return (virq <= 0) ? virq : virq + 1;
446 }
447
448 /* Indicate no pending interrupt */
449 return RISCV_EXCP_NONE;
450 }
451
452 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
453 {
454 if (interrupt_request & CPU_INTERRUPT_HARD) {
455 RISCVCPU *cpu = RISCV_CPU(cs);
456 CPURISCVState *env = &cpu->env;
457 int interruptno = riscv_cpu_local_irq_pending(env);
458 if (interruptno >= 0) {
459 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
460 riscv_cpu_do_interrupt(cs);
461 return true;
462 }
463 }
464 return false;
465 }
466
467 /* Return true is floating point support is currently enabled */
468 bool riscv_cpu_fp_enabled(CPURISCVState *env)
469 {
470 if (env->mstatus & MSTATUS_FS) {
471 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
472 return false;
473 }
474 return true;
475 }
476
477 return false;
478 }
479
480 /* Return true is vector support is currently enabled */
481 bool riscv_cpu_vector_enabled(CPURISCVState *env)
482 {
483 if (env->mstatus & MSTATUS_VS) {
484 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
485 return false;
486 }
487 return true;
488 }
489
490 return false;
491 }
492
493 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
494 {
495 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
496 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
497 MSTATUS64_UXL | MSTATUS_VS;
498
499 if (riscv_has_ext(env, RVF)) {
500 mstatus_mask |= MSTATUS_FS;
501 }
502 bool current_virt = env->virt_enabled;
503
504 g_assert(riscv_has_ext(env, RVH));
505
506 if (current_virt) {
507 /* Current V=1 and we are about to change to V=0 */
508 env->vsstatus = env->mstatus & mstatus_mask;
509 env->mstatus &= ~mstatus_mask;
510 env->mstatus |= env->mstatus_hs;
511
512 env->vstvec = env->stvec;
513 env->stvec = env->stvec_hs;
514
515 env->vsscratch = env->sscratch;
516 env->sscratch = env->sscratch_hs;
517
518 env->vsepc = env->sepc;
519 env->sepc = env->sepc_hs;
520
521 env->vscause = env->scause;
522 env->scause = env->scause_hs;
523
524 env->vstval = env->stval;
525 env->stval = env->stval_hs;
526
527 env->vsatp = env->satp;
528 env->satp = env->satp_hs;
529 } else {
530 /* Current V=0 and we are about to change to V=1 */
531 env->mstatus_hs = env->mstatus & mstatus_mask;
532 env->mstatus &= ~mstatus_mask;
533 env->mstatus |= env->vsstatus;
534
535 env->stvec_hs = env->stvec;
536 env->stvec = env->vstvec;
537
538 env->sscratch_hs = env->sscratch;
539 env->sscratch = env->vsscratch;
540
541 env->sepc_hs = env->sepc;
542 env->sepc = env->vsepc;
543
544 env->scause_hs = env->scause;
545 env->scause = env->vscause;
546
547 env->stval_hs = env->stval;
548 env->stval = env->vstval;
549
550 env->satp_hs = env->satp;
551 env->satp = env->vsatp;
552 }
553 }
554
555 target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
556 {
557 if (!riscv_has_ext(env, RVH)) {
558 return 0;
559 }
560
561 return env->geilen;
562 }
563
564 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
565 {
566 if (!riscv_has_ext(env, RVH)) {
567 return;
568 }
569
570 if (geilen > (TARGET_LONG_BITS - 1)) {
571 return;
572 }
573
574 env->geilen = geilen;
575 }
576
577 /* This function can only be called to set virt when RVH is enabled */
578 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
579 {
580 /* Flush the TLB on all virt mode changes. */
581 if (env->virt_enabled != enable) {
582 tlb_flush(env_cpu(env));
583 }
584
585 env->virt_enabled = enable;
586
587 if (enable) {
588 /*
589 * The guest external interrupts from an interrupt controller are
590 * delivered only when the Guest/VM is running (i.e. V=1). This means
591 * any guest external interrupt which is triggered while the Guest/VM
592 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
593 * with sluggish response to serial console input and other I/O events.
594 *
595 * To solve this, we check and inject interrupt after setting V=1.
596 */
597 riscv_cpu_update_mip(env, 0, 0);
598 }
599 }
600
601 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
602 {
603 CPURISCVState *env = &cpu->env;
604 if (env->miclaim & interrupts) {
605 return -1;
606 } else {
607 env->miclaim |= interrupts;
608 return 0;
609 }
610 }
611
612 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
613 uint64_t value)
614 {
615 CPUState *cs = env_cpu(env);
616 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
617
618 if (env->virt_enabled) {
619 gein = get_field(env->hstatus, HSTATUS_VGEIN);
620 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
621 }
622
623 vstip = env->vstime_irq ? MIP_VSTIP : 0;
624
625 QEMU_IOTHREAD_LOCK_GUARD();
626
627 env->mip = (env->mip & ~mask) | (value & mask);
628
629 if (env->mip | vsgein | vstip) {
630 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
631 } else {
632 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
633 }
634
635 return old;
636 }
637
638 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
639 void *arg)
640 {
641 env->rdtime_fn = fn;
642 env->rdtime_fn_arg = arg;
643 }
644
645 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
646 int (*rmw_fn)(void *arg,
647 target_ulong reg,
648 target_ulong *val,
649 target_ulong new_val,
650 target_ulong write_mask),
651 void *rmw_fn_arg)
652 {
653 if (priv <= PRV_M) {
654 env->aia_ireg_rmw_fn[priv] = rmw_fn;
655 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
656 }
657 }
658
659 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
660 {
661 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
662
663 if (icount_enabled() && newpriv != env->priv) {
664 riscv_itrigger_update_priv(env);
665 }
666 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
667 env->priv = newpriv;
668 env->xl = cpu_recompute_xl(env);
669 riscv_cpu_update_mask(env);
670
671 /*
672 * Clear the load reservation - otherwise a reservation placed in one
673 * context/process can be used by another, resulting in an SC succeeding
674 * incorrectly. Version 2.2 of the ISA specification explicitly requires
675 * this behaviour, while later revisions say that the kernel "should" use
676 * an SC instruction to force the yielding of a load reservation on a
677 * preemptive context switch. As a result, do both.
678 */
679 env->load_res = -1;
680 }
681
682 /*
683 * get_physical_address_pmp - check PMP permission for this physical address
684 *
685 * Match the PMP region and check permission for this physical address and it's
686 * TLB page. Returns 0 if the permission checking was successful
687 *
688 * @env: CPURISCVState
689 * @prot: The returned protection attributes
690 * @tlb_size: TLB page size containing addr. It could be modified after PMP
691 * permission checking. NULL if not set TLB page for addr.
692 * @addr: The physical address to be checked permission
693 * @access_type: The type of MMU access
694 * @mode: Indicates current privilege level.
695 */
696 static int get_physical_address_pmp(CPURISCVState *env, int *prot,
697 target_ulong *tlb_size, hwaddr addr,
698 int size, MMUAccessType access_type,
699 int mode)
700 {
701 pmp_priv_t pmp_priv;
702 int pmp_index = -1;
703
704 if (!riscv_cpu_cfg(env)->pmp) {
705 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
706 return TRANSLATE_SUCCESS;
707 }
708
709 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
710 &pmp_priv, mode);
711 if (pmp_index < 0) {
712 *prot = 0;
713 return TRANSLATE_PMP_FAIL;
714 }
715
716 *prot = pmp_priv_to_page_prot(pmp_priv);
717 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
718 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
719 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
720
721 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
722 }
723
724 return TRANSLATE_SUCCESS;
725 }
726
727 /*
728 * get_physical_address - get the physical address for this virtual address
729 *
730 * Do a page table walk to obtain the physical address corresponding to a
731 * virtual address. Returns 0 if the translation was successful
732 *
733 * Adapted from Spike's mmu_t::translate and mmu_t::walk
734 *
735 * @env: CPURISCVState
736 * @physical: This will be set to the calculated physical address
737 * @prot: The returned protection attributes
738 * @addr: The virtual address or guest physical address to be translated
739 * @fault_pte_addr: If not NULL, this will be set to fault pte address
740 * when a error occurs on pte address translation.
741 * This will already be shifted to match htval.
742 * @access_type: The type of MMU access
743 * @mmu_idx: Indicates current privilege level
744 * @first_stage: Are we in first stage translation?
745 * Second stage is used for hypervisor guest translation
746 * @two_stage: Are we going to perform two stage translation
747 * @is_debug: Is this access from a debugger or the monitor?
748 */
749 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
750 int *ret_prot, vaddr addr,
751 target_ulong *fault_pte_addr,
752 int access_type, int mmu_idx,
753 bool first_stage, bool two_stage,
754 bool is_debug)
755 {
756 /*
757 * NOTE: the env->pc value visible here will not be
758 * correct, but the value visible to the exception handler
759 * (riscv_cpu_do_interrupt) is correct
760 */
761 MemTxResult res;
762 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
763 int mode = mmuidx_priv(mmu_idx);
764 bool use_background = false;
765 hwaddr ppn;
766 int napot_bits = 0;
767 target_ulong napot_mask;
768
769 /*
770 * Check if we should use the background registers for the two
771 * stage translation. We don't need to check if we actually need
772 * two stage translation as that happened before this function
773 * was called. Background registers will be used if the guest has
774 * forced a two stage translation to be on (in HS or M mode).
775 */
776 if (!env->virt_enabled && two_stage) {
777 use_background = true;
778 }
779
780 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
781 *physical = addr;
782 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
783 return TRANSLATE_SUCCESS;
784 }
785
786 *ret_prot = 0;
787
788 hwaddr base;
789 int levels, ptidxbits, ptesize, vm, widened;
790
791 if (first_stage == true) {
792 if (use_background) {
793 if (riscv_cpu_mxl(env) == MXL_RV32) {
794 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
795 vm = get_field(env->vsatp, SATP32_MODE);
796 } else {
797 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
798 vm = get_field(env->vsatp, SATP64_MODE);
799 }
800 } else {
801 if (riscv_cpu_mxl(env) == MXL_RV32) {
802 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
803 vm = get_field(env->satp, SATP32_MODE);
804 } else {
805 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
806 vm = get_field(env->satp, SATP64_MODE);
807 }
808 }
809 widened = 0;
810 } else {
811 if (riscv_cpu_mxl(env) == MXL_RV32) {
812 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
813 vm = get_field(env->hgatp, SATP32_MODE);
814 } else {
815 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
816 vm = get_field(env->hgatp, SATP64_MODE);
817 }
818 widened = 2;
819 }
820
821 switch (vm) {
822 case VM_1_10_SV32:
823 levels = 2; ptidxbits = 10; ptesize = 4; break;
824 case VM_1_10_SV39:
825 levels = 3; ptidxbits = 9; ptesize = 8; break;
826 case VM_1_10_SV48:
827 levels = 4; ptidxbits = 9; ptesize = 8; break;
828 case VM_1_10_SV57:
829 levels = 5; ptidxbits = 9; ptesize = 8; break;
830 case VM_1_10_MBARE:
831 *physical = addr;
832 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
833 return TRANSLATE_SUCCESS;
834 default:
835 g_assert_not_reached();
836 }
837
838 CPUState *cs = env_cpu(env);
839 int va_bits = PGSHIFT + levels * ptidxbits + widened;
840
841 if (first_stage == true) {
842 target_ulong mask, masked_msbs;
843
844 if (TARGET_LONG_BITS > (va_bits - 1)) {
845 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
846 } else {
847 mask = 0;
848 }
849 masked_msbs = (addr >> (va_bits - 1)) & mask;
850
851 if (masked_msbs != 0 && masked_msbs != mask) {
852 return TRANSLATE_FAIL;
853 }
854 } else {
855 if (vm != VM_1_10_SV32 && addr >> va_bits != 0) {
856 return TRANSLATE_FAIL;
857 }
858 }
859
860 bool pbmte = env->menvcfg & MENVCFG_PBMTE;
861 bool hade = env->menvcfg & MENVCFG_HADE;
862
863 if (first_stage && two_stage && env->virt_enabled) {
864 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
865 hade = hade && (env->henvcfg & HENVCFG_HADE);
866 }
867
868 int ptshift = (levels - 1) * ptidxbits;
869 target_ulong pte;
870 hwaddr pte_addr;
871 int i;
872
873 #if !TCG_OVERSIZED_GUEST
874 restart:
875 #endif
876 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
877 target_ulong idx;
878 if (i == 0) {
879 idx = (addr >> (PGSHIFT + ptshift)) &
880 ((1 << (ptidxbits + widened)) - 1);
881 } else {
882 idx = (addr >> (PGSHIFT + ptshift)) &
883 ((1 << ptidxbits) - 1);
884 }
885
886 /* check that physical address of PTE is legal */
887
888 if (two_stage && first_stage) {
889 int vbase_prot;
890 hwaddr vbase;
891
892 /* Do the second stage translation on the base PTE address. */
893 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
894 base, NULL, MMU_DATA_LOAD,
895 MMUIdx_U, false, true,
896 is_debug);
897
898 if (vbase_ret != TRANSLATE_SUCCESS) {
899 if (fault_pte_addr) {
900 *fault_pte_addr = (base + idx * ptesize) >> 2;
901 }
902 return TRANSLATE_G_STAGE_FAIL;
903 }
904
905 pte_addr = vbase + idx * ptesize;
906 } else {
907 pte_addr = base + idx * ptesize;
908 }
909
910 int pmp_prot;
911 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
912 sizeof(target_ulong),
913 MMU_DATA_LOAD, PRV_S);
914 if (pmp_ret != TRANSLATE_SUCCESS) {
915 return TRANSLATE_PMP_FAIL;
916 }
917
918 if (riscv_cpu_mxl(env) == MXL_RV32) {
919 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
920 } else {
921 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
922 }
923
924 if (res != MEMTX_OK) {
925 return TRANSLATE_FAIL;
926 }
927
928 if (riscv_cpu_sxl(env) == MXL_RV32) {
929 ppn = pte >> PTE_PPN_SHIFT;
930 } else {
931 if (pte & PTE_RESERVED) {
932 return TRANSLATE_FAIL;
933 }
934
935 if (!pbmte && (pte & PTE_PBMT)) {
936 return TRANSLATE_FAIL;
937 }
938
939 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
940 return TRANSLATE_FAIL;
941 }
942
943 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
944 }
945
946 if (!(pte & PTE_V)) {
947 /* Invalid PTE */
948 return TRANSLATE_FAIL;
949 }
950 if (pte & (PTE_R | PTE_W | PTE_X)) {
951 goto leaf;
952 }
953
954 /* Inner PTE, continue walking */
955 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
956 return TRANSLATE_FAIL;
957 }
958 base = ppn << PGSHIFT;
959 }
960
961 /* No leaf pte at any translation level. */
962 return TRANSLATE_FAIL;
963
964 leaf:
965 if (ppn & ((1ULL << ptshift) - 1)) {
966 /* Misaligned PPN */
967 return TRANSLATE_FAIL;
968 }
969 if (!pbmte && (pte & PTE_PBMT)) {
970 /* Reserved without Svpbmt. */
971 return TRANSLATE_FAIL;
972 }
973
974 /* Check for reserved combinations of RWX flags. */
975 switch (pte & (PTE_R | PTE_W | PTE_X)) {
976 case PTE_W:
977 case PTE_W | PTE_X:
978 return TRANSLATE_FAIL;
979 }
980
981 int prot = 0;
982 if (pte & PTE_R) {
983 prot |= PAGE_READ;
984 }
985 if (pte & PTE_W) {
986 prot |= PAGE_WRITE;
987 }
988 if (pte & PTE_X) {
989 bool mxr;
990
991 if (first_stage == true) {
992 mxr = get_field(env->mstatus, MSTATUS_MXR);
993 } else {
994 mxr = get_field(env->vsstatus, MSTATUS_MXR);
995 }
996 if (mxr) {
997 prot |= PAGE_READ;
998 }
999 prot |= PAGE_EXEC;
1000 }
1001
1002 if (pte & PTE_U) {
1003 if (mode != PRV_U) {
1004 if (!mmuidx_sum(mmu_idx)) {
1005 return TRANSLATE_FAIL;
1006 }
1007 /* SUM allows only read+write, not execute. */
1008 prot &= PAGE_READ | PAGE_WRITE;
1009 }
1010 } else if (mode != PRV_S) {
1011 /* Supervisor PTE flags when not S mode */
1012 return TRANSLATE_FAIL;
1013 }
1014
1015 if (!((prot >> access_type) & 1)) {
1016 /* Access check failed */
1017 return TRANSLATE_FAIL;
1018 }
1019
1020 /* If necessary, set accessed and dirty bits. */
1021 target_ulong updated_pte = pte | PTE_A |
1022 (access_type == MMU_DATA_STORE ? PTE_D : 0);
1023
1024 /* Page table updates need to be atomic with MTTCG enabled */
1025 if (updated_pte != pte && !is_debug) {
1026 if (!hade) {
1027 return TRANSLATE_FAIL;
1028 }
1029
1030 /*
1031 * - if accessed or dirty bits need updating, and the PTE is
1032 * in RAM, then we do so atomically with a compare and swap.
1033 * - if the PTE is in IO space or ROM, then it can't be updated
1034 * and we return TRANSLATE_FAIL.
1035 * - if the PTE changed by the time we went to update it, then
1036 * it is no longer valid and we must re-walk the page table.
1037 */
1038 MemoryRegion *mr;
1039 hwaddr l = sizeof(target_ulong), addr1;
1040 mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
1041 false, MEMTXATTRS_UNSPECIFIED);
1042 if (memory_region_is_ram(mr)) {
1043 target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
1044 #if TCG_OVERSIZED_GUEST
1045 /*
1046 * MTTCG is not enabled on oversized TCG guests so
1047 * page table updates do not need to be atomic
1048 */
1049 *pte_pa = pte = updated_pte;
1050 #else
1051 target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
1052 if (old_pte != pte) {
1053 goto restart;
1054 }
1055 pte = updated_pte;
1056 #endif
1057 } else {
1058 /*
1059 * Misconfigured PTE in ROM (AD bits are not preset) or
1060 * PTE is in IO space and can't be updated atomically.
1061 */
1062 return TRANSLATE_FAIL;
1063 }
1064 }
1065
1066 /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */
1067 target_ulong vpn = addr >> PGSHIFT;
1068
1069 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
1070 napot_bits = ctzl(ppn) + 1;
1071 if ((i != (levels - 1)) || (napot_bits != 4)) {
1072 return TRANSLATE_FAIL;
1073 }
1074 }
1075
1076 napot_mask = (1 << napot_bits) - 1;
1077 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1078 (vpn & (((target_ulong)1 << ptshift) - 1))
1079 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
1080
1081 /*
1082 * Remove write permission unless this is a store, or the page is
1083 * already dirty, so that we TLB miss on later writes to update
1084 * the dirty bit.
1085 */
1086 if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) {
1087 prot &= ~PAGE_WRITE;
1088 }
1089 *ret_prot = prot;
1090
1091 return TRANSLATE_SUCCESS;
1092 }
1093
1094 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1095 MMUAccessType access_type, bool pmp_violation,
1096 bool first_stage, bool two_stage,
1097 bool two_stage_indirect)
1098 {
1099 CPUState *cs = env_cpu(env);
1100 int page_fault_exceptions, vm;
1101 uint64_t stap_mode;
1102
1103 if (riscv_cpu_mxl(env) == MXL_RV32) {
1104 stap_mode = SATP32_MODE;
1105 } else {
1106 stap_mode = SATP64_MODE;
1107 }
1108
1109 if (first_stage) {
1110 vm = get_field(env->satp, stap_mode);
1111 } else {
1112 vm = get_field(env->hgatp, stap_mode);
1113 }
1114
1115 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1116
1117 switch (access_type) {
1118 case MMU_INST_FETCH:
1119 if (env->virt_enabled && !first_stage) {
1120 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1121 } else {
1122 cs->exception_index = page_fault_exceptions ?
1123 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1124 }
1125 break;
1126 case MMU_DATA_LOAD:
1127 if (two_stage && !first_stage) {
1128 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1129 } else {
1130 cs->exception_index = page_fault_exceptions ?
1131 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1132 }
1133 break;
1134 case MMU_DATA_STORE:
1135 if (two_stage && !first_stage) {
1136 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1137 } else {
1138 cs->exception_index = page_fault_exceptions ?
1139 RISCV_EXCP_STORE_PAGE_FAULT :
1140 RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1141 }
1142 break;
1143 default:
1144 g_assert_not_reached();
1145 }
1146 env->badaddr = address;
1147 env->two_stage_lookup = two_stage;
1148 env->two_stage_indirect_lookup = two_stage_indirect;
1149 }
1150
1151 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1152 {
1153 RISCVCPU *cpu = RISCV_CPU(cs);
1154 CPURISCVState *env = &cpu->env;
1155 hwaddr phys_addr;
1156 int prot;
1157 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1158
1159 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
1160 true, env->virt_enabled, true)) {
1161 return -1;
1162 }
1163
1164 if (env->virt_enabled) {
1165 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
1166 0, mmu_idx, false, true, true)) {
1167 return -1;
1168 }
1169 }
1170
1171 return phys_addr & TARGET_PAGE_MASK;
1172 }
1173
1174 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1175 vaddr addr, unsigned size,
1176 MMUAccessType access_type,
1177 int mmu_idx, MemTxAttrs attrs,
1178 MemTxResult response, uintptr_t retaddr)
1179 {
1180 RISCVCPU *cpu = RISCV_CPU(cs);
1181 CPURISCVState *env = &cpu->env;
1182
1183 if (access_type == MMU_DATA_STORE) {
1184 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1185 } else if (access_type == MMU_DATA_LOAD) {
1186 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1187 } else {
1188 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
1189 }
1190
1191 env->badaddr = addr;
1192 env->two_stage_lookup = mmuidx_2stage(mmu_idx);
1193 env->two_stage_indirect_lookup = false;
1194 cpu_loop_exit_restore(cs, retaddr);
1195 }
1196
1197 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1198 MMUAccessType access_type, int mmu_idx,
1199 uintptr_t retaddr)
1200 {
1201 RISCVCPU *cpu = RISCV_CPU(cs);
1202 CPURISCVState *env = &cpu->env;
1203 switch (access_type) {
1204 case MMU_INST_FETCH:
1205 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1206 break;
1207 case MMU_DATA_LOAD:
1208 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1209 break;
1210 case MMU_DATA_STORE:
1211 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1212 break;
1213 default:
1214 g_assert_not_reached();
1215 }
1216 env->badaddr = addr;
1217 env->two_stage_lookup = mmuidx_2stage(mmu_idx);
1218 env->two_stage_indirect_lookup = false;
1219 cpu_loop_exit_restore(cs, retaddr);
1220 }
1221
1222
1223 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
1224 {
1225 enum riscv_pmu_event_idx pmu_event_type;
1226
1227 switch (access_type) {
1228 case MMU_INST_FETCH:
1229 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
1230 break;
1231 case MMU_DATA_LOAD:
1232 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
1233 break;
1234 case MMU_DATA_STORE:
1235 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
1236 break;
1237 default:
1238 return;
1239 }
1240
1241 riscv_pmu_incr_ctr(cpu, pmu_event_type);
1242 }
1243
1244 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1245 MMUAccessType access_type, int mmu_idx,
1246 bool probe, uintptr_t retaddr)
1247 {
1248 RISCVCPU *cpu = RISCV_CPU(cs);
1249 CPURISCVState *env = &cpu->env;
1250 vaddr im_address;
1251 hwaddr pa = 0;
1252 int prot, prot2, prot_pmp;
1253 bool pmp_violation = false;
1254 bool first_stage_error = true;
1255 bool two_stage_lookup = mmuidx_2stage(mmu_idx);
1256 bool two_stage_indirect_error = false;
1257 int ret = TRANSLATE_FAIL;
1258 int mode = mmu_idx;
1259 /* default TLB page size */
1260 target_ulong tlb_size = TARGET_PAGE_SIZE;
1261
1262 env->guest_phys_fault_addr = 0;
1263
1264 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1265 __func__, address, access_type, mmu_idx);
1266
1267 pmu_tlb_fill_incr_ctr(cpu, access_type);
1268 if (two_stage_lookup) {
1269 /* Two stage lookup */
1270 ret = get_physical_address(env, &pa, &prot, address,
1271 &env->guest_phys_fault_addr, access_type,
1272 mmu_idx, true, true, false);
1273
1274 /*
1275 * A G-stage exception may be triggered during two state lookup.
1276 * And the env->guest_phys_fault_addr has already been set in
1277 * get_physical_address().
1278 */
1279 if (ret == TRANSLATE_G_STAGE_FAIL) {
1280 first_stage_error = false;
1281 two_stage_indirect_error = true;
1282 access_type = MMU_DATA_LOAD;
1283 }
1284
1285 qemu_log_mask(CPU_LOG_MMU,
1286 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1287 HWADDR_FMT_plx " prot %d\n",
1288 __func__, address, ret, pa, prot);
1289
1290 if (ret == TRANSLATE_SUCCESS) {
1291 /* Second stage lookup */
1292 im_address = pa;
1293
1294 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
1295 access_type, MMUIdx_U, false, true,
1296 false);
1297
1298 qemu_log_mask(CPU_LOG_MMU,
1299 "%s 2nd-stage address=%" VADDR_PRIx
1300 " ret %d physical "
1301 HWADDR_FMT_plx " prot %d\n",
1302 __func__, im_address, ret, pa, prot2);
1303
1304 prot &= prot2;
1305
1306 if (ret == TRANSLATE_SUCCESS) {
1307 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1308 size, access_type, mode);
1309
1310 qemu_log_mask(CPU_LOG_MMU,
1311 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1312 " %d tlb_size " TARGET_FMT_lu "\n",
1313 __func__, pa, ret, prot_pmp, tlb_size);
1314
1315 prot &= prot_pmp;
1316 }
1317
1318 if (ret != TRANSLATE_SUCCESS) {
1319 /*
1320 * Guest physical address translation failed, this is a HS
1321 * level exception
1322 */
1323 first_stage_error = false;
1324 env->guest_phys_fault_addr = (im_address |
1325 (address &
1326 (TARGET_PAGE_SIZE - 1))) >> 2;
1327 }
1328 }
1329 } else {
1330 /* Single stage lookup */
1331 ret = get_physical_address(env, &pa, &prot, address, NULL,
1332 access_type, mmu_idx, true, false, false);
1333
1334 qemu_log_mask(CPU_LOG_MMU,
1335 "%s address=%" VADDR_PRIx " ret %d physical "
1336 HWADDR_FMT_plx " prot %d\n",
1337 __func__, address, ret, pa, prot);
1338
1339 if (ret == TRANSLATE_SUCCESS) {
1340 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1341 size, access_type, mode);
1342
1343 qemu_log_mask(CPU_LOG_MMU,
1344 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1345 " %d tlb_size " TARGET_FMT_lu "\n",
1346 __func__, pa, ret, prot_pmp, tlb_size);
1347
1348 prot &= prot_pmp;
1349 }
1350 }
1351
1352 if (ret == TRANSLATE_PMP_FAIL) {
1353 pmp_violation = true;
1354 }
1355
1356 if (ret == TRANSLATE_SUCCESS) {
1357 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1358 prot, mmu_idx, tlb_size);
1359 return true;
1360 } else if (probe) {
1361 return false;
1362 } else {
1363 raise_mmu_exception(env, address, access_type, pmp_violation,
1364 first_stage_error, two_stage_lookup,
1365 two_stage_indirect_error);
1366 cpu_loop_exit_restore(cs, retaddr);
1367 }
1368
1369 return true;
1370 }
1371
1372 static target_ulong riscv_transformed_insn(CPURISCVState *env,
1373 target_ulong insn,
1374 target_ulong taddr)
1375 {
1376 target_ulong xinsn = 0;
1377 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1378
1379 /*
1380 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1381 * be uncompressed. The Quadrant 1 of RVC instruction space need
1382 * not be transformed because these instructions won't generate
1383 * any load/store trap.
1384 */
1385
1386 if ((insn & 0x3) != 0x3) {
1387 /* Transform 16bit instruction into 32bit instruction */
1388 switch (GET_C_OP(insn)) {
1389 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1390 switch (GET_C_FUNC(insn)) {
1391 case OPC_RISC_C_FUNC_FLD_LQ:
1392 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1393 xinsn = OPC_RISC_FLD;
1394 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1395 access_rs1 = GET_C_RS1S(insn);
1396 access_imm = GET_C_LD_IMM(insn);
1397 access_size = 8;
1398 }
1399 break;
1400 case OPC_RISC_C_FUNC_LW: /* C.LW */
1401 xinsn = OPC_RISC_LW;
1402 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1403 access_rs1 = GET_C_RS1S(insn);
1404 access_imm = GET_C_LW_IMM(insn);
1405 access_size = 4;
1406 break;
1407 case OPC_RISC_C_FUNC_FLW_LD:
1408 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1409 xinsn = OPC_RISC_FLW;
1410 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1411 access_rs1 = GET_C_RS1S(insn);
1412 access_imm = GET_C_LW_IMM(insn);
1413 access_size = 4;
1414 } else { /* C.LD (RV64/RV128) */
1415 xinsn = OPC_RISC_LD;
1416 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1417 access_rs1 = GET_C_RS1S(insn);
1418 access_imm = GET_C_LD_IMM(insn);
1419 access_size = 8;
1420 }
1421 break;
1422 case OPC_RISC_C_FUNC_FSD_SQ:
1423 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1424 xinsn = OPC_RISC_FSD;
1425 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1426 access_rs1 = GET_C_RS1S(insn);
1427 access_imm = GET_C_SD_IMM(insn);
1428 access_size = 8;
1429 }
1430 break;
1431 case OPC_RISC_C_FUNC_SW: /* C.SW */
1432 xinsn = OPC_RISC_SW;
1433 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1434 access_rs1 = GET_C_RS1S(insn);
1435 access_imm = GET_C_SW_IMM(insn);
1436 access_size = 4;
1437 break;
1438 case OPC_RISC_C_FUNC_FSW_SD:
1439 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1440 xinsn = OPC_RISC_FSW;
1441 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1442 access_rs1 = GET_C_RS1S(insn);
1443 access_imm = GET_C_SW_IMM(insn);
1444 access_size = 4;
1445 } else { /* C.SD (RV64/RV128) */
1446 xinsn = OPC_RISC_SD;
1447 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1448 access_rs1 = GET_C_RS1S(insn);
1449 access_imm = GET_C_SD_IMM(insn);
1450 access_size = 8;
1451 }
1452 break;
1453 default:
1454 break;
1455 }
1456 break;
1457 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1458 switch (GET_C_FUNC(insn)) {
1459 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1460 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1461 xinsn = OPC_RISC_FLD;
1462 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1463 access_rs1 = 2;
1464 access_imm = GET_C_LDSP_IMM(insn);
1465 access_size = 8;
1466 }
1467 break;
1468 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1469 xinsn = OPC_RISC_LW;
1470 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1471 access_rs1 = 2;
1472 access_imm = GET_C_LWSP_IMM(insn);
1473 access_size = 4;
1474 break;
1475 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1476 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1477 xinsn = OPC_RISC_FLW;
1478 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1479 access_rs1 = 2;
1480 access_imm = GET_C_LWSP_IMM(insn);
1481 access_size = 4;
1482 } else { /* C.LDSP (RV64/RV128) */
1483 xinsn = OPC_RISC_LD;
1484 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1485 access_rs1 = 2;
1486 access_imm = GET_C_LDSP_IMM(insn);
1487 access_size = 8;
1488 }
1489 break;
1490 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1491 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1492 xinsn = OPC_RISC_FSD;
1493 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1494 access_rs1 = 2;
1495 access_imm = GET_C_SDSP_IMM(insn);
1496 access_size = 8;
1497 }
1498 break;
1499 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1500 xinsn = OPC_RISC_SW;
1501 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1502 access_rs1 = 2;
1503 access_imm = GET_C_SWSP_IMM(insn);
1504 access_size = 4;
1505 break;
1506 case 7:
1507 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1508 xinsn = OPC_RISC_FSW;
1509 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1510 access_rs1 = 2;
1511 access_imm = GET_C_SWSP_IMM(insn);
1512 access_size = 4;
1513 } else { /* C.SDSP (RV64/RV128) */
1514 xinsn = OPC_RISC_SD;
1515 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1516 access_rs1 = 2;
1517 access_imm = GET_C_SDSP_IMM(insn);
1518 access_size = 8;
1519 }
1520 break;
1521 default:
1522 break;
1523 }
1524 break;
1525 default:
1526 break;
1527 }
1528
1529 /*
1530 * Clear Bit1 of transformed instruction to indicate that
1531 * original insruction was a 16bit instruction
1532 */
1533 xinsn &= ~((target_ulong)0x2);
1534 } else {
1535 /* Transform 32bit (or wider) instructions */
1536 switch (MASK_OP_MAJOR(insn)) {
1537 case OPC_RISC_ATOMIC:
1538 xinsn = insn;
1539 access_rs1 = GET_RS1(insn);
1540 access_size = 1 << GET_FUNCT3(insn);
1541 break;
1542 case OPC_RISC_LOAD:
1543 case OPC_RISC_FP_LOAD:
1544 xinsn = SET_I_IMM(insn, 0);
1545 access_rs1 = GET_RS1(insn);
1546 access_imm = GET_IMM(insn);
1547 access_size = 1 << GET_FUNCT3(insn);
1548 break;
1549 case OPC_RISC_STORE:
1550 case OPC_RISC_FP_STORE:
1551 xinsn = SET_S_IMM(insn, 0);
1552 access_rs1 = GET_RS1(insn);
1553 access_imm = GET_STORE_IMM(insn);
1554 access_size = 1 << GET_FUNCT3(insn);
1555 break;
1556 case OPC_RISC_SYSTEM:
1557 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1558 xinsn = insn;
1559 access_rs1 = GET_RS1(insn);
1560 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1561 access_size = 1 << access_size;
1562 }
1563 break;
1564 default:
1565 break;
1566 }
1567 }
1568
1569 if (access_size) {
1570 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1571 (access_size - 1));
1572 }
1573
1574 return xinsn;
1575 }
1576 #endif /* !CONFIG_USER_ONLY */
1577
1578 /*
1579 * Handle Traps
1580 *
1581 * Adapted from Spike's processor_t::take_trap.
1582 *
1583 */
1584 void riscv_cpu_do_interrupt(CPUState *cs)
1585 {
1586 #if !defined(CONFIG_USER_ONLY)
1587
1588 RISCVCPU *cpu = RISCV_CPU(cs);
1589 CPURISCVState *env = &cpu->env;
1590 bool write_gva = false;
1591 uint64_t s;
1592
1593 /*
1594 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1595 * so we mask off the MSB and separate into trap type and cause.
1596 */
1597 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1598 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
1599 uint64_t deleg = async ? env->mideleg : env->medeleg;
1600 target_ulong tval = 0;
1601 target_ulong tinst = 0;
1602 target_ulong htval = 0;
1603 target_ulong mtval2 = 0;
1604
1605 if (cause == RISCV_EXCP_SEMIHOST) {
1606 do_common_semihosting(cs);
1607 env->pc += 4;
1608 return;
1609 }
1610
1611 if (!async) {
1612 /* set tval to badaddr for traps with address information */
1613 switch (cause) {
1614 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1615 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
1616 case RISCV_EXCP_LOAD_ADDR_MIS:
1617 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1618 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1619 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
1620 case RISCV_EXCP_LOAD_PAGE_FAULT:
1621 case RISCV_EXCP_STORE_PAGE_FAULT:
1622 write_gva = env->two_stage_lookup;
1623 tval = env->badaddr;
1624 if (env->two_stage_indirect_lookup) {
1625 /*
1626 * special pseudoinstruction for G-stage fault taken while
1627 * doing VS-stage page table walk.
1628 */
1629 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1630 } else {
1631 /*
1632 * The "Addr. Offset" field in transformed instruction is
1633 * non-zero only for misaligned access.
1634 */
1635 tinst = riscv_transformed_insn(env, env->bins, tval);
1636 }
1637 break;
1638 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1639 case RISCV_EXCP_INST_ADDR_MIS:
1640 case RISCV_EXCP_INST_ACCESS_FAULT:
1641 case RISCV_EXCP_INST_PAGE_FAULT:
1642 write_gva = env->two_stage_lookup;
1643 tval = env->badaddr;
1644 if (env->two_stage_indirect_lookup) {
1645 /*
1646 * special pseudoinstruction for G-stage fault taken while
1647 * doing VS-stage page table walk.
1648 */
1649 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1650 }
1651 break;
1652 case RISCV_EXCP_ILLEGAL_INST:
1653 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
1654 tval = env->bins;
1655 break;
1656 case RISCV_EXCP_BREAKPOINT:
1657 if (cs->watchpoint_hit) {
1658 tval = cs->watchpoint_hit->hitaddr;
1659 cs->watchpoint_hit = NULL;
1660 }
1661 break;
1662 default:
1663 break;
1664 }
1665 /* ecall is dispatched as one cause so translate based on mode */
1666 if (cause == RISCV_EXCP_U_ECALL) {
1667 assert(env->priv <= 3);
1668
1669 if (env->priv == PRV_M) {
1670 cause = RISCV_EXCP_M_ECALL;
1671 } else if (env->priv == PRV_S && env->virt_enabled) {
1672 cause = RISCV_EXCP_VS_ECALL;
1673 } else if (env->priv == PRV_S && !env->virt_enabled) {
1674 cause = RISCV_EXCP_S_ECALL;
1675 } else if (env->priv == PRV_U) {
1676 cause = RISCV_EXCP_U_ECALL;
1677 }
1678 }
1679 }
1680
1681 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
1682 riscv_cpu_get_trap_name(cause, async));
1683
1684 qemu_log_mask(CPU_LOG_INT,
1685 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1686 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1687 __func__, env->mhartid, async, cause, env->pc, tval,
1688 riscv_cpu_get_trap_name(cause, async));
1689
1690 if (env->priv <= PRV_S &&
1691 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
1692 /* handle the trap in S-mode */
1693 if (riscv_has_ext(env, RVH)) {
1694 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1695
1696 if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
1697 /* Trap to VS mode */
1698 /*
1699 * See if we need to adjust cause. Yes if its VS mode interrupt
1700 * no if hypervisor has delegated one of hs mode's interrupt
1701 */
1702 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
1703 cause == IRQ_VS_EXT) {
1704 cause = cause - 1;
1705 }
1706 write_gva = false;
1707 } else if (env->virt_enabled) {
1708 /* Trap into HS mode, from virt */
1709 riscv_cpu_swap_hypervisor_regs(env);
1710 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
1711 env->priv);
1712 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
1713
1714 htval = env->guest_phys_fault_addr;
1715
1716 riscv_cpu_set_virt_enabled(env, 0);
1717 } else {
1718 /* Trap into HS mode */
1719 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
1720 htval = env->guest_phys_fault_addr;
1721 }
1722 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
1723 }
1724
1725 s = env->mstatus;
1726 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
1727 s = set_field(s, MSTATUS_SPP, env->priv);
1728 s = set_field(s, MSTATUS_SIE, 0);
1729 env->mstatus = s;
1730 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
1731 env->sepc = env->pc;
1732 env->stval = tval;
1733 env->htval = htval;
1734 env->htinst = tinst;
1735 env->pc = (env->stvec >> 2 << 2) +
1736 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
1737 riscv_cpu_set_mode(env, PRV_S);
1738 } else {
1739 /* handle the trap in M-mode */
1740 if (riscv_has_ext(env, RVH)) {
1741 if (env->virt_enabled) {
1742 riscv_cpu_swap_hypervisor_regs(env);
1743 }
1744 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
1745 env->virt_enabled);
1746 if (env->virt_enabled && tval) {
1747 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1748 }
1749
1750 mtval2 = env->guest_phys_fault_addr;
1751
1752 /* Trapping to M mode, virt is disabled */
1753 riscv_cpu_set_virt_enabled(env, 0);
1754 }
1755
1756 s = env->mstatus;
1757 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
1758 s = set_field(s, MSTATUS_MPP, env->priv);
1759 s = set_field(s, MSTATUS_MIE, 0);
1760 env->mstatus = s;
1761 env->mcause = cause | ~(((target_ulong)-1) >> async);
1762 env->mepc = env->pc;
1763 env->mtval = tval;
1764 env->mtval2 = mtval2;
1765 env->mtinst = tinst;
1766 env->pc = (env->mtvec >> 2 << 2) +
1767 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
1768 riscv_cpu_set_mode(env, PRV_M);
1769 }
1770
1771 /*
1772 * NOTE: it is not necessary to yield load reservations here. It is only
1773 * necessary for an SC from "another hart" to cause a load reservation
1774 * to be yielded. Refer to the memory consistency model section of the
1775 * RISC-V ISA Specification.
1776 */
1777
1778 env->two_stage_lookup = false;
1779 env->two_stage_indirect_lookup = false;
1780 #endif
1781 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
1782 }
AR7 emulation for QEMU