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qapi: Inline gen_visit_members() into lone caller
[qemu/ar7.git] / target-tricore / translate.c
blobd13e5c8c623a8cc2427ff714b1775020903685ca
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "tricore-opcodes.h"
31 #include "exec/log.h"
32
33 /*
34 * TCG registers
35 */
36 static TCGv cpu_PC;
37 static TCGv cpu_PCXI;
38 static TCGv cpu_PSW;
39 static TCGv cpu_ICR;
40 /* GPR registers */
41 static TCGv cpu_gpr_a[16];
42 static TCGv cpu_gpr_d[16];
43 /* PSW Flag cache */
44 static TCGv cpu_PSW_C;
45 static TCGv cpu_PSW_V;
46 static TCGv cpu_PSW_SV;
47 static TCGv cpu_PSW_AV;
48 static TCGv cpu_PSW_SAV;
49 /* CPU env */
50 static TCGv_env cpu_env;
51
52 #include "exec/gen-icount.h"
53
54 static const char *regnames_a[] = {
55 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
56 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
57 "a12" , "a13" , "a14" , "a15",
58 };
59
60 static const char *regnames_d[] = {
61 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
62 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
63 "d12" , "d13" , "d14" , "d15",
64 };
65
66 typedef struct DisasContext {
67 struct TranslationBlock *tb;
68 target_ulong pc, saved_pc, next_pc;
69 uint32_t opcode;
70 int singlestep_enabled;
71 /* Routine used to access memory */
72 int mem_idx;
73 uint32_t hflags, saved_hflags;
74 int bstate;
75 } DisasContext;
76
77 enum {
78
79 BS_NONE = 0,
80 BS_STOP = 1,
81 BS_BRANCH = 2,
82 BS_EXCP = 3,
83 };
84
85 enum {
86 MODE_LL = 0,
87 MODE_LU = 1,
88 MODE_UL = 2,
89 MODE_UU = 3,
90 };
91
92 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
93 fprintf_function cpu_fprintf, int flags)
94 {
95 TriCoreCPU *cpu = TRICORE_CPU(cs);
96 CPUTriCoreState *env = &cpu->env;
97 uint32_t psw;
98 int i;
99
100 psw = psw_read(env);
101
102 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
103 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
104 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
105 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
106 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
107 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
108
109 for (i = 0; i < 16; ++i) {
110 if ((i & 3) == 0) {
111 cpu_fprintf(f, "\nGPR A%02d:", i);
112 }
113 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
114 }
115 for (i = 0; i < 16; ++i) {
116 if ((i & 3) == 0) {
117 cpu_fprintf(f, "\nGPR D%02d:", i);
118 }
119 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
120 }
121 cpu_fprintf(f, "\n");
122 }
123
124 /*
125 * Functions to generate micro-ops
126 */
127
128 /* Makros for generating helpers */
129
130 #define gen_helper_1arg(name, arg) do { \
131 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
132 gen_helper_##name(cpu_env, helper_tmp); \
133 tcg_temp_free_i32(helper_tmp); \
134 } while (0)
135
136 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
137 TCGv arg00 = tcg_temp_new(); \
138 TCGv arg01 = tcg_temp_new(); \
139 TCGv arg11 = tcg_temp_new(); \
140 tcg_gen_sari_tl(arg00, arg0, 16); \
141 tcg_gen_ext16s_tl(arg01, arg0); \
142 tcg_gen_ext16s_tl(arg11, arg1); \
143 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
144 tcg_temp_free(arg00); \
145 tcg_temp_free(arg01); \
146 tcg_temp_free(arg11); \
147 } while (0)
148
149 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
150 TCGv arg00 = tcg_temp_new(); \
151 TCGv arg01 = tcg_temp_new(); \
152 TCGv arg10 = tcg_temp_new(); \
153 TCGv arg11 = tcg_temp_new(); \
154 tcg_gen_sari_tl(arg00, arg0, 16); \
155 tcg_gen_ext16s_tl(arg01, arg0); \
156 tcg_gen_sari_tl(arg11, arg1, 16); \
157 tcg_gen_ext16s_tl(arg10, arg1); \
158 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
159 tcg_temp_free(arg00); \
160 tcg_temp_free(arg01); \
161 tcg_temp_free(arg10); \
162 tcg_temp_free(arg11); \
163 } while (0)
164
165 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
166 TCGv arg00 = tcg_temp_new(); \
167 TCGv arg01 = tcg_temp_new(); \
168 TCGv arg10 = tcg_temp_new(); \
169 TCGv arg11 = tcg_temp_new(); \
170 tcg_gen_sari_tl(arg00, arg0, 16); \
171 tcg_gen_ext16s_tl(arg01, arg0); \
172 tcg_gen_sari_tl(arg10, arg1, 16); \
173 tcg_gen_ext16s_tl(arg11, arg1); \
174 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
175 tcg_temp_free(arg00); \
176 tcg_temp_free(arg01); \
177 tcg_temp_free(arg10); \
178 tcg_temp_free(arg11); \
179 } while (0)
180
181 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
182 TCGv arg00 = tcg_temp_new(); \
183 TCGv arg01 = tcg_temp_new(); \
184 TCGv arg11 = tcg_temp_new(); \
185 tcg_gen_sari_tl(arg01, arg0, 16); \
186 tcg_gen_ext16s_tl(arg00, arg0); \
187 tcg_gen_sari_tl(arg11, arg1, 16); \
188 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
189 tcg_temp_free(arg00); \
190 tcg_temp_free(arg01); \
191 tcg_temp_free(arg11); \
192 } while (0)
193
194 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
195 TCGv_i64 ret = tcg_temp_new_i64(); \
196 TCGv_i64 arg1 = tcg_temp_new_i64(); \
197 \
198 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
199 gen_helper_##name(ret, arg1, arg2); \
200 tcg_gen_extr_i64_i32(rl, rh, ret); \
201 \
202 tcg_temp_free_i64(ret); \
203 tcg_temp_free_i64(arg1); \
204 } while (0)
205
206 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
207 TCGv_i64 ret = tcg_temp_new_i64(); \
208 \
209 gen_helper_##name(ret, cpu_env, arg1, arg2); \
210 tcg_gen_extr_i64_i32(rl, rh, ret); \
211 \
212 tcg_temp_free_i64(ret); \
213 } while (0)
214
215 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
216 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
217 ((offset & 0x0fffff) << 1))
218
219 /* For two 32-bit registers used a 64-bit register, the first
220 registernumber needs to be even. Otherwise we trap. */
221 static inline void generate_trap(DisasContext *ctx, int class, int tin);
222 #define CHECK_REG_PAIR(reg) do { \
223 if (reg & 0x1) { \
224 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
225 } \
226 } while (0)
227
228 /* Functions for load/save to/from memory */
229
230 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
231 int16_t con, TCGMemOp mop)
232 {
233 TCGv temp = tcg_temp_new();
234 tcg_gen_addi_tl(temp, r2, con);
235 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
236 tcg_temp_free(temp);
237 }
238
239 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
240 int16_t con, TCGMemOp mop)
241 {
242 TCGv temp = tcg_temp_new();
243 tcg_gen_addi_tl(temp, r2, con);
244 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
245 tcg_temp_free(temp);
246 }
247
248 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
249 {
250 TCGv_i64 temp = tcg_temp_new_i64();
251
252 tcg_gen_concat_i32_i64(temp, rl, rh);
253 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
254
255 tcg_temp_free_i64(temp);
256 }
257
258 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
259 DisasContext *ctx)
260 {
261 TCGv temp = tcg_temp_new();
262 tcg_gen_addi_tl(temp, base, con);
263 gen_st_2regs_64(rh, rl, temp, ctx);
264 tcg_temp_free(temp);
265 }
266
267 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
268 {
269 TCGv_i64 temp = tcg_temp_new_i64();
270
271 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
272 /* write back to two 32 bit regs */
273 tcg_gen_extr_i64_i32(rl, rh, temp);
274
275 tcg_temp_free_i64(temp);
276 }
277
278 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
279 DisasContext *ctx)
280 {
281 TCGv temp = tcg_temp_new();
282 tcg_gen_addi_tl(temp, base, con);
283 gen_ld_2regs_64(rh, rl, temp, ctx);
284 tcg_temp_free(temp);
285 }
286
287 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
288 TCGMemOp mop)
289 {
290 TCGv temp = tcg_temp_new();
291 tcg_gen_addi_tl(temp, r2, off);
292 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
293 tcg_gen_mov_tl(r2, temp);
294 tcg_temp_free(temp);
295 }
296
297 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
298 TCGMemOp mop)
299 {
300 TCGv temp = tcg_temp_new();
301 tcg_gen_addi_tl(temp, r2, off);
302 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
303 tcg_gen_mov_tl(r2, temp);
304 tcg_temp_free(temp);
305 }
306
307 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
308 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
309 {
310 TCGv temp = tcg_temp_new();
311 TCGv temp2 = tcg_temp_new();
312
313 CHECK_REG_PAIR(ereg);
314 /* temp = (M(EA, word) */
315 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
316 /* temp = temp & ~E[a][63:32]) */
317 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
318 /* temp2 = (E[a][31:0] & E[a][63:32]); */
319 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
320 /* temp = temp | temp2; */
321 tcg_gen_or_tl(temp, temp, temp2);
322 /* M(EA, word) = temp; */
323 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
324
325 tcg_temp_free(temp);
326 tcg_temp_free(temp2);
327 }
328
329 /* tmp = M(EA, word);
330 M(EA, word) = D[a];
331 D[a] = tmp[31:0];*/
332 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
333 {
334 TCGv temp = tcg_temp_new();
335
336 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
337 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
338 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
339
340 tcg_temp_free(temp);
341 }
342
343 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
344 {
345 TCGv temp = tcg_temp_new();
346 TCGv temp2 = tcg_temp_new();
347 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
348 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
349 cpu_gpr_d[reg], temp);
350 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
351 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
352
353 tcg_temp_free(temp);
354 tcg_temp_free(temp2);
355 }
356
357 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
358 {
359 TCGv temp = tcg_temp_new();
360 TCGv temp2 = tcg_temp_new();
361 TCGv temp3 = tcg_temp_new();
362
363 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
364 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
365 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
366 tcg_gen_or_tl(temp2, temp2, temp3);
367 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
368 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
369
370 tcg_temp_free(temp);
371 tcg_temp_free(temp2);
372 tcg_temp_free(temp3);
373 }
374
375
376 /* We generate loads and store to core special function register (csfr) through
377 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
378 makros R, A and E, which allow read-only, all and endinit protected access.
379 These makros also specify in which ISA version the csfr was introduced. */
380 #define R(ADDRESS, REG, FEATURE) \
381 case ADDRESS: \
382 if (tricore_feature(env, FEATURE)) { \
383 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
384 } \
385 break;
386 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
387 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
388 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
389 {
390 /* since we're caching PSW make this a special case */
391 if (offset == 0xfe04) {
392 gen_helper_psw_read(ret, cpu_env);
393 } else {
394 switch (offset) {
395 #include "csfr.def"
396 }
397 }
398 }
399 #undef R
400 #undef A
401 #undef E
402
403 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
404 since no execption occurs */
405 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
406 case ADDRESS: \
407 if (tricore_feature(env, FEATURE)) { \
408 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
409 } \
410 break;
411 /* Endinit protected registers
412 TODO: Since the endinit bit is in a register of a not yet implemented
413 watchdog device, we handle endinit protected registers like
414 all-access registers for now. */
415 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
416 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
417 int32_t offset)
418 {
419 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
420 /* since we're caching PSW make this a special case */
421 if (offset == 0xfe04) {
422 gen_helper_psw_write(cpu_env, r1);
423 } else {
424 switch (offset) {
425 #include "csfr.def"
426 }
427 }
428 } else {
429 /* generate privilege trap */
430 }
431 }
432
433 /* Functions for arithmetic instructions */
434
435 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
436 {
437 TCGv t0 = tcg_temp_new_i32();
438 TCGv result = tcg_temp_new_i32();
439 /* Addition and set V/SV bits */
440 tcg_gen_add_tl(result, r1, r2);
441 /* calc V bit */
442 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
443 tcg_gen_xor_tl(t0, r1, r2);
444 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
445 /* Calc SV bit */
446 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
447 /* Calc AV/SAV bits */
448 tcg_gen_add_tl(cpu_PSW_AV, result, result);
449 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
450 /* calc SAV */
451 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
452 /* write back result */
453 tcg_gen_mov_tl(ret, result);
454
455 tcg_temp_free(result);
456 tcg_temp_free(t0);
457 }
458
459 static inline void
460 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
461 {
462 TCGv temp = tcg_temp_new();
463 TCGv_i64 t0 = tcg_temp_new_i64();
464 TCGv_i64 t1 = tcg_temp_new_i64();
465 TCGv_i64 result = tcg_temp_new_i64();
466
467 tcg_gen_add_i64(result, r1, r2);
468 /* calc v bit */
469 tcg_gen_xor_i64(t1, result, r1);
470 tcg_gen_xor_i64(t0, r1, r2);
471 tcg_gen_andc_i64(t1, t1, t0);
472 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
473 /* calc SV bit */
474 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
475 /* calc AV/SAV bits */
476 tcg_gen_extrh_i64_i32(temp, result);
477 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
478 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
479 /* calc SAV */
480 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
481 /* write back result */
482 tcg_gen_mov_i64(ret, result);
483
484 tcg_temp_free(temp);
485 tcg_temp_free_i64(result);
486 tcg_temp_free_i64(t0);
487 tcg_temp_free_i64(t1);
488 }
489
490 static inline void
491 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
492 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
493 void(*op2)(TCGv, TCGv, TCGv))
494 {
495 TCGv temp = tcg_temp_new();
496 TCGv temp2 = tcg_temp_new();
497 TCGv temp3 = tcg_temp_new();
498 TCGv temp4 = tcg_temp_new();
499
500 (*op1)(temp, r1_low, r2);
501 /* calc V0 bit */
502 tcg_gen_xor_tl(temp2, temp, r1_low);
503 tcg_gen_xor_tl(temp3, r1_low, r2);
504 if (op1 == tcg_gen_add_tl) {
505 tcg_gen_andc_tl(temp2, temp2, temp3);
506 } else {
507 tcg_gen_and_tl(temp2, temp2, temp3);
508 }
509
510 (*op2)(temp3, r1_high, r3);
511 /* calc V1 bit */
512 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
513 tcg_gen_xor_tl(temp4, r1_high, r3);
514 if (op2 == tcg_gen_add_tl) {
515 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
516 } else {
517 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
518 }
519 /* combine V0/V1 bits */
520 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
521 /* calc sv bit */
522 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
523 /* write result */
524 tcg_gen_mov_tl(ret_low, temp);
525 tcg_gen_mov_tl(ret_high, temp3);
526 /* calc AV bit */
527 tcg_gen_add_tl(temp, ret_low, ret_low);
528 tcg_gen_xor_tl(temp, temp, ret_low);
529 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
530 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
531 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
532 /* calc SAV bit */
533 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
534
535 tcg_temp_free(temp);
536 tcg_temp_free(temp2);
537 tcg_temp_free(temp3);
538 tcg_temp_free(temp4);
539 }
540
541 /* ret = r2 + (r1 * r3); */
542 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
543 {
544 TCGv_i64 t1 = tcg_temp_new_i64();
545 TCGv_i64 t2 = tcg_temp_new_i64();
546 TCGv_i64 t3 = tcg_temp_new_i64();
547
548 tcg_gen_ext_i32_i64(t1, r1);
549 tcg_gen_ext_i32_i64(t2, r2);
550 tcg_gen_ext_i32_i64(t3, r3);
551
552 tcg_gen_mul_i64(t1, t1, t3);
553 tcg_gen_add_i64(t1, t2, t1);
554
555 tcg_gen_extrl_i64_i32(ret, t1);
556 /* calc V
557 t1 > 0x7fffffff */
558 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
559 /* t1 < -0x80000000 */
560 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
561 tcg_gen_or_i64(t2, t2, t3);
562 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
563 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
564 /* Calc SV bit */
565 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
566 /* Calc AV/SAV bits */
567 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
568 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
569 /* calc SAV */
570 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
571
572 tcg_temp_free_i64(t1);
573 tcg_temp_free_i64(t2);
574 tcg_temp_free_i64(t3);
575 }
576
577 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
578 {
579 TCGv temp = tcg_const_i32(con);
580 gen_madd32_d(ret, r1, r2, temp);
581 tcg_temp_free(temp);
582 }
583
584 static inline void
585 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
586 TCGv r3)
587 {
588 TCGv t1 = tcg_temp_new();
589 TCGv t2 = tcg_temp_new();
590 TCGv t3 = tcg_temp_new();
591 TCGv t4 = tcg_temp_new();
592
593 tcg_gen_muls2_tl(t1, t2, r1, r3);
594 /* only the add can overflow */
595 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
596 /* calc V bit */
597 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
598 tcg_gen_xor_tl(t1, r2_high, t2);
599 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
600 /* Calc SV bit */
601 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
602 /* Calc AV/SAV bits */
603 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
604 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
605 /* calc SAV */
606 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
607 /* write back the result */
608 tcg_gen_mov_tl(ret_low, t3);
609 tcg_gen_mov_tl(ret_high, t4);
610
611 tcg_temp_free(t1);
612 tcg_temp_free(t2);
613 tcg_temp_free(t3);
614 tcg_temp_free(t4);
615 }
616
617 static inline void
618 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
619 TCGv r3)
620 {
621 TCGv_i64 t1 = tcg_temp_new_i64();
622 TCGv_i64 t2 = tcg_temp_new_i64();
623 TCGv_i64 t3 = tcg_temp_new_i64();
624
625 tcg_gen_extu_i32_i64(t1, r1);
626 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
627 tcg_gen_extu_i32_i64(t3, r3);
628
629 tcg_gen_mul_i64(t1, t1, t3);
630 tcg_gen_add_i64(t2, t2, t1);
631 /* write back result */
632 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
633 /* only the add overflows, if t2 < t1
634 calc V bit */
635 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
636 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
637 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
638 /* Calc SV bit */
639 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
640 /* Calc AV/SAV bits */
641 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
642 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
643 /* calc SAV */
644 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
645
646 tcg_temp_free_i64(t1);
647 tcg_temp_free_i64(t2);
648 tcg_temp_free_i64(t3);
649 }
650
651 static inline void
652 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
653 int32_t con)
654 {
655 TCGv temp = tcg_const_i32(con);
656 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
657 tcg_temp_free(temp);
658 }
659
660 static inline void
661 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
662 int32_t con)
663 {
664 TCGv temp = tcg_const_i32(con);
665 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
666 tcg_temp_free(temp);
667 }
668
669 static inline void
670 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
671 TCGv r3, uint32_t n, uint32_t mode)
672 {
673 TCGv temp = tcg_const_i32(n);
674 TCGv temp2 = tcg_temp_new();
675 TCGv_i64 temp64 = tcg_temp_new_i64();
676 switch (mode) {
677 case MODE_LL:
678 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
679 break;
680 case MODE_LU:
681 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
682 break;
683 case MODE_UL:
684 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
685 break;
686 case MODE_UU:
687 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
688 break;
689 }
690 tcg_gen_extr_i64_i32(temp, temp2, temp64);
691 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
692 tcg_gen_add_tl, tcg_gen_add_tl);
693 tcg_temp_free(temp);
694 tcg_temp_free(temp2);
695 tcg_temp_free_i64(temp64);
696 }
697
698 static inline void
699 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
700 TCGv r3, uint32_t n, uint32_t mode)
701 {
702 TCGv temp = tcg_const_i32(n);
703 TCGv temp2 = tcg_temp_new();
704 TCGv_i64 temp64 = tcg_temp_new_i64();
705 switch (mode) {
706 case MODE_LL:
707 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
708 break;
709 case MODE_LU:
710 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
711 break;
712 case MODE_UL:
713 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
714 break;
715 case MODE_UU:
716 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
717 break;
718 }
719 tcg_gen_extr_i64_i32(temp, temp2, temp64);
720 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
721 tcg_gen_sub_tl, tcg_gen_add_tl);
722 tcg_temp_free(temp);
723 tcg_temp_free(temp2);
724 tcg_temp_free_i64(temp64);
725 }
726
727 static inline void
728 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
729 TCGv r3, uint32_t n, uint32_t mode)
730 {
731 TCGv temp = tcg_const_i32(n);
732 TCGv_i64 temp64 = tcg_temp_new_i64();
733 TCGv_i64 temp64_2 = tcg_temp_new_i64();
734 TCGv_i64 temp64_3 = tcg_temp_new_i64();
735 switch (mode) {
736 case MODE_LL:
737 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
738 break;
739 case MODE_LU:
740 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
741 break;
742 case MODE_UL:
743 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
744 break;
745 case MODE_UU:
746 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
747 break;
748 }
749 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
750 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
751 tcg_gen_ext32s_i64(temp64, temp64); /* low */
752 tcg_gen_sub_i64(temp64, temp64_2, temp64);
753 tcg_gen_shli_i64(temp64, temp64, 16);
754
755 gen_add64_d(temp64_2, temp64_3, temp64);
756 /* write back result */
757 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
758
759 tcg_temp_free(temp);
760 tcg_temp_free_i64(temp64);
761 tcg_temp_free_i64(temp64_2);
762 tcg_temp_free_i64(temp64_3);
763 }
764
765 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
766
767 static inline void
768 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
769 TCGv r3, uint32_t n, uint32_t mode)
770 {
771 TCGv temp = tcg_const_i32(n);
772 TCGv temp2 = tcg_temp_new();
773 TCGv temp3 = tcg_temp_new();
774 TCGv_i64 temp64 = tcg_temp_new_i64();
775
776 switch (mode) {
777 case MODE_LL:
778 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
779 break;
780 case MODE_LU:
781 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
782 break;
783 case MODE_UL:
784 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
785 break;
786 case MODE_UU:
787 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
788 break;
789 }
790 tcg_gen_extr_i64_i32(temp, temp2, temp64);
791 gen_adds(ret_low, r1_low, temp);
792 tcg_gen_mov_tl(temp, cpu_PSW_V);
793 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
794 gen_adds(ret_high, r1_high, temp2);
795 /* combine v bits */
796 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
797 /* combine av bits */
798 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
799
800 tcg_temp_free(temp);
801 tcg_temp_free(temp2);
802 tcg_temp_free(temp3);
803 tcg_temp_free_i64(temp64);
804
805 }
806
807 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
808
809 static inline void
810 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
811 TCGv r3, uint32_t n, uint32_t mode)
812 {
813 TCGv temp = tcg_const_i32(n);
814 TCGv temp2 = tcg_temp_new();
815 TCGv temp3 = tcg_temp_new();
816 TCGv_i64 temp64 = tcg_temp_new_i64();
817
818 switch (mode) {
819 case MODE_LL:
820 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
821 break;
822 case MODE_LU:
823 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
824 break;
825 case MODE_UL:
826 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
827 break;
828 case MODE_UU:
829 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
830 break;
831 }
832 tcg_gen_extr_i64_i32(temp, temp2, temp64);
833 gen_subs(ret_low, r1_low, temp);
834 tcg_gen_mov_tl(temp, cpu_PSW_V);
835 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
836 gen_adds(ret_high, r1_high, temp2);
837 /* combine v bits */
838 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
839 /* combine av bits */
840 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
841
842 tcg_temp_free(temp);
843 tcg_temp_free(temp2);
844 tcg_temp_free(temp3);
845 tcg_temp_free_i64(temp64);
846
847 }
848
849 static inline void
850 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
851 TCGv r3, uint32_t n, uint32_t mode)
852 {
853 TCGv temp = tcg_const_i32(n);
854 TCGv_i64 temp64 = tcg_temp_new_i64();
855 TCGv_i64 temp64_2 = tcg_temp_new_i64();
856
857 switch (mode) {
858 case MODE_LL:
859 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
860 break;
861 case MODE_LU:
862 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
863 break;
864 case MODE_UL:
865 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
866 break;
867 case MODE_UU:
868 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
869 break;
870 }
871 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
872 tcg_gen_ext32s_i64(temp64, temp64); /* low */
873 tcg_gen_sub_i64(temp64, temp64_2, temp64);
874 tcg_gen_shli_i64(temp64, temp64, 16);
875 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
876
877 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
878 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
879
880 tcg_temp_free(temp);
881 tcg_temp_free_i64(temp64);
882 tcg_temp_free_i64(temp64_2);
883 }
884
885
886 static inline void
887 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
888 TCGv r3, uint32_t n, uint32_t mode)
889 {
890 TCGv temp = tcg_const_i32(n);
891 TCGv_i64 temp64 = tcg_temp_new_i64();
892 TCGv_i64 temp64_2 = tcg_temp_new_i64();
893 TCGv_i64 temp64_3 = tcg_temp_new_i64();
894 switch (mode) {
895 case MODE_LL:
896 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
897 break;
898 case MODE_LU:
899 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
900 break;
901 case MODE_UL:
902 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
903 break;
904 case MODE_UU:
905 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
906 break;
907 }
908 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
909 gen_add64_d(temp64_3, temp64_2, temp64);
910 /* write back result */
911 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
912
913 tcg_temp_free(temp);
914 tcg_temp_free_i64(temp64);
915 tcg_temp_free_i64(temp64_2);
916 tcg_temp_free_i64(temp64_3);
917 }
918
919 static inline void
920 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
921 TCGv r3, uint32_t n, uint32_t mode)
922 {
923 TCGv temp = tcg_const_i32(n);
924 TCGv_i64 temp64 = tcg_temp_new_i64();
925 TCGv_i64 temp64_2 = tcg_temp_new_i64();
926 switch (mode) {
927 case MODE_LL:
928 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
929 break;
930 case MODE_LU:
931 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
932 break;
933 case MODE_UL:
934 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
935 break;
936 case MODE_UU:
937 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
938 break;
939 }
940 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
941 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
942 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
943
944 tcg_temp_free(temp);
945 tcg_temp_free_i64(temp64);
946 tcg_temp_free_i64(temp64_2);
947 }
948
949 static inline void
950 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
951 uint32_t mode)
952 {
953 TCGv temp = tcg_const_i32(n);
954 TCGv_i64 temp64 = tcg_temp_new_i64();
955 switch (mode) {
956 case MODE_LL:
957 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
958 break;
959 case MODE_LU:
960 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
961 break;
962 case MODE_UL:
963 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
964 break;
965 case MODE_UU:
966 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
967 break;
968 }
969 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
970
971 tcg_temp_free(temp);
972 tcg_temp_free_i64(temp64);
973 }
974
975 static inline void
976 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
977 {
978 TCGv temp = tcg_temp_new();
979 TCGv temp2 = tcg_temp_new();
980
981 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
982 tcg_gen_shli_tl(temp, r1, 16);
983 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
984
985 tcg_temp_free(temp);
986 tcg_temp_free(temp2);
987 }
988
989 static inline void
990 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
991 {
992 TCGv temp = tcg_const_i32(n);
993 TCGv temp2 = tcg_temp_new();
994 TCGv_i64 temp64 = tcg_temp_new_i64();
995 switch (mode) {
996 case MODE_LL:
997 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
998 break;
999 case MODE_LU:
1000 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1001 break;
1002 case MODE_UL:
1003 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1004 break;
1005 case MODE_UU:
1006 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1007 break;
1008 }
1009 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1010 tcg_gen_shli_tl(temp, r1, 16);
1011 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
1012
1013 tcg_temp_free(temp);
1014 tcg_temp_free(temp2);
1015 tcg_temp_free_i64(temp64);
1016 }
1017
1018
1019 static inline void
1020 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1021 uint32_t n, uint32_t mode)
1022 {
1023 TCGv temp = tcg_const_i32(n);
1024 TCGv_i64 temp64 = tcg_temp_new_i64();
1025 switch (mode) {
1026 case MODE_LL:
1027 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1028 break;
1029 case MODE_LU:
1030 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1031 break;
1032 case MODE_UL:
1033 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1034 break;
1035 case MODE_UU:
1036 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1037 break;
1038 }
1039 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1040
1041 tcg_temp_free(temp);
1042 tcg_temp_free_i64(temp64);
1043 }
1044
1045 static inline void
1046 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1047 {
1048 TCGv temp = tcg_temp_new();
1049 TCGv temp2 = tcg_temp_new();
1050
1051 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1052 tcg_gen_shli_tl(temp, r1, 16);
1053 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1054
1055 tcg_temp_free(temp);
1056 tcg_temp_free(temp2);
1057 }
1058
1059 static inline void
1060 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1061 {
1062 TCGv temp = tcg_const_i32(n);
1063 TCGv temp2 = tcg_temp_new();
1064 TCGv_i64 temp64 = tcg_temp_new_i64();
1065 switch (mode) {
1066 case MODE_LL:
1067 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1068 break;
1069 case MODE_LU:
1070 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1071 break;
1072 case MODE_UL:
1073 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1074 break;
1075 case MODE_UU:
1076 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1077 break;
1078 }
1079 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1080 tcg_gen_shli_tl(temp, r1, 16);
1081 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1082
1083 tcg_temp_free(temp);
1084 tcg_temp_free(temp2);
1085 tcg_temp_free_i64(temp64);
1086 }
1087
1088 static inline void
1089 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1090 {
1091 TCGv temp = tcg_const_i32(n);
1092 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1093 tcg_temp_free(temp);
1094 }
1095
1096 static inline void
1097 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1098 {
1099 TCGv temp = tcg_const_i32(n);
1100 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1101 tcg_temp_free(temp);
1102 }
1103
1104 static inline void
1105 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1106 uint32_t up_shift, CPUTriCoreState *env)
1107 {
1108 TCGv temp = tcg_temp_new();
1109 TCGv temp2 = tcg_temp_new();
1110 TCGv temp3 = tcg_temp_new();
1111 TCGv_i64 t1 = tcg_temp_new_i64();
1112 TCGv_i64 t2 = tcg_temp_new_i64();
1113 TCGv_i64 t3 = tcg_temp_new_i64();
1114
1115 tcg_gen_ext_i32_i64(t2, arg2);
1116 tcg_gen_ext_i32_i64(t3, arg3);
1117
1118 tcg_gen_mul_i64(t2, t2, t3);
1119 tcg_gen_shli_i64(t2, t2, n);
1120
1121 tcg_gen_ext_i32_i64(t1, arg1);
1122 tcg_gen_sari_i64(t2, t2, up_shift);
1123
1124 tcg_gen_add_i64(t3, t1, t2);
1125 tcg_gen_extrl_i64_i32(temp3, t3);
1126 /* calc v bit */
1127 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1128 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1129 tcg_gen_or_i64(t1, t1, t2);
1130 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1131 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1132 /* We produce an overflow on the host if the mul before was
1133 (0x80000000 * 0x80000000) << 1). If this is the
1134 case, we negate the ovf. */
1135 if (n == 1) {
1136 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1137 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1138 tcg_gen_and_tl(temp, temp, temp2);
1139 tcg_gen_shli_tl(temp, temp, 31);
1140 /* negate v bit, if special condition */
1141 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1142 }
1143 /* Calc SV bit */
1144 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1145 /* Calc AV/SAV bits */
1146 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1147 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1148 /* calc SAV */
1149 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1150 /* write back result */
1151 tcg_gen_mov_tl(ret, temp3);
1152
1153 tcg_temp_free(temp);
1154 tcg_temp_free(temp2);
1155 tcg_temp_free(temp3);
1156 tcg_temp_free_i64(t1);
1157 tcg_temp_free_i64(t2);
1158 tcg_temp_free_i64(t3);
1159 }
1160
1161 static inline void
1162 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1163 {
1164 TCGv temp = tcg_temp_new();
1165 TCGv temp2 = tcg_temp_new();
1166 if (n == 0) {
1167 tcg_gen_mul_tl(temp, arg2, arg3);
1168 } else { /* n is expected to be 1 */
1169 tcg_gen_mul_tl(temp, arg2, arg3);
1170 tcg_gen_shli_tl(temp, temp, 1);
1171 /* catch special case r1 = r2 = 0x8000 */
1172 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1173 tcg_gen_sub_tl(temp, temp, temp2);
1174 }
1175 gen_add_d(ret, arg1, temp);
1176
1177 tcg_temp_free(temp);
1178 tcg_temp_free(temp2);
1179 }
1180
1181 static inline void
1182 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1183 {
1184 TCGv temp = tcg_temp_new();
1185 TCGv temp2 = tcg_temp_new();
1186 if (n == 0) {
1187 tcg_gen_mul_tl(temp, arg2, arg3);
1188 } else { /* n is expected to be 1 */
1189 tcg_gen_mul_tl(temp, arg2, arg3);
1190 tcg_gen_shli_tl(temp, temp, 1);
1191 /* catch special case r1 = r2 = 0x8000 */
1192 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1193 tcg_gen_sub_tl(temp, temp, temp2);
1194 }
1195 gen_adds(ret, arg1, temp);
1196
1197 tcg_temp_free(temp);
1198 tcg_temp_free(temp2);
1199 }
1200
1201 static inline void
1202 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1203 TCGv arg3, uint32_t n)
1204 {
1205 TCGv temp = tcg_temp_new();
1206 TCGv temp2 = tcg_temp_new();
1207 TCGv_i64 t1 = tcg_temp_new_i64();
1208 TCGv_i64 t2 = tcg_temp_new_i64();
1209 TCGv_i64 t3 = tcg_temp_new_i64();
1210
1211 if (n == 0) {
1212 tcg_gen_mul_tl(temp, arg2, arg3);
1213 } else { /* n is expected to be 1 */
1214 tcg_gen_mul_tl(temp, arg2, arg3);
1215 tcg_gen_shli_tl(temp, temp, 1);
1216 /* catch special case r1 = r2 = 0x8000 */
1217 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1218 tcg_gen_sub_tl(temp, temp, temp2);
1219 }
1220 tcg_gen_ext_i32_i64(t2, temp);
1221 tcg_gen_shli_i64(t2, t2, 16);
1222 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1223 gen_add64_d(t3, t1, t2);
1224 /* write back result */
1225 tcg_gen_extr_i64_i32(rl, rh, t3);
1226
1227 tcg_temp_free_i64(t1);
1228 tcg_temp_free_i64(t2);
1229 tcg_temp_free_i64(t3);
1230 tcg_temp_free(temp);
1231 tcg_temp_free(temp2);
1232 }
1233
1234 static inline void
1235 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1236 TCGv arg3, uint32_t n)
1237 {
1238 TCGv temp = tcg_temp_new();
1239 TCGv temp2 = tcg_temp_new();
1240 TCGv_i64 t1 = tcg_temp_new_i64();
1241 TCGv_i64 t2 = tcg_temp_new_i64();
1242
1243 if (n == 0) {
1244 tcg_gen_mul_tl(temp, arg2, arg3);
1245 } else { /* n is expected to be 1 */
1246 tcg_gen_mul_tl(temp, arg2, arg3);
1247 tcg_gen_shli_tl(temp, temp, 1);
1248 /* catch special case r1 = r2 = 0x8000 */
1249 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1250 tcg_gen_sub_tl(temp, temp, temp2);
1251 }
1252 tcg_gen_ext_i32_i64(t2, temp);
1253 tcg_gen_shli_i64(t2, t2, 16);
1254 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1255
1256 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1257 tcg_gen_extr_i64_i32(rl, rh, t1);
1258
1259 tcg_temp_free(temp);
1260 tcg_temp_free(temp2);
1261 tcg_temp_free_i64(t1);
1262 tcg_temp_free_i64(t2);
1263 }
1264
1265 static inline void
1266 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1267 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1268 {
1269 TCGv_i64 t1 = tcg_temp_new_i64();
1270 TCGv_i64 t2 = tcg_temp_new_i64();
1271 TCGv_i64 t3 = tcg_temp_new_i64();
1272 TCGv_i64 t4 = tcg_temp_new_i64();
1273 TCGv temp, temp2;
1274
1275 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1276 tcg_gen_ext_i32_i64(t2, arg2);
1277 tcg_gen_ext_i32_i64(t3, arg3);
1278
1279 tcg_gen_mul_i64(t2, t2, t3);
1280 if (n != 0) {
1281 tcg_gen_shli_i64(t2, t2, 1);
1282 }
1283 tcg_gen_add_i64(t4, t1, t2);
1284 /* calc v bit */
1285 tcg_gen_xor_i64(t3, t4, t1);
1286 tcg_gen_xor_i64(t2, t1, t2);
1287 tcg_gen_andc_i64(t3, t3, t2);
1288 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1289 /* We produce an overflow on the host if the mul before was
1290 (0x80000000 * 0x80000000) << 1). If this is the
1291 case, we negate the ovf. */
1292 if (n == 1) {
1293 temp = tcg_temp_new();
1294 temp2 = tcg_temp_new();
1295 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1296 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1297 tcg_gen_and_tl(temp, temp, temp2);
1298 tcg_gen_shli_tl(temp, temp, 31);
1299 /* negate v bit, if special condition */
1300 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1301
1302 tcg_temp_free(temp);
1303 tcg_temp_free(temp2);
1304 }
1305 /* write back result */
1306 tcg_gen_extr_i64_i32(rl, rh, t4);
1307 /* Calc SV bit */
1308 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1309 /* Calc AV/SAV bits */
1310 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1311 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1312 /* calc SAV */
1313 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1314
1315 tcg_temp_free_i64(t1);
1316 tcg_temp_free_i64(t2);
1317 tcg_temp_free_i64(t3);
1318 tcg_temp_free_i64(t4);
1319 }
1320
1321 static inline void
1322 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1323 uint32_t up_shift)
1324 {
1325 TCGv_i64 t1 = tcg_temp_new_i64();
1326 TCGv_i64 t2 = tcg_temp_new_i64();
1327 TCGv_i64 t3 = tcg_temp_new_i64();
1328
1329 tcg_gen_ext_i32_i64(t1, arg1);
1330 tcg_gen_ext_i32_i64(t2, arg2);
1331 tcg_gen_ext_i32_i64(t3, arg3);
1332
1333 tcg_gen_mul_i64(t2, t2, t3);
1334 tcg_gen_sari_i64(t2, t2, up_shift - n);
1335
1336 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1337
1338 tcg_temp_free_i64(t1);
1339 tcg_temp_free_i64(t2);
1340 tcg_temp_free_i64(t3);
1341 }
1342
1343 static inline void
1344 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1345 TCGv arg3, uint32_t n)
1346 {
1347 TCGv_i64 r1 = tcg_temp_new_i64();
1348 TCGv temp = tcg_const_i32(n);
1349
1350 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1351 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1352 tcg_gen_extr_i64_i32(rl, rh, r1);
1353
1354 tcg_temp_free_i64(r1);
1355 tcg_temp_free(temp);
1356 }
1357 /* ret = r2 - (r1 * r3); */
1358 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1359 {
1360 TCGv_i64 t1 = tcg_temp_new_i64();
1361 TCGv_i64 t2 = tcg_temp_new_i64();
1362 TCGv_i64 t3 = tcg_temp_new_i64();
1363
1364 tcg_gen_ext_i32_i64(t1, r1);
1365 tcg_gen_ext_i32_i64(t2, r2);
1366 tcg_gen_ext_i32_i64(t3, r3);
1367
1368 tcg_gen_mul_i64(t1, t1, t3);
1369 tcg_gen_sub_i64(t1, t2, t1);
1370
1371 tcg_gen_extrl_i64_i32(ret, t1);
1372 /* calc V
1373 t2 > 0x7fffffff */
1374 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1375 /* result < -0x80000000 */
1376 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1377 tcg_gen_or_i64(t2, t2, t3);
1378 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1379 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1380
1381 /* Calc SV bit */
1382 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1383 /* Calc AV/SAV bits */
1384 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1385 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1386 /* calc SAV */
1387 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1388
1389 tcg_temp_free_i64(t1);
1390 tcg_temp_free_i64(t2);
1391 tcg_temp_free_i64(t3);
1392 }
1393
1394 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1395 {
1396 TCGv temp = tcg_const_i32(con);
1397 gen_msub32_d(ret, r1, r2, temp);
1398 tcg_temp_free(temp);
1399 }
1400
1401 static inline void
1402 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1403 TCGv r3)
1404 {
1405 TCGv t1 = tcg_temp_new();
1406 TCGv t2 = tcg_temp_new();
1407 TCGv t3 = tcg_temp_new();
1408 TCGv t4 = tcg_temp_new();
1409
1410 tcg_gen_muls2_tl(t1, t2, r1, r3);
1411 /* only the sub can overflow */
1412 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1413 /* calc V bit */
1414 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1415 tcg_gen_xor_tl(t1, r2_high, t2);
1416 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1417 /* Calc SV bit */
1418 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1419 /* Calc AV/SAV bits */
1420 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1421 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1422 /* calc SAV */
1423 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1424 /* write back the result */
1425 tcg_gen_mov_tl(ret_low, t3);
1426 tcg_gen_mov_tl(ret_high, t4);
1427
1428 tcg_temp_free(t1);
1429 tcg_temp_free(t2);
1430 tcg_temp_free(t3);
1431 tcg_temp_free(t4);
1432 }
1433
1434 static inline void
1435 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1436 int32_t con)
1437 {
1438 TCGv temp = tcg_const_i32(con);
1439 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1440 tcg_temp_free(temp);
1441 }
1442
1443 static inline void
1444 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1445 TCGv r3)
1446 {
1447 TCGv_i64 t1 = tcg_temp_new_i64();
1448 TCGv_i64 t2 = tcg_temp_new_i64();
1449 TCGv_i64 t3 = tcg_temp_new_i64();
1450
1451 tcg_gen_extu_i32_i64(t1, r1);
1452 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1453 tcg_gen_extu_i32_i64(t3, r3);
1454
1455 tcg_gen_mul_i64(t1, t1, t3);
1456 tcg_gen_sub_i64(t3, t2, t1);
1457 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1458 /* calc V bit, only the sub can overflow, if t1 > t2 */
1459 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1460 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1461 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1462 /* Calc SV bit */
1463 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1464 /* Calc AV/SAV bits */
1465 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1466 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1467 /* calc SAV */
1468 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1469
1470 tcg_temp_free_i64(t1);
1471 tcg_temp_free_i64(t2);
1472 tcg_temp_free_i64(t3);
1473 }
1474
1475 static inline void
1476 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1477 int32_t con)
1478 {
1479 TCGv temp = tcg_const_i32(con);
1480 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1481 tcg_temp_free(temp);
1482 }
1483
1484 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1485 {
1486 TCGv temp = tcg_const_i32(r2);
1487 gen_add_d(ret, r1, temp);
1488 tcg_temp_free(temp);
1489 }
1490 /* calculate the carry bit too */
1491 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1492 {
1493 TCGv t0 = tcg_temp_new_i32();
1494 TCGv result = tcg_temp_new_i32();
1495
1496 tcg_gen_movi_tl(t0, 0);
1497 /* Addition and set C/V/SV bits */
1498 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1499 /* calc V bit */
1500 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1501 tcg_gen_xor_tl(t0, r1, r2);
1502 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1503 /* Calc SV bit */
1504 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1505 /* Calc AV/SAV bits */
1506 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1507 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1508 /* calc SAV */
1509 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1510 /* write back result */
1511 tcg_gen_mov_tl(ret, result);
1512
1513 tcg_temp_free(result);
1514 tcg_temp_free(t0);
1515 }
1516
1517 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1518 {
1519 TCGv temp = tcg_const_i32(con);
1520 gen_add_CC(ret, r1, temp);
1521 tcg_temp_free(temp);
1522 }
1523
1524 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1525 {
1526 TCGv carry = tcg_temp_new_i32();
1527 TCGv t0 = tcg_temp_new_i32();
1528 TCGv result = tcg_temp_new_i32();
1529
1530 tcg_gen_movi_tl(t0, 0);
1531 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1532 /* Addition, carry and set C/V/SV bits */
1533 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1534 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1535 /* calc V bit */
1536 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1537 tcg_gen_xor_tl(t0, r1, r2);
1538 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1539 /* Calc SV bit */
1540 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1541 /* Calc AV/SAV bits */
1542 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1543 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1544 /* calc SAV */
1545 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1546 /* write back result */
1547 tcg_gen_mov_tl(ret, result);
1548
1549 tcg_temp_free(result);
1550 tcg_temp_free(t0);
1551 tcg_temp_free(carry);
1552 }
1553
1554 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1555 {
1556 TCGv temp = tcg_const_i32(con);
1557 gen_addc_CC(ret, r1, temp);
1558 tcg_temp_free(temp);
1559 }
1560
1561 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1562 TCGv r4)
1563 {
1564 TCGv temp = tcg_temp_new();
1565 TCGv temp2 = tcg_temp_new();
1566 TCGv result = tcg_temp_new();
1567 TCGv mask = tcg_temp_new();
1568 TCGv t0 = tcg_const_i32(0);
1569
1570 /* create mask for sticky bits */
1571 tcg_gen_setcond_tl(cond, mask, r4, t0);
1572 tcg_gen_shli_tl(mask, mask, 31);
1573
1574 tcg_gen_add_tl(result, r1, r2);
1575 /* Calc PSW_V */
1576 tcg_gen_xor_tl(temp, result, r1);
1577 tcg_gen_xor_tl(temp2, r1, r2);
1578 tcg_gen_andc_tl(temp, temp, temp2);
1579 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1580 /* Set PSW_SV */
1581 tcg_gen_and_tl(temp, temp, mask);
1582 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1583 /* calc AV bit */
1584 tcg_gen_add_tl(temp, result, result);
1585 tcg_gen_xor_tl(temp, temp, result);
1586 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1587 /* calc SAV bit */
1588 tcg_gen_and_tl(temp, temp, mask);
1589 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1590 /* write back result */
1591 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1592
1593 tcg_temp_free(t0);
1594 tcg_temp_free(temp);
1595 tcg_temp_free(temp2);
1596 tcg_temp_free(result);
1597 tcg_temp_free(mask);
1598 }
1599
1600 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1601 TCGv r3, TCGv r4)
1602 {
1603 TCGv temp = tcg_const_i32(r2);
1604 gen_cond_add(cond, r1, temp, r3, r4);
1605 tcg_temp_free(temp);
1606 }
1607
1608 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1609 {
1610 TCGv temp = tcg_temp_new_i32();
1611 TCGv result = tcg_temp_new_i32();
1612
1613 tcg_gen_sub_tl(result, r1, r2);
1614 /* calc V bit */
1615 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1616 tcg_gen_xor_tl(temp, r1, r2);
1617 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1618 /* calc SV bit */
1619 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1620 /* Calc AV bit */
1621 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1622 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1623 /* calc SAV bit */
1624 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1625 /* write back result */
1626 tcg_gen_mov_tl(ret, result);
1627
1628 tcg_temp_free(temp);
1629 tcg_temp_free(result);
1630 }
1631
1632 static inline void
1633 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1634 {
1635 TCGv temp = tcg_temp_new();
1636 TCGv_i64 t0 = tcg_temp_new_i64();
1637 TCGv_i64 t1 = tcg_temp_new_i64();
1638 TCGv_i64 result = tcg_temp_new_i64();
1639
1640 tcg_gen_sub_i64(result, r1, r2);
1641 /* calc v bit */
1642 tcg_gen_xor_i64(t1, result, r1);
1643 tcg_gen_xor_i64(t0, r1, r2);
1644 tcg_gen_and_i64(t1, t1, t0);
1645 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1646 /* calc SV bit */
1647 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1648 /* calc AV/SAV bits */
1649 tcg_gen_extrh_i64_i32(temp, result);
1650 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1651 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1652 /* calc SAV */
1653 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1654 /* write back result */
1655 tcg_gen_mov_i64(ret, result);
1656
1657 tcg_temp_free(temp);
1658 tcg_temp_free_i64(result);
1659 tcg_temp_free_i64(t0);
1660 tcg_temp_free_i64(t1);
1661 }
1662
1663 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1664 {
1665 TCGv result = tcg_temp_new();
1666 TCGv temp = tcg_temp_new();
1667
1668 tcg_gen_sub_tl(result, r1, r2);
1669 /* calc C bit */
1670 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1671 /* calc V bit */
1672 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1673 tcg_gen_xor_tl(temp, r1, r2);
1674 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1675 /* calc SV bit */
1676 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1677 /* Calc AV bit */
1678 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1679 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1680 /* calc SAV bit */
1681 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1682 /* write back result */
1683 tcg_gen_mov_tl(ret, result);
1684
1685 tcg_temp_free(result);
1686 tcg_temp_free(temp);
1687 }
1688
1689 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1690 {
1691 TCGv temp = tcg_temp_new();
1692 tcg_gen_not_tl(temp, r2);
1693 gen_addc_CC(ret, r1, temp);
1694 tcg_temp_free(temp);
1695 }
1696
1697 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1698 TCGv r4)
1699 {
1700 TCGv temp = tcg_temp_new();
1701 TCGv temp2 = tcg_temp_new();
1702 TCGv result = tcg_temp_new();
1703 TCGv mask = tcg_temp_new();
1704 TCGv t0 = tcg_const_i32(0);
1705
1706 /* create mask for sticky bits */
1707 tcg_gen_setcond_tl(cond, mask, r4, t0);
1708 tcg_gen_shli_tl(mask, mask, 31);
1709
1710 tcg_gen_sub_tl(result, r1, r2);
1711 /* Calc PSW_V */
1712 tcg_gen_xor_tl(temp, result, r1);
1713 tcg_gen_xor_tl(temp2, r1, r2);
1714 tcg_gen_and_tl(temp, temp, temp2);
1715 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1716 /* Set PSW_SV */
1717 tcg_gen_and_tl(temp, temp, mask);
1718 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1719 /* calc AV bit */
1720 tcg_gen_add_tl(temp, result, result);
1721 tcg_gen_xor_tl(temp, temp, result);
1722 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1723 /* calc SAV bit */
1724 tcg_gen_and_tl(temp, temp, mask);
1725 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1726 /* write back result */
1727 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1728
1729 tcg_temp_free(t0);
1730 tcg_temp_free(temp);
1731 tcg_temp_free(temp2);
1732 tcg_temp_free(result);
1733 tcg_temp_free(mask);
1734 }
1735
1736 static inline void
1737 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1738 TCGv r3, uint32_t n, uint32_t mode)
1739 {
1740 TCGv temp = tcg_const_i32(n);
1741 TCGv temp2 = tcg_temp_new();
1742 TCGv_i64 temp64 = tcg_temp_new_i64();
1743 switch (mode) {
1744 case MODE_LL:
1745 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1746 break;
1747 case MODE_LU:
1748 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1749 break;
1750 case MODE_UL:
1751 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1752 break;
1753 case MODE_UU:
1754 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1755 break;
1756 }
1757 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1758 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1759 tcg_gen_sub_tl, tcg_gen_sub_tl);
1760 tcg_temp_free(temp);
1761 tcg_temp_free(temp2);
1762 tcg_temp_free_i64(temp64);
1763 }
1764
1765 static inline void
1766 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1767 TCGv r3, uint32_t n, uint32_t mode)
1768 {
1769 TCGv temp = tcg_const_i32(n);
1770 TCGv temp2 = tcg_temp_new();
1771 TCGv temp3 = tcg_temp_new();
1772 TCGv_i64 temp64 = tcg_temp_new_i64();
1773
1774 switch (mode) {
1775 case MODE_LL:
1776 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1777 break;
1778 case MODE_LU:
1779 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1780 break;
1781 case MODE_UL:
1782 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1783 break;
1784 case MODE_UU:
1785 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1786 break;
1787 }
1788 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1789 gen_subs(ret_low, r1_low, temp);
1790 tcg_gen_mov_tl(temp, cpu_PSW_V);
1791 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1792 gen_subs(ret_high, r1_high, temp2);
1793 /* combine v bits */
1794 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1795 /* combine av bits */
1796 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1797
1798 tcg_temp_free(temp);
1799 tcg_temp_free(temp2);
1800 tcg_temp_free(temp3);
1801 tcg_temp_free_i64(temp64);
1802 }
1803
1804 static inline void
1805 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1806 TCGv r3, uint32_t n, uint32_t mode)
1807 {
1808 TCGv temp = tcg_const_i32(n);
1809 TCGv_i64 temp64 = tcg_temp_new_i64();
1810 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1811 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1812 switch (mode) {
1813 case MODE_LL:
1814 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1815 break;
1816 case MODE_LU:
1817 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1818 break;
1819 case MODE_UL:
1820 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1821 break;
1822 case MODE_UU:
1823 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1824 break;
1825 }
1826 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1827 gen_sub64_d(temp64_3, temp64_2, temp64);
1828 /* write back result */
1829 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1830
1831 tcg_temp_free(temp);
1832 tcg_temp_free_i64(temp64);
1833 tcg_temp_free_i64(temp64_2);
1834 tcg_temp_free_i64(temp64_3);
1835 }
1836
1837 static inline void
1838 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1839 TCGv r3, uint32_t n, uint32_t mode)
1840 {
1841 TCGv temp = tcg_const_i32(n);
1842 TCGv_i64 temp64 = tcg_temp_new_i64();
1843 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1844 switch (mode) {
1845 case MODE_LL:
1846 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1847 break;
1848 case MODE_LU:
1849 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1850 break;
1851 case MODE_UL:
1852 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1853 break;
1854 case MODE_UU:
1855 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1856 break;
1857 }
1858 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1859 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1860 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1861
1862 tcg_temp_free(temp);
1863 tcg_temp_free_i64(temp64);
1864 tcg_temp_free_i64(temp64_2);
1865 }
1866
1867 static inline void
1868 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1869 uint32_t mode)
1870 {
1871 TCGv temp = tcg_const_i32(n);
1872 TCGv_i64 temp64 = tcg_temp_new_i64();
1873 switch (mode) {
1874 case MODE_LL:
1875 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1876 break;
1877 case MODE_LU:
1878 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1879 break;
1880 case MODE_UL:
1881 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1882 break;
1883 case MODE_UU:
1884 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1885 break;
1886 }
1887 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1888
1889 tcg_temp_free(temp);
1890 tcg_temp_free_i64(temp64);
1891 }
1892
1893 static inline void
1894 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1895 {
1896 TCGv temp = tcg_temp_new();
1897 TCGv temp2 = tcg_temp_new();
1898
1899 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1900 tcg_gen_shli_tl(temp, r1, 16);
1901 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1902
1903 tcg_temp_free(temp);
1904 tcg_temp_free(temp2);
1905 }
1906
1907 static inline void
1908 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1909 uint32_t n, uint32_t mode)
1910 {
1911 TCGv temp = tcg_const_i32(n);
1912 TCGv_i64 temp64 = tcg_temp_new_i64();
1913 switch (mode) {
1914 case MODE_LL:
1915 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1916 break;
1917 case MODE_LU:
1918 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1919 break;
1920 case MODE_UL:
1921 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1922 break;
1923 case MODE_UU:
1924 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1925 break;
1926 }
1927 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1928
1929 tcg_temp_free(temp);
1930 tcg_temp_free_i64(temp64);
1931 }
1932
1933 static inline void
1934 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1935 {
1936 TCGv temp = tcg_temp_new();
1937 TCGv temp2 = tcg_temp_new();
1938
1939 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1940 tcg_gen_shli_tl(temp, r1, 16);
1941 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1942
1943 tcg_temp_free(temp);
1944 tcg_temp_free(temp2);
1945 }
1946
1947 static inline void
1948 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1949 {
1950 TCGv temp = tcg_const_i32(n);
1951 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1952 tcg_temp_free(temp);
1953 }
1954
1955 static inline void
1956 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1957 {
1958 TCGv temp = tcg_const_i32(n);
1959 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1960 tcg_temp_free(temp);
1961 }
1962
1963 static inline void
1964 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1965 uint32_t up_shift, CPUTriCoreState *env)
1966 {
1967 TCGv temp = tcg_temp_new();
1968 TCGv temp2 = tcg_temp_new();
1969 TCGv temp3 = tcg_temp_new();
1970 TCGv_i64 t1 = tcg_temp_new_i64();
1971 TCGv_i64 t2 = tcg_temp_new_i64();
1972 TCGv_i64 t3 = tcg_temp_new_i64();
1973 TCGv_i64 t4 = tcg_temp_new_i64();
1974
1975 tcg_gen_ext_i32_i64(t2, arg2);
1976 tcg_gen_ext_i32_i64(t3, arg3);
1977
1978 tcg_gen_mul_i64(t2, t2, t3);
1979
1980 tcg_gen_ext_i32_i64(t1, arg1);
1981 /* if we shift part of the fraction out, we need to round up */
1982 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1983 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1984 tcg_gen_sari_i64(t2, t2, up_shift - n);
1985 tcg_gen_add_i64(t2, t2, t4);
1986
1987 tcg_gen_sub_i64(t3, t1, t2);
1988 tcg_gen_extrl_i64_i32(temp3, t3);
1989 /* calc v bit */
1990 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1991 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1992 tcg_gen_or_i64(t1, t1, t2);
1993 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1994 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1995 /* Calc SV bit */
1996 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1997 /* Calc AV/SAV bits */
1998 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1999 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
2000 /* calc SAV */
2001 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2002 /* write back result */
2003 tcg_gen_mov_tl(ret, temp3);
2004
2005 tcg_temp_free(temp);
2006 tcg_temp_free(temp2);
2007 tcg_temp_free(temp3);
2008 tcg_temp_free_i64(t1);
2009 tcg_temp_free_i64(t2);
2010 tcg_temp_free_i64(t3);
2011 tcg_temp_free_i64(t4);
2012 }
2013
2014 static inline void
2015 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2016 {
2017 TCGv temp = tcg_temp_new();
2018 TCGv temp2 = tcg_temp_new();
2019 if (n == 0) {
2020 tcg_gen_mul_tl(temp, arg2, arg3);
2021 } else { /* n is expected to be 1 */
2022 tcg_gen_mul_tl(temp, arg2, arg3);
2023 tcg_gen_shli_tl(temp, temp, 1);
2024 /* catch special case r1 = r2 = 0x8000 */
2025 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2026 tcg_gen_sub_tl(temp, temp, temp2);
2027 }
2028 gen_sub_d(ret, arg1, temp);
2029
2030 tcg_temp_free(temp);
2031 tcg_temp_free(temp2);
2032 }
2033
2034 static inline void
2035 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2036 {
2037 TCGv temp = tcg_temp_new();
2038 TCGv temp2 = tcg_temp_new();
2039 if (n == 0) {
2040 tcg_gen_mul_tl(temp, arg2, arg3);
2041 } else { /* n is expected to be 1 */
2042 tcg_gen_mul_tl(temp, arg2, arg3);
2043 tcg_gen_shli_tl(temp, temp, 1);
2044 /* catch special case r1 = r2 = 0x8000 */
2045 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2046 tcg_gen_sub_tl(temp, temp, temp2);
2047 }
2048 gen_subs(ret, arg1, temp);
2049
2050 tcg_temp_free(temp);
2051 tcg_temp_free(temp2);
2052 }
2053
2054 static inline void
2055 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2056 TCGv arg3, uint32_t n)
2057 {
2058 TCGv temp = tcg_temp_new();
2059 TCGv temp2 = tcg_temp_new();
2060 TCGv_i64 t1 = tcg_temp_new_i64();
2061 TCGv_i64 t2 = tcg_temp_new_i64();
2062 TCGv_i64 t3 = tcg_temp_new_i64();
2063
2064 if (n == 0) {
2065 tcg_gen_mul_tl(temp, arg2, arg3);
2066 } else { /* n is expected to be 1 */
2067 tcg_gen_mul_tl(temp, arg2, arg3);
2068 tcg_gen_shli_tl(temp, temp, 1);
2069 /* catch special case r1 = r2 = 0x8000 */
2070 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2071 tcg_gen_sub_tl(temp, temp, temp2);
2072 }
2073 tcg_gen_ext_i32_i64(t2, temp);
2074 tcg_gen_shli_i64(t2, t2, 16);
2075 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2076 gen_sub64_d(t3, t1, t2);
2077 /* write back result */
2078 tcg_gen_extr_i64_i32(rl, rh, t3);
2079
2080 tcg_temp_free_i64(t1);
2081 tcg_temp_free_i64(t2);
2082 tcg_temp_free_i64(t3);
2083 tcg_temp_free(temp);
2084 tcg_temp_free(temp2);
2085 }
2086
2087 static inline void
2088 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2089 TCGv arg3, uint32_t n)
2090 {
2091 TCGv temp = tcg_temp_new();
2092 TCGv temp2 = tcg_temp_new();
2093 TCGv_i64 t1 = tcg_temp_new_i64();
2094 TCGv_i64 t2 = tcg_temp_new_i64();
2095
2096 if (n == 0) {
2097 tcg_gen_mul_tl(temp, arg2, arg3);
2098 } else { /* n is expected to be 1 */
2099 tcg_gen_mul_tl(temp, arg2, arg3);
2100 tcg_gen_shli_tl(temp, temp, 1);
2101 /* catch special case r1 = r2 = 0x8000 */
2102 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2103 tcg_gen_sub_tl(temp, temp, temp2);
2104 }
2105 tcg_gen_ext_i32_i64(t2, temp);
2106 tcg_gen_shli_i64(t2, t2, 16);
2107 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2108
2109 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
2110 tcg_gen_extr_i64_i32(rl, rh, t1);
2111
2112 tcg_temp_free(temp);
2113 tcg_temp_free(temp2);
2114 tcg_temp_free_i64(t1);
2115 tcg_temp_free_i64(t2);
2116 }
2117
2118 static inline void
2119 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2120 TCGv arg3, uint32_t n, CPUTriCoreState *env)
2121 {
2122 TCGv_i64 t1 = tcg_temp_new_i64();
2123 TCGv_i64 t2 = tcg_temp_new_i64();
2124 TCGv_i64 t3 = tcg_temp_new_i64();
2125 TCGv_i64 t4 = tcg_temp_new_i64();
2126 TCGv temp, temp2;
2127
2128 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2129 tcg_gen_ext_i32_i64(t2, arg2);
2130 tcg_gen_ext_i32_i64(t3, arg3);
2131
2132 tcg_gen_mul_i64(t2, t2, t3);
2133 if (n != 0) {
2134 tcg_gen_shli_i64(t2, t2, 1);
2135 }
2136 tcg_gen_sub_i64(t4, t1, t2);
2137 /* calc v bit */
2138 tcg_gen_xor_i64(t3, t4, t1);
2139 tcg_gen_xor_i64(t2, t1, t2);
2140 tcg_gen_and_i64(t3, t3, t2);
2141 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
2142 /* We produce an overflow on the host if the mul before was
2143 (0x80000000 * 0x80000000) << 1). If this is the
2144 case, we negate the ovf. */
2145 if (n == 1) {
2146 temp = tcg_temp_new();
2147 temp2 = tcg_temp_new();
2148 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
2149 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
2150 tcg_gen_and_tl(temp, temp, temp2);
2151 tcg_gen_shli_tl(temp, temp, 31);
2152 /* negate v bit, if special condition */
2153 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
2154
2155 tcg_temp_free(temp);
2156 tcg_temp_free(temp2);
2157 }
2158 /* write back result */
2159 tcg_gen_extr_i64_i32(rl, rh, t4);
2160 /* Calc SV bit */
2161 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2162 /* Calc AV/SAV bits */
2163 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2164 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2165 /* calc SAV */
2166 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2167
2168 tcg_temp_free_i64(t1);
2169 tcg_temp_free_i64(t2);
2170 tcg_temp_free_i64(t3);
2171 tcg_temp_free_i64(t4);
2172 }
2173
2174 static inline void
2175 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
2176 uint32_t up_shift)
2177 {
2178 TCGv_i64 t1 = tcg_temp_new_i64();
2179 TCGv_i64 t2 = tcg_temp_new_i64();
2180 TCGv_i64 t3 = tcg_temp_new_i64();
2181 TCGv_i64 t4 = tcg_temp_new_i64();
2182
2183 tcg_gen_ext_i32_i64(t1, arg1);
2184 tcg_gen_ext_i32_i64(t2, arg2);
2185 tcg_gen_ext_i32_i64(t3, arg3);
2186
2187 tcg_gen_mul_i64(t2, t2, t3);
2188 /* if we shift part of the fraction out, we need to round up */
2189 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
2190 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
2191 tcg_gen_sari_i64(t3, t2, up_shift - n);
2192 tcg_gen_add_i64(t3, t3, t4);
2193
2194 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
2195
2196 tcg_temp_free_i64(t1);
2197 tcg_temp_free_i64(t2);
2198 tcg_temp_free_i64(t3);
2199 tcg_temp_free_i64(t4);
2200 }
2201
2202 static inline void
2203 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2204 TCGv arg3, uint32_t n)
2205 {
2206 TCGv_i64 r1 = tcg_temp_new_i64();
2207 TCGv temp = tcg_const_i32(n);
2208
2209 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
2210 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
2211 tcg_gen_extr_i64_i32(rl, rh, r1);
2212
2213 tcg_temp_free_i64(r1);
2214 tcg_temp_free(temp);
2215 }
2216
2217 static inline void
2218 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2219 TCGv r3, uint32_t n, uint32_t mode)
2220 {
2221 TCGv temp = tcg_const_i32(n);
2222 TCGv temp2 = tcg_temp_new();
2223 TCGv_i64 temp64 = tcg_temp_new_i64();
2224 switch (mode) {
2225 case MODE_LL:
2226 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2227 break;
2228 case MODE_LU:
2229 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2230 break;
2231 case MODE_UL:
2232 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2233 break;
2234 case MODE_UU:
2235 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2236 break;
2237 }
2238 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2239 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
2240 tcg_gen_add_tl, tcg_gen_sub_tl);
2241 tcg_temp_free(temp);
2242 tcg_temp_free(temp2);
2243 tcg_temp_free_i64(temp64);
2244 }
2245
2246 static inline void
2247 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2248 TCGv r3, uint32_t n, uint32_t mode)
2249 {
2250 TCGv temp = tcg_const_i32(n);
2251 TCGv_i64 temp64 = tcg_temp_new_i64();
2252 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2253 TCGv_i64 temp64_3 = tcg_temp_new_i64();
2254 switch (mode) {
2255 case MODE_LL:
2256 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2257 break;
2258 case MODE_LU:
2259 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2260 break;
2261 case MODE_UL:
2262 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2263 break;
2264 case MODE_UU:
2265 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2266 break;
2267 }
2268 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
2269 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2270 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2271 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2272 tcg_gen_shli_i64(temp64, temp64, 16);
2273
2274 gen_sub64_d(temp64_2, temp64_3, temp64);
2275 /* write back result */
2276 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
2277
2278 tcg_temp_free(temp);
2279 tcg_temp_free_i64(temp64);
2280 tcg_temp_free_i64(temp64_2);
2281 tcg_temp_free_i64(temp64_3);
2282 }
2283
2284 static inline void
2285 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2286 {
2287 TCGv temp = tcg_const_i32(n);
2288 TCGv temp2 = tcg_temp_new();
2289 TCGv_i64 temp64 = tcg_temp_new_i64();
2290 switch (mode) {
2291 case MODE_LL:
2292 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2293 break;
2294 case MODE_LU:
2295 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2296 break;
2297 case MODE_UL:
2298 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2299 break;
2300 case MODE_UU:
2301 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2302 break;
2303 }
2304 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2305 tcg_gen_shli_tl(temp, r1, 16);
2306 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2307
2308 tcg_temp_free(temp);
2309 tcg_temp_free(temp2);
2310 tcg_temp_free_i64(temp64);
2311 }
2312
2313 static inline void
2314 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2315 TCGv r3, uint32_t n, uint32_t mode)
2316 {
2317 TCGv temp = tcg_const_i32(n);
2318 TCGv temp2 = tcg_temp_new();
2319 TCGv temp3 = tcg_temp_new();
2320 TCGv_i64 temp64 = tcg_temp_new_i64();
2321
2322 switch (mode) {
2323 case MODE_LL:
2324 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2325 break;
2326 case MODE_LU:
2327 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2328 break;
2329 case MODE_UL:
2330 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2331 break;
2332 case MODE_UU:
2333 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2334 break;
2335 }
2336 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2337 gen_adds(ret_low, r1_low, temp);
2338 tcg_gen_mov_tl(temp, cpu_PSW_V);
2339 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2340 gen_subs(ret_high, r1_high, temp2);
2341 /* combine v bits */
2342 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2343 /* combine av bits */
2344 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2345
2346 tcg_temp_free(temp);
2347 tcg_temp_free(temp2);
2348 tcg_temp_free(temp3);
2349 tcg_temp_free_i64(temp64);
2350 }
2351
2352 static inline void
2353 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2354 TCGv r3, uint32_t n, uint32_t mode)
2355 {
2356 TCGv temp = tcg_const_i32(n);
2357 TCGv_i64 temp64 = tcg_temp_new_i64();
2358 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2359
2360 switch (mode) {
2361 case MODE_LL:
2362 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2363 break;
2364 case MODE_LU:
2365 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2366 break;
2367 case MODE_UL:
2368 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2369 break;
2370 case MODE_UU:
2371 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2372 break;
2373 }
2374 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2375 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2376 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2377 tcg_gen_shli_i64(temp64, temp64, 16);
2378 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2379
2380 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2381 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2382
2383 tcg_temp_free(temp);
2384 tcg_temp_free_i64(temp64);
2385 tcg_temp_free_i64(temp64_2);
2386 }
2387
2388 static inline void
2389 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2390 {
2391 TCGv temp = tcg_const_i32(n);
2392 TCGv temp2 = tcg_temp_new();
2393 TCGv_i64 temp64 = tcg_temp_new_i64();
2394 switch (mode) {
2395 case MODE_LL:
2396 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2397 break;
2398 case MODE_LU:
2399 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2400 break;
2401 case MODE_UL:
2402 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2403 break;
2404 case MODE_UU:
2405 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2406 break;
2407 }
2408 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2409 tcg_gen_shli_tl(temp, r1, 16);
2410 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2411
2412 tcg_temp_free(temp);
2413 tcg_temp_free(temp2);
2414 tcg_temp_free_i64(temp64);
2415 }
2416
2417 static inline void gen_abs(TCGv ret, TCGv r1)
2418 {
2419 TCGv temp = tcg_temp_new();
2420 TCGv t0 = tcg_const_i32(0);
2421
2422 tcg_gen_neg_tl(temp, r1);
2423 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
2424 /* overflow can only happen, if r1 = 0x80000000 */
2425 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2426 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2427 /* calc SV bit */
2428 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2429 /* Calc AV bit */
2430 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2431 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2432 /* calc SAV bit */
2433 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2434
2435 tcg_temp_free(temp);
2436 tcg_temp_free(t0);
2437 }
2438
2439 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2440 {
2441 TCGv temp = tcg_temp_new_i32();
2442 TCGv result = tcg_temp_new_i32();
2443
2444 tcg_gen_sub_tl(result, r1, r2);
2445 tcg_gen_sub_tl(temp, r2, r1);
2446 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2447
2448 /* calc V bit */
2449 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2450 tcg_gen_xor_tl(temp, result, r2);
2451 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2452 tcg_gen_xor_tl(temp, r1, r2);
2453 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2454 /* calc SV bit */
2455 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2456 /* Calc AV bit */
2457 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2458 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2459 /* calc SAV bit */
2460 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2461 /* write back result */
2462 tcg_gen_mov_tl(ret, result);
2463
2464 tcg_temp_free(temp);
2465 tcg_temp_free(result);
2466 }
2467
2468 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2469 {
2470 TCGv temp = tcg_const_i32(con);
2471 gen_absdif(ret, r1, temp);
2472 tcg_temp_free(temp);
2473 }
2474
2475 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2476 {
2477 TCGv temp = tcg_const_i32(con);
2478 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2479 tcg_temp_free(temp);
2480 }
2481
2482 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2483 {
2484 TCGv high = tcg_temp_new();
2485 TCGv low = tcg_temp_new();
2486
2487 tcg_gen_muls2_tl(low, high, r1, r2);
2488 tcg_gen_mov_tl(ret, low);
2489 /* calc V bit */
2490 tcg_gen_sari_tl(low, low, 31);
2491 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2492 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2493 /* calc SV bit */
2494 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2495 /* Calc AV bit */
2496 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2497 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2498 /* calc SAV bit */
2499 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2500
2501 tcg_temp_free(high);
2502 tcg_temp_free(low);
2503 }
2504
2505 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2506 {
2507 TCGv temp = tcg_const_i32(con);
2508 gen_mul_i32s(ret, r1, temp);
2509 tcg_temp_free(temp);
2510 }
2511
2512 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2513 {
2514 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2515 /* clear V bit */
2516 tcg_gen_movi_tl(cpu_PSW_V, 0);
2517 /* calc SV bit */
2518 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2519 /* Calc AV bit */
2520 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2521 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2522 /* calc SAV bit */
2523 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2524 }
2525
2526 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2527 int32_t con)
2528 {
2529 TCGv temp = tcg_const_i32(con);
2530 gen_mul_i64s(ret_low, ret_high, r1, temp);
2531 tcg_temp_free(temp);
2532 }
2533
2534 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2535 {
2536 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2537 /* clear V bit */
2538 tcg_gen_movi_tl(cpu_PSW_V, 0);
2539 /* calc SV bit */
2540 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2541 /* Calc AV bit */
2542 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2543 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2544 /* calc SAV bit */
2545 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2546 }
2547
2548 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2549 int32_t con)
2550 {
2551 TCGv temp = tcg_const_i32(con);
2552 gen_mul_i64u(ret_low, ret_high, r1, temp);
2553 tcg_temp_free(temp);
2554 }
2555
2556 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2557 {
2558 TCGv temp = tcg_const_i32(con);
2559 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2560 tcg_temp_free(temp);
2561 }
2562
2563 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2564 {
2565 TCGv temp = tcg_const_i32(con);
2566 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2567 tcg_temp_free(temp);
2568 }
2569 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2570 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2571 {
2572 TCGv temp = tcg_const_i32(con);
2573 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2574 tcg_temp_free(temp);
2575 }
2576
2577 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2578 {
2579 TCGv temp = tcg_const_i32(con);
2580 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2581 tcg_temp_free(temp);
2582 }
2583
2584 static void
2585 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2586 {
2587 TCGv temp = tcg_temp_new();
2588 TCGv_i64 temp_64 = tcg_temp_new_i64();
2589 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2590
2591 if (n == 0) {
2592 if (up_shift == 32) {
2593 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2594 } else if (up_shift == 16) {
2595 tcg_gen_ext_i32_i64(temp_64, arg1);
2596 tcg_gen_ext_i32_i64(temp2_64, arg2);
2597
2598 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2599 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2600 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2601 } else {
2602 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2603 }
2604 /* reset v bit */
2605 tcg_gen_movi_tl(cpu_PSW_V, 0);
2606 } else { /* n is expected to be 1 */
2607 tcg_gen_ext_i32_i64(temp_64, arg1);
2608 tcg_gen_ext_i32_i64(temp2_64, arg2);
2609
2610 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2611
2612 if (up_shift == 0) {
2613 tcg_gen_shli_i64(temp_64, temp_64, 1);
2614 } else {
2615 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2616 }
2617 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2618 /* overflow only occurs if r1 = r2 = 0x8000 */
2619 if (up_shift == 0) {/* result is 64 bit */
2620 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2621 0x80000000);
2622 } else { /* result is 32 bit */
2623 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2624 0x80000000);
2625 }
2626 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2627 /* calc sv overflow bit */
2628 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2629 }
2630 /* calc av overflow bit */
2631 if (up_shift == 0) {
2632 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2633 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2634 } else {
2635 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2636 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2637 }
2638 /* calc sav overflow bit */
2639 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2640 tcg_temp_free(temp);
2641 tcg_temp_free_i64(temp_64);
2642 tcg_temp_free_i64(temp2_64);
2643 }
2644
2645 static void
2646 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2647 {
2648 TCGv temp = tcg_temp_new();
2649 if (n == 0) {
2650 tcg_gen_mul_tl(ret, arg1, arg2);
2651 } else { /* n is expected to be 1 */
2652 tcg_gen_mul_tl(ret, arg1, arg2);
2653 tcg_gen_shli_tl(ret, ret, 1);
2654 /* catch special case r1 = r2 = 0x8000 */
2655 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2656 tcg_gen_sub_tl(ret, ret, temp);
2657 }
2658 /* reset v bit */
2659 tcg_gen_movi_tl(cpu_PSW_V, 0);
2660 /* calc av overflow bit */
2661 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2662 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2663 /* calc sav overflow bit */
2664 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2665
2666 tcg_temp_free(temp);
2667 }
2668
2669 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2670 {
2671 TCGv temp = tcg_temp_new();
2672 if (n == 0) {
2673 tcg_gen_mul_tl(ret, arg1, arg2);
2674 tcg_gen_addi_tl(ret, ret, 0x8000);
2675 } else {
2676 tcg_gen_mul_tl(ret, arg1, arg2);
2677 tcg_gen_shli_tl(ret, ret, 1);
2678 tcg_gen_addi_tl(ret, ret, 0x8000);
2679 /* catch special case r1 = r2 = 0x8000 */
2680 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2681 tcg_gen_muli_tl(temp, temp, 0x8001);
2682 tcg_gen_sub_tl(ret, ret, temp);
2683 }
2684 /* reset v bit */
2685 tcg_gen_movi_tl(cpu_PSW_V, 0);
2686 /* calc av overflow bit */
2687 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2688 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2689 /* calc sav overflow bit */
2690 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2691 /* cut halfword off */
2692 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2693
2694 tcg_temp_free(temp);
2695 }
2696
2697 static inline void
2698 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2699 TCGv r3)
2700 {
2701 TCGv_i64 temp64 = tcg_temp_new_i64();
2702 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2703 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2704 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2705 tcg_temp_free_i64(temp64);
2706 }
2707
2708 static inline void
2709 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2710 int32_t con)
2711 {
2712 TCGv temp = tcg_const_i32(con);
2713 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2714 tcg_temp_free(temp);
2715 }
2716
2717 static inline void
2718 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2719 TCGv r3)
2720 {
2721 TCGv_i64 temp64 = tcg_temp_new_i64();
2722 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2723 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2724 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2725 tcg_temp_free_i64(temp64);
2726 }
2727
2728 static inline void
2729 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2730 int32_t con)
2731 {
2732 TCGv temp = tcg_const_i32(con);
2733 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2734 tcg_temp_free(temp);
2735 }
2736
2737 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2738 {
2739 TCGv temp = tcg_const_i32(con);
2740 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2741 tcg_temp_free(temp);
2742 }
2743
2744 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2745 {
2746 TCGv temp = tcg_const_i32(con);
2747 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2748 tcg_temp_free(temp);
2749 }
2750
2751 static inline void
2752 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2753 TCGv r3)
2754 {
2755 TCGv_i64 temp64 = tcg_temp_new_i64();
2756 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2757 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2758 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2759 tcg_temp_free_i64(temp64);
2760 }
2761
2762 static inline void
2763 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2764 int32_t con)
2765 {
2766 TCGv temp = tcg_const_i32(con);
2767 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2768 tcg_temp_free(temp);
2769 }
2770
2771 static inline void
2772 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2773 TCGv r3)
2774 {
2775 TCGv_i64 temp64 = tcg_temp_new_i64();
2776 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2777 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2778 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2779 tcg_temp_free_i64(temp64);
2780 }
2781
2782 static inline void
2783 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2784 int32_t con)
2785 {
2786 TCGv temp = tcg_const_i32(con);
2787 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2788 tcg_temp_free(temp);
2789 }
2790
2791 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2792 {
2793 TCGv sat_neg = tcg_const_i32(low);
2794 TCGv temp = tcg_const_i32(up);
2795
2796 /* sat_neg = (arg < low ) ? low : arg; */
2797 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2798
2799 /* ret = (sat_neg > up ) ? up : sat_neg; */
2800 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2801
2802 tcg_temp_free(sat_neg);
2803 tcg_temp_free(temp);
2804 }
2805
2806 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2807 {
2808 TCGv temp = tcg_const_i32(up);
2809 /* sat_neg = (arg > up ) ? up : arg; */
2810 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2811 tcg_temp_free(temp);
2812 }
2813
2814 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2815 {
2816 if (shift_count == -32) {
2817 tcg_gen_movi_tl(ret, 0);
2818 } else if (shift_count >= 0) {
2819 tcg_gen_shli_tl(ret, r1, shift_count);
2820 } else {
2821 tcg_gen_shri_tl(ret, r1, -shift_count);
2822 }
2823 }
2824
2825 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2826 {
2827 TCGv temp_low, temp_high;
2828
2829 if (shiftcount == -16) {
2830 tcg_gen_movi_tl(ret, 0);
2831 } else {
2832 temp_high = tcg_temp_new();
2833 temp_low = tcg_temp_new();
2834
2835 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2836 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2837 gen_shi(temp_low, temp_low, shiftcount);
2838 gen_shi(ret, temp_high, shiftcount);
2839 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2840
2841 tcg_temp_free(temp_low);
2842 tcg_temp_free(temp_high);
2843 }
2844 }
2845
2846 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2847 {
2848 uint32_t msk, msk_start;
2849 TCGv temp = tcg_temp_new();
2850 TCGv temp2 = tcg_temp_new();
2851 TCGv t_0 = tcg_const_i32(0);
2852
2853 if (shift_count == 0) {
2854 /* Clear PSW.C and PSW.V */
2855 tcg_gen_movi_tl(cpu_PSW_C, 0);
2856 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2857 tcg_gen_mov_tl(ret, r1);
2858 } else if (shift_count == -32) {
2859 /* set PSW.C */
2860 tcg_gen_mov_tl(cpu_PSW_C, r1);
2861 /* fill ret completly with sign bit */
2862 tcg_gen_sari_tl(ret, r1, 31);
2863 /* clear PSW.V */
2864 tcg_gen_movi_tl(cpu_PSW_V, 0);
2865 } else if (shift_count > 0) {
2866 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2867 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2868
2869 /* calc carry */
2870 msk_start = 32 - shift_count;
2871 msk = ((1 << shift_count) - 1) << msk_start;
2872 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2873 /* calc v/sv bits */
2874 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2875 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2876 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2877 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2878 /* calc sv */
2879 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2880 /* do shift */
2881 tcg_gen_shli_tl(ret, r1, shift_count);
2882
2883 tcg_temp_free(t_max);
2884 tcg_temp_free(t_min);
2885 } else {
2886 /* clear PSW.V */
2887 tcg_gen_movi_tl(cpu_PSW_V, 0);
2888 /* calc carry */
2889 msk = (1 << -shift_count) - 1;
2890 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2891 /* do shift */
2892 tcg_gen_sari_tl(ret, r1, -shift_count);
2893 }
2894 /* calc av overflow bit */
2895 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2896 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2897 /* calc sav overflow bit */
2898 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2899
2900 tcg_temp_free(temp);
2901 tcg_temp_free(temp2);
2902 tcg_temp_free(t_0);
2903 }
2904
2905 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2906 {
2907 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2908 }
2909
2910 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2911 {
2912 TCGv temp = tcg_const_i32(con);
2913 gen_shas(ret, r1, temp);
2914 tcg_temp_free(temp);
2915 }
2916
2917 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2918 {
2919 TCGv low, high;
2920
2921 if (shift_count == 0) {
2922 tcg_gen_mov_tl(ret, r1);
2923 } else if (shift_count > 0) {
2924 low = tcg_temp_new();
2925 high = tcg_temp_new();
2926
2927 tcg_gen_andi_tl(high, r1, 0xffff0000);
2928 tcg_gen_shli_tl(low, r1, shift_count);
2929 tcg_gen_shli_tl(ret, high, shift_count);
2930 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2931
2932 tcg_temp_free(low);
2933 tcg_temp_free(high);
2934 } else {
2935 low = tcg_temp_new();
2936 high = tcg_temp_new();
2937
2938 tcg_gen_ext16s_tl(low, r1);
2939 tcg_gen_sari_tl(low, low, -shift_count);
2940 tcg_gen_sari_tl(ret, r1, -shift_count);
2941 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2942
2943 tcg_temp_free(low);
2944 tcg_temp_free(high);
2945 }
2946
2947 }
2948
2949 /* ret = {ret[30:0], (r1 cond r2)}; */
2950 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2951 {
2952 TCGv temp = tcg_temp_new();
2953 TCGv temp2 = tcg_temp_new();
2954
2955 tcg_gen_shli_tl(temp, ret, 1);
2956 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2957 tcg_gen_or_tl(ret, temp, temp2);
2958
2959 tcg_temp_free(temp);
2960 tcg_temp_free(temp2);
2961 }
2962
2963 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2964 {
2965 TCGv temp = tcg_const_i32(con);
2966 gen_sh_cond(cond, ret, r1, temp);
2967 tcg_temp_free(temp);
2968 }
2969
2970 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2971 {
2972 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2973 }
2974
2975 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2976 {
2977 TCGv temp = tcg_const_i32(con);
2978 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2979 tcg_temp_free(temp);
2980 }
2981
2982 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2983 {
2984 TCGv temp = tcg_const_i32(con);
2985 gen_helper_add_suov(ret, cpu_env, r1, temp);
2986 tcg_temp_free(temp);
2987 }
2988
2989 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2990 {
2991 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2992 }
2993
2994 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2995 {
2996 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2997 }
2998
2999 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
3000 int pos1, int pos2,
3001 void(*op1)(TCGv, TCGv, TCGv),
3002 void(*op2)(TCGv, TCGv, TCGv))
3003 {
3004 TCGv temp1, temp2;
3005
3006 temp1 = tcg_temp_new();
3007 temp2 = tcg_temp_new();
3008
3009 tcg_gen_shri_tl(temp2, r2, pos2);
3010 tcg_gen_shri_tl(temp1, r1, pos1);
3011
3012 (*op1)(temp1, temp1, temp2);
3013 (*op2)(temp1 , ret, temp1);
3014
3015 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
3016
3017 tcg_temp_free(temp1);
3018 tcg_temp_free(temp2);
3019 }
3020
3021 /* ret = r1[pos1] op1 r2[pos2]; */
3022 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
3023 int pos1, int pos2,
3024 void(*op1)(TCGv, TCGv, TCGv))
3025 {
3026 TCGv temp1, temp2;
3027
3028 temp1 = tcg_temp_new();
3029 temp2 = tcg_temp_new();
3030
3031 tcg_gen_shri_tl(temp2, r2, pos2);
3032 tcg_gen_shri_tl(temp1, r1, pos1);
3033
3034 (*op1)(ret, temp1, temp2);
3035
3036 tcg_gen_andi_tl(ret, ret, 0x1);
3037
3038 tcg_temp_free(temp1);
3039 tcg_temp_free(temp2);
3040 }
3041
3042 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
3043 void(*op)(TCGv, TCGv, TCGv))
3044 {
3045 TCGv temp = tcg_temp_new();
3046 TCGv temp2 = tcg_temp_new();
3047 /* temp = (arg1 cond arg2 )*/
3048 tcg_gen_setcond_tl(cond, temp, r1, r2);
3049 /* temp2 = ret[0]*/
3050 tcg_gen_andi_tl(temp2, ret, 0x1);
3051 /* temp = temp insn temp2 */
3052 (*op)(temp, temp, temp2);
3053 /* ret = {ret[31:1], temp} */
3054 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
3055
3056 tcg_temp_free(temp);
3057 tcg_temp_free(temp2);
3058 }
3059
3060 static inline void
3061 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
3062 void(*op)(TCGv, TCGv, TCGv))
3063 {
3064 TCGv temp = tcg_const_i32(con);
3065 gen_accumulating_cond(cond, ret, r1, temp, op);
3066 tcg_temp_free(temp);
3067 }
3068
3069 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3070 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
3071 {
3072 tcg_gen_setcond_tl(cond, ret, r1, r2);
3073 tcg_gen_neg_tl(ret, ret);
3074 }
3075
3076 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
3077 {
3078 TCGv b0 = tcg_temp_new();
3079 TCGv b1 = tcg_temp_new();
3080 TCGv b2 = tcg_temp_new();
3081 TCGv b3 = tcg_temp_new();
3082
3083 /* byte 0 */
3084 tcg_gen_andi_tl(b0, r1, 0xff);
3085 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
3086
3087 /* byte 1 */
3088 tcg_gen_andi_tl(b1, r1, 0xff00);
3089 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
3090
3091 /* byte 2 */
3092 tcg_gen_andi_tl(b2, r1, 0xff0000);
3093 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
3094
3095 /* byte 3 */
3096 tcg_gen_andi_tl(b3, r1, 0xff000000);
3097 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
3098
3099 /* combine them */
3100 tcg_gen_or_tl(ret, b0, b1);
3101 tcg_gen_or_tl(ret, ret, b2);
3102 tcg_gen_or_tl(ret, ret, b3);
3103
3104 tcg_temp_free(b0);
3105 tcg_temp_free(b1);
3106 tcg_temp_free(b2);
3107 tcg_temp_free(b3);
3108 }
3109
3110 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
3111 {
3112 TCGv h0 = tcg_temp_new();
3113 TCGv h1 = tcg_temp_new();
3114
3115 /* halfword 0 */
3116 tcg_gen_andi_tl(h0, r1, 0xffff);
3117 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
3118
3119 /* halfword 1 */
3120 tcg_gen_andi_tl(h1, r1, 0xffff0000);
3121 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
3122
3123 /* combine them */
3124 tcg_gen_or_tl(ret, h0, h1);
3125
3126 tcg_temp_free(h0);
3127 tcg_temp_free(h1);
3128 }
3129 /* mask = ((1 << width) -1) << pos;
3130 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3131 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
3132 {
3133 TCGv mask = tcg_temp_new();
3134 TCGv temp = tcg_temp_new();
3135 TCGv temp2 = tcg_temp_new();
3136
3137 tcg_gen_movi_tl(mask, 1);
3138 tcg_gen_shl_tl(mask, mask, width);
3139 tcg_gen_subi_tl(mask, mask, 1);
3140 tcg_gen_shl_tl(mask, mask, pos);
3141
3142 tcg_gen_shl_tl(temp, r2, pos);
3143 tcg_gen_and_tl(temp, temp, mask);
3144 tcg_gen_andc_tl(temp2, r1, mask);
3145 tcg_gen_or_tl(ret, temp, temp2);
3146
3147 tcg_temp_free(mask);
3148 tcg_temp_free(temp);
3149 tcg_temp_free(temp2);
3150 }
3151
3152 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
3153 {
3154 TCGv_i64 temp = tcg_temp_new_i64();
3155
3156 gen_helper_bsplit(temp, r1);
3157 tcg_gen_extr_i64_i32(rl, rh, temp);
3158
3159 tcg_temp_free_i64(temp);
3160 }
3161
3162 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
3163 {
3164 TCGv_i64 temp = tcg_temp_new_i64();
3165
3166 gen_helper_unpack(temp, r1);
3167 tcg_gen_extr_i64_i32(rl, rh, temp);
3168
3169 tcg_temp_free_i64(temp);
3170 }
3171
3172 static inline void
3173 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3174 {
3175 TCGv_i64 ret = tcg_temp_new_i64();
3176
3177 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3178 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
3179 } else {
3180 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
3181 }
3182 tcg_gen_extr_i64_i32(rl, rh, ret);
3183
3184 tcg_temp_free_i64(ret);
3185 }
3186
3187 static inline void
3188 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3189 {
3190 TCGv_i64 ret = tcg_temp_new_i64();
3191
3192 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3193 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
3194 } else {
3195 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
3196 }
3197 tcg_gen_extr_i64_i32(rl, rh, ret);
3198
3199 tcg_temp_free_i64(ret);
3200 }
3201
3202 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
3203 {
3204 TCGv temp = tcg_temp_new();
3205 /* calc AV bit */
3206 tcg_gen_add_tl(temp, arg_low, arg_low);
3207 tcg_gen_xor_tl(temp, temp, arg_low);
3208 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
3209 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
3210 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3211 /* calc SAV bit */
3212 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3213 tcg_gen_movi_tl(cpu_PSW_V, 0);
3214 tcg_temp_free(temp);
3215 }
3216
3217 static void gen_calc_usb_mulr_h(TCGv arg)
3218 {
3219 TCGv temp = tcg_temp_new();
3220 /* calc AV bit */
3221 tcg_gen_add_tl(temp, arg, arg);
3222 tcg_gen_xor_tl(temp, temp, arg);
3223 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
3224 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3225 /* calc SAV bit */
3226 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3227 /* clear V bit */
3228 tcg_gen_movi_tl(cpu_PSW_V, 0);
3229 tcg_temp_free(temp);
3230 }
3231
3232 /* helpers for generating program flow micro-ops */
3233
3234 static inline void gen_save_pc(target_ulong pc)
3235 {
3236 tcg_gen_movi_tl(cpu_PC, pc);
3237 }
3238
3239 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3240 {
3241 TranslationBlock *tb;
3242 tb = ctx->tb;
3243 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3244 likely(!ctx->singlestep_enabled)) {
3245 tcg_gen_goto_tb(n);
3246 gen_save_pc(dest);
3247 tcg_gen_exit_tb((uintptr_t)tb + n);
3248 } else {
3249 gen_save_pc(dest);
3250 if (ctx->singlestep_enabled) {
3251 /* raise exception debug */
3252 }
3253 tcg_gen_exit_tb(0);
3254 }
3255 }
3256
3257 static void generate_trap(DisasContext *ctx, int class, int tin)
3258 {
3259 TCGv_i32 classtemp = tcg_const_i32(class);
3260 TCGv_i32 tintemp = tcg_const_i32(tin);
3261
3262 gen_save_pc(ctx->pc);
3263 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
3264 ctx->bstate = BS_EXCP;
3265
3266 tcg_temp_free(classtemp);
3267 tcg_temp_free(tintemp);
3268 }
3269
3270 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
3271 TCGv r2, int16_t address)
3272 {
3273 TCGLabel *jumpLabel = gen_new_label();
3274 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
3275
3276 gen_goto_tb(ctx, 1, ctx->next_pc);
3277
3278 gen_set_label(jumpLabel);
3279 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
3280 }
3281
3282 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
3283 int r2, int16_t address)
3284 {
3285 TCGv temp = tcg_const_i32(r2);
3286 gen_branch_cond(ctx, cond, r1, temp, address);
3287 tcg_temp_free(temp);
3288 }
3289
3290 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
3291 {
3292 TCGLabel *l1 = gen_new_label();
3293
3294 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
3295 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
3296 gen_goto_tb(ctx, 1, ctx->pc + offset);
3297 gen_set_label(l1);
3298 gen_goto_tb(ctx, 0, ctx->next_pc);
3299 }
3300
3301 static void gen_fcall_save_ctx(DisasContext *ctx)
3302 {
3303 TCGv temp = tcg_temp_new();
3304
3305 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
3306 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
3307 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3308 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
3309
3310 tcg_temp_free(temp);
3311 }
3312
3313 static void gen_fret(DisasContext *ctx)
3314 {
3315 TCGv temp = tcg_temp_new();
3316
3317 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
3318 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
3319 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
3320 tcg_gen_mov_tl(cpu_PC, temp);
3321 tcg_gen_exit_tb(0);
3322 ctx->bstate = BS_BRANCH;
3323
3324 tcg_temp_free(temp);
3325 }
3326
3327 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
3328 int r2 , int32_t constant , int32_t offset)
3329 {
3330 TCGv temp, temp2;
3331 int n;
3332
3333 switch (opc) {
3334 /* SB-format jumps */
3335 case OPC1_16_SB_J:
3336 case OPC1_32_B_J:
3337 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3338 break;
3339 case OPC1_32_B_CALL:
3340 case OPC1_16_SB_CALL:
3341 gen_helper_1arg(call, ctx->next_pc);
3342 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3343 break;
3344 case OPC1_16_SB_JZ:
3345 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
3346 break;
3347 case OPC1_16_SB_JNZ:
3348 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
3349 break;
3350 /* SBC-format jumps */
3351 case OPC1_16_SBC_JEQ:
3352 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
3353 break;
3354 case OPC1_16_SBC_JNE:
3355 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
3356 break;
3357 /* SBRN-format jumps */
3358 case OPC1_16_SBRN_JZ_T:
3359 temp = tcg_temp_new();
3360 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3361 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3362 tcg_temp_free(temp);
3363 break;
3364 case OPC1_16_SBRN_JNZ_T:
3365 temp = tcg_temp_new();
3366 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3367 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3368 tcg_temp_free(temp);
3369 break;
3370 /* SBR-format jumps */
3371 case OPC1_16_SBR_JEQ:
3372 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
3373 offset);
3374 break;
3375 case OPC1_16_SBR_JNE:
3376 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
3377 offset);
3378 break;
3379 case OPC1_16_SBR_JNZ:
3380 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
3381 break;
3382 case OPC1_16_SBR_JNZ_A:
3383 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3384 break;
3385 case OPC1_16_SBR_JGEZ:
3386 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
3387 break;
3388 case OPC1_16_SBR_JGTZ:
3389 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
3390 break;
3391 case OPC1_16_SBR_JLEZ:
3392 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
3393 break;
3394 case OPC1_16_SBR_JLTZ:
3395 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
3396 break;
3397 case OPC1_16_SBR_JZ:
3398 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
3399 break;
3400 case OPC1_16_SBR_JZ_A:
3401 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3402 break;
3403 case OPC1_16_SBR_LOOP:
3404 gen_loop(ctx, r1, offset * 2 - 32);
3405 break;
3406 /* SR-format jumps */
3407 case OPC1_16_SR_JI:
3408 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3409 tcg_gen_exit_tb(0);
3410 break;
3411 case OPC2_32_SYS_RET:
3412 case OPC2_16_SR_RET:
3413 gen_helper_ret(cpu_env);
3414 tcg_gen_exit_tb(0);
3415 break;
3416 /* B-format */
3417 case OPC1_32_B_CALLA:
3418 gen_helper_1arg(call, ctx->next_pc);
3419 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3420 break;
3421 case OPC1_32_B_FCALL:
3422 gen_fcall_save_ctx(ctx);
3423 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3424 break;
3425 case OPC1_32_B_FCALLA:
3426 gen_fcall_save_ctx(ctx);
3427 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3428 break;
3429 case OPC1_32_B_JLA:
3430 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3431 /* fall through */
3432 case OPC1_32_B_JA:
3433 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3434 break;
3435 case OPC1_32_B_JL:
3436 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3437 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3438 break;
3439 /* BOL format */
3440 case OPCM_32_BRC_EQ_NEQ:
3441 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3442 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3443 } else {
3444 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3445 }
3446 break;
3447 case OPCM_32_BRC_GE:
3448 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3449 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3450 } else {
3451 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3452 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3453 offset);
3454 }
3455 break;
3456 case OPCM_32_BRC_JLT:
3457 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3458 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3459 } else {
3460 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3461 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3462 offset);
3463 }
3464 break;
3465 case OPCM_32_BRC_JNE:
3466 temp = tcg_temp_new();
3467 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3468 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3469 /* subi is unconditional */
3470 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3471 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3472 } else {
3473 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3474 /* addi is unconditional */
3475 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3476 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3477 }
3478 tcg_temp_free(temp);
3479 break;
3480 /* BRN format */
3481 case OPCM_32_BRN_JTT:
3482 n = MASK_OP_BRN_N(ctx->opcode);
3483
3484 temp = tcg_temp_new();
3485 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3486
3487 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3488 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3489 } else {
3490 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3491 }
3492 tcg_temp_free(temp);
3493 break;
3494 /* BRR Format */
3495 case OPCM_32_BRR_EQ_NEQ:
3496 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3497 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3498 offset);
3499 } else {
3500 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3501 offset);
3502 }
3503 break;
3504 case OPCM_32_BRR_ADDR_EQ_NEQ:
3505 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3506 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3507 offset);
3508 } else {
3509 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3510 offset);
3511 }
3512 break;
3513 case OPCM_32_BRR_GE:
3514 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3515 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3516 offset);
3517 } else {
3518 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3519 offset);
3520 }
3521 break;
3522 case OPCM_32_BRR_JLT:
3523 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3524 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3525 offset);
3526 } else {
3527 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3528 offset);
3529 }
3530 break;
3531 case OPCM_32_BRR_LOOP:
3532 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3533 gen_loop(ctx, r2, offset * 2);
3534 } else {
3535 /* OPC2_32_BRR_LOOPU */
3536 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3537 }
3538 break;
3539 case OPCM_32_BRR_JNE:
3540 temp = tcg_temp_new();
3541 temp2 = tcg_temp_new();
3542 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3543 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3544 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3545 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3546 /* subi is unconditional */
3547 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3548 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3549 } else {
3550 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3551 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3552 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3553 /* addi is unconditional */
3554 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3555 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3556 }
3557 tcg_temp_free(temp);
3558 tcg_temp_free(temp2);
3559 break;
3560 case OPCM_32_BRR_JNZ:
3561 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3562 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3563 } else {
3564 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3565 }
3566 break;
3567 default:
3568 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3569 }
3570 ctx->bstate = BS_BRANCH;
3571 }
3572
3573
3574 /*
3575 * Functions for decoding instructions
3576 */
3577
3578 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
3579 {
3580 int r1;
3581 int32_t const4;
3582 TCGv temp, temp2;
3583
3584 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3585 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3586
3587 switch (op1) {
3588 case OPC1_16_SRC_ADD:
3589 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3590 break;
3591 case OPC1_16_SRC_ADD_A15:
3592 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3593 break;
3594 case OPC1_16_SRC_ADD_15A:
3595 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3596 break;
3597 case OPC1_16_SRC_ADD_A:
3598 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3599 break;
3600 case OPC1_16_SRC_CADD:
3601 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3602 cpu_gpr_d[15]);
3603 break;
3604 case OPC1_16_SRC_CADDN:
3605 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3606 cpu_gpr_d[15]);
3607 break;
3608 case OPC1_16_SRC_CMOV:
3609 temp = tcg_const_tl(0);
3610 temp2 = tcg_const_tl(const4);
3611 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3612 temp2, cpu_gpr_d[r1]);
3613 tcg_temp_free(temp);
3614 tcg_temp_free(temp2);
3615 break;
3616 case OPC1_16_SRC_CMOVN:
3617 temp = tcg_const_tl(0);
3618 temp2 = tcg_const_tl(const4);
3619 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3620 temp2, cpu_gpr_d[r1]);
3621 tcg_temp_free(temp);
3622 tcg_temp_free(temp2);
3623 break;
3624 case OPC1_16_SRC_EQ:
3625 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3626 const4);
3627 break;
3628 case OPC1_16_SRC_LT:
3629 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3630 const4);
3631 break;
3632 case OPC1_16_SRC_MOV:
3633 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3634 break;
3635 case OPC1_16_SRC_MOV_A:
3636 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3637 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3638 break;
3639 case OPC1_16_SRC_MOV_E:
3640 if (tricore_feature(env, TRICORE_FEATURE_16)) {
3641 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3642 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3643 } else {
3644 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3645 }
3646 break;
3647 case OPC1_16_SRC_SH:
3648 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3649 break;
3650 case OPC1_16_SRC_SHA:
3651 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3652 break;
3653 default:
3654 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3655 }
3656 }
3657
3658 static void decode_srr_opc(DisasContext *ctx, int op1)
3659 {
3660 int r1, r2;
3661 TCGv temp;
3662
3663 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3664 r2 = MASK_OP_SRR_S2(ctx->opcode);
3665
3666 switch (op1) {
3667 case OPC1_16_SRR_ADD:
3668 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3669 break;
3670 case OPC1_16_SRR_ADD_A15:
3671 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3672 break;
3673 case OPC1_16_SRR_ADD_15A:
3674 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3675 break;
3676 case OPC1_16_SRR_ADD_A:
3677 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3678 break;
3679 case OPC1_16_SRR_ADDS:
3680 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3681 break;
3682 case OPC1_16_SRR_AND:
3683 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3684 break;
3685 case OPC1_16_SRR_CMOV:
3686 temp = tcg_const_tl(0);
3687 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3688 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3689 tcg_temp_free(temp);
3690 break;
3691 case OPC1_16_SRR_CMOVN:
3692 temp = tcg_const_tl(0);
3693 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3694 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3695 tcg_temp_free(temp);
3696 break;
3697 case OPC1_16_SRR_EQ:
3698 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3699 cpu_gpr_d[r2]);
3700 break;
3701 case OPC1_16_SRR_LT:
3702 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3703 cpu_gpr_d[r2]);
3704 break;
3705 case OPC1_16_SRR_MOV:
3706 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3707 break;
3708 case OPC1_16_SRR_MOV_A:
3709 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3710 break;
3711 case OPC1_16_SRR_MOV_AA:
3712 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3713 break;
3714 case OPC1_16_SRR_MOV_D:
3715 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3716 break;
3717 case OPC1_16_SRR_MUL:
3718 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3719 break;
3720 case OPC1_16_SRR_OR:
3721 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3722 break;
3723 case OPC1_16_SRR_SUB:
3724 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3725 break;
3726 case OPC1_16_SRR_SUB_A15B:
3727 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3728 break;
3729 case OPC1_16_SRR_SUB_15AB:
3730 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3731 break;
3732 case OPC1_16_SRR_SUBS:
3733 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3734 break;
3735 case OPC1_16_SRR_XOR:
3736 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3737 break;
3738 default:
3739 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3740 }
3741 }
3742
3743 static void decode_ssr_opc(DisasContext *ctx, int op1)
3744 {
3745 int r1, r2;
3746
3747 r1 = MASK_OP_SSR_S1(ctx->opcode);
3748 r2 = MASK_OP_SSR_S2(ctx->opcode);
3749
3750 switch (op1) {
3751 case OPC1_16_SSR_ST_A:
3752 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3753 break;
3754 case OPC1_16_SSR_ST_A_POSTINC:
3755 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3756 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3757 break;
3758 case OPC1_16_SSR_ST_B:
3759 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3760 break;
3761 case OPC1_16_SSR_ST_B_POSTINC:
3762 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3763 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3764 break;
3765 case OPC1_16_SSR_ST_H:
3766 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3767 break;
3768 case OPC1_16_SSR_ST_H_POSTINC:
3769 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3770 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3771 break;
3772 case OPC1_16_SSR_ST_W:
3773 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3774 break;
3775 case OPC1_16_SSR_ST_W_POSTINC:
3776 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3777 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3778 break;
3779 default:
3780 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3781 }
3782 }
3783
3784 static void decode_sc_opc(DisasContext *ctx, int op1)
3785 {
3786 int32_t const16;
3787
3788 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3789
3790 switch (op1) {
3791 case OPC1_16_SC_AND:
3792 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3793 break;
3794 case OPC1_16_SC_BISR:
3795 gen_helper_1arg(bisr, const16 & 0xff);
3796 break;
3797 case OPC1_16_SC_LD_A:
3798 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3799 break;
3800 case OPC1_16_SC_LD_W:
3801 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3802 break;
3803 case OPC1_16_SC_MOV:
3804 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3805 break;
3806 case OPC1_16_SC_OR:
3807 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3808 break;
3809 case OPC1_16_SC_ST_A:
3810 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3811 break;
3812 case OPC1_16_SC_ST_W:
3813 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3814 break;
3815 case OPC1_16_SC_SUB_A:
3816 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3817 break;
3818 default:
3819 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3820 }
3821 }
3822
3823 static void decode_slr_opc(DisasContext *ctx, int op1)
3824 {
3825 int r1, r2;
3826
3827 r1 = MASK_OP_SLR_D(ctx->opcode);
3828 r2 = MASK_OP_SLR_S2(ctx->opcode);
3829
3830 switch (op1) {
3831 /* SLR-format */
3832 case OPC1_16_SLR_LD_A:
3833 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3834 break;
3835 case OPC1_16_SLR_LD_A_POSTINC:
3836 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3837 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3838 break;
3839 case OPC1_16_SLR_LD_BU:
3840 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3841 break;
3842 case OPC1_16_SLR_LD_BU_POSTINC:
3843 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3844 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3845 break;
3846 case OPC1_16_SLR_LD_H:
3847 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3848 break;
3849 case OPC1_16_SLR_LD_H_POSTINC:
3850 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3851 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3852 break;
3853 case OPC1_16_SLR_LD_W:
3854 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3855 break;
3856 case OPC1_16_SLR_LD_W_POSTINC:
3857 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3858 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3859 break;
3860 default:
3861 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3862 }
3863 }
3864
3865 static void decode_sro_opc(DisasContext *ctx, int op1)
3866 {
3867 int r2;
3868 int32_t address;
3869
3870 r2 = MASK_OP_SRO_S2(ctx->opcode);
3871 address = MASK_OP_SRO_OFF4(ctx->opcode);
3872
3873 /* SRO-format */
3874 switch (op1) {
3875 case OPC1_16_SRO_LD_A:
3876 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3877 break;
3878 case OPC1_16_SRO_LD_BU:
3879 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3880 break;
3881 case OPC1_16_SRO_LD_H:
3882 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3883 break;
3884 case OPC1_16_SRO_LD_W:
3885 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3886 break;
3887 case OPC1_16_SRO_ST_A:
3888 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3889 break;
3890 case OPC1_16_SRO_ST_B:
3891 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3892 break;
3893 case OPC1_16_SRO_ST_H:
3894 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3895 break;
3896 case OPC1_16_SRO_ST_W:
3897 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3898 break;
3899 default:
3900 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3901 }
3902 }
3903
3904 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3905 {
3906 uint32_t op2;
3907 op2 = MASK_OP_SR_OP2(ctx->opcode);
3908
3909 switch (op2) {
3910 case OPC2_16_SR_NOP:
3911 break;
3912 case OPC2_16_SR_RET:
3913 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3914 break;
3915 case OPC2_16_SR_RFE:
3916 gen_helper_rfe(cpu_env);
3917 tcg_gen_exit_tb(0);
3918 ctx->bstate = BS_BRANCH;
3919 break;
3920 case OPC2_16_SR_DEBUG:
3921 /* raise EXCP_DEBUG */
3922 break;
3923 case OPC2_16_SR_FRET:
3924 gen_fret(ctx);
3925 break;
3926 default:
3927 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3928 }
3929 }
3930
3931 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3932 {
3933 uint32_t op2;
3934 uint32_t r1;
3935 TCGv temp;
3936
3937 r1 = MASK_OP_SR_S1D(ctx->opcode);
3938 op2 = MASK_OP_SR_OP2(ctx->opcode);
3939
3940 switch (op2) {
3941 case OPC2_16_SR_RSUB:
3942 /* overflow only if r1 = -0x80000000 */
3943 temp = tcg_const_i32(-0x80000000);
3944 /* calc V bit */
3945 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3946 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3947 /* calc SV bit */
3948 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3949 /* sub */
3950 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3951 /* calc av */
3952 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3953 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3954 /* calc sav */
3955 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3956 tcg_temp_free(temp);
3957 break;
3958 case OPC2_16_SR_SAT_B:
3959 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3960 break;
3961 case OPC2_16_SR_SAT_BU:
3962 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3963 break;
3964 case OPC2_16_SR_SAT_H:
3965 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3966 break;
3967 case OPC2_16_SR_SAT_HU:
3968 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3969 break;
3970 default:
3971 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3972 }
3973 }
3974
3975 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3976 {
3977 int op1;
3978 int r1, r2;
3979 int32_t const16;
3980 int32_t address;
3981 TCGv temp;
3982
3983 op1 = MASK_OP_MAJOR(ctx->opcode);
3984
3985 /* handle ADDSC.A opcode only being 6 bit long */
3986 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3987 op1 = OPC1_16_SRRS_ADDSC_A;
3988 }
3989
3990 switch (op1) {
3991 case OPC1_16_SRC_ADD:
3992 case OPC1_16_SRC_ADD_A15:
3993 case OPC1_16_SRC_ADD_15A:
3994 case OPC1_16_SRC_ADD_A:
3995 case OPC1_16_SRC_CADD:
3996 case OPC1_16_SRC_CADDN:
3997 case OPC1_16_SRC_CMOV:
3998 case OPC1_16_SRC_CMOVN:
3999 case OPC1_16_SRC_EQ:
4000 case OPC1_16_SRC_LT:
4001 case OPC1_16_SRC_MOV:
4002 case OPC1_16_SRC_MOV_A:
4003 case OPC1_16_SRC_MOV_E:
4004 case OPC1_16_SRC_SH:
4005 case OPC1_16_SRC_SHA:
4006 decode_src_opc(env, ctx, op1);
4007 break;
4008 /* SRR-format */
4009 case OPC1_16_SRR_ADD:
4010 case OPC1_16_SRR_ADD_A15:
4011 case OPC1_16_SRR_ADD_15A:
4012 case OPC1_16_SRR_ADD_A:
4013 case OPC1_16_SRR_ADDS:
4014 case OPC1_16_SRR_AND:
4015 case OPC1_16_SRR_CMOV:
4016 case OPC1_16_SRR_CMOVN:
4017 case OPC1_16_SRR_EQ:
4018 case OPC1_16_SRR_LT:
4019 case OPC1_16_SRR_MOV:
4020 case OPC1_16_SRR_MOV_A:
4021 case OPC1_16_SRR_MOV_AA:
4022 case OPC1_16_SRR_MOV_D:
4023 case OPC1_16_SRR_MUL:
4024 case OPC1_16_SRR_OR:
4025 case OPC1_16_SRR_SUB:
4026 case OPC1_16_SRR_SUB_A15B:
4027 case OPC1_16_SRR_SUB_15AB:
4028 case OPC1_16_SRR_SUBS:
4029 case OPC1_16_SRR_XOR:
4030 decode_srr_opc(ctx, op1);
4031 break;
4032 /* SSR-format */
4033 case OPC1_16_SSR_ST_A:
4034 case OPC1_16_SSR_ST_A_POSTINC:
4035 case OPC1_16_SSR_ST_B:
4036 case OPC1_16_SSR_ST_B_POSTINC:
4037 case OPC1_16_SSR_ST_H:
4038 case OPC1_16_SSR_ST_H_POSTINC:
4039 case OPC1_16_SSR_ST_W:
4040 case OPC1_16_SSR_ST_W_POSTINC:
4041 decode_ssr_opc(ctx, op1);
4042 break;
4043 /* SRRS-format */
4044 case OPC1_16_SRRS_ADDSC_A:
4045 r2 = MASK_OP_SRRS_S2(ctx->opcode);
4046 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
4047 const16 = MASK_OP_SRRS_N(ctx->opcode);
4048 temp = tcg_temp_new();
4049 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
4050 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
4051 tcg_temp_free(temp);
4052 break;
4053 /* SLRO-format */
4054 case OPC1_16_SLRO_LD_A:
4055 r1 = MASK_OP_SLRO_D(ctx->opcode);
4056 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4057 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4058 break;
4059 case OPC1_16_SLRO_LD_BU:
4060 r1 = MASK_OP_SLRO_D(ctx->opcode);
4061 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4062 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4063 break;
4064 case OPC1_16_SLRO_LD_H:
4065 r1 = MASK_OP_SLRO_D(ctx->opcode);
4066 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4067 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4068 break;
4069 case OPC1_16_SLRO_LD_W:
4070 r1 = MASK_OP_SLRO_D(ctx->opcode);
4071 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4072 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4073 break;
4074 /* SB-format */
4075 case OPC1_16_SB_CALL:
4076 case OPC1_16_SB_J:
4077 case OPC1_16_SB_JNZ:
4078 case OPC1_16_SB_JZ:
4079 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
4080 gen_compute_branch(ctx, op1, 0, 0, 0, address);
4081 break;
4082 /* SBC-format */
4083 case OPC1_16_SBC_JEQ:
4084 case OPC1_16_SBC_JNE:
4085 address = MASK_OP_SBC_DISP4(ctx->opcode);
4086 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
4087 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4088 break;
4089 /* SBRN-format */
4090 case OPC1_16_SBRN_JNZ_T:
4091 case OPC1_16_SBRN_JZ_T:
4092 address = MASK_OP_SBRN_DISP4(ctx->opcode);
4093 const16 = MASK_OP_SBRN_N(ctx->opcode);
4094 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4095 break;
4096 /* SBR-format */
4097 case OPC1_16_SBR_JEQ:
4098 case OPC1_16_SBR_JGEZ:
4099 case OPC1_16_SBR_JGTZ:
4100 case OPC1_16_SBR_JLEZ:
4101 case OPC1_16_SBR_JLTZ:
4102 case OPC1_16_SBR_JNE:
4103 case OPC1_16_SBR_JNZ:
4104 case OPC1_16_SBR_JNZ_A:
4105 case OPC1_16_SBR_JZ:
4106 case OPC1_16_SBR_JZ_A:
4107 case OPC1_16_SBR_LOOP:
4108 r1 = MASK_OP_SBR_S2(ctx->opcode);
4109 address = MASK_OP_SBR_DISP4(ctx->opcode);
4110 gen_compute_branch(ctx, op1, r1, 0, 0, address);
4111 break;
4112 /* SC-format */
4113 case OPC1_16_SC_AND:
4114 case OPC1_16_SC_BISR:
4115 case OPC1_16_SC_LD_A:
4116 case OPC1_16_SC_LD_W:
4117 case OPC1_16_SC_MOV:
4118 case OPC1_16_SC_OR:
4119 case OPC1_16_SC_ST_A:
4120 case OPC1_16_SC_ST_W:
4121 case OPC1_16_SC_SUB_A:
4122 decode_sc_opc(ctx, op1);
4123 break;
4124 /* SLR-format */
4125 case OPC1_16_SLR_LD_A:
4126 case OPC1_16_SLR_LD_A_POSTINC:
4127 case OPC1_16_SLR_LD_BU:
4128 case OPC1_16_SLR_LD_BU_POSTINC:
4129 case OPC1_16_SLR_LD_H:
4130 case OPC1_16_SLR_LD_H_POSTINC:
4131 case OPC1_16_SLR_LD_W:
4132 case OPC1_16_SLR_LD_W_POSTINC:
4133 decode_slr_opc(ctx, op1);
4134 break;
4135 /* SRO-format */
4136 case OPC1_16_SRO_LD_A:
4137 case OPC1_16_SRO_LD_BU:
4138 case OPC1_16_SRO_LD_H:
4139 case OPC1_16_SRO_LD_W:
4140 case OPC1_16_SRO_ST_A:
4141 case OPC1_16_SRO_ST_B:
4142 case OPC1_16_SRO_ST_H:
4143 case OPC1_16_SRO_ST_W:
4144 decode_sro_opc(ctx, op1);
4145 break;
4146 /* SSRO-format */
4147 case OPC1_16_SSRO_ST_A:
4148 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4149 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4150 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4151 break;
4152 case OPC1_16_SSRO_ST_B:
4153 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4154 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4155 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4156 break;
4157 case OPC1_16_SSRO_ST_H:
4158 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4159 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4160 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4161 break;
4162 case OPC1_16_SSRO_ST_W:
4163 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4164 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4165 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4166 break;
4167 /* SR-format */
4168 case OPCM_16_SR_SYSTEM:
4169 decode_sr_system(env, ctx);
4170 break;
4171 case OPCM_16_SR_ACCU:
4172 decode_sr_accu(env, ctx);
4173 break;
4174 case OPC1_16_SR_JI:
4175 r1 = MASK_OP_SR_S1D(ctx->opcode);
4176 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
4177 break;
4178 case OPC1_16_SR_NOT:
4179 r1 = MASK_OP_SR_S1D(ctx->opcode);
4180 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
4181 break;
4182 default:
4183 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4184 }
4185 }
4186
4187 /*
4188 * 32 bit instructions
4189 */
4190
4191 /* ABS-format */
4192 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
4193 {
4194 int32_t op2;
4195 int32_t r1;
4196 uint32_t address;
4197 TCGv temp;
4198
4199 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4200 address = MASK_OP_ABS_OFF18(ctx->opcode);
4201 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4202
4203 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4204
4205 switch (op2) {
4206 case OPC2_32_ABS_LD_A:
4207 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4208 break;
4209 case OPC2_32_ABS_LD_D:
4210 CHECK_REG_PAIR(r1);
4211 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4212 break;
4213 case OPC2_32_ABS_LD_DA:
4214 CHECK_REG_PAIR(r1);
4215 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4216 break;
4217 case OPC2_32_ABS_LD_W:
4218 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4219 break;
4220 default:
4221 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4222 }
4223
4224 tcg_temp_free(temp);
4225 }
4226
4227 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
4228 {
4229 int32_t op2;
4230 int32_t r1;
4231 uint32_t address;
4232 TCGv temp;
4233
4234 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4235 address = MASK_OP_ABS_OFF18(ctx->opcode);
4236 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4237
4238 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4239
4240 switch (op2) {
4241 case OPC2_32_ABS_LD_B:
4242 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
4243 break;
4244 case OPC2_32_ABS_LD_BU:
4245 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4246 break;
4247 case OPC2_32_ABS_LD_H:
4248 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
4249 break;
4250 case OPC2_32_ABS_LD_HU:
4251 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4252 break;
4253 default:
4254 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4255 }
4256
4257 tcg_temp_free(temp);
4258 }
4259
4260 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
4261 {
4262 int32_t op2;
4263 int32_t r1;
4264 uint32_t address;
4265 TCGv temp;
4266
4267 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4268 address = MASK_OP_ABS_OFF18(ctx->opcode);
4269 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4270
4271 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4272
4273 switch (op2) {
4274 case OPC2_32_ABS_LDMST:
4275 gen_ldmst(ctx, r1, temp);
4276 break;
4277 case OPC2_32_ABS_SWAP_W:
4278 gen_swap(ctx, r1, temp);
4279 break;
4280 default:
4281 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4282 }
4283
4284 tcg_temp_free(temp);
4285 }
4286
4287 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
4288 {
4289 uint32_t op2;
4290 int32_t off18;
4291
4292 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
4293 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4294
4295 switch (op2) {
4296 case OPC2_32_ABS_LDLCX:
4297 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
4298 break;
4299 case OPC2_32_ABS_LDUCX:
4300 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
4301 break;
4302 case OPC2_32_ABS_STLCX:
4303 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
4304 break;
4305 case OPC2_32_ABS_STUCX:
4306 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
4307 break;
4308 default:
4309 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4310 }
4311 }
4312
4313 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
4314 {
4315 int32_t op2;
4316 int32_t r1;
4317 uint32_t address;
4318 TCGv temp;
4319
4320 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4321 address = MASK_OP_ABS_OFF18(ctx->opcode);
4322 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4323
4324 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4325
4326 switch (op2) {
4327 case OPC2_32_ABS_ST_A:
4328 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4329 break;
4330 case OPC2_32_ABS_ST_D:
4331 CHECK_REG_PAIR(r1);
4332 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4333 break;
4334 case OPC2_32_ABS_ST_DA:
4335 CHECK_REG_PAIR(r1);
4336 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4337 break;
4338 case OPC2_32_ABS_ST_W:
4339 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4340 break;
4341 default:
4342 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4343 }
4344 tcg_temp_free(temp);
4345 }
4346
4347 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
4348 {
4349 int32_t op2;
4350 int32_t r1;
4351 uint32_t address;
4352 TCGv temp;
4353
4354 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4355 address = MASK_OP_ABS_OFF18(ctx->opcode);
4356 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4357
4358 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4359
4360 switch (op2) {
4361 case OPC2_32_ABS_ST_B:
4362 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4363 break;
4364 case OPC2_32_ABS_ST_H:
4365 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4366 break;
4367 default:
4368 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4369 }
4370 tcg_temp_free(temp);
4371 }
4372
4373 /* Bit-format */
4374
4375 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
4376 {
4377 uint32_t op2;
4378 int r1, r2, r3;
4379 int pos1, pos2;
4380
4381 r1 = MASK_OP_BIT_S1(ctx->opcode);
4382 r2 = MASK_OP_BIT_S2(ctx->opcode);
4383 r3 = MASK_OP_BIT_D(ctx->opcode);
4384 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4385 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4386 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4387
4388
4389 switch (op2) {
4390 case OPC2_32_BIT_AND_AND_T:
4391 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4392 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
4393 break;
4394 case OPC2_32_BIT_AND_ANDN_T:
4395 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4396 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
4397 break;
4398 case OPC2_32_BIT_AND_NOR_T:
4399 if (TCG_TARGET_HAS_andc_i32) {
4400 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4401 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
4402 } else {
4403 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4404 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
4405 }
4406 break;
4407 case OPC2_32_BIT_AND_OR_T:
4408 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4409 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4410 break;
4411 default:
4412 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4413 }
4414 }
4415
4416 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
4417 {
4418 uint32_t op2;
4419 int r1, r2, r3;
4420 int pos1, pos2;
4421 r1 = MASK_OP_BIT_S1(ctx->opcode);
4422 r2 = MASK_OP_BIT_S2(ctx->opcode);
4423 r3 = MASK_OP_BIT_D(ctx->opcode);
4424 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4425 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4426 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4427
4428 switch (op2) {
4429 case OPC2_32_BIT_AND_T:
4430 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4431 pos1, pos2, &tcg_gen_and_tl);
4432 break;
4433 case OPC2_32_BIT_ANDN_T:
4434 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4435 pos1, pos2, &tcg_gen_andc_tl);
4436 break;
4437 case OPC2_32_BIT_NOR_T:
4438 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4439 pos1, pos2, &tcg_gen_nor_tl);
4440 break;
4441 case OPC2_32_BIT_OR_T:
4442 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4443 pos1, pos2, &tcg_gen_or_tl);
4444 break;
4445 default:
4446 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4447 }
4448 }
4449
4450 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
4451 {
4452 uint32_t op2;
4453 int r1, r2, r3;
4454 int pos1, pos2;
4455 TCGv temp;
4456 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4457 r1 = MASK_OP_BIT_S1(ctx->opcode);
4458 r2 = MASK_OP_BIT_S2(ctx->opcode);
4459 r3 = MASK_OP_BIT_D(ctx->opcode);
4460 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4461 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4462
4463 temp = tcg_temp_new();
4464
4465 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4466 if (op2 == OPC2_32_BIT_INSN_T) {
4467 tcg_gen_not_tl(temp, temp);
4468 }
4469 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4470 tcg_temp_free(temp);
4471 }
4472
4473 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
4474 {
4475 uint32_t op2;
4476
4477 int r1, r2, r3;
4478 int pos1, pos2;
4479
4480 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4481 r1 = MASK_OP_BIT_S1(ctx->opcode);
4482 r2 = MASK_OP_BIT_S2(ctx->opcode);
4483 r3 = MASK_OP_BIT_D(ctx->opcode);
4484 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4485 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4486
4487 switch (op2) {
4488 case OPC2_32_BIT_NAND_T:
4489 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4490 pos1, pos2, &tcg_gen_nand_tl);
4491 break;
4492 case OPC2_32_BIT_ORN_T:
4493 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4494 pos1, pos2, &tcg_gen_orc_tl);
4495 break;
4496 case OPC2_32_BIT_XNOR_T:
4497 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4498 pos1, pos2, &tcg_gen_eqv_tl);
4499 break;
4500 case OPC2_32_BIT_XOR_T:
4501 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4502 pos1, pos2, &tcg_gen_xor_tl);
4503 break;
4504 default:
4505 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4506 }
4507 }
4508
4509 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
4510 {
4511 uint32_t op2;
4512
4513 int r1, r2, r3;
4514 int pos1, pos2;
4515
4516 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4517 r1 = MASK_OP_BIT_S1(ctx->opcode);
4518 r2 = MASK_OP_BIT_S2(ctx->opcode);
4519 r3 = MASK_OP_BIT_D(ctx->opcode);
4520 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4521 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4522
4523 switch (op2) {
4524 case OPC2_32_BIT_OR_AND_T:
4525 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4526 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4527 break;
4528 case OPC2_32_BIT_OR_ANDN_T:
4529 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4530 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4531 break;
4532 case OPC2_32_BIT_OR_NOR_T:
4533 if (TCG_TARGET_HAS_orc_i32) {
4534 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4535 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4536 } else {
4537 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4538 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4539 }
4540 break;
4541 case OPC2_32_BIT_OR_OR_T:
4542 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4543 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4544 break;
4545 default:
4546 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4547 }
4548 }
4549
4550 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
4551 {
4552 uint32_t op2;
4553 int r1, r2, r3;
4554 int pos1, pos2;
4555 TCGv temp;
4556
4557 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4558 r1 = MASK_OP_BIT_S1(ctx->opcode);
4559 r2 = MASK_OP_BIT_S2(ctx->opcode);
4560 r3 = MASK_OP_BIT_D(ctx->opcode);
4561 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4562 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4563
4564 temp = tcg_temp_new();
4565
4566 switch (op2) {
4567 case OPC2_32_BIT_SH_AND_T:
4568 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4569 pos1, pos2, &tcg_gen_and_tl);
4570 break;
4571 case OPC2_32_BIT_SH_ANDN_T:
4572 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4573 pos1, pos2, &tcg_gen_andc_tl);
4574 break;
4575 case OPC2_32_BIT_SH_NOR_T:
4576 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4577 pos1, pos2, &tcg_gen_nor_tl);
4578 break;
4579 case OPC2_32_BIT_SH_OR_T:
4580 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4581 pos1, pos2, &tcg_gen_or_tl);
4582 break;
4583 default:
4584 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4585 }
4586 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4587 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4588 tcg_temp_free(temp);
4589 }
4590
4591 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
4592 {
4593 uint32_t op2;
4594 int r1, r2, r3;
4595 int pos1, pos2;
4596 TCGv temp;
4597
4598 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4599 r1 = MASK_OP_BIT_S1(ctx->opcode);
4600 r2 = MASK_OP_BIT_S2(ctx->opcode);
4601 r3 = MASK_OP_BIT_D(ctx->opcode);
4602 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4603 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4604
4605 temp = tcg_temp_new();
4606
4607 switch (op2) {
4608 case OPC2_32_BIT_SH_NAND_T:
4609 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4610 pos1, pos2, &tcg_gen_nand_tl);
4611 break;
4612 case OPC2_32_BIT_SH_ORN_T:
4613 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4614 pos1, pos2, &tcg_gen_orc_tl);
4615 break;
4616 case OPC2_32_BIT_SH_XNOR_T:
4617 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4618 pos1, pos2, &tcg_gen_eqv_tl);
4619 break;
4620 case OPC2_32_BIT_SH_XOR_T:
4621 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4622 pos1, pos2, &tcg_gen_xor_tl);
4623 break;
4624 default:
4625 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4626 }
4627 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4628 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4629 tcg_temp_free(temp);
4630 }
4631
4632 /* BO-format */
4633
4634
4635 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
4636 DisasContext *ctx)
4637 {
4638 uint32_t op2;
4639 uint32_t off10;
4640 int32_t r1, r2;
4641 TCGv temp;
4642
4643 r1 = MASK_OP_BO_S1D(ctx->opcode);
4644 r2 = MASK_OP_BO_S2(ctx->opcode);
4645 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4646 op2 = MASK_OP_BO_OP2(ctx->opcode);
4647
4648 switch (op2) {
4649 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4650 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4651 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4652 /* instruction to access the cache */
4653 break;
4654 case OPC2_32_BO_CACHEA_WI_POSTINC:
4655 case OPC2_32_BO_CACHEA_W_POSTINC:
4656 case OPC2_32_BO_CACHEA_I_POSTINC:
4657 /* instruction to access the cache, but we still need to handle
4658 the addressing mode */
4659 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4660 break;
4661 case OPC2_32_BO_CACHEA_WI_PREINC:
4662 case OPC2_32_BO_CACHEA_W_PREINC:
4663 case OPC2_32_BO_CACHEA_I_PREINC:
4664 /* instruction to access the cache, but we still need to handle
4665 the addressing mode */
4666 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4667 break;
4668 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4669 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4670 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
4671 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4672 }
4673 break;
4674 case OPC2_32_BO_CACHEI_W_POSTINC:
4675 case OPC2_32_BO_CACHEI_WI_POSTINC:
4676 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4677 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4678 } else {
4679 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4680 }
4681 break;
4682 case OPC2_32_BO_CACHEI_W_PREINC:
4683 case OPC2_32_BO_CACHEI_WI_PREINC:
4684 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4685 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4686 } else {
4687 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4688 }
4689 break;
4690 case OPC2_32_BO_ST_A_SHORTOFF:
4691 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4692 break;
4693 case OPC2_32_BO_ST_A_POSTINC:
4694 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4695 MO_LESL);
4696 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4697 break;
4698 case OPC2_32_BO_ST_A_PREINC:
4699 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4700 break;
4701 case OPC2_32_BO_ST_B_SHORTOFF:
4702 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4703 break;
4704 case OPC2_32_BO_ST_B_POSTINC:
4705 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4706 MO_UB);
4707 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4708 break;
4709 case OPC2_32_BO_ST_B_PREINC:
4710 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4711 break;
4712 case OPC2_32_BO_ST_D_SHORTOFF:
4713 CHECK_REG_PAIR(r1);
4714 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4715 off10, ctx);
4716 break;
4717 case OPC2_32_BO_ST_D_POSTINC:
4718 CHECK_REG_PAIR(r1);
4719 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4720 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4721 break;
4722 case OPC2_32_BO_ST_D_PREINC:
4723 CHECK_REG_PAIR(r1);
4724 temp = tcg_temp_new();
4725 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4726 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4727 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4728 tcg_temp_free(temp);
4729 break;
4730 case OPC2_32_BO_ST_DA_SHORTOFF:
4731 CHECK_REG_PAIR(r1);
4732 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4733 off10, ctx);
4734 break;
4735 case OPC2_32_BO_ST_DA_POSTINC:
4736 CHECK_REG_PAIR(r1);
4737 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4738 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4739 break;
4740 case OPC2_32_BO_ST_DA_PREINC:
4741 CHECK_REG_PAIR(r1);
4742 temp = tcg_temp_new();
4743 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4744 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4745 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4746 tcg_temp_free(temp);
4747 break;
4748 case OPC2_32_BO_ST_H_SHORTOFF:
4749 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4750 break;
4751 case OPC2_32_BO_ST_H_POSTINC:
4752 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4753 MO_LEUW);
4754 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4755 break;
4756 case OPC2_32_BO_ST_H_PREINC:
4757 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4758 break;
4759 case OPC2_32_BO_ST_Q_SHORTOFF:
4760 temp = tcg_temp_new();
4761 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4762 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4763 tcg_temp_free(temp);
4764 break;
4765 case OPC2_32_BO_ST_Q_POSTINC:
4766 temp = tcg_temp_new();
4767 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4768 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4769 MO_LEUW);
4770 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4771 tcg_temp_free(temp);
4772 break;
4773 case OPC2_32_BO_ST_Q_PREINC:
4774 temp = tcg_temp_new();
4775 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4776 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4777 tcg_temp_free(temp);
4778 break;
4779 case OPC2_32_BO_ST_W_SHORTOFF:
4780 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4781 break;
4782 case OPC2_32_BO_ST_W_POSTINC:
4783 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4784 MO_LEUL);
4785 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4786 break;
4787 case OPC2_32_BO_ST_W_PREINC:
4788 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4789 break;
4790 default:
4791 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4792 }
4793 }
4794
4795 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
4796 DisasContext *ctx)
4797 {
4798 uint32_t op2;
4799 uint32_t off10;
4800 int32_t r1, r2;
4801 TCGv temp, temp2, temp3;
4802
4803 r1 = MASK_OP_BO_S1D(ctx->opcode);
4804 r2 = MASK_OP_BO_S2(ctx->opcode);
4805 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4806 op2 = MASK_OP_BO_OP2(ctx->opcode);
4807
4808 temp = tcg_temp_new();
4809 temp2 = tcg_temp_new();
4810 temp3 = tcg_const_i32(off10);
4811 CHECK_REG_PAIR(r2);
4812 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4813 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4814
4815 switch (op2) {
4816 case OPC2_32_BO_CACHEA_WI_BR:
4817 case OPC2_32_BO_CACHEA_W_BR:
4818 case OPC2_32_BO_CACHEA_I_BR:
4819 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4820 break;
4821 case OPC2_32_BO_CACHEA_WI_CIRC:
4822 case OPC2_32_BO_CACHEA_W_CIRC:
4823 case OPC2_32_BO_CACHEA_I_CIRC:
4824 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4825 break;
4826 case OPC2_32_BO_ST_A_BR:
4827 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4828 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4829 break;
4830 case OPC2_32_BO_ST_A_CIRC:
4831 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4832 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4833 break;
4834 case OPC2_32_BO_ST_B_BR:
4835 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4836 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4837 break;
4838 case OPC2_32_BO_ST_B_CIRC:
4839 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4840 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4841 break;
4842 case OPC2_32_BO_ST_D_BR:
4843 CHECK_REG_PAIR(r1);
4844 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4845 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4846 break;
4847 case OPC2_32_BO_ST_D_CIRC:
4848 CHECK_REG_PAIR(r1);
4849 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4850 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4851 tcg_gen_addi_tl(temp, temp, 4);
4852 tcg_gen_rem_tl(temp, temp, temp2);
4853 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4854 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4855 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4856 break;
4857 case OPC2_32_BO_ST_DA_BR:
4858 CHECK_REG_PAIR(r1);
4859 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4860 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4861 break;
4862 case OPC2_32_BO_ST_DA_CIRC:
4863 CHECK_REG_PAIR(r1);
4864 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4865 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4866 tcg_gen_addi_tl(temp, temp, 4);
4867 tcg_gen_rem_tl(temp, temp, temp2);
4868 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4869 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4870 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4871 break;
4872 case OPC2_32_BO_ST_H_BR:
4873 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4874 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4875 break;
4876 case OPC2_32_BO_ST_H_CIRC:
4877 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4878 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4879 break;
4880 case OPC2_32_BO_ST_Q_BR:
4881 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4882 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4883 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4884 break;
4885 case OPC2_32_BO_ST_Q_CIRC:
4886 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4887 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4888 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4889 break;
4890 case OPC2_32_BO_ST_W_BR:
4891 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4892 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4893 break;
4894 case OPC2_32_BO_ST_W_CIRC:
4895 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4896 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4897 break;
4898 default:
4899 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4900 }
4901 tcg_temp_free(temp);
4902 tcg_temp_free(temp2);
4903 tcg_temp_free(temp3);
4904 }
4905
4906 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
4907 DisasContext *ctx)
4908 {
4909 uint32_t op2;
4910 uint32_t off10;
4911 int32_t r1, r2;
4912 TCGv temp;
4913
4914 r1 = MASK_OP_BO_S1D(ctx->opcode);
4915 r2 = MASK_OP_BO_S2(ctx->opcode);
4916 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4917 op2 = MASK_OP_BO_OP2(ctx->opcode);
4918
4919 switch (op2) {
4920 case OPC2_32_BO_LD_A_SHORTOFF:
4921 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4922 break;
4923 case OPC2_32_BO_LD_A_POSTINC:
4924 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4925 MO_LEUL);
4926 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4927 break;
4928 case OPC2_32_BO_LD_A_PREINC:
4929 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4930 break;
4931 case OPC2_32_BO_LD_B_SHORTOFF:
4932 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4933 break;
4934 case OPC2_32_BO_LD_B_POSTINC:
4935 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4936 MO_SB);
4937 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4938 break;
4939 case OPC2_32_BO_LD_B_PREINC:
4940 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4941 break;
4942 case OPC2_32_BO_LD_BU_SHORTOFF:
4943 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4944 break;
4945 case OPC2_32_BO_LD_BU_POSTINC:
4946 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4947 MO_UB);
4948 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4949 break;
4950 case OPC2_32_BO_LD_BU_PREINC:
4951 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4952 break;
4953 case OPC2_32_BO_LD_D_SHORTOFF:
4954 CHECK_REG_PAIR(r1);
4955 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4956 off10, ctx);
4957 break;
4958 case OPC2_32_BO_LD_D_POSTINC:
4959 CHECK_REG_PAIR(r1);
4960 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4961 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4962 break;
4963 case OPC2_32_BO_LD_D_PREINC:
4964 CHECK_REG_PAIR(r1);
4965 temp = tcg_temp_new();
4966 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4967 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4968 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4969 tcg_temp_free(temp);
4970 break;
4971 case OPC2_32_BO_LD_DA_SHORTOFF:
4972 CHECK_REG_PAIR(r1);
4973 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4974 off10, ctx);
4975 break;
4976 case OPC2_32_BO_LD_DA_POSTINC:
4977 CHECK_REG_PAIR(r1);
4978 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4979 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4980 break;
4981 case OPC2_32_BO_LD_DA_PREINC:
4982 CHECK_REG_PAIR(r1);
4983 temp = tcg_temp_new();
4984 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4985 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4986 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4987 tcg_temp_free(temp);
4988 break;
4989 case OPC2_32_BO_LD_H_SHORTOFF:
4990 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4991 break;
4992 case OPC2_32_BO_LD_H_POSTINC:
4993 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4994 MO_LESW);
4995 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4996 break;
4997 case OPC2_32_BO_LD_H_PREINC:
4998 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4999 break;
5000 case OPC2_32_BO_LD_HU_SHORTOFF:
5001 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5002 break;
5003 case OPC2_32_BO_LD_HU_POSTINC:
5004 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5005 MO_LEUW);
5006 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5007 break;
5008 case OPC2_32_BO_LD_HU_PREINC:
5009 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5010 break;
5011 case OPC2_32_BO_LD_Q_SHORTOFF:
5012 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5013 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5014 break;
5015 case OPC2_32_BO_LD_Q_POSTINC:
5016 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5017 MO_LEUW);
5018 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5019 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5020 break;
5021 case OPC2_32_BO_LD_Q_PREINC:
5022 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
5023 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5024 break;
5025 case OPC2_32_BO_LD_W_SHORTOFF:
5026 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
5027 break;
5028 case OPC2_32_BO_LD_W_POSTINC:
5029 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
5030 MO_LEUL);
5031 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5032 break;
5033 case OPC2_32_BO_LD_W_PREINC:
5034 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
5035 break;
5036 default:
5037 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5038 }
5039 }
5040
5041 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
5042 DisasContext *ctx)
5043 {
5044 uint32_t op2;
5045 uint32_t off10;
5046 int r1, r2;
5047
5048 TCGv temp, temp2, temp3;
5049
5050 r1 = MASK_OP_BO_S1D(ctx->opcode);
5051 r2 = MASK_OP_BO_S2(ctx->opcode);
5052 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5053 op2 = MASK_OP_BO_OP2(ctx->opcode);
5054
5055 temp = tcg_temp_new();
5056 temp2 = tcg_temp_new();
5057 temp3 = tcg_const_i32(off10);
5058 CHECK_REG_PAIR(r2);
5059 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5060 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5061
5062
5063 switch (op2) {
5064 case OPC2_32_BO_LD_A_BR:
5065 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5066 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5067 break;
5068 case OPC2_32_BO_LD_A_CIRC:
5069 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5070 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5071 break;
5072 case OPC2_32_BO_LD_B_BR:
5073 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
5074 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5075 break;
5076 case OPC2_32_BO_LD_B_CIRC:
5077 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
5078 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5079 break;
5080 case OPC2_32_BO_LD_BU_BR:
5081 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
5082 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5083 break;
5084 case OPC2_32_BO_LD_BU_CIRC:
5085 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
5086 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5087 break;
5088 case OPC2_32_BO_LD_D_BR:
5089 CHECK_REG_PAIR(r1);
5090 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
5091 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5092 break;
5093 case OPC2_32_BO_LD_D_CIRC:
5094 CHECK_REG_PAIR(r1);
5095 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5096 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
5097 tcg_gen_addi_tl(temp, temp, 4);
5098 tcg_gen_rem_tl(temp, temp, temp2);
5099 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5100 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5101 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5102 break;
5103 case OPC2_32_BO_LD_DA_BR:
5104 CHECK_REG_PAIR(r1);
5105 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
5106 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5107 break;
5108 case OPC2_32_BO_LD_DA_CIRC:
5109 CHECK_REG_PAIR(r1);
5110 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5111 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
5112 tcg_gen_addi_tl(temp, temp, 4);
5113 tcg_gen_rem_tl(temp, temp, temp2);
5114 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5115 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5116 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5117 break;
5118 case OPC2_32_BO_LD_H_BR:
5119 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5120 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5121 break;
5122 case OPC2_32_BO_LD_H_CIRC:
5123 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5124 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5125 break;
5126 case OPC2_32_BO_LD_HU_BR:
5127 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5128 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5129 break;
5130 case OPC2_32_BO_LD_HU_CIRC:
5131 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5132 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5133 break;
5134 case OPC2_32_BO_LD_Q_BR:
5135 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5136 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5137 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5138 break;
5139 case OPC2_32_BO_LD_Q_CIRC:
5140 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5141 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5142 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5143 break;
5144 case OPC2_32_BO_LD_W_BR:
5145 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5146 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5147 break;
5148 case OPC2_32_BO_LD_W_CIRC:
5149 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5150 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5151 break;
5152 default:
5153 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5154 }
5155 tcg_temp_free(temp);
5156 tcg_temp_free(temp2);
5157 tcg_temp_free(temp3);
5158 }
5159
5160 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
5161 DisasContext *ctx)
5162 {
5163 uint32_t op2;
5164 uint32_t off10;
5165 int r1, r2;
5166
5167 TCGv temp, temp2;
5168
5169 r1 = MASK_OP_BO_S1D(ctx->opcode);
5170 r2 = MASK_OP_BO_S2(ctx->opcode);
5171 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5172 op2 = MASK_OP_BO_OP2(ctx->opcode);
5173
5174
5175 temp = tcg_temp_new();
5176 temp2 = tcg_temp_new();
5177
5178 switch (op2) {
5179 case OPC2_32_BO_LDLCX_SHORTOFF:
5180 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5181 gen_helper_ldlcx(cpu_env, temp);
5182 break;
5183 case OPC2_32_BO_LDMST_SHORTOFF:
5184 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5185 gen_ldmst(ctx, r1, temp);
5186 break;
5187 case OPC2_32_BO_LDMST_POSTINC:
5188 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5189 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5190 break;
5191 case OPC2_32_BO_LDMST_PREINC:
5192 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5193 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5194 break;
5195 case OPC2_32_BO_LDUCX_SHORTOFF:
5196 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5197 gen_helper_lducx(cpu_env, temp);
5198 break;
5199 case OPC2_32_BO_LEA_SHORTOFF:
5200 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
5201 break;
5202 case OPC2_32_BO_STLCX_SHORTOFF:
5203 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5204 gen_helper_stlcx(cpu_env, temp);
5205 break;
5206 case OPC2_32_BO_STUCX_SHORTOFF:
5207 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5208 gen_helper_stucx(cpu_env, temp);
5209 break;
5210 case OPC2_32_BO_SWAP_W_SHORTOFF:
5211 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5212 gen_swap(ctx, r1, temp);
5213 break;
5214 case OPC2_32_BO_SWAP_W_POSTINC:
5215 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5216 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5217 break;
5218 case OPC2_32_BO_SWAP_W_PREINC:
5219 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5220 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5221 break;
5222 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
5223 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5224 gen_cmpswap(ctx, r1, temp);
5225 break;
5226 case OPC2_32_BO_CMPSWAP_W_POSTINC:
5227 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5228 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5229 break;
5230 case OPC2_32_BO_CMPSWAP_W_PREINC:
5231 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5232 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5233 break;
5234 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
5235 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5236 gen_swapmsk(ctx, r1, temp);
5237 break;
5238 case OPC2_32_BO_SWAPMSK_W_POSTINC:
5239 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5240 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5241 break;
5242 case OPC2_32_BO_SWAPMSK_W_PREINC:
5243 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5244 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5245 break;
5246 default:
5247 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5248 }
5249 tcg_temp_free(temp);
5250 tcg_temp_free(temp2);
5251 }
5252
5253 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
5254 DisasContext *ctx)
5255 {
5256 uint32_t op2;
5257 uint32_t off10;
5258 int r1, r2;
5259
5260 TCGv temp, temp2, temp3;
5261
5262 r1 = MASK_OP_BO_S1D(ctx->opcode);
5263 r2 = MASK_OP_BO_S2(ctx->opcode);
5264 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5265 op2 = MASK_OP_BO_OP2(ctx->opcode);
5266
5267 temp = tcg_temp_new();
5268 temp2 = tcg_temp_new();
5269 temp3 = tcg_const_i32(off10);
5270 CHECK_REG_PAIR(r2);
5271 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5272 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5273
5274 switch (op2) {
5275 case OPC2_32_BO_LDMST_BR:
5276 gen_ldmst(ctx, r1, temp2);
5277 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5278 break;
5279 case OPC2_32_BO_LDMST_CIRC:
5280 gen_ldmst(ctx, r1, temp2);
5281 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5282 break;
5283 case OPC2_32_BO_SWAP_W_BR:
5284 gen_swap(ctx, r1, temp2);
5285 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5286 break;
5287 case OPC2_32_BO_SWAP_W_CIRC:
5288 gen_swap(ctx, r1, temp2);
5289 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5290 break;
5291 case OPC2_32_BO_CMPSWAP_W_BR:
5292 gen_cmpswap(ctx, r1, temp2);
5293 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5294 break;
5295 case OPC2_32_BO_CMPSWAP_W_CIRC:
5296 gen_cmpswap(ctx, r1, temp2);
5297 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5298 break;
5299 case OPC2_32_BO_SWAPMSK_W_BR:
5300 gen_swapmsk(ctx, r1, temp2);
5301 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5302 break;
5303 case OPC2_32_BO_SWAPMSK_W_CIRC:
5304 gen_swapmsk(ctx, r1, temp2);
5305 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5306 break;
5307 default:
5308 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5309 }
5310
5311 tcg_temp_free(temp);
5312 tcg_temp_free(temp2);
5313 tcg_temp_free(temp3);
5314 }
5315
5316 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
5317 {
5318 int r1, r2;
5319 int32_t address;
5320 TCGv temp;
5321
5322 r1 = MASK_OP_BOL_S1D(ctx->opcode);
5323 r2 = MASK_OP_BOL_S2(ctx->opcode);
5324 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
5325
5326 switch (op1) {
5327 case OPC1_32_BOL_LD_A_LONGOFF:
5328 temp = tcg_temp_new();
5329 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5330 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
5331 tcg_temp_free(temp);
5332 break;
5333 case OPC1_32_BOL_LD_W_LONGOFF:
5334 temp = tcg_temp_new();
5335 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5336 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
5337 tcg_temp_free(temp);
5338 break;
5339 case OPC1_32_BOL_LEA_LONGOFF:
5340 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
5341 break;
5342 case OPC1_32_BOL_ST_A_LONGOFF:
5343 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5344 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
5345 } else {
5346 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5347 }
5348 break;
5349 case OPC1_32_BOL_ST_W_LONGOFF:
5350 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
5351 break;
5352 case OPC1_32_BOL_LD_B_LONGOFF:
5353 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5354 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5355 } else {
5356 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5357 }
5358 break;
5359 case OPC1_32_BOL_LD_BU_LONGOFF:
5360 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5361 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
5362 } else {
5363 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5364 }
5365 break;
5366 case OPC1_32_BOL_LD_H_LONGOFF:
5367 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5368 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5369 } else {
5370 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5371 }
5372 break;
5373 case OPC1_32_BOL_LD_HU_LONGOFF:
5374 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5375 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
5376 } else {
5377 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5378 }
5379 break;
5380 case OPC1_32_BOL_ST_B_LONGOFF:
5381 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5382 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5383 } else {
5384 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5385 }
5386 break;
5387 case OPC1_32_BOL_ST_H_LONGOFF:
5388 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5389 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5390 } else {
5391 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5392 }
5393 break;
5394 default:
5395 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5396 }
5397 }
5398
5399 /* RC format */
5400 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5401 {
5402 uint32_t op2;
5403 int r1, r2;
5404 int32_t const9;
5405 TCGv temp;
5406
5407 r2 = MASK_OP_RC_D(ctx->opcode);
5408 r1 = MASK_OP_RC_S1(ctx->opcode);
5409 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5410 op2 = MASK_OP_RC_OP2(ctx->opcode);
5411
5412 temp = tcg_temp_new();
5413
5414 switch (op2) {
5415 case OPC2_32_RC_AND:
5416 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5417 break;
5418 case OPC2_32_RC_ANDN:
5419 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5420 break;
5421 case OPC2_32_RC_NAND:
5422 tcg_gen_movi_tl(temp, const9);
5423 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5424 break;
5425 case OPC2_32_RC_NOR:
5426 tcg_gen_movi_tl(temp, const9);
5427 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5428 break;
5429 case OPC2_32_RC_OR:
5430 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5431 break;
5432 case OPC2_32_RC_ORN:
5433 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5434 break;
5435 case OPC2_32_RC_SH:
5436 const9 = sextract32(const9, 0, 6);
5437 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5438 break;
5439 case OPC2_32_RC_SH_H:
5440 const9 = sextract32(const9, 0, 5);
5441 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5442 break;
5443 case OPC2_32_RC_SHA:
5444 const9 = sextract32(const9, 0, 6);
5445 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5446 break;
5447 case OPC2_32_RC_SHA_H:
5448 const9 = sextract32(const9, 0, 5);
5449 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5450 break;
5451 case OPC2_32_RC_SHAS:
5452 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5453 break;
5454 case OPC2_32_RC_XNOR:
5455 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5456 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5457 break;
5458 case OPC2_32_RC_XOR:
5459 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5460 break;
5461 default:
5462 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5463 }
5464 tcg_temp_free(temp);
5465 }
5466
5467 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5468 {
5469 uint32_t op2;
5470 int r1, r2;
5471 int16_t const9;
5472
5473 TCGv temp;
5474
5475 r2 = MASK_OP_RC_D(ctx->opcode);
5476 r1 = MASK_OP_RC_S1(ctx->opcode);
5477 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5478
5479 op2 = MASK_OP_RC_OP2(ctx->opcode);
5480
5481 temp = tcg_temp_new();
5482
5483 switch (op2) {
5484 case OPC2_32_RC_ABSDIF:
5485 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5486 break;
5487 case OPC2_32_RC_ABSDIFS:
5488 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5489 break;
5490 case OPC2_32_RC_ADD:
5491 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5492 break;
5493 case OPC2_32_RC_ADDC:
5494 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5495 break;
5496 case OPC2_32_RC_ADDS:
5497 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5498 break;
5499 case OPC2_32_RC_ADDS_U:
5500 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5501 break;
5502 case OPC2_32_RC_ADDX:
5503 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5504 break;
5505 case OPC2_32_RC_AND_EQ:
5506 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5507 const9, &tcg_gen_and_tl);
5508 break;
5509 case OPC2_32_RC_AND_GE:
5510 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5511 const9, &tcg_gen_and_tl);
5512 break;
5513 case OPC2_32_RC_AND_GE_U:
5514 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5515 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5516 const9, &tcg_gen_and_tl);
5517 break;
5518 case OPC2_32_RC_AND_LT:
5519 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5520 const9, &tcg_gen_and_tl);
5521 break;
5522 case OPC2_32_RC_AND_LT_U:
5523 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5524 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5525 const9, &tcg_gen_and_tl);
5526 break;
5527 case OPC2_32_RC_AND_NE:
5528 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5529 const9, &tcg_gen_and_tl);
5530 break;
5531 case OPC2_32_RC_EQ:
5532 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5533 break;
5534 case OPC2_32_RC_EQANY_B:
5535 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5536 break;
5537 case OPC2_32_RC_EQANY_H:
5538 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5539 break;
5540 case OPC2_32_RC_GE:
5541 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5542 break;
5543 case OPC2_32_RC_GE_U:
5544 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5545 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5546 break;
5547 case OPC2_32_RC_LT:
5548 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5549 break;
5550 case OPC2_32_RC_LT_U:
5551 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5552 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5553 break;
5554 case OPC2_32_RC_MAX:
5555 tcg_gen_movi_tl(temp, const9);
5556 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5557 cpu_gpr_d[r1], temp);
5558 break;
5559 case OPC2_32_RC_MAX_U:
5560 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5561 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5562 cpu_gpr_d[r1], temp);
5563 break;
5564 case OPC2_32_RC_MIN:
5565 tcg_gen_movi_tl(temp, const9);
5566 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5567 cpu_gpr_d[r1], temp);
5568 break;
5569 case OPC2_32_RC_MIN_U:
5570 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5571 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5572 cpu_gpr_d[r1], temp);
5573 break;
5574 case OPC2_32_RC_NE:
5575 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5576 break;
5577 case OPC2_32_RC_OR_EQ:
5578 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5579 const9, &tcg_gen_or_tl);
5580 break;
5581 case OPC2_32_RC_OR_GE:
5582 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5583 const9, &tcg_gen_or_tl);
5584 break;
5585 case OPC2_32_RC_OR_GE_U:
5586 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5587 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5588 const9, &tcg_gen_or_tl);
5589 break;
5590 case OPC2_32_RC_OR_LT:
5591 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5592 const9, &tcg_gen_or_tl);
5593 break;
5594 case OPC2_32_RC_OR_LT_U:
5595 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5596 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5597 const9, &tcg_gen_or_tl);
5598 break;
5599 case OPC2_32_RC_OR_NE:
5600 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5601 const9, &tcg_gen_or_tl);
5602 break;
5603 case OPC2_32_RC_RSUB:
5604 tcg_gen_movi_tl(temp, const9);
5605 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5606 break;
5607 case OPC2_32_RC_RSUBS:
5608 tcg_gen_movi_tl(temp, const9);
5609 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5610 break;
5611 case OPC2_32_RC_RSUBS_U:
5612 tcg_gen_movi_tl(temp, const9);
5613 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5614 break;
5615 case OPC2_32_RC_SH_EQ:
5616 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5617 break;
5618 case OPC2_32_RC_SH_GE:
5619 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5620 break;
5621 case OPC2_32_RC_SH_GE_U:
5622 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5623 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5624 break;
5625 case OPC2_32_RC_SH_LT:
5626 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5627 break;
5628 case OPC2_32_RC_SH_LT_U:
5629 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5630 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5631 break;
5632 case OPC2_32_RC_SH_NE:
5633 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5634 break;
5635 case OPC2_32_RC_XOR_EQ:
5636 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5637 const9, &tcg_gen_xor_tl);
5638 break;
5639 case OPC2_32_RC_XOR_GE:
5640 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5641 const9, &tcg_gen_xor_tl);
5642 break;
5643 case OPC2_32_RC_XOR_GE_U:
5644 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5645 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5646 const9, &tcg_gen_xor_tl);
5647 break;
5648 case OPC2_32_RC_XOR_LT:
5649 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5650 const9, &tcg_gen_xor_tl);
5651 break;
5652 case OPC2_32_RC_XOR_LT_U:
5653 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5654 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5655 const9, &tcg_gen_xor_tl);
5656 break;
5657 case OPC2_32_RC_XOR_NE:
5658 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5659 const9, &tcg_gen_xor_tl);
5660 break;
5661 default:
5662 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5663 }
5664 tcg_temp_free(temp);
5665 }
5666
5667 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
5668 {
5669 uint32_t op2;
5670 uint32_t const9;
5671
5672 op2 = MASK_OP_RC_OP2(ctx->opcode);
5673 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5674
5675 switch (op2) {
5676 case OPC2_32_RC_BISR:
5677 gen_helper_1arg(bisr, const9);
5678 break;
5679 case OPC2_32_RC_SYSCALL:
5680 /* TODO: Add exception generation */
5681 break;
5682 default:
5683 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5684 }
5685 }
5686
5687 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
5688 {
5689 uint32_t op2;
5690 int r1, r2;
5691 int16_t const9;
5692
5693 r2 = MASK_OP_RC_D(ctx->opcode);
5694 r1 = MASK_OP_RC_S1(ctx->opcode);
5695 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5696
5697 op2 = MASK_OP_RC_OP2(ctx->opcode);
5698
5699 switch (op2) {
5700 case OPC2_32_RC_MUL_32:
5701 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5702 break;
5703 case OPC2_32_RC_MUL_64:
5704 CHECK_REG_PAIR(r2);
5705 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5706 break;
5707 case OPC2_32_RC_MULS_32:
5708 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5709 break;
5710 case OPC2_32_RC_MUL_U_64:
5711 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5712 CHECK_REG_PAIR(r2);
5713 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5714 break;
5715 case OPC2_32_RC_MULS_U_32:
5716 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5717 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5718 break;
5719 default:
5720 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5721 }
5722 }
5723
5724 /* RCPW format */
5725 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
5726 {
5727 uint32_t op2;
5728 int r1, r2;
5729 int32_t pos, width, const4;
5730
5731 TCGv temp;
5732
5733 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5734 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5735 r2 = MASK_OP_RCPW_D(ctx->opcode);
5736 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5737 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5738 pos = MASK_OP_RCPW_POS(ctx->opcode);
5739
5740 switch (op2) {
5741 case OPC2_32_RCPW_IMASK:
5742 CHECK_REG_PAIR(r2);
5743 /* if pos + width > 31 undefined result */
5744 if (pos + width <= 31) {
5745 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5746 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5747 }
5748 break;
5749 case OPC2_32_RCPW_INSERT:
5750 /* if pos + width > 32 undefined result */
5751 if (pos + width <= 32) {
5752 temp = tcg_const_i32(const4);
5753 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5754 tcg_temp_free(temp);
5755 }
5756 break;
5757 default:
5758 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5759 }
5760 }
5761
5762 /* RCRW format */
5763
5764 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
5765 {
5766 uint32_t op2;
5767 int r1, r3, r4;
5768 int32_t width, const4;
5769
5770 TCGv temp, temp2, temp3;
5771
5772 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5773 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5774 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5775 r4 = MASK_OP_RCRW_D(ctx->opcode);
5776 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5777 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5778
5779 temp = tcg_temp_new();
5780 temp2 = tcg_temp_new();
5781
5782 switch (op2) {
5783 case OPC2_32_RCRW_IMASK:
5784 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
5785 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5786 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
5787 tcg_gen_movi_tl(temp2, const4);
5788 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
5789 break;
5790 case OPC2_32_RCRW_INSERT:
5791 temp3 = tcg_temp_new();
5792
5793 tcg_gen_movi_tl(temp, width);
5794 tcg_gen_movi_tl(temp2, const4);
5795 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
5796 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
5797
5798 tcg_temp_free(temp3);
5799 break;
5800 default:
5801 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5802 }
5803 tcg_temp_free(temp);
5804 tcg_temp_free(temp2);
5805 }
5806
5807 /* RCR format */
5808
5809 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5810 {
5811 uint32_t op2;
5812 int r1, r3, r4;
5813 int32_t const9;
5814
5815 TCGv temp, temp2;
5816
5817 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5818 r1 = MASK_OP_RCR_S1(ctx->opcode);
5819 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5820 r3 = MASK_OP_RCR_S3(ctx->opcode);
5821 r4 = MASK_OP_RCR_D(ctx->opcode);
5822
5823 switch (op2) {
5824 case OPC2_32_RCR_CADD:
5825 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5826 cpu_gpr_d[r4]);
5827 break;
5828 case OPC2_32_RCR_CADDN:
5829 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5830 cpu_gpr_d[r4]);
5831 break;
5832 case OPC2_32_RCR_SEL:
5833 temp = tcg_const_i32(0);
5834 temp2 = tcg_const_i32(const9);
5835 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5836 cpu_gpr_d[r1], temp2);
5837 tcg_temp_free(temp);
5838 tcg_temp_free(temp2);
5839 break;
5840 case OPC2_32_RCR_SELN:
5841 temp = tcg_const_i32(0);
5842 temp2 = tcg_const_i32(const9);
5843 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5844 cpu_gpr_d[r1], temp2);
5845 tcg_temp_free(temp);
5846 tcg_temp_free(temp2);
5847 break;
5848 default:
5849 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5850 }
5851 }
5852
5853 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
5854 {
5855 uint32_t op2;
5856 int r1, r3, r4;
5857 int32_t const9;
5858
5859
5860 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5861 r1 = MASK_OP_RCR_S1(ctx->opcode);
5862 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5863 r3 = MASK_OP_RCR_S3(ctx->opcode);
5864 r4 = MASK_OP_RCR_D(ctx->opcode);
5865
5866 switch (op2) {
5867 case OPC2_32_RCR_MADD_32:
5868 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5869 break;
5870 case OPC2_32_RCR_MADD_64:
5871 CHECK_REG_PAIR(r4);
5872 CHECK_REG_PAIR(r3);
5873 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5874 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5875 break;
5876 case OPC2_32_RCR_MADDS_32:
5877 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5878 break;
5879 case OPC2_32_RCR_MADDS_64:
5880 CHECK_REG_PAIR(r4);
5881 CHECK_REG_PAIR(r3);
5882 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5883 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5884 break;
5885 case OPC2_32_RCR_MADD_U_64:
5886 CHECK_REG_PAIR(r4);
5887 CHECK_REG_PAIR(r3);
5888 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5889 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5890 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5891 break;
5892 case OPC2_32_RCR_MADDS_U_32:
5893 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5894 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5895 break;
5896 case OPC2_32_RCR_MADDS_U_64:
5897 CHECK_REG_PAIR(r4);
5898 CHECK_REG_PAIR(r3);
5899 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5900 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5901 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5902 break;
5903 default:
5904 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5905 }
5906 }
5907
5908 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
5909 {
5910 uint32_t op2;
5911 int r1, r3, r4;
5912 int32_t const9;
5913
5914
5915 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5916 r1 = MASK_OP_RCR_S1(ctx->opcode);
5917 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5918 r3 = MASK_OP_RCR_S3(ctx->opcode);
5919 r4 = MASK_OP_RCR_D(ctx->opcode);
5920
5921 switch (op2) {
5922 case OPC2_32_RCR_MSUB_32:
5923 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5924 break;
5925 case OPC2_32_RCR_MSUB_64:
5926 CHECK_REG_PAIR(r4);
5927 CHECK_REG_PAIR(r3);
5928 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5929 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5930 break;
5931 case OPC2_32_RCR_MSUBS_32:
5932 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5933 break;
5934 case OPC2_32_RCR_MSUBS_64:
5935 CHECK_REG_PAIR(r4);
5936 CHECK_REG_PAIR(r3);
5937 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5938 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5939 break;
5940 case OPC2_32_RCR_MSUB_U_64:
5941 CHECK_REG_PAIR(r4);
5942 CHECK_REG_PAIR(r3);
5943 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5944 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5945 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5946 break;
5947 case OPC2_32_RCR_MSUBS_U_32:
5948 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5949 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5950 break;
5951 case OPC2_32_RCR_MSUBS_U_64:
5952 CHECK_REG_PAIR(r4);
5953 CHECK_REG_PAIR(r3);
5954 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5955 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5956 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5957 break;
5958 default:
5959 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5960 }
5961 }
5962
5963 /* RLC format */
5964
5965 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
5966 uint32_t op1)
5967 {
5968 int32_t const16;
5969 int r1, r2;
5970
5971 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5972 r1 = MASK_OP_RLC_S1(ctx->opcode);
5973 r2 = MASK_OP_RLC_D(ctx->opcode);
5974
5975 switch (op1) {
5976 case OPC1_32_RLC_ADDI:
5977 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5978 break;
5979 case OPC1_32_RLC_ADDIH:
5980 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5981 break;
5982 case OPC1_32_RLC_ADDIH_A:
5983 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5984 break;
5985 case OPC1_32_RLC_MFCR:
5986 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5987 gen_mfcr(env, cpu_gpr_d[r2], const16);
5988 break;
5989 case OPC1_32_RLC_MOV:
5990 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5991 break;
5992 case OPC1_32_RLC_MOV_64:
5993 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5994 CHECK_REG_PAIR(r2);
5995 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5996 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5997 } else {
5998 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5999 }
6000 break;
6001 case OPC1_32_RLC_MOV_U:
6002 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
6003 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
6004 break;
6005 case OPC1_32_RLC_MOV_H:
6006 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
6007 break;
6008 case OPC1_32_RLC_MOVH_A:
6009 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
6010 break;
6011 case OPC1_32_RLC_MTCR:
6012 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
6013 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
6014 break;
6015 default:
6016 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6017 }
6018 }
6019
6020 /* RR format */
6021 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
6022 {
6023 uint32_t op2;
6024 int r3, r2, r1;
6025
6026 r3 = MASK_OP_RR_D(ctx->opcode);
6027 r2 = MASK_OP_RR_S2(ctx->opcode);
6028 r1 = MASK_OP_RR_S1(ctx->opcode);
6029 op2 = MASK_OP_RR_OP2(ctx->opcode);
6030
6031 switch (op2) {
6032 case OPC2_32_RR_ABS:
6033 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6034 break;
6035 case OPC2_32_RR_ABS_B:
6036 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6037 break;
6038 case OPC2_32_RR_ABS_H:
6039 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6040 break;
6041 case OPC2_32_RR_ABSDIF:
6042 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6043 break;
6044 case OPC2_32_RR_ABSDIF_B:
6045 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6046 cpu_gpr_d[r2]);
6047 break;
6048 case OPC2_32_RR_ABSDIF_H:
6049 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6050 cpu_gpr_d[r2]);
6051 break;
6052 case OPC2_32_RR_ABSDIFS:
6053 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6054 cpu_gpr_d[r2]);
6055 break;
6056 case OPC2_32_RR_ABSDIFS_H:
6057 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6058 cpu_gpr_d[r2]);
6059 break;
6060 case OPC2_32_RR_ABSS:
6061 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6062 break;
6063 case OPC2_32_RR_ABSS_H:
6064 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
6065 break;
6066 case OPC2_32_RR_ADD:
6067 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6068 break;
6069 case OPC2_32_RR_ADD_B:
6070 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6071 break;
6072 case OPC2_32_RR_ADD_H:
6073 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6074 break;
6075 case OPC2_32_RR_ADDC:
6076 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6077 break;
6078 case OPC2_32_RR_ADDS:
6079 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6080 break;
6081 case OPC2_32_RR_ADDS_H:
6082 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6083 cpu_gpr_d[r2]);
6084 break;
6085 case OPC2_32_RR_ADDS_HU:
6086 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6087 cpu_gpr_d[r2]);
6088 break;
6089 case OPC2_32_RR_ADDS_U:
6090 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6091 cpu_gpr_d[r2]);
6092 break;
6093 case OPC2_32_RR_ADDX:
6094 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6095 break;
6096 case OPC2_32_RR_AND_EQ:
6097 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6098 cpu_gpr_d[r2], &tcg_gen_and_tl);
6099 break;
6100 case OPC2_32_RR_AND_GE:
6101 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6102 cpu_gpr_d[r2], &tcg_gen_and_tl);
6103 break;
6104 case OPC2_32_RR_AND_GE_U:
6105 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6106 cpu_gpr_d[r2], &tcg_gen_and_tl);
6107 break;
6108 case OPC2_32_RR_AND_LT:
6109 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6110 cpu_gpr_d[r2], &tcg_gen_and_tl);
6111 break;
6112 case OPC2_32_RR_AND_LT_U:
6113 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6114 cpu_gpr_d[r2], &tcg_gen_and_tl);
6115 break;
6116 case OPC2_32_RR_AND_NE:
6117 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6118 cpu_gpr_d[r2], &tcg_gen_and_tl);
6119 break;
6120 case OPC2_32_RR_EQ:
6121 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6122 cpu_gpr_d[r2]);
6123 break;
6124 case OPC2_32_RR_EQ_B:
6125 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6126 break;
6127 case OPC2_32_RR_EQ_H:
6128 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6129 break;
6130 case OPC2_32_RR_EQ_W:
6131 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6132 break;
6133 case OPC2_32_RR_EQANY_B:
6134 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6135 break;
6136 case OPC2_32_RR_EQANY_H:
6137 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6138 break;
6139 case OPC2_32_RR_GE:
6140 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6141 cpu_gpr_d[r2]);
6142 break;
6143 case OPC2_32_RR_GE_U:
6144 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6145 cpu_gpr_d[r2]);
6146 break;
6147 case OPC2_32_RR_LT:
6148 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6149 cpu_gpr_d[r2]);
6150 break;
6151 case OPC2_32_RR_LT_U:
6152 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6153 cpu_gpr_d[r2]);
6154 break;
6155 case OPC2_32_RR_LT_B:
6156 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6157 break;
6158 case OPC2_32_RR_LT_BU:
6159 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6160 break;
6161 case OPC2_32_RR_LT_H:
6162 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6163 break;
6164 case OPC2_32_RR_LT_HU:
6165 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6166 break;
6167 case OPC2_32_RR_LT_W:
6168 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6169 break;
6170 case OPC2_32_RR_LT_WU:
6171 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6172 break;
6173 case OPC2_32_RR_MAX:
6174 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6175 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6176 break;
6177 case OPC2_32_RR_MAX_U:
6178 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6179 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6180 break;
6181 case OPC2_32_RR_MAX_B:
6182 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6183 break;
6184 case OPC2_32_RR_MAX_BU:
6185 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6186 break;
6187 case OPC2_32_RR_MAX_H:
6188 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6189 break;
6190 case OPC2_32_RR_MAX_HU:
6191 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6192 break;
6193 case OPC2_32_RR_MIN:
6194 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6195 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6196 break;
6197 case OPC2_32_RR_MIN_U:
6198 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6199 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6200 break;
6201 case OPC2_32_RR_MIN_B:
6202 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6203 break;
6204 case OPC2_32_RR_MIN_BU:
6205 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6206 break;
6207 case OPC2_32_RR_MIN_H:
6208 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6209 break;
6210 case OPC2_32_RR_MIN_HU:
6211 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6212 break;
6213 case OPC2_32_RR_MOV:
6214 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6215 break;
6216 case OPC2_32_RR_NE:
6217 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6218 cpu_gpr_d[r2]);
6219 break;
6220 case OPC2_32_RR_OR_EQ:
6221 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6222 cpu_gpr_d[r2], &tcg_gen_or_tl);
6223 break;
6224 case OPC2_32_RR_OR_GE:
6225 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6226 cpu_gpr_d[r2], &tcg_gen_or_tl);
6227 break;
6228 case OPC2_32_RR_OR_GE_U:
6229 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6230 cpu_gpr_d[r2], &tcg_gen_or_tl);
6231 break;
6232 case OPC2_32_RR_OR_LT:
6233 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6234 cpu_gpr_d[r2], &tcg_gen_or_tl);
6235 break;
6236 case OPC2_32_RR_OR_LT_U:
6237 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6238 cpu_gpr_d[r2], &tcg_gen_or_tl);
6239 break;
6240 case OPC2_32_RR_OR_NE:
6241 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6242 cpu_gpr_d[r2], &tcg_gen_or_tl);
6243 break;
6244 case OPC2_32_RR_SAT_B:
6245 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
6246 break;
6247 case OPC2_32_RR_SAT_BU:
6248 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
6249 break;
6250 case OPC2_32_RR_SAT_H:
6251 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
6252 break;
6253 case OPC2_32_RR_SAT_HU:
6254 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
6255 break;
6256 case OPC2_32_RR_SH_EQ:
6257 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6258 cpu_gpr_d[r2]);
6259 break;
6260 case OPC2_32_RR_SH_GE:
6261 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6262 cpu_gpr_d[r2]);
6263 break;
6264 case OPC2_32_RR_SH_GE_U:
6265 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6266 cpu_gpr_d[r2]);
6267 break;
6268 case OPC2_32_RR_SH_LT:
6269 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6270 cpu_gpr_d[r2]);
6271 break;
6272 case OPC2_32_RR_SH_LT_U:
6273 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6274 cpu_gpr_d[r2]);
6275 break;
6276 case OPC2_32_RR_SH_NE:
6277 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6278 cpu_gpr_d[r2]);
6279 break;
6280 case OPC2_32_RR_SUB:
6281 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6282 break;
6283 case OPC2_32_RR_SUB_B:
6284 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6285 break;
6286 case OPC2_32_RR_SUB_H:
6287 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6288 break;
6289 case OPC2_32_RR_SUBC:
6290 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6291 break;
6292 case OPC2_32_RR_SUBS:
6293 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6294 break;
6295 case OPC2_32_RR_SUBS_U:
6296 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6297 break;
6298 case OPC2_32_RR_SUBS_H:
6299 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6300 cpu_gpr_d[r2]);
6301 break;
6302 case OPC2_32_RR_SUBS_HU:
6303 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6304 cpu_gpr_d[r2]);
6305 break;
6306 case OPC2_32_RR_SUBX:
6307 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6308 break;
6309 case OPC2_32_RR_XOR_EQ:
6310 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6311 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6312 break;
6313 case OPC2_32_RR_XOR_GE:
6314 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6315 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6316 break;
6317 case OPC2_32_RR_XOR_GE_U:
6318 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6319 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6320 break;
6321 case OPC2_32_RR_XOR_LT:
6322 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6323 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6324 break;
6325 case OPC2_32_RR_XOR_LT_U:
6326 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6327 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6328 break;
6329 case OPC2_32_RR_XOR_NE:
6330 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6331 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6332 break;
6333 default:
6334 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6335 }
6336 }
6337
6338 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
6339 {
6340 uint32_t op2;
6341 int r3, r2, r1;
6342 TCGv temp;
6343
6344 r3 = MASK_OP_RR_D(ctx->opcode);
6345 r2 = MASK_OP_RR_S2(ctx->opcode);
6346 r1 = MASK_OP_RR_S1(ctx->opcode);
6347
6348 temp = tcg_temp_new();
6349 op2 = MASK_OP_RR_OP2(ctx->opcode);
6350
6351 switch (op2) {
6352 case OPC2_32_RR_AND:
6353 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6354 break;
6355 case OPC2_32_RR_ANDN:
6356 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6357 break;
6358 case OPC2_32_RR_CLO:
6359 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6360 break;
6361 case OPC2_32_RR_CLO_H:
6362 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6363 break;
6364 case OPC2_32_RR_CLS:
6365 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6366 break;
6367 case OPC2_32_RR_CLS_H:
6368 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6369 break;
6370 case OPC2_32_RR_CLZ:
6371 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6372 break;
6373 case OPC2_32_RR_CLZ_H:
6374 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6375 break;
6376 case OPC2_32_RR_NAND:
6377 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6378 break;
6379 case OPC2_32_RR_NOR:
6380 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6381 break;
6382 case OPC2_32_RR_OR:
6383 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6384 break;
6385 case OPC2_32_RR_ORN:
6386 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6387 break;
6388 case OPC2_32_RR_SH:
6389 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6390 break;
6391 case OPC2_32_RR_SH_H:
6392 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6393 break;
6394 case OPC2_32_RR_SHA:
6395 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6396 break;
6397 case OPC2_32_RR_SHA_H:
6398 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6399 break;
6400 case OPC2_32_RR_SHAS:
6401 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6402 break;
6403 case OPC2_32_RR_XNOR:
6404 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6405 break;
6406 case OPC2_32_RR_XOR:
6407 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6408 break;
6409 default:
6410 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6411 }
6412 tcg_temp_free(temp);
6413 }
6414
6415 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
6416 {
6417 uint32_t op2, n;
6418 int r1, r2, r3;
6419 TCGv temp;
6420
6421 op2 = MASK_OP_RR_OP2(ctx->opcode);
6422 r3 = MASK_OP_RR_D(ctx->opcode);
6423 r2 = MASK_OP_RR_S2(ctx->opcode);
6424 r1 = MASK_OP_RR_S1(ctx->opcode);
6425 n = MASK_OP_RR_N(ctx->opcode);
6426
6427 switch (op2) {
6428 case OPC2_32_RR_ADD_A:
6429 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6430 break;
6431 case OPC2_32_RR_ADDSC_A:
6432 temp = tcg_temp_new();
6433 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6434 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6435 tcg_temp_free(temp);
6436 break;
6437 case OPC2_32_RR_ADDSC_AT:
6438 temp = tcg_temp_new();
6439 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6440 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6441 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6442 tcg_temp_free(temp);
6443 break;
6444 case OPC2_32_RR_EQ_A:
6445 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6446 cpu_gpr_a[r2]);
6447 break;
6448 case OPC2_32_RR_EQZ:
6449 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6450 break;
6451 case OPC2_32_RR_GE_A:
6452 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6453 cpu_gpr_a[r2]);
6454 break;
6455 case OPC2_32_RR_LT_A:
6456 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6457 cpu_gpr_a[r2]);
6458 break;
6459 case OPC2_32_RR_MOV_A:
6460 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6461 break;
6462 case OPC2_32_RR_MOV_AA:
6463 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6464 break;
6465 case OPC2_32_RR_MOV_D:
6466 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6467 break;
6468 case OPC2_32_RR_NE_A:
6469 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6470 cpu_gpr_a[r2]);
6471 break;
6472 case OPC2_32_RR_NEZ_A:
6473 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6474 break;
6475 case OPC2_32_RR_SUB_A:
6476 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6477 break;
6478 default:
6479 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6480 }
6481 }
6482
6483 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
6484 {
6485 uint32_t op2;
6486 int r1;
6487
6488 op2 = MASK_OP_RR_OP2(ctx->opcode);
6489 r1 = MASK_OP_RR_S1(ctx->opcode);
6490
6491 switch (op2) {
6492 case OPC2_32_RR_JI:
6493 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6494 break;
6495 case OPC2_32_RR_JLI:
6496 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
6497 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6498 break;
6499 case OPC2_32_RR_CALLI:
6500 gen_helper_1arg(call, ctx->next_pc);
6501 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6502 break;
6503 case OPC2_32_RR_FCALLI:
6504 gen_fcall_save_ctx(ctx);
6505 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6506 break;
6507 default:
6508 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6509 }
6510 tcg_gen_exit_tb(0);
6511 ctx->bstate = BS_BRANCH;
6512 }
6513
6514 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
6515 {
6516 uint32_t op2;
6517 int r1, r2, r3;
6518
6519 TCGv temp, temp2, temp3;
6520
6521 op2 = MASK_OP_RR_OP2(ctx->opcode);
6522 r3 = MASK_OP_RR_D(ctx->opcode);
6523 r2 = MASK_OP_RR_S2(ctx->opcode);
6524 r1 = MASK_OP_RR_S1(ctx->opcode);
6525
6526 switch (op2) {
6527 case OPC2_32_RR_BMERGE:
6528 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6529 break;
6530 case OPC2_32_RR_BSPLIT:
6531 CHECK_REG_PAIR(r3);
6532 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6533 break;
6534 case OPC2_32_RR_DVINIT_B:
6535 CHECK_REG_PAIR(r3);
6536 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6537 cpu_gpr_d[r2]);
6538 break;
6539 case OPC2_32_RR_DVINIT_BU:
6540 temp = tcg_temp_new();
6541 temp2 = tcg_temp_new();
6542 temp3 = tcg_temp_new();
6543 CHECK_REG_PAIR(r3);
6544 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6545 /* reset av */
6546 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6547 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6548 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6549 tcg_gen_neg_tl(temp, temp3);
6550 /* use cpu_PSW_AV to compare against 0 */
6551 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6552 temp, temp3);
6553 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6554 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6555 temp2, cpu_gpr_d[r2]);
6556 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6557 } else {
6558 /* overflow = (D[b] == 0) */
6559 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6560 }
6561 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6562 /* sv */
6563 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6564 /* write result */
6565 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6566 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6567
6568 tcg_temp_free(temp);
6569 tcg_temp_free(temp2);
6570 tcg_temp_free(temp3);
6571 break;
6572 case OPC2_32_RR_DVINIT_H:
6573 CHECK_REG_PAIR(r3);
6574 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6575 cpu_gpr_d[r2]);
6576 break;
6577 case OPC2_32_RR_DVINIT_HU:
6578 temp = tcg_temp_new();
6579 temp2 = tcg_temp_new();
6580 temp3 = tcg_temp_new();
6581 CHECK_REG_PAIR(r3);
6582 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6583 /* reset av */
6584 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6585 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6586 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6587 tcg_gen_neg_tl(temp, temp3);
6588 /* use cpu_PSW_AV to compare against 0 */
6589 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6590 temp, temp3);
6591 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6592 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6593 temp2, cpu_gpr_d[r2]);
6594 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6595 } else {
6596 /* overflow = (D[b] == 0) */
6597 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6598 }
6599 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6600 /* sv */
6601 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6602 /* write result */
6603 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6604 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6605 tcg_temp_free(temp);
6606 tcg_temp_free(temp2);
6607 tcg_temp_free(temp3);
6608 break;
6609 case OPC2_32_RR_DVINIT:
6610 temp = tcg_temp_new();
6611 temp2 = tcg_temp_new();
6612 CHECK_REG_PAIR(r3);
6613 /* overflow = ((D[b] == 0) ||
6614 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6615 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6616 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6617 tcg_gen_and_tl(temp, temp, temp2);
6618 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6619 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6620 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6621 /* sv */
6622 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6623 /* reset av */
6624 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6625 /* write result */
6626 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6627 /* sign extend to high reg */
6628 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6629 tcg_temp_free(temp);
6630 tcg_temp_free(temp2);
6631 break;
6632 case OPC2_32_RR_DVINIT_U:
6633 /* overflow = (D[b] == 0) */
6634 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6635 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6636 /* sv */
6637 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6638 /* reset av */
6639 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6640 /* write result */
6641 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6642 /* zero extend to high reg*/
6643 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6644 break;
6645 case OPC2_32_RR_PARITY:
6646 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6647 break;
6648 case OPC2_32_RR_UNPACK:
6649 CHECK_REG_PAIR(r3);
6650 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6651 break;
6652 case OPC2_32_RR_CRC32:
6653 if (tricore_feature(env, TRICORE_FEATURE_161)) {
6654 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6655 } else {
6656 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6657 }
6658 break;
6659 case OPC2_32_RR_DIV:
6660 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6661 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6662 cpu_gpr_d[r2]);
6663 } else {
6664 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6665 }
6666 break;
6667 case OPC2_32_RR_DIV_U:
6668 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6669 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6670 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6671 } else {
6672 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6673 }
6674 break;
6675 default:
6676 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6677 }
6678 }
6679
6680 /* RR1 Format */
6681 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
6682 {
6683 uint32_t op2;
6684
6685 int r1, r2, r3;
6686 TCGv n;
6687 TCGv_i64 temp64;
6688
6689 r1 = MASK_OP_RR1_S1(ctx->opcode);
6690 r2 = MASK_OP_RR1_S2(ctx->opcode);
6691 r3 = MASK_OP_RR1_D(ctx->opcode);
6692 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6693 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6694
6695 switch (op2) {
6696 case OPC2_32_RR1_MUL_H_32_LL:
6697 temp64 = tcg_temp_new_i64();
6698 CHECK_REG_PAIR(r3);
6699 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6700 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6701 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6702 tcg_temp_free_i64(temp64);
6703 break;
6704 case OPC2_32_RR1_MUL_H_32_LU:
6705 temp64 = tcg_temp_new_i64();
6706 CHECK_REG_PAIR(r3);
6707 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6708 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6709 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6710 tcg_temp_free_i64(temp64);
6711 break;
6712 case OPC2_32_RR1_MUL_H_32_UL:
6713 temp64 = tcg_temp_new_i64();
6714 CHECK_REG_PAIR(r3);
6715 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6716 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6717 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6718 tcg_temp_free_i64(temp64);
6719 break;
6720 case OPC2_32_RR1_MUL_H_32_UU:
6721 temp64 = tcg_temp_new_i64();
6722 CHECK_REG_PAIR(r3);
6723 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6724 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6725 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6726 tcg_temp_free_i64(temp64);
6727 break;
6728 case OPC2_32_RR1_MULM_H_64_LL:
6729 temp64 = tcg_temp_new_i64();
6730 CHECK_REG_PAIR(r3);
6731 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6732 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6733 /* reset V bit */
6734 tcg_gen_movi_tl(cpu_PSW_V, 0);
6735 /* reset AV bit */
6736 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6737 tcg_temp_free_i64(temp64);
6738 break;
6739 case OPC2_32_RR1_MULM_H_64_LU:
6740 temp64 = tcg_temp_new_i64();
6741 CHECK_REG_PAIR(r3);
6742 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6743 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6744 /* reset V bit */
6745 tcg_gen_movi_tl(cpu_PSW_V, 0);
6746 /* reset AV bit */
6747 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6748 tcg_temp_free_i64(temp64);
6749 break;
6750 case OPC2_32_RR1_MULM_H_64_UL:
6751 temp64 = tcg_temp_new_i64();
6752 CHECK_REG_PAIR(r3);
6753 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6754 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6755 /* reset V bit */
6756 tcg_gen_movi_tl(cpu_PSW_V, 0);
6757 /* reset AV bit */
6758 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6759 tcg_temp_free_i64(temp64);
6760 break;
6761 case OPC2_32_RR1_MULM_H_64_UU:
6762 temp64 = tcg_temp_new_i64();
6763 CHECK_REG_PAIR(r3);
6764 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6765 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6766 /* reset V bit */
6767 tcg_gen_movi_tl(cpu_PSW_V, 0);
6768 /* reset AV bit */
6769 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6770 tcg_temp_free_i64(temp64);
6771
6772 break;
6773 case OPC2_32_RR1_MULR_H_16_LL:
6774 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6775 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6776 break;
6777 case OPC2_32_RR1_MULR_H_16_LU:
6778 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6779 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6780 break;
6781 case OPC2_32_RR1_MULR_H_16_UL:
6782 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6783 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6784 break;
6785 case OPC2_32_RR1_MULR_H_16_UU:
6786 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6787 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6788 break;
6789 default:
6790 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6791 }
6792 tcg_temp_free(n);
6793 }
6794
6795 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
6796 {
6797 uint32_t op2;
6798 int r1, r2, r3;
6799 uint32_t n;
6800
6801 TCGv temp, temp2;
6802
6803 r1 = MASK_OP_RR1_S1(ctx->opcode);
6804 r2 = MASK_OP_RR1_S2(ctx->opcode);
6805 r3 = MASK_OP_RR1_D(ctx->opcode);
6806 n = MASK_OP_RR1_N(ctx->opcode);
6807 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6808
6809 temp = tcg_temp_new();
6810 temp2 = tcg_temp_new();
6811
6812 switch (op2) {
6813 case OPC2_32_RR1_MUL_Q_32:
6814 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6815 break;
6816 case OPC2_32_RR1_MUL_Q_64:
6817 CHECK_REG_PAIR(r3);
6818 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6819 n, 0);
6820 break;
6821 case OPC2_32_RR1_MUL_Q_32_L:
6822 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6823 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6824 break;
6825 case OPC2_32_RR1_MUL_Q_64_L:
6826 CHECK_REG_PAIR(r3);
6827 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6828 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6829 break;
6830 case OPC2_32_RR1_MUL_Q_32_U:
6831 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6832 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6833 break;
6834 case OPC2_32_RR1_MUL_Q_64_U:
6835 CHECK_REG_PAIR(r3);
6836 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6837 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6838 break;
6839 case OPC2_32_RR1_MUL_Q_32_LL:
6840 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6841 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6842 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6843 break;
6844 case OPC2_32_RR1_MUL_Q_32_UU:
6845 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6846 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6847 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6848 break;
6849 case OPC2_32_RR1_MULR_Q_32_L:
6850 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6851 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6852 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6853 break;
6854 case OPC2_32_RR1_MULR_Q_32_U:
6855 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6856 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6857 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6858 break;
6859 default:
6860 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6861 }
6862 tcg_temp_free(temp);
6863 tcg_temp_free(temp2);
6864 }
6865
6866 /* RR2 format */
6867 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
6868 {
6869 uint32_t op2;
6870 int r1, r2, r3;
6871
6872 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6873 r1 = MASK_OP_RR2_S1(ctx->opcode);
6874 r2 = MASK_OP_RR2_S2(ctx->opcode);
6875 r3 = MASK_OP_RR2_D(ctx->opcode);
6876 switch (op2) {
6877 case OPC2_32_RR2_MUL_32:
6878 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6879 break;
6880 case OPC2_32_RR2_MUL_64:
6881 CHECK_REG_PAIR(r3);
6882 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6883 cpu_gpr_d[r2]);
6884 break;
6885 case OPC2_32_RR2_MULS_32:
6886 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6887 cpu_gpr_d[r2]);
6888 break;
6889 case OPC2_32_RR2_MUL_U_64:
6890 CHECK_REG_PAIR(r3);
6891 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6892 cpu_gpr_d[r2]);
6893 break;
6894 case OPC2_32_RR2_MULS_U_32:
6895 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6896 cpu_gpr_d[r2]);
6897 break;
6898 default:
6899 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6900 }
6901 }
6902
6903 /* RRPW format */
6904 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
6905 {
6906 uint32_t op2;
6907 int r1, r2, r3;
6908 int32_t pos, width;
6909
6910 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6911 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6912 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6913 r3 = MASK_OP_RRPW_D(ctx->opcode);
6914 pos = MASK_OP_RRPW_POS(ctx->opcode);
6915 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6916
6917 switch (op2) {
6918 case OPC2_32_RRPW_EXTR:
6919 if (pos + width <= 31) {
6920 /* optimize special cases */
6921 if ((pos == 0) && (width == 8)) {
6922 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6923 } else if ((pos == 0) && (width == 16)) {
6924 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6925 } else {
6926 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6927 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6928 }
6929 }
6930 break;
6931 case OPC2_32_RRPW_EXTR_U:
6932 if (width == 0) {
6933 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6934 } else {
6935 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6936 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6937 }
6938 break;
6939 case OPC2_32_RRPW_IMASK:
6940 CHECK_REG_PAIR(r3);
6941 if (pos + width <= 31) {
6942 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
6943 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6944 }
6945 break;
6946 case OPC2_32_RRPW_INSERT:
6947 if (pos + width <= 31) {
6948 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6949 width, pos);
6950 }
6951 break;
6952 default:
6953 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6954 }
6955 }
6956
6957 /* RRR format */
6958 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
6959 {
6960 uint32_t op2;
6961 int r1, r2, r3, r4;
6962 TCGv temp;
6963
6964 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6965 r1 = MASK_OP_RRR_S1(ctx->opcode);
6966 r2 = MASK_OP_RRR_S2(ctx->opcode);
6967 r3 = MASK_OP_RRR_S3(ctx->opcode);
6968 r4 = MASK_OP_RRR_D(ctx->opcode);
6969
6970 switch (op2) {
6971 case OPC2_32_RRR_CADD:
6972 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6973 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6974 break;
6975 case OPC2_32_RRR_CADDN:
6976 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6977 cpu_gpr_d[r3]);
6978 break;
6979 case OPC2_32_RRR_CSUB:
6980 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6981 cpu_gpr_d[r3]);
6982 break;
6983 case OPC2_32_RRR_CSUBN:
6984 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6985 cpu_gpr_d[r3]);
6986 break;
6987 case OPC2_32_RRR_SEL:
6988 temp = tcg_const_i32(0);
6989 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6990 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6991 tcg_temp_free(temp);
6992 break;
6993 case OPC2_32_RRR_SELN:
6994 temp = tcg_const_i32(0);
6995 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6996 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6997 tcg_temp_free(temp);
6998 break;
6999 default:
7000 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7001 }
7002 }
7003
7004 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
7005 {
7006 uint32_t op2;
7007
7008 int r1, r2, r3, r4;
7009
7010 op2 = MASK_OP_RRR_OP2(ctx->opcode);
7011 r1 = MASK_OP_RRR_S1(ctx->opcode);
7012 r2 = MASK_OP_RRR_S2(ctx->opcode);
7013 r3 = MASK_OP_RRR_S3(ctx->opcode);
7014 r4 = MASK_OP_RRR_D(ctx->opcode);
7015
7016 CHECK_REG_PAIR(r3);
7017
7018 switch (op2) {
7019 case OPC2_32_RRR_DVADJ:
7020 CHECK_REG_PAIR(r4);
7021 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7022 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7023 break;
7024 case OPC2_32_RRR_DVSTEP:
7025 CHECK_REG_PAIR(r4);
7026 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7027 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7028 break;
7029 case OPC2_32_RRR_DVSTEP_U:
7030 CHECK_REG_PAIR(r4);
7031 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7032 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7033 break;
7034 case OPC2_32_RRR_IXMAX:
7035 CHECK_REG_PAIR(r4);
7036 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7037 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7038 break;
7039 case OPC2_32_RRR_IXMAX_U:
7040 CHECK_REG_PAIR(r4);
7041 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7042 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7043 break;
7044 case OPC2_32_RRR_IXMIN:
7045 CHECK_REG_PAIR(r4);
7046 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7047 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7048 break;
7049 case OPC2_32_RRR_IXMIN_U:
7050 CHECK_REG_PAIR(r4);
7051 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7052 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7053 break;
7054 case OPC2_32_RRR_PACK:
7055 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
7056 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
7057 break;
7058 default:
7059 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7060 }
7061 }
7062
7063 /* RRR2 format */
7064 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
7065 {
7066 uint32_t op2;
7067 uint32_t r1, r2, r3, r4;
7068
7069 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
7070 r1 = MASK_OP_RRR2_S1(ctx->opcode);
7071 r2 = MASK_OP_RRR2_S2(ctx->opcode);
7072 r3 = MASK_OP_RRR2_S3(ctx->opcode);
7073 r4 = MASK_OP_RRR2_D(ctx->opcode);
7074 switch (op2) {
7075 case OPC2_32_RRR2_MADD_32:
7076 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
7077 cpu_gpr_d[r2]);
7078 break;
7079 case OPC2_32_RRR2_MADD_64:
7080 CHECK_REG_PAIR(r4);
7081 CHECK_REG_PAIR(r3);
7082 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7083 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7084 break;
7085 case OPC2_32_RRR2_MADDS_32:
7086 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7087 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7088 break;
7089 case OPC2_32_RRR2_MADDS_64:
7090 CHECK_REG_PAIR(r4);
7091 CHECK_REG_PAIR(r3);
7092 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7093 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7094 break;
7095 case OPC2_32_RRR2_MADD_U_64:
7096 CHECK_REG_PAIR(r4);
7097 CHECK_REG_PAIR(r3);
7098 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7099 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7100 break;
7101 case OPC2_32_RRR2_MADDS_U_32:
7102 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7103 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7104 break;
7105 case OPC2_32_RRR2_MADDS_U_64:
7106 CHECK_REG_PAIR(r4);
7107 CHECK_REG_PAIR(r3);
7108 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7109 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7110 break;
7111 default:
7112 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7113 }
7114 }
7115
7116 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
7117 {
7118 uint32_t op2;
7119 uint32_t r1, r2, r3, r4;
7120
7121 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
7122 r1 = MASK_OP_RRR2_S1(ctx->opcode);
7123 r2 = MASK_OP_RRR2_S2(ctx->opcode);
7124 r3 = MASK_OP_RRR2_S3(ctx->opcode);
7125 r4 = MASK_OP_RRR2_D(ctx->opcode);
7126
7127 switch (op2) {
7128 case OPC2_32_RRR2_MSUB_32:
7129 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
7130 cpu_gpr_d[r2]);
7131 break;
7132 case OPC2_32_RRR2_MSUB_64:
7133 CHECK_REG_PAIR(r4);
7134 CHECK_REG_PAIR(r3);
7135 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7136 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7137 break;
7138 case OPC2_32_RRR2_MSUBS_32:
7139 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7140 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7141 break;
7142 case OPC2_32_RRR2_MSUBS_64:
7143 CHECK_REG_PAIR(r4);
7144 CHECK_REG_PAIR(r3);
7145 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7146 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7147 break;
7148 case OPC2_32_RRR2_MSUB_U_64:
7149 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7150 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7151 break;
7152 case OPC2_32_RRR2_MSUBS_U_32:
7153 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
7154 cpu_gpr_d[r3], cpu_gpr_d[r2]);
7155 break;
7156 case OPC2_32_RRR2_MSUBS_U_64:
7157 CHECK_REG_PAIR(r4);
7158 CHECK_REG_PAIR(r3);
7159 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
7160 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
7161 break;
7162 default:
7163 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7164 }
7165 }
7166
7167 /* RRR1 format */
7168 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
7169 {
7170 uint32_t op2;
7171 uint32_t r1, r2, r3, r4, n;
7172
7173 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7174 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7175 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7176 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7177 r4 = MASK_OP_RRR1_D(ctx->opcode);
7178 n = MASK_OP_RRR1_N(ctx->opcode);
7179
7180 switch (op2) {
7181 case OPC2_32_RRR1_MADD_H_LL:
7182 CHECK_REG_PAIR(r4);
7183 CHECK_REG_PAIR(r3);
7184 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7185 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7186 break;
7187 case OPC2_32_RRR1_MADD_H_LU:
7188 CHECK_REG_PAIR(r4);
7189 CHECK_REG_PAIR(r3);
7190 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7191 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7192 break;
7193 case OPC2_32_RRR1_MADD_H_UL:
7194 CHECK_REG_PAIR(r4);
7195 CHECK_REG_PAIR(r3);
7196 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7197 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7198 break;
7199 case OPC2_32_RRR1_MADD_H_UU:
7200 CHECK_REG_PAIR(r4);
7201 CHECK_REG_PAIR(r3);
7202 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7203 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7204 break;
7205 case OPC2_32_RRR1_MADDS_H_LL:
7206 CHECK_REG_PAIR(r4);
7207 CHECK_REG_PAIR(r3);
7208 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7209 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7210 break;
7211 case OPC2_32_RRR1_MADDS_H_LU:
7212 CHECK_REG_PAIR(r4);
7213 CHECK_REG_PAIR(r3);
7214 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7215 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7216 break;
7217 case OPC2_32_RRR1_MADDS_H_UL:
7218 CHECK_REG_PAIR(r4);
7219 CHECK_REG_PAIR(r3);
7220 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7221 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7222 break;
7223 case OPC2_32_RRR1_MADDS_H_UU:
7224 CHECK_REG_PAIR(r4);
7225 CHECK_REG_PAIR(r3);
7226 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7227 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7228 break;
7229 case OPC2_32_RRR1_MADDM_H_LL:
7230 CHECK_REG_PAIR(r4);
7231 CHECK_REG_PAIR(r3);
7232 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7233 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7234 break;
7235 case OPC2_32_RRR1_MADDM_H_LU:
7236 CHECK_REG_PAIR(r4);
7237 CHECK_REG_PAIR(r3);
7238 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7239 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7240 break;
7241 case OPC2_32_RRR1_MADDM_H_UL:
7242 CHECK_REG_PAIR(r4);
7243 CHECK_REG_PAIR(r3);
7244 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7245 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7246 break;
7247 case OPC2_32_RRR1_MADDM_H_UU:
7248 CHECK_REG_PAIR(r4);
7249 CHECK_REG_PAIR(r3);
7250 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7251 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7252 break;
7253 case OPC2_32_RRR1_MADDMS_H_LL:
7254 CHECK_REG_PAIR(r4);
7255 CHECK_REG_PAIR(r3);
7256 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7257 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7258 break;
7259 case OPC2_32_RRR1_MADDMS_H_LU:
7260 CHECK_REG_PAIR(r4);
7261 CHECK_REG_PAIR(r3);
7262 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7263 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7264 break;
7265 case OPC2_32_RRR1_MADDMS_H_UL:
7266 CHECK_REG_PAIR(r4);
7267 CHECK_REG_PAIR(r3);
7268 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7269 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7270 break;
7271 case OPC2_32_RRR1_MADDMS_H_UU:
7272 CHECK_REG_PAIR(r4);
7273 CHECK_REG_PAIR(r3);
7274 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7275 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7276 break;
7277 case OPC2_32_RRR1_MADDR_H_LL:
7278 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7279 cpu_gpr_d[r2], n, MODE_LL);
7280 break;
7281 case OPC2_32_RRR1_MADDR_H_LU:
7282 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7283 cpu_gpr_d[r2], n, MODE_LU);
7284 break;
7285 case OPC2_32_RRR1_MADDR_H_UL:
7286 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7287 cpu_gpr_d[r2], n, MODE_UL);
7288 break;
7289 case OPC2_32_RRR1_MADDR_H_UU:
7290 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7291 cpu_gpr_d[r2], n, MODE_UU);
7292 break;
7293 case OPC2_32_RRR1_MADDRS_H_LL:
7294 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7295 cpu_gpr_d[r2], n, MODE_LL);
7296 break;
7297 case OPC2_32_RRR1_MADDRS_H_LU:
7298 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7299 cpu_gpr_d[r2], n, MODE_LU);
7300 break;
7301 case OPC2_32_RRR1_MADDRS_H_UL:
7302 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7303 cpu_gpr_d[r2], n, MODE_UL);
7304 break;
7305 case OPC2_32_RRR1_MADDRS_H_UU:
7306 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7307 cpu_gpr_d[r2], n, MODE_UU);
7308 break;
7309 default:
7310 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7311 }
7312 }
7313
7314 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
7315 {
7316 uint32_t op2;
7317 uint32_t r1, r2, r3, r4, n;
7318 TCGv temp, temp2;
7319
7320 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7321 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7322 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7323 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7324 r4 = MASK_OP_RRR1_D(ctx->opcode);
7325 n = MASK_OP_RRR1_N(ctx->opcode);
7326
7327 temp = tcg_const_i32(n);
7328 temp2 = tcg_temp_new();
7329
7330 switch (op2) {
7331 case OPC2_32_RRR1_MADD_Q_32:
7332 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7333 cpu_gpr_d[r2], n, 32, env);
7334 break;
7335 case OPC2_32_RRR1_MADD_Q_64:
7336 CHECK_REG_PAIR(r4);
7337 CHECK_REG_PAIR(r3);
7338 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7339 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7340 n, env);
7341 break;
7342 case OPC2_32_RRR1_MADD_Q_32_L:
7343 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7344 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7345 temp, n, 16, env);
7346 break;
7347 case OPC2_32_RRR1_MADD_Q_64_L:
7348 CHECK_REG_PAIR(r4);
7349 CHECK_REG_PAIR(r3);
7350 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7351 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7352 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7353 n, env);
7354 break;
7355 case OPC2_32_RRR1_MADD_Q_32_U:
7356 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7357 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7358 temp, n, 16, env);
7359 break;
7360 case OPC2_32_RRR1_MADD_Q_64_U:
7361 CHECK_REG_PAIR(r4);
7362 CHECK_REG_PAIR(r3);
7363 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7364 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7365 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7366 n, env);
7367 break;
7368 case OPC2_32_RRR1_MADD_Q_32_LL:
7369 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7370 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7371 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7372 break;
7373 case OPC2_32_RRR1_MADD_Q_64_LL:
7374 CHECK_REG_PAIR(r4);
7375 CHECK_REG_PAIR(r3);
7376 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7377 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7378 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7379 cpu_gpr_d[r3+1], temp, temp2, n);
7380 break;
7381 case OPC2_32_RRR1_MADD_Q_32_UU:
7382 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7383 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7384 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7385 break;
7386 case OPC2_32_RRR1_MADD_Q_64_UU:
7387 CHECK_REG_PAIR(r4);
7388 CHECK_REG_PAIR(r3);
7389 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7390 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7391 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7392 cpu_gpr_d[r3+1], temp, temp2, n);
7393 break;
7394 case OPC2_32_RRR1_MADDS_Q_32:
7395 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7396 cpu_gpr_d[r2], n, 32);
7397 break;
7398 case OPC2_32_RRR1_MADDS_Q_64:
7399 CHECK_REG_PAIR(r4);
7400 CHECK_REG_PAIR(r3);
7401 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7402 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7403 n);
7404 break;
7405 case OPC2_32_RRR1_MADDS_Q_32_L:
7406 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7407 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7408 temp, n, 16);
7409 break;
7410 case OPC2_32_RRR1_MADDS_Q_64_L:
7411 CHECK_REG_PAIR(r4);
7412 CHECK_REG_PAIR(r3);
7413 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7414 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7415 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7416 n);
7417 break;
7418 case OPC2_32_RRR1_MADDS_Q_32_U:
7419 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7420 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7421 temp, n, 16);
7422 break;
7423 case OPC2_32_RRR1_MADDS_Q_64_U:
7424 CHECK_REG_PAIR(r4);
7425 CHECK_REG_PAIR(r3);
7426 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7427 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7428 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7429 n);
7430 break;
7431 case OPC2_32_RRR1_MADDS_Q_32_LL:
7432 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7433 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7434 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7435 break;
7436 case OPC2_32_RRR1_MADDS_Q_64_LL:
7437 CHECK_REG_PAIR(r4);
7438 CHECK_REG_PAIR(r3);
7439 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7440 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7441 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7442 cpu_gpr_d[r3+1], temp, temp2, n);
7443 break;
7444 case OPC2_32_RRR1_MADDS_Q_32_UU:
7445 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7446 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7447 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7448 break;
7449 case OPC2_32_RRR1_MADDS_Q_64_UU:
7450 CHECK_REG_PAIR(r4);
7451 CHECK_REG_PAIR(r3);
7452 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7453 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7454 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7455 cpu_gpr_d[r3+1], temp, temp2, n);
7456 break;
7457 case OPC2_32_RRR1_MADDR_H_64_UL:
7458 CHECK_REG_PAIR(r3);
7459 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7460 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7461 break;
7462 case OPC2_32_RRR1_MADDRS_H_64_UL:
7463 CHECK_REG_PAIR(r3);
7464 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7465 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7466 break;
7467 case OPC2_32_RRR1_MADDR_Q_32_LL:
7468 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7469 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7470 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7471 break;
7472 case OPC2_32_RRR1_MADDR_Q_32_UU:
7473 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7474 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7475 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7476 break;
7477 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7478 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7479 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7480 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7481 break;
7482 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7483 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7484 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7485 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7486 break;
7487 default:
7488 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7489 }
7490 tcg_temp_free(temp);
7491 tcg_temp_free(temp2);
7492 }
7493
7494 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
7495 {
7496 uint32_t op2;
7497 uint32_t r1, r2, r3, r4, n;
7498
7499 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7500 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7501 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7502 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7503 r4 = MASK_OP_RRR1_D(ctx->opcode);
7504 n = MASK_OP_RRR1_N(ctx->opcode);
7505
7506 switch (op2) {
7507 case OPC2_32_RRR1_MADDSU_H_32_LL:
7508 CHECK_REG_PAIR(r4);
7509 CHECK_REG_PAIR(r3);
7510 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7511 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7512 break;
7513 case OPC2_32_RRR1_MADDSU_H_32_LU:
7514 CHECK_REG_PAIR(r4);
7515 CHECK_REG_PAIR(r3);
7516 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7517 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7518 break;
7519 case OPC2_32_RRR1_MADDSU_H_32_UL:
7520 CHECK_REG_PAIR(r4);
7521 CHECK_REG_PAIR(r3);
7522 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7523 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7524 break;
7525 case OPC2_32_RRR1_MADDSU_H_32_UU:
7526 CHECK_REG_PAIR(r4);
7527 CHECK_REG_PAIR(r3);
7528 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7529 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7530 break;
7531 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7532 CHECK_REG_PAIR(r4);
7533 CHECK_REG_PAIR(r3);
7534 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7535 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7536 n, MODE_LL);
7537 break;
7538 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7539 CHECK_REG_PAIR(r4);
7540 CHECK_REG_PAIR(r3);
7541 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7542 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7543 n, MODE_LU);
7544 break;
7545 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7546 CHECK_REG_PAIR(r4);
7547 CHECK_REG_PAIR(r3);
7548 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7549 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7550 n, MODE_UL);
7551 break;
7552 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7553 CHECK_REG_PAIR(r4);
7554 CHECK_REG_PAIR(r3);
7555 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7556 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7557 n, MODE_UU);
7558 break;
7559 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7560 CHECK_REG_PAIR(r4);
7561 CHECK_REG_PAIR(r3);
7562 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7563 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7564 n, MODE_LL);
7565 break;
7566 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7567 CHECK_REG_PAIR(r4);
7568 CHECK_REG_PAIR(r3);
7569 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7570 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7571 n, MODE_LU);
7572 break;
7573 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7574 CHECK_REG_PAIR(r4);
7575 CHECK_REG_PAIR(r3);
7576 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7577 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7578 n, MODE_UL);
7579 break;
7580 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7581 CHECK_REG_PAIR(r4);
7582 CHECK_REG_PAIR(r3);
7583 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7584 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7585 n, MODE_UU);
7586 break;
7587 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7588 CHECK_REG_PAIR(r4);
7589 CHECK_REG_PAIR(r3);
7590 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7591 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7592 n, MODE_LL);
7593 break;
7594 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7595 CHECK_REG_PAIR(r4);
7596 CHECK_REG_PAIR(r3);
7597 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7598 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7599 n, MODE_LU);
7600 break;
7601 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7602 CHECK_REG_PAIR(r4);
7603 CHECK_REG_PAIR(r3);
7604 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7605 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7606 n, MODE_UL);
7607 break;
7608 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7609 CHECK_REG_PAIR(r4);
7610 CHECK_REG_PAIR(r3);
7611 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7612 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7613 n, MODE_UU);
7614 break;
7615 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7616 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7617 cpu_gpr_d[r2], n, MODE_LL);
7618 break;
7619 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7620 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7621 cpu_gpr_d[r2], n, MODE_LU);
7622 break;
7623 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7624 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7625 cpu_gpr_d[r2], n, MODE_UL);
7626 break;
7627 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7628 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7629 cpu_gpr_d[r2], n, MODE_UU);
7630 break;
7631 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7632 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7633 cpu_gpr_d[r2], n, MODE_LL);
7634 break;
7635 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7636 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7637 cpu_gpr_d[r2], n, MODE_LU);
7638 break;
7639 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7640 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7641 cpu_gpr_d[r2], n, MODE_UL);
7642 break;
7643 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7644 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7645 cpu_gpr_d[r2], n, MODE_UU);
7646 break;
7647 default:
7648 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7649 }
7650 }
7651
7652 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
7653 {
7654 uint32_t op2;
7655 uint32_t r1, r2, r3, r4, n;
7656
7657 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7658 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7659 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7660 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7661 r4 = MASK_OP_RRR1_D(ctx->opcode);
7662 n = MASK_OP_RRR1_N(ctx->opcode);
7663
7664 switch (op2) {
7665 case OPC2_32_RRR1_MSUB_H_LL:
7666 CHECK_REG_PAIR(r4);
7667 CHECK_REG_PAIR(r3);
7668 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7669 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7670 break;
7671 case OPC2_32_RRR1_MSUB_H_LU:
7672 CHECK_REG_PAIR(r4);
7673 CHECK_REG_PAIR(r3);
7674 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7675 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7676 break;
7677 case OPC2_32_RRR1_MSUB_H_UL:
7678 CHECK_REG_PAIR(r4);
7679 CHECK_REG_PAIR(r3);
7680 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7681 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7682 break;
7683 case OPC2_32_RRR1_MSUB_H_UU:
7684 CHECK_REG_PAIR(r4);
7685 CHECK_REG_PAIR(r3);
7686 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7687 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7688 break;
7689 case OPC2_32_RRR1_MSUBS_H_LL:
7690 CHECK_REG_PAIR(r4);
7691 CHECK_REG_PAIR(r3);
7692 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7693 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7694 break;
7695 case OPC2_32_RRR1_MSUBS_H_LU:
7696 CHECK_REG_PAIR(r4);
7697 CHECK_REG_PAIR(r3);
7698 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7699 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7700 break;
7701 case OPC2_32_RRR1_MSUBS_H_UL:
7702 CHECK_REG_PAIR(r4);
7703 CHECK_REG_PAIR(r3);
7704 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7705 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7706 break;
7707 case OPC2_32_RRR1_MSUBS_H_UU:
7708 CHECK_REG_PAIR(r4);
7709 CHECK_REG_PAIR(r3);
7710 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7711 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7712 break;
7713 case OPC2_32_RRR1_MSUBM_H_LL:
7714 CHECK_REG_PAIR(r4);
7715 CHECK_REG_PAIR(r3);
7716 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7717 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7718 break;
7719 case OPC2_32_RRR1_MSUBM_H_LU:
7720 CHECK_REG_PAIR(r4);
7721 CHECK_REG_PAIR(r3);
7722 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7723 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7724 break;
7725 case OPC2_32_RRR1_MSUBM_H_UL:
7726 CHECK_REG_PAIR(r4);
7727 CHECK_REG_PAIR(r3);
7728 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7729 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7730 break;
7731 case OPC2_32_RRR1_MSUBM_H_UU:
7732 CHECK_REG_PAIR(r4);
7733 CHECK_REG_PAIR(r3);
7734 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7735 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7736 break;
7737 case OPC2_32_RRR1_MSUBMS_H_LL:
7738 CHECK_REG_PAIR(r4);
7739 CHECK_REG_PAIR(r3);
7740 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7741 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7742 break;
7743 case OPC2_32_RRR1_MSUBMS_H_LU:
7744 CHECK_REG_PAIR(r4);
7745 CHECK_REG_PAIR(r3);
7746 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7747 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7748 break;
7749 case OPC2_32_RRR1_MSUBMS_H_UL:
7750 CHECK_REG_PAIR(r4);
7751 CHECK_REG_PAIR(r3);
7752 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7753 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7754 break;
7755 case OPC2_32_RRR1_MSUBMS_H_UU:
7756 CHECK_REG_PAIR(r4);
7757 CHECK_REG_PAIR(r3);
7758 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7759 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7760 break;
7761 case OPC2_32_RRR1_MSUBR_H_LL:
7762 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7763 cpu_gpr_d[r2], n, MODE_LL);
7764 break;
7765 case OPC2_32_RRR1_MSUBR_H_LU:
7766 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7767 cpu_gpr_d[r2], n, MODE_LU);
7768 break;
7769 case OPC2_32_RRR1_MSUBR_H_UL:
7770 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7771 cpu_gpr_d[r2], n, MODE_UL);
7772 break;
7773 case OPC2_32_RRR1_MSUBR_H_UU:
7774 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7775 cpu_gpr_d[r2], n, MODE_UU);
7776 break;
7777 case OPC2_32_RRR1_MSUBRS_H_LL:
7778 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7779 cpu_gpr_d[r2], n, MODE_LL);
7780 break;
7781 case OPC2_32_RRR1_MSUBRS_H_LU:
7782 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7783 cpu_gpr_d[r2], n, MODE_LU);
7784 break;
7785 case OPC2_32_RRR1_MSUBRS_H_UL:
7786 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7787 cpu_gpr_d[r2], n, MODE_UL);
7788 break;
7789 case OPC2_32_RRR1_MSUBRS_H_UU:
7790 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7791 cpu_gpr_d[r2], n, MODE_UU);
7792 break;
7793 default:
7794 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7795 }
7796 }
7797
7798 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
7799 {
7800 uint32_t op2;
7801 uint32_t r1, r2, r3, r4, n;
7802 TCGv temp, temp2;
7803
7804 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7805 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7806 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7807 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7808 r4 = MASK_OP_RRR1_D(ctx->opcode);
7809 n = MASK_OP_RRR1_N(ctx->opcode);
7810
7811 temp = tcg_const_i32(n);
7812 temp2 = tcg_temp_new();
7813
7814 switch (op2) {
7815 case OPC2_32_RRR1_MSUB_Q_32:
7816 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7817 cpu_gpr_d[r2], n, 32, env);
7818 break;
7819 case OPC2_32_RRR1_MSUB_Q_64:
7820 CHECK_REG_PAIR(r4);
7821 CHECK_REG_PAIR(r3);
7822 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7823 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7824 n, env);
7825 break;
7826 case OPC2_32_RRR1_MSUB_Q_32_L:
7827 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7828 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7829 temp, n, 16, env);
7830 break;
7831 case OPC2_32_RRR1_MSUB_Q_64_L:
7832 CHECK_REG_PAIR(r4);
7833 CHECK_REG_PAIR(r3);
7834 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7835 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7836 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7837 n, env);
7838 break;
7839 case OPC2_32_RRR1_MSUB_Q_32_U:
7840 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7841 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7842 temp, n, 16, env);
7843 break;
7844 case OPC2_32_RRR1_MSUB_Q_64_U:
7845 CHECK_REG_PAIR(r4);
7846 CHECK_REG_PAIR(r3);
7847 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7848 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7849 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7850 n, env);
7851 break;
7852 case OPC2_32_RRR1_MSUB_Q_32_LL:
7853 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7854 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7855 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7856 break;
7857 case OPC2_32_RRR1_MSUB_Q_64_LL:
7858 CHECK_REG_PAIR(r4);
7859 CHECK_REG_PAIR(r3);
7860 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7861 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7862 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7863 cpu_gpr_d[r3+1], temp, temp2, n);
7864 break;
7865 case OPC2_32_RRR1_MSUB_Q_32_UU:
7866 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7867 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7868 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7869 break;
7870 case OPC2_32_RRR1_MSUB_Q_64_UU:
7871 CHECK_REG_PAIR(r4);
7872 CHECK_REG_PAIR(r3);
7873 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7874 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7875 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7876 cpu_gpr_d[r3+1], temp, temp2, n);
7877 break;
7878 case OPC2_32_RRR1_MSUBS_Q_32:
7879 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7880 cpu_gpr_d[r2], n, 32);
7881 break;
7882 case OPC2_32_RRR1_MSUBS_Q_64:
7883 CHECK_REG_PAIR(r4);
7884 CHECK_REG_PAIR(r3);
7885 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7886 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7887 n);
7888 break;
7889 case OPC2_32_RRR1_MSUBS_Q_32_L:
7890 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7891 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7892 temp, n, 16);
7893 break;
7894 case OPC2_32_RRR1_MSUBS_Q_64_L:
7895 CHECK_REG_PAIR(r4);
7896 CHECK_REG_PAIR(r3);
7897 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7898 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7899 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7900 n);
7901 break;
7902 case OPC2_32_RRR1_MSUBS_Q_32_U:
7903 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7904 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7905 temp, n, 16);
7906 break;
7907 case OPC2_32_RRR1_MSUBS_Q_64_U:
7908 CHECK_REG_PAIR(r4);
7909 CHECK_REG_PAIR(r3);
7910 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7911 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7912 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7913 n);
7914 break;
7915 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7916 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7917 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7918 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7919 break;
7920 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7921 CHECK_REG_PAIR(r4);
7922 CHECK_REG_PAIR(r3);
7923 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7924 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7925 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7926 cpu_gpr_d[r3+1], temp, temp2, n);
7927 break;
7928 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7929 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7930 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7931 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7932 break;
7933 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7934 CHECK_REG_PAIR(r4);
7935 CHECK_REG_PAIR(r3);
7936 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7937 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7938 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7939 cpu_gpr_d[r3+1], temp, temp2, n);
7940 break;
7941 case OPC2_32_RRR1_MSUBR_H_64_UL:
7942 CHECK_REG_PAIR(r3);
7943 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7944 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7945 break;
7946 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7947 CHECK_REG_PAIR(r3);
7948 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7949 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7950 break;
7951 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7952 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7953 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7954 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7955 break;
7956 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7957 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7958 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7959 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7960 break;
7961 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7962 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7963 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7964 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7965 break;
7966 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7967 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7968 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7969 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7970 break;
7971 default:
7972 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7973 }
7974 tcg_temp_free(temp);
7975 tcg_temp_free(temp2);
7976 }
7977
7978 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
7979 {
7980 uint32_t op2;
7981 uint32_t r1, r2, r3, r4, n;
7982
7983 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7984 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7985 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7986 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7987 r4 = MASK_OP_RRR1_D(ctx->opcode);
7988 n = MASK_OP_RRR1_N(ctx->opcode);
7989
7990 switch (op2) {
7991 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7992 CHECK_REG_PAIR(r4);
7993 CHECK_REG_PAIR(r3);
7994 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7995 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7996 break;
7997 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7998 CHECK_REG_PAIR(r4);
7999 CHECK_REG_PAIR(r3);
8000 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8001 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
8002 break;
8003 case OPC2_32_RRR1_MSUBAD_H_32_UL:
8004 CHECK_REG_PAIR(r4);
8005 CHECK_REG_PAIR(r3);
8006 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8007 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
8008 break;
8009 case OPC2_32_RRR1_MSUBAD_H_32_UU:
8010 CHECK_REG_PAIR(r4);
8011 CHECK_REG_PAIR(r3);
8012 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8013 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
8014 break;
8015 case OPC2_32_RRR1_MSUBADS_H_32_LL:
8016 CHECK_REG_PAIR(r4);
8017 CHECK_REG_PAIR(r3);
8018 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8019 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8020 n, MODE_LL);
8021 break;
8022 case OPC2_32_RRR1_MSUBADS_H_32_LU:
8023 CHECK_REG_PAIR(r4);
8024 CHECK_REG_PAIR(r3);
8025 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8026 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8027 n, MODE_LU);
8028 break;
8029 case OPC2_32_RRR1_MSUBADS_H_32_UL:
8030 CHECK_REG_PAIR(r4);
8031 CHECK_REG_PAIR(r3);
8032 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8033 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8034 n, MODE_UL);
8035 break;
8036 case OPC2_32_RRR1_MSUBADS_H_32_UU:
8037 CHECK_REG_PAIR(r4);
8038 CHECK_REG_PAIR(r3);
8039 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8040 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8041 n, MODE_UU);
8042 break;
8043 case OPC2_32_RRR1_MSUBADM_H_64_LL:
8044 CHECK_REG_PAIR(r4);
8045 CHECK_REG_PAIR(r3);
8046 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8047 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8048 n, MODE_LL);
8049 break;
8050 case OPC2_32_RRR1_MSUBADM_H_64_LU:
8051 CHECK_REG_PAIR(r4);
8052 CHECK_REG_PAIR(r3);
8053 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8054 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8055 n, MODE_LU);
8056 break;
8057 case OPC2_32_RRR1_MSUBADM_H_64_UL:
8058 CHECK_REG_PAIR(r4);
8059 CHECK_REG_PAIR(r3);
8060 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8061 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8062 n, MODE_UL);
8063 break;
8064 case OPC2_32_RRR1_MSUBADM_H_64_UU:
8065 CHECK_REG_PAIR(r4);
8066 CHECK_REG_PAIR(r3);
8067 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8068 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8069 n, MODE_UU);
8070 break;
8071 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
8072 CHECK_REG_PAIR(r4);
8073 CHECK_REG_PAIR(r3);
8074 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8075 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8076 n, MODE_LL);
8077 break;
8078 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
8079 CHECK_REG_PAIR(r4);
8080 CHECK_REG_PAIR(r3);
8081 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8082 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8083 n, MODE_LU);
8084 break;
8085 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
8086 CHECK_REG_PAIR(r4);
8087 CHECK_REG_PAIR(r3);
8088 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8089 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8090 n, MODE_UL);
8091 break;
8092 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
8093 CHECK_REG_PAIR(r4);
8094 CHECK_REG_PAIR(r3);
8095 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
8096 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
8097 n, MODE_UU);
8098 break;
8099 case OPC2_32_RRR1_MSUBADR_H_16_LL:
8100 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8101 cpu_gpr_d[r2], n, MODE_LL);
8102 break;
8103 case OPC2_32_RRR1_MSUBADR_H_16_LU:
8104 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8105 cpu_gpr_d[r2], n, MODE_LU);
8106 break;
8107 case OPC2_32_RRR1_MSUBADR_H_16_UL:
8108 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8109 cpu_gpr_d[r2], n, MODE_UL);
8110 break;
8111 case OPC2_32_RRR1_MSUBADR_H_16_UU:
8112 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8113 cpu_gpr_d[r2], n, MODE_UU);
8114 break;
8115 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
8116 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8117 cpu_gpr_d[r2], n, MODE_LL);
8118 break;
8119 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
8120 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8121 cpu_gpr_d[r2], n, MODE_LU);
8122 break;
8123 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
8124 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8125 cpu_gpr_d[r2], n, MODE_UL);
8126 break;
8127 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
8128 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
8129 cpu_gpr_d[r2], n, MODE_UU);
8130 break;
8131 default:
8132 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8133 }
8134 }
8135
8136 /* RRRR format */
8137 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
8138 {
8139 uint32_t op2;
8140 int r1, r2, r3, r4;
8141 TCGv tmp_width, tmp_pos;
8142
8143 r1 = MASK_OP_RRRR_S1(ctx->opcode);
8144 r2 = MASK_OP_RRRR_S2(ctx->opcode);
8145 r3 = MASK_OP_RRRR_S3(ctx->opcode);
8146 r4 = MASK_OP_RRRR_D(ctx->opcode);
8147 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
8148
8149 tmp_pos = tcg_temp_new();
8150 tmp_width = tcg_temp_new();
8151
8152 switch (op2) {
8153 case OPC2_32_RRRR_DEXTR:
8154 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
8155 if (r1 == r2) {
8156 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
8157 } else {
8158 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
8159 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
8160 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
8161 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
8162 }
8163 break;
8164 case OPC2_32_RRRR_EXTR:
8165 case OPC2_32_RRRR_EXTR_U:
8166 CHECK_REG_PAIR(r3);
8167 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
8168 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
8169 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
8170 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
8171 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
8172 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
8173 if (op2 == OPC2_32_RRRR_EXTR) {
8174 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
8175 } else {
8176 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
8177 }
8178 break;
8179 case OPC2_32_RRRR_INSERT:
8180 CHECK_REG_PAIR(r3);
8181 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
8182 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
8183 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
8184 tmp_pos);
8185 break;
8186 default:
8187 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8188 }
8189 tcg_temp_free(tmp_pos);
8190 tcg_temp_free(tmp_width);
8191 }
8192
8193 /* RRRW format */
8194 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
8195 {
8196 uint32_t op2;
8197 int r1, r2, r3, r4;
8198 int32_t width;
8199
8200 TCGv temp, temp2;
8201
8202 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
8203 r1 = MASK_OP_RRRW_S1(ctx->opcode);
8204 r2 = MASK_OP_RRRW_S2(ctx->opcode);
8205 r3 = MASK_OP_RRRW_S3(ctx->opcode);
8206 r4 = MASK_OP_RRRW_D(ctx->opcode);
8207 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
8208
8209 temp = tcg_temp_new();
8210
8211 switch (op2) {
8212 case OPC2_32_RRRW_EXTR:
8213 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
8214 tcg_gen_addi_tl(temp, temp, width);
8215 tcg_gen_subfi_tl(temp, 32, temp);
8216 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
8217 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
8218 break;
8219 case OPC2_32_RRRW_EXTR_U:
8220 if (width == 0) {
8221 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
8222 } else {
8223 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
8224 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
8225 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
8226 }
8227 break;
8228 case OPC2_32_RRRW_IMASK:
8229 temp2 = tcg_temp_new();
8230
8231 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
8232 tcg_gen_movi_tl(temp2, (1 << width) - 1);
8233 tcg_gen_shl_tl(temp2, temp2, temp);
8234 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
8235 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
8236
8237 tcg_temp_free(temp2);
8238 break;
8239 case OPC2_32_RRRW_INSERT:
8240 temp2 = tcg_temp_new();
8241
8242 tcg_gen_movi_tl(temp, width);
8243 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
8244 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
8245
8246 tcg_temp_free(temp2);
8247 break;
8248 default:
8249 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8250 }
8251 tcg_temp_free(temp);
8252 }
8253
8254 /* SYS Format*/
8255 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
8256 {
8257 uint32_t op2;
8258 uint32_t r1;
8259 TCGLabel *l1;
8260 TCGv tmp;
8261
8262 op2 = MASK_OP_SYS_OP2(ctx->opcode);
8263 r1 = MASK_OP_SYS_S1D(ctx->opcode);
8264
8265 switch (op2) {
8266 case OPC2_32_SYS_DEBUG:
8267 /* raise EXCP_DEBUG */
8268 break;
8269 case OPC2_32_SYS_DISABLE:
8270 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
8271 break;
8272 case OPC2_32_SYS_DSYNC:
8273 break;
8274 case OPC2_32_SYS_ENABLE:
8275 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
8276 break;
8277 case OPC2_32_SYS_ISYNC:
8278 break;
8279 case OPC2_32_SYS_NOP:
8280 break;
8281 case OPC2_32_SYS_RET:
8282 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
8283 break;
8284 case OPC2_32_SYS_FRET:
8285 gen_fret(ctx);
8286 break;
8287 case OPC2_32_SYS_RFE:
8288 gen_helper_rfe(cpu_env);
8289 tcg_gen_exit_tb(0);
8290 ctx->bstate = BS_BRANCH;
8291 break;
8292 case OPC2_32_SYS_RFM:
8293 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
8294 tmp = tcg_temp_new();
8295 l1 = gen_new_label();
8296
8297 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
8298 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
8299 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
8300 gen_helper_rfm(cpu_env);
8301 gen_set_label(l1);
8302 tcg_gen_exit_tb(0);
8303 ctx->bstate = BS_BRANCH;
8304 tcg_temp_free(tmp);
8305 } else {
8306 /* generate privilege trap */
8307 }
8308 break;
8309 case OPC2_32_SYS_RSLCX:
8310 gen_helper_rslcx(cpu_env);
8311 break;
8312 case OPC2_32_SYS_SVLCX:
8313 gen_helper_svlcx(cpu_env);
8314 break;
8315 case OPC2_32_SYS_RESTORE:
8316 if (tricore_feature(env, TRICORE_FEATURE_16)) {
8317 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
8318 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
8319 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
8320 } /* else raise privilege trap */
8321 } else {
8322 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8323 }
8324 break;
8325 case OPC2_32_SYS_TRAPSV:
8326 l1 = gen_new_label();
8327 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
8328 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
8329 gen_set_label(l1);
8330 break;
8331 case OPC2_32_SYS_TRAPV:
8332 l1 = gen_new_label();
8333 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
8334 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
8335 gen_set_label(l1);
8336 break;
8337 default:
8338 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8339 }
8340 }
8341
8342 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
8343 {
8344 int op1;
8345 int32_t r1, r2, r3;
8346 int32_t address, const16;
8347 int8_t b, const4;
8348 int32_t bpos;
8349 TCGv temp, temp2, temp3;
8350
8351 op1 = MASK_OP_MAJOR(ctx->opcode);
8352
8353 /* handle JNZ.T opcode only being 7 bit long */
8354 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
8355 op1 = OPCM_32_BRN_JTT;
8356 }
8357
8358 switch (op1) {
8359 /* ABS-format */
8360 case OPCM_32_ABS_LDW:
8361 decode_abs_ldw(env, ctx);
8362 break;
8363 case OPCM_32_ABS_LDB:
8364 decode_abs_ldb(env, ctx);
8365 break;
8366 case OPCM_32_ABS_LDMST_SWAP:
8367 decode_abs_ldst_swap(env, ctx);
8368 break;
8369 case OPCM_32_ABS_LDST_CONTEXT:
8370 decode_abs_ldst_context(env, ctx);
8371 break;
8372 case OPCM_32_ABS_STORE:
8373 decode_abs_store(env, ctx);
8374 break;
8375 case OPCM_32_ABS_STOREB_H:
8376 decode_abs_storeb_h(env, ctx);
8377 break;
8378 case OPC1_32_ABS_STOREQ:
8379 address = MASK_OP_ABS_OFF18(ctx->opcode);
8380 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8381 temp = tcg_const_i32(EA_ABS_FORMAT(address));
8382 temp2 = tcg_temp_new();
8383
8384 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
8385 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
8386
8387 tcg_temp_free(temp2);
8388 tcg_temp_free(temp);
8389 break;
8390 case OPC1_32_ABS_LD_Q:
8391 address = MASK_OP_ABS_OFF18(ctx->opcode);
8392 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8393 temp = tcg_const_i32(EA_ABS_FORMAT(address));
8394
8395 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
8396 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
8397
8398 tcg_temp_free(temp);
8399 break;
8400 case OPC1_32_ABS_LEA:
8401 address = MASK_OP_ABS_OFF18(ctx->opcode);
8402 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8403 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
8404 break;
8405 /* ABSB-format */
8406 case OPC1_32_ABSB_ST_T:
8407 address = MASK_OP_ABS_OFF18(ctx->opcode);
8408 b = MASK_OP_ABSB_B(ctx->opcode);
8409 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
8410
8411 temp = tcg_const_i32(EA_ABS_FORMAT(address));
8412 temp2 = tcg_temp_new();
8413
8414 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
8415 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
8416 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
8417 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
8418
8419 tcg_temp_free(temp);
8420 tcg_temp_free(temp2);
8421 break;
8422 /* B-format */
8423 case OPC1_32_B_CALL:
8424 case OPC1_32_B_CALLA:
8425 case OPC1_32_B_FCALL:
8426 case OPC1_32_B_FCALLA:
8427 case OPC1_32_B_J:
8428 case OPC1_32_B_JA:
8429 case OPC1_32_B_JL:
8430 case OPC1_32_B_JLA:
8431 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8432 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8433 break;
8434 /* Bit-format */
8435 case OPCM_32_BIT_ANDACC:
8436 decode_bit_andacc(env, ctx);
8437 break;
8438 case OPCM_32_BIT_LOGICAL_T1:
8439 decode_bit_logical_t(env, ctx);
8440 break;
8441 case OPCM_32_BIT_INSERT:
8442 decode_bit_insert(env, ctx);
8443 break;
8444 case OPCM_32_BIT_LOGICAL_T2:
8445 decode_bit_logical_t2(env, ctx);
8446 break;
8447 case OPCM_32_BIT_ORAND:
8448 decode_bit_orand(env, ctx);
8449 break;
8450 case OPCM_32_BIT_SH_LOGIC1:
8451 decode_bit_sh_logic1(env, ctx);
8452 break;
8453 case OPCM_32_BIT_SH_LOGIC2:
8454 decode_bit_sh_logic2(env, ctx);
8455 break;
8456 /* BO Format */
8457 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8458 decode_bo_addrmode_post_pre_base(env, ctx);
8459 break;
8460 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8461 decode_bo_addrmode_bitreverse_circular(env, ctx);
8462 break;
8463 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8464 decode_bo_addrmode_ld_post_pre_base(env, ctx);
8465 break;
8466 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8467 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
8468 break;
8469 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8470 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
8471 break;
8472 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8473 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
8474 break;
8475 /* BOL-format */
8476 case OPC1_32_BOL_LD_A_LONGOFF:
8477 case OPC1_32_BOL_LD_W_LONGOFF:
8478 case OPC1_32_BOL_LEA_LONGOFF:
8479 case OPC1_32_BOL_ST_W_LONGOFF:
8480 case OPC1_32_BOL_ST_A_LONGOFF:
8481 case OPC1_32_BOL_LD_B_LONGOFF:
8482 case OPC1_32_BOL_LD_BU_LONGOFF:
8483 case OPC1_32_BOL_LD_H_LONGOFF:
8484 case OPC1_32_BOL_LD_HU_LONGOFF:
8485 case OPC1_32_BOL_ST_B_LONGOFF:
8486 case OPC1_32_BOL_ST_H_LONGOFF:
8487 decode_bol_opc(env, ctx, op1);
8488 break;
8489 /* BRC Format */
8490 case OPCM_32_BRC_EQ_NEQ:
8491 case OPCM_32_BRC_GE:
8492 case OPCM_32_BRC_JLT:
8493 case OPCM_32_BRC_JNE:
8494 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8495 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8496 r1 = MASK_OP_BRC_S1(ctx->opcode);
8497 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8498 break;
8499 /* BRN Format */
8500 case OPCM_32_BRN_JTT:
8501 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8502 r1 = MASK_OP_BRN_S1(ctx->opcode);
8503 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8504 break;
8505 /* BRR Format */
8506 case OPCM_32_BRR_EQ_NEQ:
8507 case OPCM_32_BRR_ADDR_EQ_NEQ:
8508 case OPCM_32_BRR_GE:
8509 case OPCM_32_BRR_JLT:
8510 case OPCM_32_BRR_JNE:
8511 case OPCM_32_BRR_JNZ:
8512 case OPCM_32_BRR_LOOP:
8513 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8514 r2 = MASK_OP_BRR_S2(ctx->opcode);
8515 r1 = MASK_OP_BRR_S1(ctx->opcode);
8516 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8517 break;
8518 /* RC Format */
8519 case OPCM_32_RC_LOGICAL_SHIFT:
8520 decode_rc_logical_shift(env, ctx);
8521 break;
8522 case OPCM_32_RC_ACCUMULATOR:
8523 decode_rc_accumulator(env, ctx);
8524 break;
8525 case OPCM_32_RC_SERVICEROUTINE:
8526 decode_rc_serviceroutine(env, ctx);
8527 break;
8528 case OPCM_32_RC_MUL:
8529 decode_rc_mul(env, ctx);
8530 break;
8531 /* RCPW Format */
8532 case OPCM_32_RCPW_MASK_INSERT:
8533 decode_rcpw_insert(env, ctx);
8534 break;
8535 /* RCRR Format */
8536 case OPC1_32_RCRR_INSERT:
8537 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8538 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8539 r3 = MASK_OP_RCRR_D(ctx->opcode);
8540 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8541 temp = tcg_const_i32(const16);
8542 temp2 = tcg_temp_new(); /* width*/
8543 temp3 = tcg_temp_new(); /* pos */
8544
8545 CHECK_REG_PAIR(r3);
8546
8547 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8548 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8549
8550 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8551
8552 tcg_temp_free(temp);
8553 tcg_temp_free(temp2);
8554 tcg_temp_free(temp3);
8555 break;
8556 /* RCRW Format */
8557 case OPCM_32_RCRW_MASK_INSERT:
8558 decode_rcrw_insert(env, ctx);
8559 break;
8560 /* RCR Format */
8561 case OPCM_32_RCR_COND_SELECT:
8562 decode_rcr_cond_select(env, ctx);
8563 break;
8564 case OPCM_32_RCR_MADD:
8565 decode_rcr_madd(env, ctx);
8566 break;
8567 case OPCM_32_RCR_MSUB:
8568 decode_rcr_msub(env, ctx);
8569 break;
8570 /* RLC Format */
8571 case OPC1_32_RLC_ADDI:
8572 case OPC1_32_RLC_ADDIH:
8573 case OPC1_32_RLC_ADDIH_A:
8574 case OPC1_32_RLC_MFCR:
8575 case OPC1_32_RLC_MOV:
8576 case OPC1_32_RLC_MOV_64:
8577 case OPC1_32_RLC_MOV_U:
8578 case OPC1_32_RLC_MOV_H:
8579 case OPC1_32_RLC_MOVH_A:
8580 case OPC1_32_RLC_MTCR:
8581 decode_rlc_opc(env, ctx, op1);
8582 break;
8583 /* RR Format */
8584 case OPCM_32_RR_ACCUMULATOR:
8585 decode_rr_accumulator(env, ctx);
8586 break;
8587 case OPCM_32_RR_LOGICAL_SHIFT:
8588 decode_rr_logical_shift(env, ctx);
8589 break;
8590 case OPCM_32_RR_ADDRESS:
8591 decode_rr_address(env, ctx);
8592 break;
8593 case OPCM_32_RR_IDIRECT:
8594 decode_rr_idirect(env, ctx);
8595 break;
8596 case OPCM_32_RR_DIVIDE:
8597 decode_rr_divide(env, ctx);
8598 break;
8599 /* RR1 Format */
8600 case OPCM_32_RR1_MUL:
8601 decode_rr1_mul(env, ctx);
8602 break;
8603 case OPCM_32_RR1_MULQ:
8604 decode_rr1_mulq(env, ctx);
8605 break;
8606 /* RR2 format */
8607 case OPCM_32_RR2_MUL:
8608 decode_rr2_mul(env, ctx);
8609 break;
8610 /* RRPW format */
8611 case OPCM_32_RRPW_EXTRACT_INSERT:
8612 decode_rrpw_extract_insert(env, ctx);
8613 break;
8614 case OPC1_32_RRPW_DEXTR:
8615 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8616 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8617 r3 = MASK_OP_RRPW_D(ctx->opcode);
8618 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8619 if (r1 == r2) {
8620 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
8621 } else {
8622 temp = tcg_temp_new();
8623 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
8624 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
8625 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
8626 tcg_temp_free(temp);
8627 }
8628 break;
8629 /* RRR Format */
8630 case OPCM_32_RRR_COND_SELECT:
8631 decode_rrr_cond_select(env, ctx);
8632 break;
8633 case OPCM_32_RRR_DIVIDE:
8634 decode_rrr_divide(env, ctx);
8635 /* RRR2 Format */
8636 case OPCM_32_RRR2_MADD:
8637 decode_rrr2_madd(env, ctx);
8638 break;
8639 case OPCM_32_RRR2_MSUB:
8640 decode_rrr2_msub(env, ctx);
8641 break;
8642 /* RRR1 format */
8643 case OPCM_32_RRR1_MADD:
8644 decode_rrr1_madd(env, ctx);
8645 break;
8646 case OPCM_32_RRR1_MADDQ_H:
8647 decode_rrr1_maddq_h(env, ctx);
8648 break;
8649 case OPCM_32_RRR1_MADDSU_H:
8650 decode_rrr1_maddsu_h(env, ctx);
8651 break;
8652 case OPCM_32_RRR1_MSUB_H:
8653 decode_rrr1_msub(env, ctx);
8654 break;
8655 case OPCM_32_RRR1_MSUB_Q:
8656 decode_rrr1_msubq_h(env, ctx);
8657 break;
8658 case OPCM_32_RRR1_MSUBAD_H:
8659 decode_rrr1_msubad_h(env, ctx);
8660 break;
8661 /* RRRR format */
8662 case OPCM_32_RRRR_EXTRACT_INSERT:
8663 decode_rrrr_extract_insert(env, ctx);
8664 /* RRRW format */
8665 case OPCM_32_RRRW_EXTRACT_INSERT:
8666 decode_rrrw_extract_insert(env, ctx);
8667 break;
8668 /* SYS format */
8669 case OPCM_32_SYS_INTERRUPTS:
8670 decode_sys_interrupts(env, ctx);
8671 break;
8672 case OPC1_32_SYS_RSTV:
8673 tcg_gen_movi_tl(cpu_PSW_V, 0);
8674 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8675 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8676 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8677 break;
8678 default:
8679 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8680 }
8681 }
8682
8683 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
8684 {
8685 /* 16-Bit Instruction */
8686 if ((ctx->opcode & 0x1) == 0) {
8687 ctx->next_pc = ctx->pc + 2;
8688 decode_16Bit_opc(env, ctx);
8689 /* 32-Bit Instruction */
8690 } else {
8691 ctx->next_pc = ctx->pc + 4;
8692 decode_32Bit_opc(env, ctx);
8693 }
8694 }
8695
8696 void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
8697 {
8698 TriCoreCPU *cpu = tricore_env_get_cpu(env);
8699 CPUState *cs = CPU(cpu);
8700 DisasContext ctx;
8701 target_ulong pc_start;
8702 int num_insns, max_insns;
8703
8704 num_insns = 0;
8705 max_insns = tb->cflags & CF_COUNT_MASK;
8706 if (max_insns == 0) {
8707 max_insns = CF_COUNT_MASK;
8708 }
8709 if (singlestep) {
8710 max_insns = 1;
8711 }
8712 if (max_insns > TCG_MAX_INSNS) {
8713 max_insns = TCG_MAX_INSNS;
8714 }
8715
8716 pc_start = tb->pc;
8717 ctx.pc = pc_start;
8718 ctx.saved_pc = -1;
8719 ctx.tb = tb;
8720 ctx.singlestep_enabled = cs->singlestep_enabled;
8721 ctx.bstate = BS_NONE;
8722 ctx.mem_idx = cpu_mmu_index(env, false);
8723
8724 tcg_clear_temp_count();
8725 gen_tb_start(tb);
8726 while (ctx.bstate == BS_NONE) {
8727 tcg_gen_insn_start(ctx.pc);
8728 num_insns++;
8729
8730 ctx.opcode = cpu_ldl_code(env, ctx.pc);
8731 decode_opc(env, &ctx, 0);
8732
8733 if (num_insns >= max_insns || tcg_op_buf_full()) {
8734 gen_save_pc(ctx.next_pc);
8735 tcg_gen_exit_tb(0);
8736 break;
8737 }
8738 ctx.pc = ctx.next_pc;
8739 }
8740
8741 gen_tb_end(tb, num_insns);
8742 tb->size = ctx.pc - pc_start;
8743 tb->icount = num_insns;
8744
8745 if (tcg_check_temp_count()) {
8746 printf("LEAK at %08x\n", env->PC);
8747 }
8748
8749 #ifdef DEBUG_DISAS
8750 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8751 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8752 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
8753 qemu_log("\n");
8754 }
8755 #endif
8756 }
8757
8758 void
8759 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb,
8760 target_ulong *data)
8761 {
8762 env->PC = data[0];
8763 }
8764 /*
8765 *
8766 * Initialization
8767 *
8768 */
8769
8770 void cpu_state_reset(CPUTriCoreState *env)
8771 {
8772 /* Reset Regs to Default Value */
8773 env->PSW = 0xb80;
8774 }
8775
8776 static void tricore_tcg_init_csfr(void)
8777 {
8778 cpu_PCXI = tcg_global_mem_new(cpu_env,
8779 offsetof(CPUTriCoreState, PCXI), "PCXI");
8780 cpu_PSW = tcg_global_mem_new(cpu_env,
8781 offsetof(CPUTriCoreState, PSW), "PSW");
8782 cpu_PC = tcg_global_mem_new(cpu_env,
8783 offsetof(CPUTriCoreState, PC), "PC");
8784 cpu_ICR = tcg_global_mem_new(cpu_env,
8785 offsetof(CPUTriCoreState, ICR), "ICR");
8786 }
8787
8788 void tricore_tcg_init(void)
8789 {
8790 int i;
8791 static int inited;
8792 if (inited) {
8793 return;
8794 }
8795 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8796 /* reg init */
8797 for (i = 0 ; i < 16 ; i++) {
8798 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8799 offsetof(CPUTriCoreState, gpr_a[i]),
8800 regnames_a[i]);
8801 }
8802 for (i = 0 ; i < 16 ; i++) {
8803 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8804 offsetof(CPUTriCoreState, gpr_d[i]),
8805 regnames_d[i]);
8806 }
8807 tricore_tcg_init_csfr();
8808 /* init PSW flag cache */
8809 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8810 offsetof(CPUTriCoreState, PSW_USB_C),
8811 "PSW_C");
8812 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8813 offsetof(CPUTriCoreState, PSW_USB_V),
8814 "PSW_V");
8815 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8816 offsetof(CPUTriCoreState, PSW_USB_SV),
8817 "PSW_SV");
8818 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8819 offsetof(CPUTriCoreState, PSW_USB_AV),
8820 "PSW_AV");
8821 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8822 offsetof(CPUTriCoreState, PSW_USB_SAV),
8823 "PSW_SAV");
8824 }
AR7 emulation for QEMU