arm: Rename hw/arm/arm.h to hw/arm/boot.h
[qemu/ar7.git] / hw / ppc / spapr_rtas_ddw.c
blobf6538189f4fc9df53e1b7395fa78d96082953c95
1 /*
2 * QEMU sPAPR Dynamic DMA windows support
4 * Copyright (c) 2015 Alexey Kardashevskiy, IBM Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License,
9 * or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu/error-report.h"
23 #include "hw/ppc/spapr.h"
24 #include "hw/pci-host/spapr.h"
25 #include "trace.h"
27 static int spapr_phb_get_active_win_num_cb(Object *child, void *opaque)
29 SpaprTceTable *tcet;
31 tcet = (SpaprTceTable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE);
32 if (tcet && tcet->nb_table) {
33 ++*(unsigned *)opaque;
35 return 0;
38 static unsigned spapr_phb_get_active_win_num(SpaprPhbState *sphb)
40 unsigned ret = 0;
42 object_child_foreach(OBJECT(sphb), spapr_phb_get_active_win_num_cb, &ret);
44 return ret;
47 static int spapr_phb_get_free_liobn_cb(Object *child, void *opaque)
49 SpaprTceTable *tcet;
51 tcet = (SpaprTceTable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE);
52 if (tcet && !tcet->nb_table) {
53 *(uint32_t *)opaque = tcet->liobn;
54 return 1;
56 return 0;
59 static unsigned spapr_phb_get_free_liobn(SpaprPhbState *sphb)
61 uint32_t liobn = 0;
63 object_child_foreach(OBJECT(sphb), spapr_phb_get_free_liobn_cb, &liobn);
65 return liobn;
68 static uint32_t spapr_page_mask_to_query_mask(uint64_t page_mask)
70 int i;
71 uint32_t mask = 0;
72 const struct { int shift; uint32_t mask; } masks[] = {
73 { 12, RTAS_DDW_PGSIZE_4K },
74 { 16, RTAS_DDW_PGSIZE_64K },
75 { 24, RTAS_DDW_PGSIZE_16M },
76 { 25, RTAS_DDW_PGSIZE_32M },
77 { 26, RTAS_DDW_PGSIZE_64M },
78 { 27, RTAS_DDW_PGSIZE_128M },
79 { 28, RTAS_DDW_PGSIZE_256M },
80 { 34, RTAS_DDW_PGSIZE_16G },
83 for (i = 0; i < ARRAY_SIZE(masks); ++i) {
84 if (page_mask & (1ULL << masks[i].shift)) {
85 mask |= masks[i].mask;
89 return mask;
92 static void rtas_ibm_query_pe_dma_window(PowerPCCPU *cpu,
93 SpaprMachineState *spapr,
94 uint32_t token, uint32_t nargs,
95 target_ulong args,
96 uint32_t nret, target_ulong rets)
98 SpaprPhbState *sphb;
99 uint64_t buid;
100 uint32_t avail, addr, pgmask = 0;
102 if ((nargs != 3) || (nret != 5)) {
103 goto param_error_exit;
106 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
107 addr = rtas_ld(args, 0);
108 sphb = spapr_pci_find_phb(spapr, buid);
109 if (!sphb || !sphb->ddw_enabled) {
110 goto param_error_exit;
113 /* Translate page mask to LoPAPR format */
114 pgmask = spapr_page_mask_to_query_mask(sphb->page_size_mask);
116 avail = SPAPR_PCI_DMA_MAX_WINDOWS - spapr_phb_get_active_win_num(sphb);
118 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
119 rtas_st(rets, 1, avail);
120 rtas_st(rets, 2, 0x80000000); /* The largest window we can possibly have */
121 rtas_st(rets, 3, pgmask);
122 rtas_st(rets, 4, 0); /* DMA migration mask, not supported */
124 trace_spapr_iommu_ddw_query(buid, addr, avail, 0x80000000, pgmask);
125 return;
127 param_error_exit:
128 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
131 static void rtas_ibm_create_pe_dma_window(PowerPCCPU *cpu,
132 SpaprMachineState *spapr,
133 uint32_t token, uint32_t nargs,
134 target_ulong args,
135 uint32_t nret, target_ulong rets)
137 SpaprPhbState *sphb;
138 SpaprTceTable *tcet = NULL;
139 uint32_t addr, page_shift, window_shift, liobn;
140 uint64_t buid, win_addr;
141 int windows;
143 if ((nargs != 5) || (nret != 4)) {
144 goto param_error_exit;
147 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
148 addr = rtas_ld(args, 0);
149 sphb = spapr_pci_find_phb(spapr, buid);
150 if (!sphb || !sphb->ddw_enabled) {
151 goto param_error_exit;
154 page_shift = rtas_ld(args, 3);
155 window_shift = rtas_ld(args, 4);
156 liobn = spapr_phb_get_free_liobn(sphb);
157 windows = spapr_phb_get_active_win_num(sphb);
159 if (!(sphb->page_size_mask & (1ULL << page_shift)) ||
160 (window_shift < page_shift)) {
161 goto param_error_exit;
164 if (!liobn || !sphb->ddw_enabled || windows == SPAPR_PCI_DMA_MAX_WINDOWS) {
165 goto hw_error_exit;
168 tcet = spapr_tce_find_by_liobn(liobn);
169 if (!tcet) {
170 goto hw_error_exit;
173 win_addr = (windows == 0) ? sphb->dma_win_addr : sphb->dma64_win_addr;
175 * We have just created a window, we know for the fact that it is empty,
176 * use a hack to avoid iterating over the table as it is quite possible
177 * to have billions of TCEs, all empty.
178 * Note that we cannot delay this to the first H_PUT_TCE as this hcall is
179 * mostly likely to be handled in KVM so QEMU just does not know if it
180 * happened.
182 tcet->skipping_replay = true;
183 spapr_tce_table_enable(tcet, page_shift, win_addr,
184 1ULL << (window_shift - page_shift));
185 tcet->skipping_replay = false;
186 if (!tcet->nb_table) {
187 goto hw_error_exit;
190 trace_spapr_iommu_ddw_create(buid, addr, 1ULL << page_shift,
191 1ULL << window_shift, tcet->bus_offset, liobn);
193 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
194 rtas_st(rets, 1, liobn);
195 rtas_st(rets, 2, tcet->bus_offset >> 32);
196 rtas_st(rets, 3, tcet->bus_offset & ((uint32_t) -1));
198 return;
200 hw_error_exit:
201 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
202 return;
204 param_error_exit:
205 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
208 static void rtas_ibm_remove_pe_dma_window(PowerPCCPU *cpu,
209 SpaprMachineState *spapr,
210 uint32_t token, uint32_t nargs,
211 target_ulong args,
212 uint32_t nret, target_ulong rets)
214 SpaprPhbState *sphb;
215 SpaprTceTable *tcet;
216 uint32_t liobn;
218 if ((nargs != 1) || (nret != 1)) {
219 goto param_error_exit;
222 liobn = rtas_ld(args, 0);
223 tcet = spapr_tce_find_by_liobn(liobn);
224 if (!tcet) {
225 goto param_error_exit;
228 sphb = SPAPR_PCI_HOST_BRIDGE(OBJECT(tcet)->parent);
229 if (!sphb || !sphb->ddw_enabled || !tcet->nb_table) {
230 goto param_error_exit;
233 spapr_tce_table_disable(tcet);
234 trace_spapr_iommu_ddw_remove(liobn);
236 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
237 return;
239 param_error_exit:
240 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
243 static void rtas_ibm_reset_pe_dma_window(PowerPCCPU *cpu,
244 SpaprMachineState *spapr,
245 uint32_t token, uint32_t nargs,
246 target_ulong args,
247 uint32_t nret, target_ulong rets)
249 SpaprPhbState *sphb;
250 uint64_t buid;
251 uint32_t addr;
253 if ((nargs != 3) || (nret != 1)) {
254 goto param_error_exit;
257 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
258 addr = rtas_ld(args, 0);
259 sphb = spapr_pci_find_phb(spapr, buid);
260 if (!sphb || !sphb->ddw_enabled) {
261 goto param_error_exit;
264 spapr_phb_dma_reset(sphb);
265 trace_spapr_iommu_ddw_reset(buid, addr);
267 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
269 return;
271 param_error_exit:
272 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
275 static void spapr_rtas_ddw_init(void)
277 spapr_rtas_register(RTAS_IBM_QUERY_PE_DMA_WINDOW,
278 "ibm,query-pe-dma-window",
279 rtas_ibm_query_pe_dma_window);
280 spapr_rtas_register(RTAS_IBM_CREATE_PE_DMA_WINDOW,
281 "ibm,create-pe-dma-window",
282 rtas_ibm_create_pe_dma_window);
283 spapr_rtas_register(RTAS_IBM_REMOVE_PE_DMA_WINDOW,
284 "ibm,remove-pe-dma-window",
285 rtas_ibm_remove_pe_dma_window);
286 spapr_rtas_register(RTAS_IBM_RESET_PE_DMA_WINDOW,
287 "ibm,reset-pe-dma-window",
288 rtas_ibm_reset_pe_dma_window);
291 type_init(spapr_rtas_ddw_init)