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arm: Rename hw/arm/arm.h to hw/arm/boot.h
[qemu/ar7.git] / hw / ppc / spapr_pci.c
blob97961b012859e730be4d758c7d7a691544ca5091
1 /*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/hw.h"
30 #include "hw/sysbus.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/address-spaces.h"
38 #include "exec/ram_addr.h"
39 #include <libfdt.h>
40 #include "trace.h"
41 #include "qemu/error-report.h"
42 #include "qapi/qmp/qerror.h"
43 #include "hw/ppc/fdt.h"
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/pci/pci_ids.h"
47 #include "hw/ppc/spapr_drc.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/hostmem.h"
51 #include "sysemu/numa.h"
52
53 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
54 #define RTAS_QUERY_FN 0
55 #define RTAS_CHANGE_FN 1
56 #define RTAS_RESET_FN 2
57 #define RTAS_CHANGE_MSI_FN 3
58 #define RTAS_CHANGE_MSIX_FN 4
59
60 /* Interrupt types to return on RTAS_CHANGE_* */
61 #define RTAS_TYPE_MSI 1
62 #define RTAS_TYPE_MSIX 2
63
64 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid)
65 {
66 SpaprPhbState *sphb;
67
68 QLIST_FOREACH(sphb, &spapr->phbs, list) {
69 if (sphb->buid != buid) {
70 continue;
71 }
72 return sphb;
73 }
74
75 return NULL;
76 }
77
78 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
79 uint32_t config_addr)
80 {
81 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid);
82 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
83 int bus_num = (config_addr >> 16) & 0xFF;
84 int devfn = (config_addr >> 8) & 0xFF;
85
86 if (!phb) {
87 return NULL;
88 }
89
90 return pci_find_device(phb->bus, bus_num, devfn);
91 }
92
93 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
94 {
95 /* This handles the encoding of extended config space addresses */
96 return ((arg >> 20) & 0xf00) | (arg & 0xff);
97 }
98
99 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid,
100 uint32_t addr, uint32_t size,
101 target_ulong rets)
102 {
103 PCIDevice *pci_dev;
104 uint32_t val;
105
106 if ((size != 1) && (size != 2) && (size != 4)) {
107 /* access must be 1, 2 or 4 bytes */
108 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
109 return;
110 }
111
112 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
113 addr = rtas_pci_cfgaddr(addr);
114
115 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
116 /* Access must be to a valid device, within bounds and
117 * naturally aligned */
118 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
119 return;
120 }
121
122 val = pci_host_config_read_common(pci_dev, addr,
123 pci_config_size(pci_dev), size);
124
125 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
126 rtas_st(rets, 1, val);
127 }
128
129 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
130 uint32_t token, uint32_t nargs,
131 target_ulong args,
132 uint32_t nret, target_ulong rets)
133 {
134 uint64_t buid;
135 uint32_t size, addr;
136
137 if ((nargs != 4) || (nret != 2)) {
138 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
139 return;
140 }
141
142 buid = rtas_ldq(args, 1);
143 size = rtas_ld(args, 3);
144 addr = rtas_ld(args, 0);
145
146 finish_read_pci_config(spapr, buid, addr, size, rets);
147 }
148
149 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
150 uint32_t token, uint32_t nargs,
151 target_ulong args,
152 uint32_t nret, target_ulong rets)
153 {
154 uint32_t size, addr;
155
156 if ((nargs != 2) || (nret != 2)) {
157 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
158 return;
159 }
160
161 size = rtas_ld(args, 1);
162 addr = rtas_ld(args, 0);
163
164 finish_read_pci_config(spapr, 0, addr, size, rets);
165 }
166
167 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid,
168 uint32_t addr, uint32_t size,
169 uint32_t val, target_ulong rets)
170 {
171 PCIDevice *pci_dev;
172
173 if ((size != 1) && (size != 2) && (size != 4)) {
174 /* access must be 1, 2 or 4 bytes */
175 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
176 return;
177 }
178
179 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
180 addr = rtas_pci_cfgaddr(addr);
181
182 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
183 /* Access must be to a valid device, within bounds and
184 * naturally aligned */
185 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
186 return;
187 }
188
189 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
190 val, size);
191
192 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
193 }
194
195 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
196 uint32_t token, uint32_t nargs,
197 target_ulong args,
198 uint32_t nret, target_ulong rets)
199 {
200 uint64_t buid;
201 uint32_t val, size, addr;
202
203 if ((nargs != 5) || (nret != 1)) {
204 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
205 return;
206 }
207
208 buid = rtas_ldq(args, 1);
209 val = rtas_ld(args, 4);
210 size = rtas_ld(args, 3);
211 addr = rtas_ld(args, 0);
212
213 finish_write_pci_config(spapr, buid, addr, size, val, rets);
214 }
215
216 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
217 uint32_t token, uint32_t nargs,
218 target_ulong args,
219 uint32_t nret, target_ulong rets)
220 {
221 uint32_t val, size, addr;
222
223 if ((nargs != 3) || (nret != 1)) {
224 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
225 return;
226 }
227
228
229 val = rtas_ld(args, 2);
230 size = rtas_ld(args, 1);
231 addr = rtas_ld(args, 0);
232
233 finish_write_pci_config(spapr, 0, addr, size, val, rets);
234 }
235
236 /*
237 * Set MSI/MSIX message data.
238 * This is required for msi_notify()/msix_notify() which
239 * will write at the addresses via spapr_msi_write().
240 *
241 * If hwaddr == 0, all entries will have .data == first_irq i.e.
242 * table will be reset.
243 */
244 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
245 unsigned first_irq, unsigned req_num)
246 {
247 unsigned i;
248 MSIMessage msg = { .address = addr, .data = first_irq };
249
250 if (!msix) {
251 msi_set_message(pdev, msg);
252 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
253 return;
254 }
255
256 for (i = 0; i < req_num; ++i) {
257 msix_set_message(pdev, i, msg);
258 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
259 if (addr) {
260 ++msg.data;
261 }
262 }
263 }
264
265 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
266 uint32_t token, uint32_t nargs,
267 target_ulong args, uint32_t nret,
268 target_ulong rets)
269 {
270 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
271 uint32_t config_addr = rtas_ld(args, 0);
272 uint64_t buid = rtas_ldq(args, 1);
273 unsigned int func = rtas_ld(args, 3);
274 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
275 unsigned int seq_num = rtas_ld(args, 5);
276 unsigned int ret_intr_type;
277 unsigned int irq, max_irqs = 0;
278 SpaprPhbState *phb = NULL;
279 PCIDevice *pdev = NULL;
280 spapr_pci_msi *msi;
281 int *config_addr_key;
282 Error *err = NULL;
283 int i;
284
285 /* Fins SpaprPhbState */
286 phb = spapr_pci_find_phb(spapr, buid);
287 if (phb) {
288 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
289 }
290 if (!phb || !pdev) {
291 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
292 return;
293 }
294
295 switch (func) {
296 case RTAS_CHANGE_FN:
297 if (msi_present(pdev)) {
298 ret_intr_type = RTAS_TYPE_MSI;
299 } else if (msix_present(pdev)) {
300 ret_intr_type = RTAS_TYPE_MSIX;
301 } else {
302 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
303 return;
304 }
305 break;
306 case RTAS_CHANGE_MSI_FN:
307 if (msi_present(pdev)) {
308 ret_intr_type = RTAS_TYPE_MSI;
309 } else {
310 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
311 return;
312 }
313 break;
314 case RTAS_CHANGE_MSIX_FN:
315 if (msix_present(pdev)) {
316 ret_intr_type = RTAS_TYPE_MSIX;
317 } else {
318 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
319 return;
320 }
321 break;
322 default:
323 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
324 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
325 return;
326 }
327
328 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
329
330 /* Releasing MSIs */
331 if (!req_num) {
332 if (!msi) {
333 trace_spapr_pci_msi("Releasing wrong config", config_addr);
334 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
335 return;
336 }
337
338 if (!smc->legacy_irq_allocation) {
339 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
340 }
341 spapr_irq_free(spapr, msi->first_irq, msi->num);
342 if (msi_present(pdev)) {
343 spapr_msi_setmsg(pdev, 0, false, 0, 0);
344 }
345 if (msix_present(pdev)) {
346 spapr_msi_setmsg(pdev, 0, true, 0, 0);
347 }
348 g_hash_table_remove(phb->msi, &config_addr);
349
350 trace_spapr_pci_msi("Released MSIs", config_addr);
351 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
352 rtas_st(rets, 1, 0);
353 return;
354 }
355
356 /* Enabling MSI */
357
358 /* Check if the device supports as many IRQs as requested */
359 if (ret_intr_type == RTAS_TYPE_MSI) {
360 max_irqs = msi_nr_vectors_allocated(pdev);
361 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
362 max_irqs = pdev->msix_entries_nr;
363 }
364 if (!max_irqs) {
365 error_report("Requested interrupt type %d is not enabled for device %x",
366 ret_intr_type, config_addr);
367 rtas_st(rets, 0, -1); /* Hardware error */
368 return;
369 }
370 /* Correct the number if the guest asked for too many */
371 if (req_num > max_irqs) {
372 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
373 req_num = max_irqs;
374 irq = 0; /* to avoid misleading trace */
375 goto out;
376 }
377
378 /* Allocate MSIs */
379 if (smc->legacy_irq_allocation) {
380 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
381 &err);
382 } else {
383 irq = spapr_irq_msi_alloc(spapr, req_num,
384 ret_intr_type == RTAS_TYPE_MSI, &err);
385 }
386 if (err) {
387 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
388 config_addr);
389 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
390 return;
391 }
392
393 for (i = 0; i < req_num; i++) {
394 spapr_irq_claim(spapr, irq + i, false, &err);
395 if (err) {
396 if (i) {
397 spapr_irq_free(spapr, irq, i);
398 }
399 if (!smc->legacy_irq_allocation) {
400 spapr_irq_msi_free(spapr, irq, req_num);
401 }
402 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
403 config_addr);
404 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
405 return;
406 }
407 }
408
409 /* Release previous MSIs */
410 if (msi) {
411 if (!smc->legacy_irq_allocation) {
412 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
413 }
414 spapr_irq_free(spapr, msi->first_irq, msi->num);
415 g_hash_table_remove(phb->msi, &config_addr);
416 }
417
418 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
419 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
420 irq, req_num);
421
422 /* Add MSI device to cache */
423 msi = g_new(spapr_pci_msi, 1);
424 msi->first_irq = irq;
425 msi->num = req_num;
426 config_addr_key = g_new(int, 1);
427 *config_addr_key = config_addr;
428 g_hash_table_insert(phb->msi, config_addr_key, msi);
429
430 out:
431 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
432 rtas_st(rets, 1, req_num);
433 rtas_st(rets, 2, ++seq_num);
434 if (nret > 3) {
435 rtas_st(rets, 3, ret_intr_type);
436 }
437
438 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
439 }
440
441 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
442 SpaprMachineState *spapr,
443 uint32_t token,
444 uint32_t nargs,
445 target_ulong args,
446 uint32_t nret,
447 target_ulong rets)
448 {
449 uint32_t config_addr = rtas_ld(args, 0);
450 uint64_t buid = rtas_ldq(args, 1);
451 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
452 SpaprPhbState *phb = NULL;
453 PCIDevice *pdev = NULL;
454 spapr_pci_msi *msi;
455
456 /* Find SpaprPhbState */
457 phb = spapr_pci_find_phb(spapr, buid);
458 if (phb) {
459 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
460 }
461 if (!phb || !pdev) {
462 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
463 return;
464 }
465
466 /* Find device descriptor and start IRQ */
467 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
468 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
469 trace_spapr_pci_msi("Failed to return vector", config_addr);
470 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
471 return;
472 }
473 intr_src_num = msi->first_irq + ioa_intr_num;
474 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
475 intr_src_num);
476
477 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
478 rtas_st(rets, 1, intr_src_num);
479 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
480 }
481
482 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
483 SpaprMachineState *spapr,
484 uint32_t token, uint32_t nargs,
485 target_ulong args, uint32_t nret,
486 target_ulong rets)
487 {
488 SpaprPhbState *sphb;
489 uint32_t addr, option;
490 uint64_t buid;
491 int ret;
492
493 if ((nargs != 4) || (nret != 1)) {
494 goto param_error_exit;
495 }
496
497 buid = rtas_ldq(args, 1);
498 addr = rtas_ld(args, 0);
499 option = rtas_ld(args, 3);
500
501 sphb = spapr_pci_find_phb(spapr, buid);
502 if (!sphb) {
503 goto param_error_exit;
504 }
505
506 if (!spapr_phb_eeh_available(sphb)) {
507 goto param_error_exit;
508 }
509
510 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
511 rtas_st(rets, 0, ret);
512 return;
513
514 param_error_exit:
515 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
516 }
517
518 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
519 SpaprMachineState *spapr,
520 uint32_t token, uint32_t nargs,
521 target_ulong args, uint32_t nret,
522 target_ulong rets)
523 {
524 SpaprPhbState *sphb;
525 PCIDevice *pdev;
526 uint32_t addr, option;
527 uint64_t buid;
528
529 if ((nargs != 4) || (nret != 2)) {
530 goto param_error_exit;
531 }
532
533 buid = rtas_ldq(args, 1);
534 sphb = spapr_pci_find_phb(spapr, buid);
535 if (!sphb) {
536 goto param_error_exit;
537 }
538
539 if (!spapr_phb_eeh_available(sphb)) {
540 goto param_error_exit;
541 }
542
543 /*
544 * We always have PE address of form "00BB0001". "BB"
545 * represents the bus number of PE's primary bus.
546 */
547 option = rtas_ld(args, 3);
548 switch (option) {
549 case RTAS_GET_PE_ADDR:
550 addr = rtas_ld(args, 0);
551 pdev = spapr_pci_find_dev(spapr, buid, addr);
552 if (!pdev) {
553 goto param_error_exit;
554 }
555
556 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
557 break;
558 case RTAS_GET_PE_MODE:
559 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
560 break;
561 default:
562 goto param_error_exit;
563 }
564
565 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
566 return;
567
568 param_error_exit:
569 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
570 }
571
572 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
573 SpaprMachineState *spapr,
574 uint32_t token, uint32_t nargs,
575 target_ulong args, uint32_t nret,
576 target_ulong rets)
577 {
578 SpaprPhbState *sphb;
579 uint64_t buid;
580 int state, ret;
581
582 if ((nargs != 3) || (nret != 4 && nret != 5)) {
583 goto param_error_exit;
584 }
585
586 buid = rtas_ldq(args, 1);
587 sphb = spapr_pci_find_phb(spapr, buid);
588 if (!sphb) {
589 goto param_error_exit;
590 }
591
592 if (!spapr_phb_eeh_available(sphb)) {
593 goto param_error_exit;
594 }
595
596 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
597 rtas_st(rets, 0, ret);
598 if (ret != RTAS_OUT_SUCCESS) {
599 return;
600 }
601
602 rtas_st(rets, 1, state);
603 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
604 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
605 if (nret >= 5) {
606 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
607 }
608 return;
609
610 param_error_exit:
611 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
612 }
613
614 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
615 SpaprMachineState *spapr,
616 uint32_t token, uint32_t nargs,
617 target_ulong args, uint32_t nret,
618 target_ulong rets)
619 {
620 SpaprPhbState *sphb;
621 uint32_t option;
622 uint64_t buid;
623 int ret;
624
625 if ((nargs != 4) || (nret != 1)) {
626 goto param_error_exit;
627 }
628
629 buid = rtas_ldq(args, 1);
630 option = rtas_ld(args, 3);
631 sphb = spapr_pci_find_phb(spapr, buid);
632 if (!sphb) {
633 goto param_error_exit;
634 }
635
636 if (!spapr_phb_eeh_available(sphb)) {
637 goto param_error_exit;
638 }
639
640 ret = spapr_phb_vfio_eeh_reset(sphb, option);
641 rtas_st(rets, 0, ret);
642 return;
643
644 param_error_exit:
645 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
646 }
647
648 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
649 SpaprMachineState *spapr,
650 uint32_t token, uint32_t nargs,
651 target_ulong args, uint32_t nret,
652 target_ulong rets)
653 {
654 SpaprPhbState *sphb;
655 uint64_t buid;
656 int ret;
657
658 if ((nargs != 3) || (nret != 1)) {
659 goto param_error_exit;
660 }
661
662 buid = rtas_ldq(args, 1);
663 sphb = spapr_pci_find_phb(spapr, buid);
664 if (!sphb) {
665 goto param_error_exit;
666 }
667
668 if (!spapr_phb_eeh_available(sphb)) {
669 goto param_error_exit;
670 }
671
672 ret = spapr_phb_vfio_eeh_configure(sphb);
673 rtas_st(rets, 0, ret);
674 return;
675
676 param_error_exit:
677 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
678 }
679
680 /* To support it later */
681 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
682 SpaprMachineState *spapr,
683 uint32_t token, uint32_t nargs,
684 target_ulong args, uint32_t nret,
685 target_ulong rets)
686 {
687 SpaprPhbState *sphb;
688 int option;
689 uint64_t buid;
690
691 if ((nargs != 8) || (nret != 1)) {
692 goto param_error_exit;
693 }
694
695 buid = rtas_ldq(args, 1);
696 sphb = spapr_pci_find_phb(spapr, buid);
697 if (!sphb) {
698 goto param_error_exit;
699 }
700
701 if (!spapr_phb_eeh_available(sphb)) {
702 goto param_error_exit;
703 }
704
705 option = rtas_ld(args, 7);
706 switch (option) {
707 case RTAS_SLOT_TEMP_ERR_LOG:
708 case RTAS_SLOT_PERM_ERR_LOG:
709 break;
710 default:
711 goto param_error_exit;
712 }
713
714 /* We don't have error log yet */
715 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
716 return;
717
718 param_error_exit:
719 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
720 }
721
722 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
723 {
724 /*
725 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
726 * corresponding qemu_irq.
727 */
728 SpaprPhbState *phb = opaque;
729
730 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
731 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
732 }
733
734 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
735 {
736 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
737 PCIINTxRoute route;
738
739 route.mode = PCI_INTX_ENABLED;
740 route.irq = sphb->lsi_table[pin].irq;
741
742 return route;
743 }
744
745 /*
746 * MSI/MSIX memory region implementation.
747 * The handler handles both MSI and MSIX.
748 * The vector number is encoded in least bits in data.
749 */
750 static void spapr_msi_write(void *opaque, hwaddr addr,
751 uint64_t data, unsigned size)
752 {
753 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
754 uint32_t irq = data;
755
756 trace_spapr_pci_msi_write(addr, data, irq);
757
758 qemu_irq_pulse(spapr_qirq(spapr, irq));
759 }
760
761 static const MemoryRegionOps spapr_msi_ops = {
762 /* There is no .read as the read result is undefined by PCI spec */
763 .read = NULL,
764 .write = spapr_msi_write,
765 .endianness = DEVICE_LITTLE_ENDIAN
766 };
767
768 /*
769 * PHB PCI device
770 */
771 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
772 {
773 SpaprPhbState *phb = opaque;
774
775 return &phb->iommu_as;
776 }
777
778 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
779 {
780 char *path = NULL, *buf = NULL, *host = NULL;
781
782 /* Get the PCI VFIO host id */
783 host = object_property_get_str(OBJECT(pdev), "host", NULL);
784 if (!host) {
785 goto err_out;
786 }
787
788 /* Construct the path of the file that will give us the DT location */
789 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
790 g_free(host);
791 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
792 goto err_out;
793 }
794 g_free(path);
795
796 /* Construct and read from host device tree the loc-code */
797 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
798 g_free(buf);
799 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
800 goto err_out;
801 }
802 return buf;
803
804 err_out:
805 g_free(path);
806 return NULL;
807 }
808
809 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
810 {
811 char *buf;
812 const char *devtype = "qemu";
813 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
814
815 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
816 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
817 if (buf) {
818 return buf;
819 }
820 devtype = "vfio";
821 }
822 /*
823 * For emulated devices and VFIO-failure case, make up
824 * the loc-code.
825 */
826 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
827 devtype, pdev->name, sphb->index, busnr,
828 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
829 return buf;
830 }
831
832 /* Macros to operate with address in OF binding to PCI */
833 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
834 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
835 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
836 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
837 #define b_ss(x) b_x((x), 24, 2) /* the space code */
838 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
839 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
840 #define b_fff(x) b_x((x), 8, 3) /* function number */
841 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
842
843 /* for 'reg'/'assigned-addresses' OF properties */
844 #define RESOURCE_CELLS_SIZE 2
845 #define RESOURCE_CELLS_ADDRESS 3
846
847 typedef struct ResourceFields {
848 uint32_t phys_hi;
849 uint32_t phys_mid;
850 uint32_t phys_lo;
851 uint32_t size_hi;
852 uint32_t size_lo;
853 } QEMU_PACKED ResourceFields;
854
855 typedef struct ResourceProps {
856 ResourceFields reg[8];
857 ResourceFields assigned[7];
858 uint32_t reg_len;
859 uint32_t assigned_len;
860 } ResourceProps;
861
862 /* fill in the 'reg'/'assigned-resources' OF properties for
863 * a PCI device. 'reg' describes resource requirements for a
864 * device's IO/MEM regions, 'assigned-addresses' describes the
865 * actual resource assignments.
866 *
867 * the properties are arrays of ('phys-addr', 'size') pairs describing
868 * the addressable regions of the PCI device, where 'phys-addr' is a
869 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
870 * (phys.hi, phys.mid, phys.lo), and 'size' is a
871 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
872 *
873 * phys.hi = 0xYYXXXXZZ, where:
874 * 0xYY = npt000ss
875 * ||| |
876 * ||| +-- space code
877 * ||| |
878 * ||| + 00 if configuration space
879 * ||| + 01 if IO region,
880 * ||| + 10 if 32-bit MEM region
881 * ||| + 11 if 64-bit MEM region
882 * |||
883 * ||+------ for non-relocatable IO: 1 if aliased
884 * || for relocatable IO: 1 if below 64KB
885 * || for MEM: 1 if below 1MB
886 * |+------- 1 if region is prefetchable
887 * +-------- 1 if region is non-relocatable
888 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
889 * bits respectively
890 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
891 * to the region
892 *
893 * phys.mid and phys.lo correspond respectively to the hi/lo portions
894 * of the actual address of the region.
895 *
896 * how the phys-addr/size values are used differ slightly between
897 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
898 * an additional description for the config space region of the
899 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
900 * to describe the region as relocatable, with an address-mapping
901 * that corresponds directly to the PHB's address space for the
902 * resource. 'assigned-addresses' always has n=1 set with an absolute
903 * address assigned for the resource. in general, 'assigned-addresses'
904 * won't be populated, since addresses for PCI devices are generally
905 * unmapped initially and left to the guest to assign.
906 *
907 * note also that addresses defined in these properties are, at least
908 * for PAPR guests, relative to the PHBs IO/MEM windows, and
909 * correspond directly to the addresses in the BARs.
910 *
911 * in accordance with PCI Bus Binding to Open Firmware,
912 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
913 * Appendix C.
914 */
915 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
916 {
917 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
918 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
919 b_ddddd(PCI_SLOT(d->devfn)) |
920 b_fff(PCI_FUNC(d->devfn)));
921 ResourceFields *reg, *assigned;
922 int i, reg_idx = 0, assigned_idx = 0;
923
924 /* config space region */
925 reg = &rp->reg[reg_idx++];
926 reg->phys_hi = cpu_to_be32(dev_id);
927 reg->phys_mid = 0;
928 reg->phys_lo = 0;
929 reg->size_hi = 0;
930 reg->size_lo = 0;
931
932 for (i = 0; i < PCI_NUM_REGIONS; i++) {
933 if (!d->io_regions[i].size) {
934 continue;
935 }
936
937 reg = &rp->reg[reg_idx++];
938
939 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
940 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
941 reg->phys_hi |= cpu_to_be32(b_ss(1));
942 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
943 reg->phys_hi |= cpu_to_be32(b_ss(3));
944 } else {
945 reg->phys_hi |= cpu_to_be32(b_ss(2));
946 }
947 reg->phys_mid = 0;
948 reg->phys_lo = 0;
949 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
950 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
951
952 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
953 continue;
954 }
955
956 assigned = &rp->assigned[assigned_idx++];
957 assigned->phys_hi = cpu_to_be32(be32_to_cpu(reg->phys_hi) | b_n(1));
958 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
959 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
960 assigned->size_hi = reg->size_hi;
961 assigned->size_lo = reg->size_lo;
962 }
963
964 rp->reg_len = reg_idx * sizeof(ResourceFields);
965 rp->assigned_len = assigned_idx * sizeof(ResourceFields);
966 }
967
968 typedef struct PCIClass PCIClass;
969 typedef struct PCISubClass PCISubClass;
970 typedef struct PCIIFace PCIIFace;
971
972 struct PCIIFace {
973 int iface;
974 const char *name;
975 };
976
977 struct PCISubClass {
978 int subclass;
979 const char *name;
980 const PCIIFace *iface;
981 };
982
983 struct PCIClass {
984 const char *name;
985 const PCISubClass *subc;
986 };
987
988 static const PCISubClass undef_subclass[] = {
989 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
990 { 0xFF, NULL, NULL },
991 };
992
993 static const PCISubClass mass_subclass[] = {
994 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
995 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
996 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
997 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
998 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
999 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
1000 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
1001 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
1002 { 0xFF, NULL, NULL },
1003 };
1004
1005 static const PCISubClass net_subclass[] = {
1006 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
1007 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
1008 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
1009 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
1010 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
1011 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
1012 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
1013 { 0xFF, NULL, NULL },
1014 };
1015
1016 static const PCISubClass displ_subclass[] = {
1017 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
1018 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
1019 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
1020 { 0xFF, NULL, NULL },
1021 };
1022
1023 static const PCISubClass media_subclass[] = {
1024 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1025 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1026 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1027 { 0xFF, NULL, NULL },
1028 };
1029
1030 static const PCISubClass mem_subclass[] = {
1031 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1032 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1033 { 0xFF, NULL, NULL },
1034 };
1035
1036 static const PCISubClass bridg_subclass[] = {
1037 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1038 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1039 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1040 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1041 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1042 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1043 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1044 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1045 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1046 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1047 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1048 { 0xFF, NULL, NULL },
1049 };
1050
1051 static const PCISubClass comm_subclass[] = {
1052 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1053 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1054 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1055 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1056 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1057 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1058 { 0xFF, NULL, NULL, },
1059 };
1060
1061 static const PCIIFace pic_iface[] = {
1062 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1063 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1064 { 0xFF, NULL },
1065 };
1066
1067 static const PCISubClass sys_subclass[] = {
1068 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1069 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1070 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1071 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1072 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1073 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1074 { 0xFF, NULL, NULL },
1075 };
1076
1077 static const PCISubClass inp_subclass[] = {
1078 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1079 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1080 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1081 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1082 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1083 { 0xFF, NULL, NULL },
1084 };
1085
1086 static const PCISubClass dock_subclass[] = {
1087 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1088 { 0xFF, NULL, NULL },
1089 };
1090
1091 static const PCISubClass cpu_subclass[] = {
1092 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1093 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1094 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1095 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1096 { 0xFF, NULL, NULL },
1097 };
1098
1099 static const PCIIFace usb_iface[] = {
1100 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1101 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1102 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1103 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1104 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1105 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1106 { 0xFF, NULL },
1107 };
1108
1109 static const PCISubClass ser_subclass[] = {
1110 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1111 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1112 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1113 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1114 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1115 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1116 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1117 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1118 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1119 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1120 { 0xFF, NULL, NULL },
1121 };
1122
1123 static const PCISubClass wrl_subclass[] = {
1124 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1125 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1126 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1127 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1128 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1129 { 0xFF, NULL, NULL },
1130 };
1131
1132 static const PCISubClass sat_subclass[] = {
1133 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1134 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1135 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1136 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1137 { 0xFF, NULL, NULL },
1138 };
1139
1140 static const PCISubClass crypt_subclass[] = {
1141 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1142 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1143 "entertainment-encryption", NULL },
1144 { 0xFF, NULL, NULL },
1145 };
1146
1147 static const PCISubClass spc_subclass[] = {
1148 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1149 { PCI_CLASS_SP_PERF, "counter", NULL },
1150 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1151 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1152 { 0xFF, NULL, NULL },
1153 };
1154
1155 static const PCIClass pci_classes[] = {
1156 { "legacy-device", undef_subclass },
1157 { "mass-storage", mass_subclass },
1158 { "network", net_subclass },
1159 { "display", displ_subclass, },
1160 { "multimedia-device", media_subclass },
1161 { "memory-controller", mem_subclass },
1162 { "unknown-bridge", bridg_subclass },
1163 { "communication-controller", comm_subclass},
1164 { "system-peripheral", sys_subclass },
1165 { "input-controller", inp_subclass },
1166 { "docking-station", dock_subclass },
1167 { "cpu", cpu_subclass },
1168 { "serial-bus", ser_subclass },
1169 { "wireless-controller", wrl_subclass },
1170 { "intelligent-io", NULL },
1171 { "satellite-device", sat_subclass },
1172 { "encryption", crypt_subclass },
1173 { "data-processing-controller", spc_subclass },
1174 };
1175
1176 static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
1177 uint8_t iface)
1178 {
1179 const PCIClass *pclass;
1180 const PCISubClass *psubclass;
1181 const PCIIFace *piface;
1182 const char *name;
1183
1184 if (class >= ARRAY_SIZE(pci_classes)) {
1185 return "pci";
1186 }
1187
1188 pclass = pci_classes + class;
1189 name = pclass->name;
1190
1191 if (pclass->subc == NULL) {
1192 return name;
1193 }
1194
1195 psubclass = pclass->subc;
1196 while ((psubclass->subclass & 0xff) != 0xff) {
1197 if ((psubclass->subclass & 0xff) == subclass) {
1198 name = psubclass->name;
1199 break;
1200 }
1201 psubclass++;
1202 }
1203
1204 piface = psubclass->iface;
1205 if (piface == NULL) {
1206 return name;
1207 }
1208 while ((piface->iface & 0xff) != 0xff) {
1209 if ((piface->iface & 0xff) == iface) {
1210 name = piface->name;
1211 break;
1212 }
1213 piface++;
1214 }
1215
1216 return name;
1217 }
1218
1219 static gchar *pci_get_node_name(PCIDevice *dev)
1220 {
1221 int slot = PCI_SLOT(dev->devfn);
1222 int func = PCI_FUNC(dev->devfn);
1223 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1224 const char *name;
1225
1226 name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1227 ccode & 0xff);
1228
1229 if (func != 0) {
1230 return g_strdup_printf("%s@%x,%x", name, slot, func);
1231 } else {
1232 return g_strdup_printf("%s@%x", name, slot);
1233 }
1234 }
1235
1236 static uint32_t spapr_phb_get_pci_drc_index(SpaprPhbState *phb,
1237 PCIDevice *pdev);
1238
1239 static void spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
1240 SpaprPhbState *sphb)
1241 {
1242 ResourceProps rp;
1243 bool is_bridge = false;
1244 int pci_status;
1245 char *buf = NULL;
1246 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
1247 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1248 uint32_t max_msi, max_msix;
1249
1250 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
1251 PCI_HEADER_TYPE_BRIDGE) {
1252 is_bridge = true;
1253 }
1254
1255 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1256 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id",
1257 pci_default_read_config(dev, PCI_VENDOR_ID, 2)));
1258 _FDT(fdt_setprop_cell(fdt, offset, "device-id",
1259 pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
1260 _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
1261 pci_default_read_config(dev, PCI_REVISION_ID, 1)));
1262 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1263 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
1264 _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
1265 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
1266 }
1267
1268 if (!is_bridge) {
1269 _FDT(fdt_setprop_cell(fdt, offset, "min-grant",
1270 pci_default_read_config(dev, PCI_MIN_GNT, 1)));
1271 _FDT(fdt_setprop_cell(fdt, offset, "max-latency",
1272 pci_default_read_config(dev, PCI_MAX_LAT, 1)));
1273 }
1274
1275 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) {
1276 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id",
1277 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)));
1278 }
1279
1280 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) {
1281 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1282 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)));
1283 }
1284
1285 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size",
1286 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1)));
1287
1288 /* the following fdt cells are masked off the pci status register */
1289 pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1290 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1291 PCI_STATUS_DEVSEL_MASK & pci_status));
1292
1293 if (pci_status & PCI_STATUS_FAST_BACK) {
1294 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1295 }
1296 if (pci_status & PCI_STATUS_66MHZ) {
1297 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1298 }
1299 if (pci_status & PCI_STATUS_UDF) {
1300 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1301 }
1302
1303 _FDT(fdt_setprop_string(fdt, offset, "name",
1304 pci_find_device_name((ccode >> 16) & 0xff,
1305 (ccode >> 8) & 0xff,
1306 ccode & 0xff)));
1307
1308 buf = spapr_phb_get_loc_code(sphb, dev);
1309 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", buf));
1310 g_free(buf);
1311
1312 if (drc_index) {
1313 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index));
1314 }
1315
1316 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1317 RESOURCE_CELLS_ADDRESS));
1318 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1319 RESOURCE_CELLS_SIZE));
1320
1321 if (msi_present(dev)) {
1322 max_msi = msi_nr_vectors_allocated(dev);
1323 if (max_msi) {
1324 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1325 }
1326 }
1327 if (msix_present(dev)) {
1328 max_msix = dev->msix_entries_nr;
1329 if (max_msix) {
1330 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1331 }
1332 }
1333
1334 populate_resource_props(dev, &rp);
1335 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1336 _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1337 (uint8_t *)rp.assigned, rp.assigned_len));
1338
1339 if (sphb->pcie_ecs && pci_is_express(dev)) {
1340 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1341 }
1342
1343 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb);
1344 }
1345
1346 /* create OF node for pci device and required OF DT properties */
1347 static int spapr_create_pci_child_dt(SpaprPhbState *phb, PCIDevice *dev,
1348 void *fdt, int node_offset)
1349 {
1350 int offset;
1351 gchar *nodename;
1352
1353 nodename = pci_get_node_name(dev);
1354 _FDT(offset = fdt_add_subnode(fdt, node_offset, nodename));
1355 g_free(nodename);
1356
1357 spapr_populate_pci_child_dt(dev, fdt, offset, phb);
1358
1359 return offset;
1360 }
1361
1362 /* Callback to be called during DRC release. */
1363 void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1364 {
1365 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
1366
1367 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
1368 object_unparent(OBJECT(dev));
1369 }
1370
1371 static SpaprDrc *spapr_phb_get_pci_func_drc(SpaprPhbState *phb,
1372 uint32_t busnr,
1373 int32_t devfn)
1374 {
1375 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1376 (phb->index << 16) | (busnr << 8) | devfn);
1377 }
1378
1379 static SpaprDrc *spapr_phb_get_pci_drc(SpaprPhbState *phb,
1380 PCIDevice *pdev)
1381 {
1382 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
1383 return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn);
1384 }
1385
1386 static uint32_t spapr_phb_get_pci_drc_index(SpaprPhbState *phb,
1387 PCIDevice *pdev)
1388 {
1389 SpaprDrc *drc = spapr_phb_get_pci_drc(phb, pdev);
1390
1391 if (!drc) {
1392 return 0;
1393 }
1394
1395 return spapr_drc_index(drc);
1396 }
1397
1398 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
1399 void *fdt, int *fdt_start_offset, Error **errp)
1400 {
1401 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev);
1402 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler);
1403 PCIDevice *pdev = PCI_DEVICE(drc->dev);
1404
1405 *fdt_start_offset = spapr_create_pci_child_dt(sphb, pdev, fdt, 0);
1406 return 0;
1407 }
1408
1409 static void spapr_pci_plug(HotplugHandler *plug_handler,
1410 DeviceState *plugged_dev, Error **errp)
1411 {
1412 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1413 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1414 SpaprDrc *drc = spapr_phb_get_pci_drc(phb, pdev);
1415 Error *local_err = NULL;
1416 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1417 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1418
1419 /* if DR is disabled we don't need to do anything in the case of
1420 * hotplug or coldplug callbacks
1421 */
1422 if (!phb->dr_enabled) {
1423 /* if this is a hotplug operation initiated by the user
1424 * we need to let them know it's not enabled
1425 */
1426 if (plugged_dev->hotplugged) {
1427 error_setg(&local_err, QERR_BUS_NO_HOTPLUG,
1428 object_get_typename(OBJECT(phb)));
1429 }
1430 goto out;
1431 }
1432
1433 g_assert(drc);
1434
1435 /* Following the QEMU convention used for PCIe multifunction
1436 * hotplug, we do not allow functions to be hotplugged to a
1437 * slot that already has function 0 present
1438 */
1439 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1440 PCI_FUNC(pdev->devfn) != 0) {
1441 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s,"
1442 " additional functions can no longer be exposed to guest.",
1443 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1444 goto out;
1445 }
1446
1447 spapr_drc_attach(drc, DEVICE(pdev), &local_err);
1448 if (local_err) {
1449 goto out;
1450 }
1451
1452 /* If this is function 0, signal hotplug for all the device functions.
1453 * Otherwise defer sending the hotplug event.
1454 */
1455 if (!spapr_drc_hotplugged(plugged_dev)) {
1456 spapr_drc_reset(drc);
1457 } else if (PCI_FUNC(pdev->devfn) == 0) {
1458 int i;
1459
1460 for (i = 0; i < 8; i++) {
1461 SpaprDrc *func_drc;
1462 SpaprDrcClass *func_drck;
1463 SpaprDREntitySense state;
1464
1465 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1466 PCI_DEVFN(slotnr, i));
1467 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1468 state = func_drck->dr_entity_sense(func_drc);
1469
1470 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1471 spapr_hotplug_req_add_by_index(func_drc);
1472 }
1473 }
1474 }
1475
1476 out:
1477 error_propagate(errp, local_err);
1478 }
1479
1480 static void spapr_pci_unplug(HotplugHandler *plug_handler,
1481 DeviceState *plugged_dev, Error **errp)
1482 {
1483 /* some version guests do not wait for completion of a device
1484 * cleanup (generally done asynchronously by the kernel) before
1485 * signaling to QEMU that the device is safe, but instead sleep
1486 * for some 'safe' period of time. unfortunately on a busy host
1487 * this sleep isn't guaranteed to be long enough, resulting in
1488 * bad things like IRQ lines being left asserted during final
1489 * device removal. to deal with this we call reset just prior
1490 * to finalizing the device, which will put the device back into
1491 * an 'idle' state, as the device cleanup code expects.
1492 */
1493 pci_device_reset(PCI_DEVICE(plugged_dev));
1494 object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL);
1495 }
1496
1497 static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1498 DeviceState *plugged_dev, Error **errp)
1499 {
1500 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1501 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1502 SpaprDrc *drc = spapr_phb_get_pci_drc(phb, pdev);
1503
1504 if (!phb->dr_enabled) {
1505 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1506 object_get_typename(OBJECT(phb)));
1507 return;
1508 }
1509
1510 g_assert(drc);
1511 g_assert(drc->dev == plugged_dev);
1512
1513 if (!spapr_drc_unplug_requested(drc)) {
1514 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1515 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1516 SpaprDrc *func_drc;
1517 SpaprDrcClass *func_drck;
1518 SpaprDREntitySense state;
1519 int i;
1520
1521 /* ensure any other present functions are pending unplug */
1522 if (PCI_FUNC(pdev->devfn) == 0) {
1523 for (i = 1; i < 8; i++) {
1524 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1525 PCI_DEVFN(slotnr, i));
1526 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1527 state = func_drck->dr_entity_sense(func_drc);
1528 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1529 && !spapr_drc_unplug_requested(func_drc)) {
1530 error_setg(errp,
1531 "PCI: slot %d, function %d still present. "
1532 "Must unplug all non-0 functions first.",
1533 slotnr, i);
1534 return;
1535 }
1536 }
1537 }
1538
1539 spapr_drc_detach(drc);
1540
1541 /* if this isn't func 0, defer unplug event. otherwise signal removal
1542 * for all present functions
1543 */
1544 if (PCI_FUNC(pdev->devfn) == 0) {
1545 for (i = 7; i >= 0; i--) {
1546 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1547 PCI_DEVFN(slotnr, i));
1548 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1549 state = func_drck->dr_entity_sense(func_drc);
1550 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1551 spapr_hotplug_req_remove_by_index(func_drc);
1552 }
1553 }
1554 }
1555 }
1556 }
1557
1558 static void spapr_phb_finalizefn(Object *obj)
1559 {
1560 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj);
1561
1562 g_free(sphb->dtbusname);
1563 sphb->dtbusname = NULL;
1564 }
1565
1566 static void spapr_phb_unrealize(DeviceState *dev, Error **errp)
1567 {
1568 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1569 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1570 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1571 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb);
1572 SpaprTceTable *tcet;
1573 int i;
1574 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1575
1576 spapr_phb_nvgpu_free(sphb);
1577
1578 if (sphb->msi) {
1579 g_hash_table_unref(sphb->msi);
1580 sphb->msi = NULL;
1581 }
1582
1583 /*
1584 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1585 * via PHB's unrealize->object_finalize
1586 */
1587 for (i = windows_supported - 1; i >= 0; i--) {
1588 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1589 if (tcet) {
1590 memory_region_del_subregion(&sphb->iommu_root,
1591 spapr_tce_get_iommu(tcet));
1592 }
1593 }
1594
1595 if (sphb->dr_enabled) {
1596 for (i = PCI_SLOT_MAX * 8 - 1; i >= 0; i--) {
1597 SpaprDrc *drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1598 (sphb->index << 16) | i);
1599
1600 if (drc) {
1601 object_unparent(OBJECT(drc));
1602 }
1603 }
1604 }
1605
1606 for (i = PCI_NUM_PINS - 1; i >= 0; i--) {
1607 if (sphb->lsi_table[i].irq) {
1608 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1);
1609 sphb->lsi_table[i].irq = 0;
1610 }
1611 }
1612
1613 QLIST_REMOVE(sphb, list);
1614
1615 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow);
1616
1617 address_space_destroy(&sphb->iommu_as);
1618
1619 qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort);
1620 pci_unregister_root_bus(phb->bus);
1621
1622 memory_region_del_subregion(get_system_memory(), &sphb->iowindow);
1623 if (sphb->mem64_win_pciaddr != (hwaddr)-1) {
1624 memory_region_del_subregion(get_system_memory(), &sphb->mem64window);
1625 }
1626 memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
1627 }
1628
1629 static bool spapr_phb_allows_extended_config_space(PCIBus *bus)
1630 {
1631 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(BUS(bus)->parent);
1632
1633 return sphb->pcie_ecs;
1634 }
1635
1636 static void spapr_phb_root_bus_class_init(ObjectClass *klass, void *data)
1637 {
1638 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
1639
1640 pbc->allows_extended_config_space = spapr_phb_allows_extended_config_space;
1641 }
1642
1643 #define TYPE_SPAPR_PHB_ROOT_BUS "pci"
1644
1645 static const TypeInfo spapr_phb_root_bus_info = {
1646 .name = TYPE_SPAPR_PHB_ROOT_BUS,
1647 .parent = TYPE_PCI_BUS,
1648 .class_init = spapr_phb_root_bus_class_init,
1649 };
1650
1651 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1652 {
1653 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1654 * tries to add a sPAPR PHB to a non-pseries machine.
1655 */
1656 SpaprMachineState *spapr =
1657 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
1658 TYPE_SPAPR_MACHINE);
1659 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL;
1660 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1661 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1662 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1663 char *namebuf;
1664 int i;
1665 PCIBus *bus;
1666 uint64_t msi_window_size = 4096;
1667 SpaprTceTable *tcet;
1668 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1669
1670 if (!spapr) {
1671 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1672 return;
1673 }
1674
1675 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1676
1677 if (sphb->mem64_win_size != 0) {
1678 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1679 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1680 " (max 2 GiB)", sphb->mem_win_size);
1681 return;
1682 }
1683
1684 /* 64-bit window defaults to identity mapping */
1685 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1686 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1687 /*
1688 * For compatibility with old configuration, if no 64-bit MMIO
1689 * window is specified, but the ordinary (32-bit) memory
1690 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1691 * window, with a 64-bit MMIO window following on immediately
1692 * afterwards
1693 */
1694 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1695 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1696 sphb->mem64_win_pciaddr =
1697 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1698 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1699 }
1700
1701 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1702 error_setg(errp, "PCI host bridges must have unique BUIDs");
1703 return;
1704 }
1705
1706 if (sphb->numa_node != -1 &&
1707 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1708 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1709 return;
1710 }
1711
1712 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1713
1714 /* Initialize memory regions */
1715 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1716 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1717 g_free(namebuf);
1718
1719 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1720 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1721 namebuf, &sphb->memspace,
1722 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1723 g_free(namebuf);
1724 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1725 &sphb->mem32window);
1726
1727 if (sphb->mem64_win_size != 0) {
1728 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1729 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1730 namebuf, &sphb->memspace,
1731 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1732 g_free(namebuf);
1733
1734 memory_region_add_subregion(get_system_memory(),
1735 sphb->mem64_win_addr,
1736 &sphb->mem64window);
1737 }
1738
1739 /* Initialize IO regions */
1740 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1741 memory_region_init(&sphb->iospace, OBJECT(sphb),
1742 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1743 g_free(namebuf);
1744
1745 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1746 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1747 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1748 g_free(namebuf);
1749 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1750 &sphb->iowindow);
1751
1752 bus = pci_register_root_bus(dev, NULL,
1753 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
1754 &sphb->memspace, &sphb->iospace,
1755 PCI_DEVFN(0, 0), PCI_NUM_PINS,
1756 TYPE_SPAPR_PHB_ROOT_BUS);
1757 phb->bus = bus;
1758 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL);
1759
1760 /*
1761 * Initialize PHB address space.
1762 * By default there will be at least one subregion for default
1763 * 32bit DMA window.
1764 * Later the guest might want to create another DMA window
1765 * which will become another memory subregion.
1766 */
1767 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1768 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1769 namebuf, UINT64_MAX);
1770 g_free(namebuf);
1771 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1772 sphb->dtbusname);
1773
1774 /*
1775 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1776 * we need to allocate some memory to catch those writes coming
1777 * from msi_notify()/msix_notify().
1778 * As MSIMessage:addr is going to be the same and MSIMessage:data
1779 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1780 * be used.
1781 *
1782 * For KVM we want to ensure that this memory is a full page so that
1783 * our memory slot is of page size granularity.
1784 */
1785 #ifdef CONFIG_KVM
1786 if (kvm_enabled()) {
1787 msi_window_size = getpagesize();
1788 }
1789 #endif
1790
1791 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1792 "msi", msi_window_size);
1793 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1794 &sphb->msiwindow);
1795
1796 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1797
1798 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1799
1800 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1801
1802 /* Initialize the LSI table */
1803 for (i = 0; i < PCI_NUM_PINS; i++) {
1804 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
1805 Error *local_err = NULL;
1806
1807 if (smc->legacy_irq_allocation) {
1808 irq = spapr_irq_findone(spapr, &local_err);
1809 if (local_err) {
1810 error_propagate_prepend(errp, local_err,
1811 "can't allocate LSIs: ");
1812 /*
1813 * Older machines will never support PHB hotplug, ie, this is an
1814 * init only path and QEMU will terminate. No need to rollback.
1815 */
1816 return;
1817 }
1818 }
1819
1820 spapr_irq_claim(spapr, irq, true, &local_err);
1821 if (local_err) {
1822 error_propagate_prepend(errp, local_err, "can't allocate LSIs: ");
1823 goto unrealize;
1824 }
1825
1826 sphb->lsi_table[i].irq = irq;
1827 }
1828
1829 /* allocate connectors for child PCI devices */
1830 if (sphb->dr_enabled) {
1831 for (i = 0; i < PCI_SLOT_MAX * 8; i++) {
1832 spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI,
1833 (sphb->index << 16) | i);
1834 }
1835 }
1836
1837 /* DMA setup */
1838 for (i = 0; i < windows_supported; ++i) {
1839 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1840 if (!tcet) {
1841 error_setg(errp, "Creating window#%d failed for %s",
1842 i, sphb->dtbusname);
1843 goto unrealize;
1844 }
1845 memory_region_add_subregion(&sphb->iommu_root, 0,
1846 spapr_tce_get_iommu(tcet));
1847 }
1848
1849 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
1850 return;
1851
1852 unrealize:
1853 spapr_phb_unrealize(dev, NULL);
1854 }
1855
1856 static int spapr_phb_children_reset(Object *child, void *opaque)
1857 {
1858 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1859
1860 if (dev) {
1861 device_reset(dev);
1862 }
1863
1864 return 0;
1865 }
1866
1867 void spapr_phb_dma_reset(SpaprPhbState *sphb)
1868 {
1869 int i;
1870 SpaprTceTable *tcet;
1871
1872 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1873 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1874
1875 if (tcet && tcet->nb_table) {
1876 spapr_tce_table_disable(tcet);
1877 }
1878 }
1879
1880 /* Register default 32bit DMA window */
1881 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
1882 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
1883 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
1884 }
1885
1886 static void spapr_phb_reset(DeviceState *qdev)
1887 {
1888 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
1889 Error *errp = NULL;
1890
1891 spapr_phb_dma_reset(sphb);
1892 spapr_phb_nvgpu_free(sphb);
1893 spapr_phb_nvgpu_setup(sphb, &errp);
1894 if (errp) {
1895 error_report_err(errp);
1896 }
1897
1898 /* Reset the IOMMU state */
1899 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
1900
1901 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
1902 spapr_phb_vfio_reset(qdev);
1903 }
1904 }
1905
1906 static Property spapr_phb_properties[] = {
1907 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1),
1908 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size,
1909 SPAPR_PCI_MEM32_WIN_SIZE),
1910 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size,
1911 SPAPR_PCI_MEM64_WIN_SIZE),
1912 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size,
1913 SPAPR_PCI_IO_WIN_SIZE),
1914 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled,
1915 true),
1916 /* Default DMA window is 0..1GB */
1917 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0),
1918 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000),
1919 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr,
1920 0x800000000000000ULL),
1921 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true),
1922 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask,
1923 (1ULL << 12) | (1ULL << 16)),
1924 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
1925 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState,
1926 pre_2_8_migration, false),
1927 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
1928 pcie_ecs, true),
1929 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0),
1930 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0),
1931 DEFINE_PROP_END_OF_LIST(),
1932 };
1933
1934 static const VMStateDescription vmstate_spapr_pci_lsi = {
1935 .name = "spapr_pci/lsi",
1936 .version_id = 1,
1937 .minimum_version_id = 1,
1938 .fields = (VMStateField[]) {
1939 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
1940
1941 VMSTATE_END_OF_LIST()
1942 },
1943 };
1944
1945 static const VMStateDescription vmstate_spapr_pci_msi = {
1946 .name = "spapr_pci/msi",
1947 .version_id = 1,
1948 .minimum_version_id = 1,
1949 .fields = (VMStateField []) {
1950 VMSTATE_UINT32(key, spapr_pci_msi_mig),
1951 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
1952 VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1953 VMSTATE_END_OF_LIST()
1954 },
1955 };
1956
1957 static int spapr_pci_pre_save(void *opaque)
1958 {
1959 SpaprPhbState *sphb = opaque;
1960 GHashTableIter iter;
1961 gpointer key, value;
1962 int i;
1963
1964 if (sphb->pre_2_8_migration) {
1965 sphb->mig_liobn = sphb->dma_liobn[0];
1966 sphb->mig_mem_win_addr = sphb->mem_win_addr;
1967 sphb->mig_mem_win_size = sphb->mem_win_size;
1968 sphb->mig_io_win_addr = sphb->io_win_addr;
1969 sphb->mig_io_win_size = sphb->io_win_size;
1970
1971 if ((sphb->mem64_win_size != 0)
1972 && (sphb->mem64_win_addr
1973 == (sphb->mem_win_addr + sphb->mem_win_size))) {
1974 sphb->mig_mem_win_size += sphb->mem64_win_size;
1975 }
1976 }
1977
1978 g_free(sphb->msi_devs);
1979 sphb->msi_devs = NULL;
1980 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
1981 if (!sphb->msi_devs_num) {
1982 return 0;
1983 }
1984 sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num);
1985
1986 g_hash_table_iter_init(&iter, sphb->msi);
1987 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
1988 sphb->msi_devs[i].key = *(uint32_t *) key;
1989 sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
1990 }
1991
1992 return 0;
1993 }
1994
1995 static int spapr_pci_post_load(void *opaque, int version_id)
1996 {
1997 SpaprPhbState *sphb = opaque;
1998 gpointer key, value;
1999 int i;
2000
2001 for (i = 0; i < sphb->msi_devs_num; ++i) {
2002 key = g_memdup(&sphb->msi_devs[i].key,
2003 sizeof(sphb->msi_devs[i].key));
2004 value = g_memdup(&sphb->msi_devs[i].value,
2005 sizeof(sphb->msi_devs[i].value));
2006 g_hash_table_insert(sphb->msi, key, value);
2007 }
2008 g_free(sphb->msi_devs);
2009 sphb->msi_devs = NULL;
2010 sphb->msi_devs_num = 0;
2011
2012 return 0;
2013 }
2014
2015 static bool pre_2_8_migration(void *opaque, int version_id)
2016 {
2017 SpaprPhbState *sphb = opaque;
2018
2019 return sphb->pre_2_8_migration;
2020 }
2021
2022 static const VMStateDescription vmstate_spapr_pci = {
2023 .name = "spapr_pci",
2024 .version_id = 2,
2025 .minimum_version_id = 2,
2026 .pre_save = spapr_pci_pre_save,
2027 .post_load = spapr_pci_post_load,
2028 .fields = (VMStateField[]) {
2029 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL),
2030 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration),
2031 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration),
2032 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration),
2033 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration),
2034 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration),
2035 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
2036 vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
2037 VMSTATE_INT32(msi_devs_num, SpaprPhbState),
2038 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
2039 vmstate_spapr_pci_msi, spapr_pci_msi_mig),
2040 VMSTATE_END_OF_LIST()
2041 },
2042 };
2043
2044 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
2045 PCIBus *rootbus)
2046 {
2047 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
2048
2049 return sphb->dtbusname;
2050 }
2051
2052 static void spapr_phb_class_init(ObjectClass *klass, void *data)
2053 {
2054 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
2055 DeviceClass *dc = DEVICE_CLASS(klass);
2056 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
2057
2058 hc->root_bus_path = spapr_phb_root_bus_path;
2059 dc->realize = spapr_phb_realize;
2060 dc->unrealize = spapr_phb_unrealize;
2061 dc->props = spapr_phb_properties;
2062 dc->reset = spapr_phb_reset;
2063 dc->vmsd = &vmstate_spapr_pci;
2064 /* Supported by TYPE_SPAPR_MACHINE */
2065 dc->user_creatable = true;
2066 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
2067 hp->plug = spapr_pci_plug;
2068 hp->unplug = spapr_pci_unplug;
2069 hp->unplug_request = spapr_pci_unplug_request;
2070 }
2071
2072 static const TypeInfo spapr_phb_info = {
2073 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
2074 .parent = TYPE_PCI_HOST_BRIDGE,
2075 .instance_size = sizeof(SpaprPhbState),
2076 .instance_finalize = spapr_phb_finalizefn,
2077 .class_init = spapr_phb_class_init,
2078 .interfaces = (InterfaceInfo[]) {
2079 { TYPE_HOTPLUG_HANDLER },
2080 { }
2081 }
2082 };
2083
2084 typedef struct SpaprFdt {
2085 void *fdt;
2086 int node_off;
2087 SpaprPhbState *sphb;
2088 } SpaprFdt;
2089
2090 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev,
2091 void *opaque)
2092 {
2093 PCIBus *sec_bus;
2094 SpaprFdt *p = opaque;
2095 int offset;
2096 SpaprFdt s_fdt;
2097
2098 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off);
2099 if (!offset) {
2100 error_report("Failed to create pci child device tree node");
2101 return;
2102 }
2103
2104 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2105 PCI_HEADER_TYPE_BRIDGE)) {
2106 return;
2107 }
2108
2109 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2110 if (!sec_bus) {
2111 return;
2112 }
2113
2114 s_fdt.fdt = p->fdt;
2115 s_fdt.node_off = offset;
2116 s_fdt.sphb = p->sphb;
2117 pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus),
2118 spapr_populate_pci_devices_dt,
2119 &s_fdt);
2120 }
2121
2122 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2123 void *opaque)
2124 {
2125 unsigned int *bus_no = opaque;
2126 PCIBus *sec_bus = NULL;
2127
2128 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2129 PCI_HEADER_TYPE_BRIDGE)) {
2130 return;
2131 }
2132
2133 (*bus_no)++;
2134 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
2135 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2136 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2137
2138 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2139 if (!sec_bus) {
2140 return;
2141 }
2142
2143 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2144 spapr_phb_pci_enumerate_bridge, bus_no);
2145 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2146 }
2147
2148 static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
2149 {
2150 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2151 unsigned int bus_no = 0;
2152
2153 pci_for_each_device(bus, pci_bus_num(bus),
2154 spapr_phb_pci_enumerate_bridge,
2155 &bus_no);
2156
2157 }
2158
2159 int spapr_populate_pci_dt(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
2160 uint32_t nr_msis, int *node_offset)
2161 {
2162 int bus_off, i, j, ret;
2163 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2164 struct {
2165 uint32_t hi;
2166 uint64_t child;
2167 uint64_t parent;
2168 uint64_t size;
2169 } QEMU_PACKED ranges[] = {
2170 {
2171 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2172 cpu_to_be64(phb->io_win_addr),
2173 cpu_to_be64(memory_region_size(&phb->iospace)),
2174 },
2175 {
2176 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2177 cpu_to_be64(phb->mem_win_addr),
2178 cpu_to_be64(phb->mem_win_size),
2179 },
2180 {
2181 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2182 cpu_to_be64(phb->mem64_win_addr),
2183 cpu_to_be64(phb->mem64_win_size),
2184 },
2185 };
2186 const unsigned sizeof_ranges =
2187 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2188 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2189 uint32_t interrupt_map_mask[] = {
2190 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2191 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2192 uint32_t ddw_applicable[] = {
2193 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2194 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2195 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2196 };
2197 uint32_t ddw_extensions[] = {
2198 cpu_to_be32(1),
2199 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2200 };
2201 uint32_t associativity[] = {cpu_to_be32(0x4),
2202 cpu_to_be32(0x0),
2203 cpu_to_be32(0x0),
2204 cpu_to_be32(0x0),
2205 cpu_to_be32(phb->numa_node)};
2206 SpaprTceTable *tcet;
2207 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2208 SpaprFdt s_fdt;
2209 SpaprDrc *drc;
2210 Error *errp = NULL;
2211
2212 /* Start populating the FDT */
2213 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname));
2214 if (node_offset) {
2215 *node_offset = bus_off;
2216 }
2217
2218 /* Write PHB properties */
2219 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2220 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2221 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
2222 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
2223 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2224 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2225 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2226 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2227 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2228 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2229 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis));
2230
2231 /* Dynamic DMA window */
2232 if (phb->ddw_enabled) {
2233 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2234 sizeof(ddw_applicable)));
2235 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2236 &ddw_extensions, sizeof(ddw_extensions)));
2237 }
2238
2239 /* Advertise NUMA via ibm,associativity */
2240 if (phb->numa_node != -1) {
2241 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2242 sizeof(associativity)));
2243 }
2244
2245 /* Build the interrupt-map, this must matches what is done
2246 * in pci_swizzle_map_irq_fn
2247 */
2248 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2249 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2250 for (i = 0; i < PCI_SLOT_MAX; i++) {
2251 for (j = 0; j < PCI_NUM_PINS; j++) {
2252 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2253 int lsi_num = pci_swizzle(i, j);
2254
2255 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2256 irqmap[1] = 0;
2257 irqmap[2] = 0;
2258 irqmap[3] = cpu_to_be32(j+1);
2259 irqmap[4] = cpu_to_be32(intc_phandle);
2260 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
2261 }
2262 }
2263 /* Write interrupt map */
2264 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2265 sizeof(interrupt_map)));
2266
2267 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2268 if (!tcet) {
2269 return -1;
2270 }
2271 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2272 tcet->liobn, tcet->bus_offset,
2273 tcet->nb_table << tcet->page_shift);
2274
2275 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index);
2276 if (drc) {
2277 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc));
2278
2279 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index,
2280 sizeof(drc_index)));
2281 }
2282
2283 /* Walk the bridges and program the bus numbers*/
2284 spapr_phb_pci_enumerate(phb);
2285 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2286
2287 /* Populate tree nodes with PCI devices attached */
2288 s_fdt.fdt = fdt;
2289 s_fdt.node_off = bus_off;
2290 s_fdt.sphb = phb;
2291 pci_for_each_device_reverse(bus, pci_bus_num(bus),
2292 spapr_populate_pci_devices_dt,
2293 &s_fdt);
2294
2295 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb),
2296 SPAPR_DR_CONNECTOR_TYPE_PCI);
2297 if (ret) {
2298 return ret;
2299 }
2300
2301 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp);
2302 if (errp) {
2303 error_report_err(errp);
2304 }
2305 spapr_phb_nvgpu_ram_populate_dt(phb, fdt);
2306
2307 return 0;
2308 }
2309
2310 void spapr_pci_rtas_init(void)
2311 {
2312 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2313 rtas_read_pci_config);
2314 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2315 rtas_write_pci_config);
2316 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2317 rtas_ibm_read_pci_config);
2318 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2319 rtas_ibm_write_pci_config);
2320 if (msi_nonbroken) {
2321 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2322 "ibm,query-interrupt-source-number",
2323 rtas_ibm_query_interrupt_source_number);
2324 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2325 rtas_ibm_change_msi);
2326 }
2327
2328 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2329 "ibm,set-eeh-option",
2330 rtas_ibm_set_eeh_option);
2331 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2332 "ibm,get-config-addr-info2",
2333 rtas_ibm_get_config_addr_info2);
2334 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2335 "ibm,read-slot-reset-state2",
2336 rtas_ibm_read_slot_reset_state2);
2337 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2338 "ibm,set-slot-reset",
2339 rtas_ibm_set_slot_reset);
2340 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2341 "ibm,configure-pe",
2342 rtas_ibm_configure_pe);
2343 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2344 "ibm,slot-error-detail",
2345 rtas_ibm_slot_error_detail);
2346 }
2347
2348 static void spapr_pci_register_types(void)
2349 {
2350 type_register_static(&spapr_phb_info);
2351 type_register_static(&spapr_phb_root_bus_info);
2352 }
2353
2354 type_init(spapr_pci_register_types)
2355
2356 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2357 {
2358 bool be = *(bool *)opaque;
2359
2360 if (object_dynamic_cast(OBJECT(dev), "VGA")
2361 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2362 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2363 &error_abort);
2364 }
2365 return 0;
2366 }
2367
2368 void spapr_pci_switch_vga(bool big_endian)
2369 {
2370 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2371 SpaprPhbState *sphb;
2372
2373 /*
2374 * For backward compatibility with existing guests, we switch
2375 * the endianness of the VGA controller when changing the guest
2376 * interrupt mode
2377 */
2378 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2379 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2380 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2381 &big_endian);
2382 }
2383 }
AR7 emulation for QEMU