hw/ppc/pnv_lpc.c

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "sysemu/sysemu.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qapi/error.h"
  24 #include "qemu/log.h"
  25 #include "hw/isa/isa.h"
  26
  27 #include "hw/ppc/pnv.h"
  28 #include "hw/ppc/pnv_lpc.h"
  29 #include "hw/ppc/pnv_xscom.h"
  30 #include "hw/ppc/fdt.h"
  31
  32 #include <libfdt.h>
  33
  34 enum {
  35     ECCB_CTL    = 0,
  36     ECCB_RESET  = 1,
  37     ECCB_STAT   = 2,
  38     ECCB_DATA   = 3,
  39 };
  40
  41 /* OPB Master LS registers */
  42 #define OPB_MASTER_LS_ROUTE0    0x8
  43 #define OPB_MASTER_LS_ROUTE1    0xC
  44 #define OPB_MASTER_LS_IRQ_STAT  0x50
  45 #define   OPB_MASTER_IRQ_LPC            0x00000800
  46 #define OPB_MASTER_LS_IRQ_MASK  0x54
  47 #define OPB_MASTER_LS_IRQ_POL   0x58
  48 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
  49
  50 /* LPC HC registers */
  51 #define LPC_HC_FW_SEG_IDSEL     0x24
  52 #define LPC_HC_FW_RD_ACC_SIZE   0x28
  53 #define   LPC_HC_FW_RD_1B               0x00000000
  54 #define   LPC_HC_FW_RD_2B               0x01000000
  55 #define   LPC_HC_FW_RD_4B               0x02000000
  56 #define   LPC_HC_FW_RD_16B              0x04000000
  57 #define   LPC_HC_FW_RD_128B             0x07000000
  58 #define LPC_HC_IRQSER_CTRL      0x30
  59 #define   LPC_HC_IRQSER_EN              0x80000000
  60 #define   LPC_HC_IRQSER_QMODE           0x40000000
  61 #define   LPC_HC_IRQSER_START_MASK      0x03000000
  62 #define   LPC_HC_IRQSER_START_4CLK      0x00000000
  63 #define   LPC_HC_IRQSER_START_6CLK      0x01000000
  64 #define   LPC_HC_IRQSER_START_8CLK      0x02000000
  65 #define LPC_HC_IRQMASK          0x34    /* same bit defs as LPC_HC_IRQSTAT */
  66 #define LPC_HC_IRQSTAT          0x38
  67 #define   LPC_HC_IRQ_SERIRQ0            0x80000000 /* all bits down to ... */
  68 #define   LPC_HC_IRQ_SERIRQ16           0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
  69 #define   LPC_HC_IRQ_SERIRQ_ALL         0xffff8000
  70 #define   LPC_HC_IRQ_LRESET             0x00000400
  71 #define   LPC_HC_IRQ_SYNC_ABNORM_ERR    0x00000080
  72 #define   LPC_HC_IRQ_SYNC_NORESP_ERR    0x00000040
  73 #define   LPC_HC_IRQ_SYNC_NORM_ERR      0x00000020
  74 #define   LPC_HC_IRQ_SYNC_TIMEOUT_ERR   0x00000010
  75 #define   LPC_HC_IRQ_SYNC_TARG_TAR_ERR  0x00000008
  76 #define   LPC_HC_IRQ_SYNC_BM_TAR_ERR    0x00000004
  77 #define   LPC_HC_IRQ_SYNC_BM0_REQ       0x00000002
  78 #define   LPC_HC_IRQ_SYNC_BM1_REQ       0x00000001
  79 #define LPC_HC_ERROR_ADDRESS    0x40
  80
  81 #define LPC_OPB_SIZE            0x100000000ull
  82
  83 #define ISA_IO_SIZE             0x00010000
  84 #define ISA_MEM_SIZE            0x10000000
  85 #define ISA_FW_SIZE             0x10000000
  86 #define LPC_IO_OPB_ADDR         0xd0010000
  87 #define LPC_IO_OPB_SIZE         0x00010000
  88 #define LPC_MEM_OPB_ADDR        0xe0010000
  89 #define LPC_MEM_OPB_SIZE        0x10000000
  90 #define LPC_FW_OPB_ADDR         0xf0000000
  91 #define LPC_FW_OPB_SIZE         0x10000000
  92
  93 #define LPC_OPB_REGS_OPB_ADDR   0xc0010000
  94 #define LPC_OPB_REGS_OPB_SIZE   0x00000060
  95 #define LPC_OPB_REGS_OPBA_ADDR  0xc0011000
  96 #define LPC_OPB_REGS_OPBA_SIZE  0x00000008
  97 #define LPC_HC_REGS_OPB_ADDR    0xc0012000
  98 #define LPC_HC_REGS_OPB_SIZE    0x00000100
  99
 100 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 101 {
 102     const char compat[] = "ibm,power8-lpc\0ibm,lpc";
 103     char *name;
 104     int offset;
 105     uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
 106     uint32_t reg[] = {
 107         cpu_to_be32(lpc_pcba),
 108         cpu_to_be32(PNV_XSCOM_LPC_SIZE)
 109     };
 110
 111     name = g_strdup_printf("isa@%x", lpc_pcba);
 112     offset = fdt_add_subnode(fdt, xscom_offset, name);
 113     _FDT(offset);
 114     g_free(name);
 115
 116     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 117     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 118     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 119     _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
 120     return 0;
 121 }
 122
 123 /* POWER9 only */
 124 int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
 125 {
 126     const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
 127     const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
 128     char *name;
 129     int offset, lpcm_offset;
 130     uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
 131     uint32_t opb_ranges[8] = { 0,
 132                                cpu_to_be32(lpcm_addr >> 32),
 133                                cpu_to_be32((uint32_t)lpcm_addr),
 134                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 135                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 136                                cpu_to_be32(lpcm_addr >> 32),
 137                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 138                                cpu_to_be32(PNV9_LPCM_SIZE / 2),
 139     };
 140     uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
 141                             cpu_to_be32((uint32_t)lpcm_addr),
 142                             cpu_to_be32(PNV9_LPCM_SIZE >> 32),
 143                             cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
 144     };
 145     uint32_t reg[2];
 146
 147     /*
 148      * OPB bus
 149      */
 150     name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr);
 151     lpcm_offset = fdt_add_subnode(fdt, root_offset, name);
 152     _FDT(lpcm_offset);
 153     g_free(name);
 154
 155     _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg))));
 156     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1)));
 157     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1)));
 158     _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat))));
 159     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id)));
 160     _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges,
 161                       sizeof(opb_ranges))));
 162
 163     /*
 164      * OPB Master registers
 165      */
 166     name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR);
 167     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 168     _FDT(offset);
 169     g_free(name);
 170
 171     reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR);
 172     reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE);
 173     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 174     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 175                              "ibm,power9-lpcm-opb-master")));
 176
 177     /*
 178      * OPB arbitrer registers
 179      */
 180     name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR);
 181     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 182     _FDT(offset);
 183     g_free(name);
 184
 185     reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR);
 186     reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE);
 187     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 188     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 189                              "ibm,power9-lpcm-opb-arbiter")));
 190
 191     /*
 192      * LPC Host Controller registers
 193      */
 194     name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR);
 195     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 196     _FDT(offset);
 197     g_free(name);
 198
 199     reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR);
 200     reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE);
 201     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 202     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 203                              "ibm,power9-lpc-controller")));
 204
 205     name = g_strdup_printf("lpc@0");
 206     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 207     _FDT(offset);
 208     g_free(name);
 209     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 210     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 211     _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
 212                       sizeof(lpc_compat))));
 213
 214     return 0;
 215 }
 216
 217 /*
 218  * These read/write handlers of the OPB address space should be common
 219  * with the P9 LPC Controller which uses direct MMIOs.
 220  *
 221  * TODO: rework to use address_space_stq() and address_space_ldq()
 222  * instead.
 223  */
 224 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 225                      int sz)
 226 {
 227     /* XXX Handle access size limits and FW read caching here */
 228     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 229                              data, sz, false);
 230 }
 231
 232 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 233                       int sz)
 234 {
 235     /* XXX Handle access size limits here */
 236     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 237                              data, sz, true);
 238 }
 239
 240 #define ECCB_CTL_READ           PPC_BIT(15)
 241 #define ECCB_CTL_SZ_LSH         (63 - 7)
 242 #define ECCB_CTL_SZ_MASK        PPC_BITMASK(4, 7)
 243 #define ECCB_CTL_ADDR_MASK      PPC_BITMASK(32, 63)
 244
 245 #define ECCB_STAT_OP_DONE       PPC_BIT(52)
 246 #define ECCB_STAT_OP_ERR        PPC_BIT(52)
 247 #define ECCB_STAT_RD_DATA_LSH   (63 - 37)
 248 #define ECCB_STAT_RD_DATA_MASK  (0xffffffff << ECCB_STAT_RD_DATA_LSH)
 249
 250 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
 251 {
 252     /* XXX Check for magic bits at the top, addr size etc... */
 253     unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
 254     uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
 255     uint8_t data[8];
 256     bool success;
 257
 258     if (sz > sizeof(data)) {
 259         qemu_log_mask(LOG_GUEST_ERROR,
 260             "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz);
 261         return;
 262     }
 263
 264     if (cmd & ECCB_CTL_READ) {
 265         success = opb_read(lpc, opb_addr, data, sz);
 266         if (success) {
 267             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 268                     (((uint64_t)data[0]) << 24 |
 269                      ((uint64_t)data[1]) << 16 |
 270                      ((uint64_t)data[2]) <<  8 |
 271                      ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
 272         } else {
 273             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 274                     (0xffffffffull << ECCB_STAT_RD_DATA_LSH);
 275         }
 276     } else {
 277         data[0] = lpc->eccb_data_reg >> 24;
 278         data[1] = lpc->eccb_data_reg >> 16;
 279         data[2] = lpc->eccb_data_reg >>  8;
 280         data[3] = lpc->eccb_data_reg;
 281
 282         success = opb_write(lpc, opb_addr, data, sz);
 283         lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
 284     }
 285     /* XXX Which error bit (if any) to signal OPB error ? */
 286 }
 287
 288 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
 289 {
 290     PnvLpcController *lpc = PNV_LPC(opaque);
 291     uint32_t offset = addr >> 3;
 292     uint64_t val = 0;
 293
 294     switch (offset & 3) {
 295     case ECCB_CTL:
 296     case ECCB_RESET:
 297         val = 0;
 298         break;
 299     case ECCB_STAT:
 300         val = lpc->eccb_stat_reg;
 301         lpc->eccb_stat_reg = 0;
 302         break;
 303     case ECCB_DATA:
 304         val = ((uint64_t)lpc->eccb_data_reg) << 32;
 305         break;
 306     }
 307     return val;
 308 }
 309
 310 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
 311                                 uint64_t val, unsigned size)
 312 {
 313     PnvLpcController *lpc = PNV_LPC(opaque);
 314     uint32_t offset = addr >> 3;
 315
 316     switch (offset & 3) {
 317     case ECCB_CTL:
 318         pnv_lpc_do_eccb(lpc, val);
 319         break;
 320     case ECCB_RESET:
 321         /*  XXXX  */
 322         break;
 323     case ECCB_STAT:
 324         break;
 325     case ECCB_DATA:
 326         lpc->eccb_data_reg = val >> 32;
 327         break;
 328     }
 329 }
 330
 331 static const MemoryRegionOps pnv_lpc_xscom_ops = {
 332     .read = pnv_lpc_xscom_read,
 333     .write = pnv_lpc_xscom_write,
 334     .valid.min_access_size = 8,
 335     .valid.max_access_size = 8,
 336     .impl.min_access_size = 8,
 337     .impl.max_access_size = 8,
 338     .endianness = DEVICE_BIG_ENDIAN,
 339 };
 340
 341 static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
 342 {
 343     PnvLpcController *lpc = PNV_LPC(opaque);
 344     uint64_t val = 0;
 345     uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
 346     MemTxResult result;
 347
 348     switch (size) {
 349     case 4:
 350         val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
 351                                 &result);
 352         break;
 353     case 1:
 354         val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
 355                                  &result);
 356         break;
 357     default:
 358         qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
 359                       HWADDR_PRIx " invalid size %d\n", addr, size);
 360         return 0;
 361     }
 362
 363     if (result != MEMTX_OK) {
 364         qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
 365                       HWADDR_PRIx "\n", addr);
 366     }
 367
 368     return val;
 369 }
 370
 371 static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
 372                                 uint64_t val, unsigned size)
 373 {
 374     PnvLpcController *lpc = PNV_LPC(opaque);
 375     uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
 376     MemTxResult result;
 377
 378     switch (size) {
 379     case 4:
 380         address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
 381                           &result);
 382          break;
 383     case 1:
 384         address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
 385                           &result);
 386         break;
 387     default:
 388         qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
 389                       HWADDR_PRIx " invalid size %d\n", addr, size);
 390         return;
 391     }
 392
 393     if (result != MEMTX_OK) {
 394         qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
 395                       HWADDR_PRIx "\n", addr);
 396     }
 397 }
 398
 399 static const MemoryRegionOps pnv_lpc_mmio_ops = {
 400     .read = pnv_lpc_mmio_read,
 401     .write = pnv_lpc_mmio_write,
 402     .impl = {
 403         .min_access_size = 1,
 404         .max_access_size = 4,
 405     },
 406     .endianness = DEVICE_BIG_ENDIAN,
 407 };
 408
 409 static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
 410 {
 411     bool lpc_to_opb_irq = false;
 412     PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
 413
 414     /* Update LPC controller to OPB line */
 415     if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
 416         uint32_t irqs;
 417
 418         irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
 419         lpc_to_opb_irq = (irqs != 0);
 420     }
 421
 422     /* We don't honor the polarity register, it's pointless and unused
 423      * anyway
 424      */
 425     if (lpc_to_opb_irq) {
 426         lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
 427     } else {
 428         lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
 429     }
 430
 431     /* Update OPB internal latch */
 432     lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
 433
 434     /* Reflect the interrupt */
 435     pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
 436 }
 437
 438 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
 439 {
 440     PnvLpcController *lpc = opaque;
 441     uint64_t val = 0xfffffffffffffffful;
 442
 443     switch (addr) {
 444     case LPC_HC_FW_SEG_IDSEL:
 445         val =  lpc->lpc_hc_fw_seg_idsel;
 446         break;
 447     case LPC_HC_FW_RD_ACC_SIZE:
 448         val =  lpc->lpc_hc_fw_rd_acc_size;
 449         break;
 450     case LPC_HC_IRQSER_CTRL:
 451         val =  lpc->lpc_hc_irqser_ctrl;
 452         break;
 453     case LPC_HC_IRQMASK:
 454         val =  lpc->lpc_hc_irqmask;
 455         break;
 456     case LPC_HC_IRQSTAT:
 457         val =  lpc->lpc_hc_irqstat;
 458         break;
 459     case LPC_HC_ERROR_ADDRESS:
 460         val =  lpc->lpc_hc_error_addr;
 461         break;
 462     default:
 463         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
 464                       HWADDR_PRIx "\n", addr);
 465     }
 466     return val;
 467 }
 468
 469 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
 470                          unsigned size)
 471 {
 472     PnvLpcController *lpc = opaque;
 473
 474     /* XXX Filter out reserved bits */
 475
 476     switch (addr) {
 477     case LPC_HC_FW_SEG_IDSEL:
 478         /* XXX Actually figure out how that works as this impact
 479          * memory regions/aliases
 480          */
 481         lpc->lpc_hc_fw_seg_idsel = val;
 482         break;
 483     case LPC_HC_FW_RD_ACC_SIZE:
 484         lpc->lpc_hc_fw_rd_acc_size = val;
 485         break;
 486     case LPC_HC_IRQSER_CTRL:
 487         lpc->lpc_hc_irqser_ctrl = val;
 488         pnv_lpc_eval_irqs(lpc);
 489         break;
 490     case LPC_HC_IRQMASK:
 491         lpc->lpc_hc_irqmask = val;
 492         pnv_lpc_eval_irqs(lpc);
 493         break;
 494     case LPC_HC_IRQSTAT:
 495         lpc->lpc_hc_irqstat &= ~val;
 496         pnv_lpc_eval_irqs(lpc);
 497         break;
 498     case LPC_HC_ERROR_ADDRESS:
 499         break;
 500     default:
 501         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
 502                       HWADDR_PRIx "\n", addr);
 503     }
 504 }
 505
 506 static const MemoryRegionOps lpc_hc_ops = {
 507     .read = lpc_hc_read,
 508     .write = lpc_hc_write,
 509     .endianness = DEVICE_BIG_ENDIAN,
 510     .valid = {
 511         .min_access_size = 4,
 512         .max_access_size = 4,
 513     },
 514     .impl = {
 515         .min_access_size = 4,
 516         .max_access_size = 4,
 517     },
 518 };
 519
 520 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
 521 {
 522     PnvLpcController *lpc = opaque;
 523     uint64_t val = 0xfffffffffffffffful;
 524
 525     switch (addr) {
 526     case OPB_MASTER_LS_ROUTE0: /* TODO */
 527         val = lpc->opb_irq_route0;
 528         break;
 529     case OPB_MASTER_LS_ROUTE1: /* TODO */
 530         val = lpc->opb_irq_route1;
 531         break;
 532     case OPB_MASTER_LS_IRQ_STAT:
 533         val = lpc->opb_irq_stat;
 534         break;
 535     case OPB_MASTER_LS_IRQ_MASK:
 536         val = lpc->opb_irq_mask;
 537         break;
 538     case OPB_MASTER_LS_IRQ_POL:
 539         val = lpc->opb_irq_pol;
 540         break;
 541     case OPB_MASTER_LS_IRQ_INPUT:
 542         val = lpc->opb_irq_input;
 543         break;
 544     default:
 545         qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
 546                       HWADDR_PRIx "\n", addr);
 547     }
 548
 549     return val;
 550 }
 551
 552 static void opb_master_write(void *opaque, hwaddr addr,
 553                              uint64_t val, unsigned size)
 554 {
 555     PnvLpcController *lpc = opaque;
 556
 557     switch (addr) {
 558     case OPB_MASTER_LS_ROUTE0: /* TODO */
 559         lpc->opb_irq_route0 = val;
 560         break;
 561     case OPB_MASTER_LS_ROUTE1: /* TODO */
 562         lpc->opb_irq_route1 = val;
 563         break;
 564     case OPB_MASTER_LS_IRQ_STAT:
 565         lpc->opb_irq_stat &= ~val;
 566         pnv_lpc_eval_irqs(lpc);
 567         break;
 568     case OPB_MASTER_LS_IRQ_MASK:
 569         lpc->opb_irq_mask = val;
 570         pnv_lpc_eval_irqs(lpc);
 571         break;
 572     case OPB_MASTER_LS_IRQ_POL:
 573         lpc->opb_irq_pol = val;
 574         pnv_lpc_eval_irqs(lpc);
 575         break;
 576     case OPB_MASTER_LS_IRQ_INPUT:
 577         /* Read only */
 578         break;
 579     default:
 580         qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
 581                       HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
 582     }
 583 }
 584
 585 static const MemoryRegionOps opb_master_ops = {
 586     .read = opb_master_read,
 587     .write = opb_master_write,
 588     .endianness = DEVICE_BIG_ENDIAN,
 589     .valid = {
 590         .min_access_size = 4,
 591         .max_access_size = 4,
 592     },
 593     .impl = {
 594         .min_access_size = 4,
 595         .max_access_size = 4,
 596     },
 597 };
 598
 599 static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp)
 600 {
 601     PnvLpcController *lpc = PNV_LPC(dev);
 602     PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
 603     Error *local_err = NULL;
 604
 605     plc->parent_realize(dev, &local_err);
 606     if (local_err) {
 607         error_propagate(errp, local_err);
 608         return;
 609     }
 610
 611     /* P8 uses a XSCOM region for LPC registers */
 612     pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc),
 613                           &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
 614                           PNV_XSCOM_LPC_SIZE);
 615 }
 616
 617 static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
 618 {
 619     DeviceClass *dc = DEVICE_CLASS(klass);
 620     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 621     PnvLpcClass *plc = PNV_LPC_CLASS(klass);
 622
 623     dc->desc = "PowerNV LPC Controller POWER8";
 624
 625     xdc->dt_xscom = pnv_lpc_dt_xscom;
 626
 627     plc->psi_irq = PSIHB_IRQ_LPC_I2C;
 628
 629     device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
 630                                     &plc->parent_realize);
 631 }
 632
 633 static const TypeInfo pnv_lpc_power8_info = {
 634     .name          = TYPE_PNV8_LPC,
 635     .parent        = TYPE_PNV_LPC,
 636     .instance_size = sizeof(PnvLpcController),
 637     .class_init    = pnv_lpc_power8_class_init,
 638     .interfaces = (InterfaceInfo[]) {
 639         { TYPE_PNV_XSCOM_INTERFACE },
 640         { }
 641     }
 642 };
 643
 644 static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp)
 645 {
 646     PnvLpcController *lpc = PNV_LPC(dev);
 647     PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
 648     Error *local_err = NULL;
 649
 650     plc->parent_realize(dev, &local_err);
 651     if (local_err) {
 652         error_propagate(errp, local_err);
 653         return;
 654     }
 655
 656     /* P9 uses a MMIO region */
 657     memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops,
 658                           lpc, "lpcm", PNV9_LPCM_SIZE);
 659 }
 660
 661 static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
 662 {
 663     DeviceClass *dc = DEVICE_CLASS(klass);
 664     PnvLpcClass *plc = PNV_LPC_CLASS(klass);
 665
 666     dc->desc = "PowerNV LPC Controller POWER9";
 667
 668     plc->psi_irq = PSIHB9_IRQ_LPCHC;
 669
 670     device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
 671                                     &plc->parent_realize);
 672 }
 673
 674 static const TypeInfo pnv_lpc_power9_info = {
 675     .name          = TYPE_PNV9_LPC,
 676     .parent        = TYPE_PNV_LPC,
 677     .instance_size = sizeof(PnvLpcController),
 678     .class_init    = pnv_lpc_power9_class_init,
 679 };
 680
 681 static void pnv_lpc_realize(DeviceState *dev, Error **errp)
 682 {
 683     PnvLpcController *lpc = PNV_LPC(dev);
 684     Object *obj;
 685     Error *local_err = NULL;
 686
 687     obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
 688     if (!obj) {
 689         error_propagate(errp, local_err);
 690         error_prepend(errp, "required link 'psi' not found: ");
 691         return;
 692     }
 693     /* The LPC controller needs PSI to generate interrupts  */
 694     lpc->psi = PNV_PSI(obj);
 695
 696     /* Reg inits */
 697     lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
 698
 699     /* Create address space and backing MR for the OPB bus */
 700     memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
 701     address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
 702
 703     /* Create ISA IO and Mem space regions which are the root of
 704      * the ISA bus (ie, ISA address spaces). We don't create a
 705      * separate one for FW which we alias to memory.
 706      */
 707     memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
 708     memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
 709     memory_region_init(&lpc->isa_fw, OBJECT(dev),  "isa-fw", ISA_FW_SIZE);
 710
 711     /* Create windows from the OPB space to the ISA space */
 712     memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
 713                              &lpc->isa_io, 0, LPC_IO_OPB_SIZE);
 714     memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
 715                                 &lpc->opb_isa_io);
 716     memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
 717                              &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
 718     memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
 719                                 &lpc->opb_isa_mem);
 720     memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
 721                              &lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
 722     memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
 723                                 &lpc->opb_isa_fw);
 724
 725     /* Create MMIO regions for LPC HC and OPB registers */
 726     memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
 727                           lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
 728     memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
 729                                 &lpc->opb_master_regs);
 730     memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
 731                           "lpc-hc", LPC_HC_REGS_OPB_SIZE);
 732     memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
 733                                 &lpc->lpc_hc_regs);
 734 }
 735
 736 static void pnv_lpc_class_init(ObjectClass *klass, void *data)
 737 {
 738     DeviceClass *dc = DEVICE_CLASS(klass);
 739
 740     dc->realize = pnv_lpc_realize;
 741     dc->desc = "PowerNV LPC Controller";
 742 }
 743
 744 static const TypeInfo pnv_lpc_info = {
 745     .name          = TYPE_PNV_LPC,
 746     .parent        = TYPE_DEVICE,
 747     .class_init    = pnv_lpc_class_init,
 748     .class_size    = sizeof(PnvLpcClass),
 749     .abstract      = true,
 750 };
 751
 752 static void pnv_lpc_register_types(void)
 753 {
 754     type_register_static(&pnv_lpc_info);
 755     type_register_static(&pnv_lpc_power8_info);
 756     type_register_static(&pnv_lpc_power9_info);
 757 }
 758
 759 type_init(pnv_lpc_register_types)
 760
 761 /* If we don't use the built-in LPC interrupt deserializer, we need
 762  * to provide a set of qirqs for the ISA bus or things will go bad.
 763  *
 764  * Most machines using pre-Naples chips (without said deserializer)
 765  * have a CPLD that will collect the SerIRQ and shoot them as a
 766  * single level interrupt to the P8 chip. So let's setup a hook
 767  * for doing just that.
 768  */
 769 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 770 {
 771     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
 772     uint32_t old_state = pnv->cpld_irqstate;
 773     PnvLpcController *lpc = PNV_LPC(opaque);
 774
 775     if (level) {
 776         pnv->cpld_irqstate |= 1u << n;
 777     } else {
 778         pnv->cpld_irqstate &= ~(1u << n);
 779     }
 780
 781     if (pnv->cpld_irqstate != old_state) {
 782         pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
 783     }
 784 }
 785
 786 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 787 {
 788     PnvLpcController *lpc = PNV_LPC(opaque);
 789
 790     /* The Naples HW latches the 1 levels, clearing is done by SW */
 791     if (level) {
 792         lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
 793         pnv_lpc_eval_irqs(lpc);
 794     }
 795 }
 796
 797 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
 798 {
 799     Error *local_err = NULL;
 800     ISABus *isa_bus;
 801     qemu_irq *irqs;
 802     qemu_irq_handler handler;
 803
 804     /* let isa_bus_new() create its own bridge on SysBus otherwise
 805      * devices speficied on the command line won't find the bus and
 806      * will fail to create.
 807      */
 808     isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
 809     if (local_err) {
 810         error_propagate(errp, local_err);
 811         return NULL;
 812     }
 813
 814     /* Not all variants have a working serial irq decoder. If not,
 815      * handling of LPC interrupts becomes a platform issue (some
 816      * platforms have a CPLD to do it).
 817      */
 818     if (use_cpld) {
 819         handler = pnv_lpc_isa_irq_handler_cpld;
 820     } else {
 821         handler = pnv_lpc_isa_irq_handler;
 822     }
 823
 824     irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
 825
 826     isa_bus_irqs(isa_bus, irqs);
 827     return isa_bus;
 828 }