2 * PowerPC implementation of KVM hooks
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
17 #include "qemu/osdep.h"
19 #include <sys/ioctl.h>
22 #include <linux/kvm.h>
24 #include "qemu-common.h"
25 #include "qapi/error.h"
26 #include "qemu/error-report.h"
28 #include "cpu-models.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/hw_accel.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/device_tree.h"
35 #include "mmu-hash64.h"
37 #include "hw/sysbus.h"
38 #include "hw/ppc/spapr.h"
39 #include "hw/ppc/spapr_cpu_core.h"
41 #include "hw/ppc/ppc.h"
42 #include "migration/qemu-file-types.h"
43 #include "sysemu/watchdog.h"
45 #include "exec/gdbstub.h"
46 #include "exec/memattrs.h"
47 #include "exec/ram_addr.h"
48 #include "sysemu/hostmem.h"
49 #include "qemu/cutils.h"
50 #include "qemu/main-loop.h"
51 #include "qemu/mmap-alloc.h"
53 #include "sysemu/kvm_int.h"
55 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
57 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
61 static int cap_interrupt_unset
;
62 static int cap_interrupt_level
;
63 static int cap_segstate
;
64 static int cap_booke_sregs
;
65 static int cap_ppc_smt
;
66 static int cap_ppc_smt_possible
;
67 static int cap_spapr_tce
;
68 static int cap_spapr_tce_64
;
69 static int cap_spapr_multitce
;
70 static int cap_spapr_vfio
;
72 static int cap_one_reg
;
74 static int cap_ppc_watchdog
;
76 static int cap_htab_fd
;
77 static int cap_fixup_hcalls
;
78 static int cap_htm
; /* Hardware transactional memory support */
79 static int cap_mmu_radix
;
80 static int cap_mmu_hash_v3
;
82 static int cap_resize_hpt
;
83 static int cap_ppc_pvr_compat
;
84 static int cap_ppc_safe_cache
;
85 static int cap_ppc_safe_bounds_check
;
86 static int cap_ppc_safe_indirect_branch
;
87 static int cap_ppc_count_cache_flush_assist
;
88 static int cap_ppc_nested_kvm_hv
;
89 static int cap_large_decr
;
91 static uint32_t debug_inst_opcode
;
94 * XXX We have a race condition where we actually have a level triggered
95 * interrupt, but the infrastructure can't expose that yet, so the guest
96 * takes but ignores it, goes to sleep and never gets notified that there's
97 * still an interrupt pending.
99 * As a quick workaround, let's just wake up again 20 ms after we injected
100 * an interrupt. That way we can assure that we're always reinjecting
101 * interrupts in case the guest swallowed them.
103 static QEMUTimer
*idle_timer
;
105 static void kvm_kick_cpu(void *opaque
)
107 PowerPCCPU
*cpu
= opaque
;
109 qemu_cpu_kick(CPU(cpu
));
113 * Check whether we are running with KVM-PR (instead of KVM-HV). This
114 * should only be used for fallback tests - generally we should use
115 * explicit capabilities for the features we want, rather than
116 * assuming what is/isn't available depending on the KVM variant.
118 static bool kvmppc_is_pr(KVMState
*ks
)
120 /* Assume KVM-PR if the GET_PVINFO capability is available */
121 return kvm_vm_check_extension(ks
, KVM_CAP_PPC_GET_PVINFO
) != 0;
124 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
);
125 static void kvmppc_get_cpu_characteristics(KVMState
*s
);
126 static int kvmppc_get_dec_bits(void);
128 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
130 cap_interrupt_unset
= kvm_check_extension(s
, KVM_CAP_PPC_UNSET_IRQ
);
131 cap_interrupt_level
= kvm_check_extension(s
, KVM_CAP_PPC_IRQ_LEVEL
);
132 cap_segstate
= kvm_check_extension(s
, KVM_CAP_PPC_SEGSTATE
);
133 cap_booke_sregs
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_SREGS
);
134 cap_ppc_smt_possible
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT_POSSIBLE
);
135 cap_spapr_tce
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE
);
136 cap_spapr_tce_64
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE_64
);
137 cap_spapr_multitce
= kvm_check_extension(s
, KVM_CAP_SPAPR_MULTITCE
);
138 cap_spapr_vfio
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_TCE_VFIO
);
139 cap_one_reg
= kvm_check_extension(s
, KVM_CAP_ONE_REG
);
140 cap_hior
= kvm_check_extension(s
, KVM_CAP_PPC_HIOR
);
141 cap_epr
= kvm_check_extension(s
, KVM_CAP_PPC_EPR
);
142 cap_ppc_watchdog
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_WATCHDOG
);
144 * Note: we don't set cap_papr here, because this capability is
145 * only activated after this by kvmppc_set_papr()
147 cap_htab_fd
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTAB_FD
);
148 cap_fixup_hcalls
= kvm_check_extension(s
, KVM_CAP_PPC_FIXUP_HCALL
);
149 cap_ppc_smt
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT
);
150 cap_htm
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTM
);
151 cap_mmu_radix
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
);
152 cap_mmu_hash_v3
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_HASH_V3
);
153 cap_xive
= kvm_vm_check_extension(s
, KVM_CAP_PPC_IRQ_XIVE
);
154 cap_resize_hpt
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_RESIZE_HPT
);
155 kvmppc_get_cpu_characteristics(s
);
156 cap_ppc_nested_kvm_hv
= kvm_vm_check_extension(s
, KVM_CAP_PPC_NESTED_HV
);
157 cap_large_decr
= kvmppc_get_dec_bits();
159 * Note: setting it to false because there is not such capability
160 * in KVM at this moment.
162 * TODO: call kvm_vm_check_extension() with the right capability
163 * after the kernel starts implementing it.
165 cap_ppc_pvr_compat
= false;
167 if (!cap_interrupt_level
) {
168 fprintf(stderr
, "KVM: Couldn't find level irq capability. Expect the "
169 "VM to stall at times!\n");
172 kvm_ppc_register_host_cpu_type(ms
);
177 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
182 static int kvm_arch_sync_sregs(PowerPCCPU
*cpu
)
184 CPUPPCState
*cenv
= &cpu
->env
;
185 CPUState
*cs
= CPU(cpu
);
186 struct kvm_sregs sregs
;
189 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
191 * What we're really trying to say is "if we're on BookE, we
192 * use the native PVR for now". This is the only sane way to
193 * check it though, so we potentially confuse users that they
194 * can run BookE guests on BookS. Let's hope nobody dares
200 fprintf(stderr
, "kvm error: missing PVR setting capability\n");
205 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
210 sregs
.pvr
= cenv
->spr
[SPR_PVR
];
211 return kvm_vcpu_ioctl(cs
, KVM_SET_SREGS
, &sregs
);
214 /* Set up a shared TLB array with KVM */
215 static int kvm_booke206_tlb_init(PowerPCCPU
*cpu
)
217 CPUPPCState
*env
= &cpu
->env
;
218 CPUState
*cs
= CPU(cpu
);
219 struct kvm_book3e_206_tlb_params params
= {};
220 struct kvm_config_tlb cfg
= {};
221 unsigned int entries
= 0;
224 if (!kvm_enabled() ||
225 !kvm_check_extension(cs
->kvm_state
, KVM_CAP_SW_TLB
)) {
229 assert(ARRAY_SIZE(params
.tlb_sizes
) == BOOKE206_MAX_TLBN
);
231 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
232 params
.tlb_sizes
[i
] = booke206_tlb_size(env
, i
);
233 params
.tlb_ways
[i
] = booke206_tlb_ways(env
, i
);
234 entries
+= params
.tlb_sizes
[i
];
237 assert(entries
== env
->nb_tlb
);
238 assert(sizeof(struct kvm_book3e_206_tlb_entry
) == sizeof(ppcmas_tlb_t
));
240 env
->tlb_dirty
= true;
242 cfg
.array
= (uintptr_t)env
->tlb
.tlbm
;
243 cfg
.array_len
= sizeof(ppcmas_tlb_t
) * entries
;
244 cfg
.params
= (uintptr_t)¶ms
;
245 cfg
.mmu_type
= KVM_MMU_FSL_BOOKE_NOHV
;
247 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_SW_TLB
, 0, (uintptr_t)&cfg
);
249 fprintf(stderr
, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
250 __func__
, strerror(-ret
));
254 env
->kvm_sw_tlb
= true;
259 #if defined(TARGET_PPC64)
260 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info
*info
, Error
**errp
)
264 assert(kvm_state
!= NULL
);
266 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_GET_SMMU_INFO
)) {
267 error_setg(errp
, "KVM doesn't expose the MMU features it supports");
268 error_append_hint(errp
, "Consider switching to a newer KVM\n");
272 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_SMMU_INFO
, info
);
277 error_setg_errno(errp
, -ret
,
278 "KVM failed to provide the MMU features it supports");
281 struct ppc_radix_page_info
*kvm_get_radix_page_info(void)
283 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
284 struct ppc_radix_page_info
*radix_page_info
;
285 struct kvm_ppc_rmmu_info rmmu_info
;
288 if (!kvm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
)) {
291 if (kvm_vm_ioctl(s
, KVM_PPC_GET_RMMU_INFO
, &rmmu_info
)) {
294 radix_page_info
= g_malloc0(sizeof(*radix_page_info
));
295 radix_page_info
->count
= 0;
296 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
297 if (rmmu_info
.ap_encodings
[i
]) {
298 radix_page_info
->entries
[i
] = rmmu_info
.ap_encodings
[i
];
299 radix_page_info
->count
++;
302 return radix_page_info
;
305 target_ulong
kvmppc_configure_v3_mmu(PowerPCCPU
*cpu
,
306 bool radix
, bool gtse
,
309 CPUState
*cs
= CPU(cpu
);
312 struct kvm_ppc_mmuv3_cfg cfg
= {
313 .process_table
= proc_tbl
,
317 flags
|= KVM_PPC_MMUV3_RADIX
;
320 flags
|= KVM_PPC_MMUV3_GTSE
;
323 ret
= kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_CONFIGURE_V3_MMU
, &cfg
);
330 return H_NOT_AVAILABLE
;
336 bool kvmppc_hpt_needs_host_contiguous_pages(void)
338 static struct kvm_ppc_smmu_info smmu_info
;
340 if (!kvm_enabled()) {
344 kvm_get_smmu_info(&smmu_info
, &error_fatal
);
345 return !!(smmu_info
.flags
& KVM_PPC_PAGE_SIZES_REAL
);
348 void kvm_check_mmu(PowerPCCPU
*cpu
, Error
**errp
)
350 struct kvm_ppc_smmu_info smmu_info
;
352 Error
*local_err
= NULL
;
354 /* For now, we only have anything to check on hash64 MMUs */
355 if (!cpu
->hash64_opts
|| !kvm_enabled()) {
359 kvm_get_smmu_info(&smmu_info
, &local_err
);
361 error_propagate(errp
, local_err
);
365 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)
366 && !(smmu_info
.flags
& KVM_PPC_1T_SEGMENTS
)) {
368 "KVM does not support 1TiB segments which guest expects");
372 if (smmu_info
.slb_size
< cpu
->hash64_opts
->slb_size
) {
373 error_setg(errp
, "KVM only supports %u SLB entries, but guest needs %u",
374 smmu_info
.slb_size
, cpu
->hash64_opts
->slb_size
);
379 * Verify that every pagesize supported by the cpu model is
380 * supported by KVM with the same encodings
382 for (iq
= 0; iq
< ARRAY_SIZE(cpu
->hash64_opts
->sps
); iq
++) {
383 PPCHash64SegmentPageSizes
*qsps
= &cpu
->hash64_opts
->sps
[iq
];
384 struct kvm_ppc_one_seg_page_size
*ksps
;
386 for (ik
= 0; ik
< ARRAY_SIZE(smmu_info
.sps
); ik
++) {
387 if (qsps
->page_shift
== smmu_info
.sps
[ik
].page_shift
) {
391 if (ik
>= ARRAY_SIZE(smmu_info
.sps
)) {
392 error_setg(errp
, "KVM doesn't support for base page shift %u",
397 ksps
= &smmu_info
.sps
[ik
];
398 if (ksps
->slb_enc
!= qsps
->slb_enc
) {
400 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
401 ksps
->slb_enc
, ksps
->page_shift
, qsps
->slb_enc
);
405 for (jq
= 0; jq
< ARRAY_SIZE(qsps
->enc
); jq
++) {
406 for (jk
= 0; jk
< ARRAY_SIZE(ksps
->enc
); jk
++) {
407 if (qsps
->enc
[jq
].page_shift
== ksps
->enc
[jk
].page_shift
) {
412 if (jk
>= ARRAY_SIZE(ksps
->enc
)) {
413 error_setg(errp
, "KVM doesn't support page shift %u/%u",
414 qsps
->enc
[jq
].page_shift
, qsps
->page_shift
);
417 if (qsps
->enc
[jq
].pte_enc
!= ksps
->enc
[jk
].pte_enc
) {
419 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
420 ksps
->enc
[jk
].pte_enc
, qsps
->enc
[jq
].page_shift
,
421 qsps
->page_shift
, qsps
->enc
[jq
].pte_enc
);
427 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
429 * Mostly what guest pagesizes we can use are related to the
430 * host pages used to map guest RAM, which is handled in the
431 * platform code. Cache-Inhibited largepages (64k) however are
432 * used for I/O, so if they're mapped to the host at all it
433 * will be a normal mapping, not a special hugepage one used
436 if (getpagesize() < 0x10000) {
438 "KVM can't supply 64kiB CI pages, which guest expects");
442 #endif /* !defined (TARGET_PPC64) */
444 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
446 return POWERPC_CPU(cpu
)->vcpu_id
;
450 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
451 * only 1 watchpoint, so array size of 4 is sufficient for now.
453 #define MAX_HW_BKPTS 4
455 static struct HWBreakpoint
{
458 } hw_debug_points
[MAX_HW_BKPTS
];
460 static CPUWatchpoint hw_watchpoint
;
462 /* Default there is no breakpoint and watchpoint supported */
463 static int max_hw_breakpoint
;
464 static int max_hw_watchpoint
;
465 static int nb_hw_breakpoint
;
466 static int nb_hw_watchpoint
;
468 static void kvmppc_hw_debug_points_init(CPUPPCState
*cenv
)
470 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
471 max_hw_breakpoint
= 2;
472 max_hw_watchpoint
= 2;
475 if ((max_hw_breakpoint
+ max_hw_watchpoint
) > MAX_HW_BKPTS
) {
476 fprintf(stderr
, "Error initializing h/w breakpoints\n");
481 int kvm_arch_init_vcpu(CPUState
*cs
)
483 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
484 CPUPPCState
*cenv
= &cpu
->env
;
487 /* Synchronize sregs with kvm */
488 ret
= kvm_arch_sync_sregs(cpu
);
490 if (ret
== -EINVAL
) {
491 error_report("Register sync failed... If you're using kvm-hv.ko,"
492 " only \"-cpu host\" is possible");
497 idle_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, kvm_kick_cpu
, cpu
);
499 switch (cenv
->mmu_model
) {
500 case POWERPC_MMU_BOOKE206
:
501 /* This target supports access to KVM's guest TLB */
502 ret
= kvm_booke206_tlb_init(cpu
);
504 case POWERPC_MMU_2_07
:
505 if (!cap_htm
&& !kvmppc_is_pr(cs
->kvm_state
)) {
507 * KVM-HV has transactional memory on POWER8 also without
508 * the KVM_CAP_PPC_HTM extension, so enable it here
509 * instead as long as it's availble to userspace on the
512 if (qemu_getauxval(AT_HWCAP2
) & PPC_FEATURE2_HAS_HTM
) {
521 kvm_get_one_reg(cs
, KVM_REG_PPC_DEBUG_INST
, &debug_inst_opcode
);
522 kvmppc_hw_debug_points_init(cenv
);
527 int kvm_arch_destroy_vcpu(CPUState
*cs
)
532 static void kvm_sw_tlb_put(PowerPCCPU
*cpu
)
534 CPUPPCState
*env
= &cpu
->env
;
535 CPUState
*cs
= CPU(cpu
);
536 struct kvm_dirty_tlb dirty_tlb
;
537 unsigned char *bitmap
;
540 if (!env
->kvm_sw_tlb
) {
544 bitmap
= g_malloc((env
->nb_tlb
+ 7) / 8);
545 memset(bitmap
, 0xFF, (env
->nb_tlb
+ 7) / 8);
547 dirty_tlb
.bitmap
= (uintptr_t)bitmap
;
548 dirty_tlb
.num_dirty
= env
->nb_tlb
;
550 ret
= kvm_vcpu_ioctl(cs
, KVM_DIRTY_TLB
, &dirty_tlb
);
552 fprintf(stderr
, "%s: KVM_DIRTY_TLB: %s\n",
553 __func__
, strerror(-ret
));
559 static void kvm_get_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
561 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
562 CPUPPCState
*env
= &cpu
->env
;
567 struct kvm_one_reg reg
= {
569 .addr
= (uintptr_t) &val
,
573 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
575 trace_kvm_failed_spr_get(spr
, strerror(errno
));
577 switch (id
& KVM_REG_SIZE_MASK
) {
578 case KVM_REG_SIZE_U32
:
579 env
->spr
[spr
] = val
.u32
;
582 case KVM_REG_SIZE_U64
:
583 env
->spr
[spr
] = val
.u64
;
587 /* Don't handle this size yet */
593 static void kvm_put_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
595 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
596 CPUPPCState
*env
= &cpu
->env
;
601 struct kvm_one_reg reg
= {
603 .addr
= (uintptr_t) &val
,
607 switch (id
& KVM_REG_SIZE_MASK
) {
608 case KVM_REG_SIZE_U32
:
609 val
.u32
= env
->spr
[spr
];
612 case KVM_REG_SIZE_U64
:
613 val
.u64
= env
->spr
[spr
];
617 /* Don't handle this size yet */
621 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
623 trace_kvm_failed_spr_set(spr
, strerror(errno
));
627 static int kvm_put_fp(CPUState
*cs
)
629 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
630 CPUPPCState
*env
= &cpu
->env
;
631 struct kvm_one_reg reg
;
635 if (env
->insns_flags
& PPC_FLOAT
) {
636 uint64_t fpscr
= env
->fpscr
;
637 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
639 reg
.id
= KVM_REG_PPC_FPSCR
;
640 reg
.addr
= (uintptr_t)&fpscr
;
641 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
643 trace_kvm_failed_fpscr_set(strerror(errno
));
647 for (i
= 0; i
< 32; i
++) {
649 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
650 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
652 #ifdef HOST_WORDS_BIGENDIAN
653 vsr
[0] = float64_val(*fpr
);
657 vsr
[1] = float64_val(*fpr
);
659 reg
.addr
= (uintptr_t) &vsr
;
660 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
662 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
664 trace_kvm_failed_fp_set(vsx
? "VSR" : "FPR", i
,
671 if (env
->insns_flags
& PPC_ALTIVEC
) {
672 reg
.id
= KVM_REG_PPC_VSCR
;
673 reg
.addr
= (uintptr_t)&env
->vscr
;
674 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
676 trace_kvm_failed_vscr_set(strerror(errno
));
680 for (i
= 0; i
< 32; i
++) {
681 reg
.id
= KVM_REG_PPC_VR(i
);
682 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
683 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
685 trace_kvm_failed_vr_set(i
, strerror(errno
));
694 static int kvm_get_fp(CPUState
*cs
)
696 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
697 CPUPPCState
*env
= &cpu
->env
;
698 struct kvm_one_reg reg
;
702 if (env
->insns_flags
& PPC_FLOAT
) {
704 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
706 reg
.id
= KVM_REG_PPC_FPSCR
;
707 reg
.addr
= (uintptr_t)&fpscr
;
708 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
710 trace_kvm_failed_fpscr_get(strerror(errno
));
716 for (i
= 0; i
< 32; i
++) {
718 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
719 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
721 reg
.addr
= (uintptr_t) &vsr
;
722 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
724 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
726 trace_kvm_failed_fp_get(vsx
? "VSR" : "FPR", i
,
730 #ifdef HOST_WORDS_BIGENDIAN
745 if (env
->insns_flags
& PPC_ALTIVEC
) {
746 reg
.id
= KVM_REG_PPC_VSCR
;
747 reg
.addr
= (uintptr_t)&env
->vscr
;
748 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
750 trace_kvm_failed_vscr_get(strerror(errno
));
754 for (i
= 0; i
< 32; i
++) {
755 reg
.id
= KVM_REG_PPC_VR(i
);
756 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
757 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
759 trace_kvm_failed_vr_get(i
, strerror(errno
));
768 #if defined(TARGET_PPC64)
769 static int kvm_get_vpa(CPUState
*cs
)
771 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
772 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
773 struct kvm_one_reg reg
;
776 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
777 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
778 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
780 trace_kvm_failed_vpa_addr_get(strerror(errno
));
784 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
785 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
786 reg
.id
= KVM_REG_PPC_VPA_SLB
;
787 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
788 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
790 trace_kvm_failed_slb_get(strerror(errno
));
794 assert((uintptr_t)&spapr_cpu
->dtl_size
795 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
796 reg
.id
= KVM_REG_PPC_VPA_DTL
;
797 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
798 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
800 trace_kvm_failed_dtl_get(strerror(errno
));
807 static int kvm_put_vpa(CPUState
*cs
)
809 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
810 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
811 struct kvm_one_reg reg
;
815 * SLB shadow or DTL can't be registered unless a master VPA is
816 * registered. That means when restoring state, if a VPA *is*
817 * registered, we need to set that up first. If not, we need to
818 * deregister the others before deregistering the master VPA
820 assert(spapr_cpu
->vpa_addr
821 || !(spapr_cpu
->slb_shadow_addr
|| spapr_cpu
->dtl_addr
));
823 if (spapr_cpu
->vpa_addr
) {
824 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
825 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
826 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
828 trace_kvm_failed_vpa_addr_set(strerror(errno
));
833 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
834 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
835 reg
.id
= KVM_REG_PPC_VPA_SLB
;
836 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
837 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
839 trace_kvm_failed_slb_set(strerror(errno
));
843 assert((uintptr_t)&spapr_cpu
->dtl_size
844 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
845 reg
.id
= KVM_REG_PPC_VPA_DTL
;
846 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
847 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
849 trace_kvm_failed_dtl_set(strerror(errno
));
853 if (!spapr_cpu
->vpa_addr
) {
854 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
855 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
856 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
858 trace_kvm_failed_null_vpa_addr_set(strerror(errno
));
865 #endif /* TARGET_PPC64 */
867 int kvmppc_put_books_sregs(PowerPCCPU
*cpu
)
869 CPUPPCState
*env
= &cpu
->env
;
870 struct kvm_sregs sregs
;
873 sregs
.pvr
= env
->spr
[SPR_PVR
];
876 PPCVirtualHypervisorClass
*vhc
=
877 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
878 sregs
.u
.s
.sdr1
= vhc
->encode_hpt_for_kvm_pr(cpu
->vhyp
);
880 sregs
.u
.s
.sdr1
= env
->spr
[SPR_SDR1
];
885 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
886 sregs
.u
.s
.ppc64
.slb
[i
].slbe
= env
->slb
[i
].esid
;
887 if (env
->slb
[i
].esid
& SLB_ESID_V
) {
888 sregs
.u
.s
.ppc64
.slb
[i
].slbe
|= i
;
890 sregs
.u
.s
.ppc64
.slb
[i
].slbv
= env
->slb
[i
].vsid
;
895 for (i
= 0; i
< 16; i
++) {
896 sregs
.u
.s
.ppc32
.sr
[i
] = env
->sr
[i
];
900 for (i
= 0; i
< 8; i
++) {
901 /* Beware. We have to swap upper and lower bits here */
902 sregs
.u
.s
.ppc32
.dbat
[i
] = ((uint64_t)env
->DBAT
[0][i
] << 32)
904 sregs
.u
.s
.ppc32
.ibat
[i
] = ((uint64_t)env
->IBAT
[0][i
] << 32)
908 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
911 int kvm_arch_put_registers(CPUState
*cs
, int level
)
913 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
914 CPUPPCState
*env
= &cpu
->env
;
915 struct kvm_regs regs
;
919 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
926 regs
.xer
= cpu_read_xer(env
);
930 regs
.srr0
= env
->spr
[SPR_SRR0
];
931 regs
.srr1
= env
->spr
[SPR_SRR1
];
933 regs
.sprg0
= env
->spr
[SPR_SPRG0
];
934 regs
.sprg1
= env
->spr
[SPR_SPRG1
];
935 regs
.sprg2
= env
->spr
[SPR_SPRG2
];
936 regs
.sprg3
= env
->spr
[SPR_SPRG3
];
937 regs
.sprg4
= env
->spr
[SPR_SPRG4
];
938 regs
.sprg5
= env
->spr
[SPR_SPRG5
];
939 regs
.sprg6
= env
->spr
[SPR_SPRG6
];
940 regs
.sprg7
= env
->spr
[SPR_SPRG7
];
942 regs
.pid
= env
->spr
[SPR_BOOKE_PID
];
944 for (i
= 0; i
< 32; i
++) {
945 regs
.gpr
[i
] = env
->gpr
[i
];
949 for (i
= 0; i
< 8; i
++) {
950 regs
.cr
|= (env
->crf
[i
] & 15) << (4 * (7 - i
));
953 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
960 if (env
->tlb_dirty
) {
962 env
->tlb_dirty
= false;
965 if (cap_segstate
&& (level
>= KVM_PUT_RESET_STATE
)) {
966 ret
= kvmppc_put_books_sregs(cpu
);
972 if (cap_hior
&& (level
>= KVM_PUT_RESET_STATE
)) {
973 kvm_put_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
980 * We deliberately ignore errors here, for kernels which have
981 * the ONE_REG calls, but don't support the specific
982 * registers, there's a reasonable chance things will still
983 * work, at least until we try to migrate.
985 for (i
= 0; i
< 1024; i
++) {
986 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
989 kvm_put_one_spr(cs
, id
, i
);
995 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
996 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
998 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
999 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
1001 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
1002 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
1003 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
1004 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
1005 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
1006 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
1007 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1008 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1009 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1010 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1014 if (kvm_put_vpa(cs
) < 0) {
1015 trace_kvm_failed_put_vpa();
1019 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1020 #endif /* TARGET_PPC64 */
1026 static void kvm_sync_excp(CPUPPCState
*env
, int vector
, int ivor
)
1028 env
->excp_vectors
[vector
] = env
->spr
[ivor
] + env
->spr
[SPR_BOOKE_IVPR
];
1031 static int kvmppc_get_booke_sregs(PowerPCCPU
*cpu
)
1033 CPUPPCState
*env
= &cpu
->env
;
1034 struct kvm_sregs sregs
;
1037 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1042 if (sregs
.u
.e
.features
& KVM_SREGS_E_BASE
) {
1043 env
->spr
[SPR_BOOKE_CSRR0
] = sregs
.u
.e
.csrr0
;
1044 env
->spr
[SPR_BOOKE_CSRR1
] = sregs
.u
.e
.csrr1
;
1045 env
->spr
[SPR_BOOKE_ESR
] = sregs
.u
.e
.esr
;
1046 env
->spr
[SPR_BOOKE_DEAR
] = sregs
.u
.e
.dear
;
1047 env
->spr
[SPR_BOOKE_MCSR
] = sregs
.u
.e
.mcsr
;
1048 env
->spr
[SPR_BOOKE_TSR
] = sregs
.u
.e
.tsr
;
1049 env
->spr
[SPR_BOOKE_TCR
] = sregs
.u
.e
.tcr
;
1050 env
->spr
[SPR_DECR
] = sregs
.u
.e
.dec
;
1051 env
->spr
[SPR_TBL
] = sregs
.u
.e
.tb
& 0xffffffff;
1052 env
->spr
[SPR_TBU
] = sregs
.u
.e
.tb
>> 32;
1053 env
->spr
[SPR_VRSAVE
] = sregs
.u
.e
.vrsave
;
1056 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206
) {
1057 env
->spr
[SPR_BOOKE_PIR
] = sregs
.u
.e
.pir
;
1058 env
->spr
[SPR_BOOKE_MCSRR0
] = sregs
.u
.e
.mcsrr0
;
1059 env
->spr
[SPR_BOOKE_MCSRR1
] = sregs
.u
.e
.mcsrr1
;
1060 env
->spr
[SPR_BOOKE_DECAR
] = sregs
.u
.e
.decar
;
1061 env
->spr
[SPR_BOOKE_IVPR
] = sregs
.u
.e
.ivpr
;
1064 if (sregs
.u
.e
.features
& KVM_SREGS_E_64
) {
1065 env
->spr
[SPR_BOOKE_EPCR
] = sregs
.u
.e
.epcr
;
1068 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPRG8
) {
1069 env
->spr
[SPR_BOOKE_SPRG8
] = sregs
.u
.e
.sprg8
;
1072 if (sregs
.u
.e
.features
& KVM_SREGS_E_IVOR
) {
1073 env
->spr
[SPR_BOOKE_IVOR0
] = sregs
.u
.e
.ivor_low
[0];
1074 kvm_sync_excp(env
, POWERPC_EXCP_CRITICAL
, SPR_BOOKE_IVOR0
);
1075 env
->spr
[SPR_BOOKE_IVOR1
] = sregs
.u
.e
.ivor_low
[1];
1076 kvm_sync_excp(env
, POWERPC_EXCP_MCHECK
, SPR_BOOKE_IVOR1
);
1077 env
->spr
[SPR_BOOKE_IVOR2
] = sregs
.u
.e
.ivor_low
[2];
1078 kvm_sync_excp(env
, POWERPC_EXCP_DSI
, SPR_BOOKE_IVOR2
);
1079 env
->spr
[SPR_BOOKE_IVOR3
] = sregs
.u
.e
.ivor_low
[3];
1080 kvm_sync_excp(env
, POWERPC_EXCP_ISI
, SPR_BOOKE_IVOR3
);
1081 env
->spr
[SPR_BOOKE_IVOR4
] = sregs
.u
.e
.ivor_low
[4];
1082 kvm_sync_excp(env
, POWERPC_EXCP_EXTERNAL
, SPR_BOOKE_IVOR4
);
1083 env
->spr
[SPR_BOOKE_IVOR5
] = sregs
.u
.e
.ivor_low
[5];
1084 kvm_sync_excp(env
, POWERPC_EXCP_ALIGN
, SPR_BOOKE_IVOR5
);
1085 env
->spr
[SPR_BOOKE_IVOR6
] = sregs
.u
.e
.ivor_low
[6];
1086 kvm_sync_excp(env
, POWERPC_EXCP_PROGRAM
, SPR_BOOKE_IVOR6
);
1087 env
->spr
[SPR_BOOKE_IVOR7
] = sregs
.u
.e
.ivor_low
[7];
1088 kvm_sync_excp(env
, POWERPC_EXCP_FPU
, SPR_BOOKE_IVOR7
);
1089 env
->spr
[SPR_BOOKE_IVOR8
] = sregs
.u
.e
.ivor_low
[8];
1090 kvm_sync_excp(env
, POWERPC_EXCP_SYSCALL
, SPR_BOOKE_IVOR8
);
1091 env
->spr
[SPR_BOOKE_IVOR9
] = sregs
.u
.e
.ivor_low
[9];
1092 kvm_sync_excp(env
, POWERPC_EXCP_APU
, SPR_BOOKE_IVOR9
);
1093 env
->spr
[SPR_BOOKE_IVOR10
] = sregs
.u
.e
.ivor_low
[10];
1094 kvm_sync_excp(env
, POWERPC_EXCP_DECR
, SPR_BOOKE_IVOR10
);
1095 env
->spr
[SPR_BOOKE_IVOR11
] = sregs
.u
.e
.ivor_low
[11];
1096 kvm_sync_excp(env
, POWERPC_EXCP_FIT
, SPR_BOOKE_IVOR11
);
1097 env
->spr
[SPR_BOOKE_IVOR12
] = sregs
.u
.e
.ivor_low
[12];
1098 kvm_sync_excp(env
, POWERPC_EXCP_WDT
, SPR_BOOKE_IVOR12
);
1099 env
->spr
[SPR_BOOKE_IVOR13
] = sregs
.u
.e
.ivor_low
[13];
1100 kvm_sync_excp(env
, POWERPC_EXCP_DTLB
, SPR_BOOKE_IVOR13
);
1101 env
->spr
[SPR_BOOKE_IVOR14
] = sregs
.u
.e
.ivor_low
[14];
1102 kvm_sync_excp(env
, POWERPC_EXCP_ITLB
, SPR_BOOKE_IVOR14
);
1103 env
->spr
[SPR_BOOKE_IVOR15
] = sregs
.u
.e
.ivor_low
[15];
1104 kvm_sync_excp(env
, POWERPC_EXCP_DEBUG
, SPR_BOOKE_IVOR15
);
1106 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPE
) {
1107 env
->spr
[SPR_BOOKE_IVOR32
] = sregs
.u
.e
.ivor_high
[0];
1108 kvm_sync_excp(env
, POWERPC_EXCP_SPEU
, SPR_BOOKE_IVOR32
);
1109 env
->spr
[SPR_BOOKE_IVOR33
] = sregs
.u
.e
.ivor_high
[1];
1110 kvm_sync_excp(env
, POWERPC_EXCP_EFPDI
, SPR_BOOKE_IVOR33
);
1111 env
->spr
[SPR_BOOKE_IVOR34
] = sregs
.u
.e
.ivor_high
[2];
1112 kvm_sync_excp(env
, POWERPC_EXCP_EFPRI
, SPR_BOOKE_IVOR34
);
1115 if (sregs
.u
.e
.features
& KVM_SREGS_E_PM
) {
1116 env
->spr
[SPR_BOOKE_IVOR35
] = sregs
.u
.e
.ivor_high
[3];
1117 kvm_sync_excp(env
, POWERPC_EXCP_EPERFM
, SPR_BOOKE_IVOR35
);
1120 if (sregs
.u
.e
.features
& KVM_SREGS_E_PC
) {
1121 env
->spr
[SPR_BOOKE_IVOR36
] = sregs
.u
.e
.ivor_high
[4];
1122 kvm_sync_excp(env
, POWERPC_EXCP_DOORI
, SPR_BOOKE_IVOR36
);
1123 env
->spr
[SPR_BOOKE_IVOR37
] = sregs
.u
.e
.ivor_high
[5];
1124 kvm_sync_excp(env
, POWERPC_EXCP_DOORCI
, SPR_BOOKE_IVOR37
);
1128 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206_MMU
) {
1129 env
->spr
[SPR_BOOKE_MAS0
] = sregs
.u
.e
.mas0
;
1130 env
->spr
[SPR_BOOKE_MAS1
] = sregs
.u
.e
.mas1
;
1131 env
->spr
[SPR_BOOKE_MAS2
] = sregs
.u
.e
.mas2
;
1132 env
->spr
[SPR_BOOKE_MAS3
] = sregs
.u
.e
.mas7_3
& 0xffffffff;
1133 env
->spr
[SPR_BOOKE_MAS4
] = sregs
.u
.e
.mas4
;
1134 env
->spr
[SPR_BOOKE_MAS6
] = sregs
.u
.e
.mas6
;
1135 env
->spr
[SPR_BOOKE_MAS7
] = sregs
.u
.e
.mas7_3
>> 32;
1136 env
->spr
[SPR_MMUCFG
] = sregs
.u
.e
.mmucfg
;
1137 env
->spr
[SPR_BOOKE_TLB0CFG
] = sregs
.u
.e
.tlbcfg
[0];
1138 env
->spr
[SPR_BOOKE_TLB1CFG
] = sregs
.u
.e
.tlbcfg
[1];
1141 if (sregs
.u
.e
.features
& KVM_SREGS_EXP
) {
1142 env
->spr
[SPR_BOOKE_EPR
] = sregs
.u
.e
.epr
;
1145 if (sregs
.u
.e
.features
& KVM_SREGS_E_PD
) {
1146 env
->spr
[SPR_BOOKE_EPLC
] = sregs
.u
.e
.eplc
;
1147 env
->spr
[SPR_BOOKE_EPSC
] = sregs
.u
.e
.epsc
;
1150 if (sregs
.u
.e
.impl_id
== KVM_SREGS_E_IMPL_FSL
) {
1151 env
->spr
[SPR_E500_SVR
] = sregs
.u
.e
.impl
.fsl
.svr
;
1152 env
->spr
[SPR_Exxx_MCAR
] = sregs
.u
.e
.impl
.fsl
.mcar
;
1153 env
->spr
[SPR_HID0
] = sregs
.u
.e
.impl
.fsl
.hid0
;
1155 if (sregs
.u
.e
.impl
.fsl
.features
& KVM_SREGS_E_FSL_PIDn
) {
1156 env
->spr
[SPR_BOOKE_PID1
] = sregs
.u
.e
.impl
.fsl
.pid1
;
1157 env
->spr
[SPR_BOOKE_PID2
] = sregs
.u
.e
.impl
.fsl
.pid2
;
1164 static int kvmppc_get_books_sregs(PowerPCCPU
*cpu
)
1166 CPUPPCState
*env
= &cpu
->env
;
1167 struct kvm_sregs sregs
;
1171 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1177 ppc_store_sdr1(env
, sregs
.u
.s
.sdr1
);
1183 * The packed SLB array we get from KVM_GET_SREGS only contains
1184 * information about valid entries. So we flush our internal copy
1185 * to get rid of stale ones, then put all valid SLB entries back
1188 memset(env
->slb
, 0, sizeof(env
->slb
));
1189 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
1190 target_ulong rb
= sregs
.u
.s
.ppc64
.slb
[i
].slbe
;
1191 target_ulong rs
= sregs
.u
.s
.ppc64
.slb
[i
].slbv
;
1193 * Only restore valid entries
1195 if (rb
& SLB_ESID_V
) {
1196 ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
);
1202 for (i
= 0; i
< 16; i
++) {
1203 env
->sr
[i
] = sregs
.u
.s
.ppc32
.sr
[i
];
1207 for (i
= 0; i
< 8; i
++) {
1208 env
->DBAT
[0][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] & 0xffffffff;
1209 env
->DBAT
[1][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] >> 32;
1210 env
->IBAT
[0][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] & 0xffffffff;
1211 env
->IBAT
[1][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] >> 32;
1217 int kvm_arch_get_registers(CPUState
*cs
)
1219 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1220 CPUPPCState
*env
= &cpu
->env
;
1221 struct kvm_regs regs
;
1225 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1231 for (i
= 7; i
>= 0; i
--) {
1232 env
->crf
[i
] = cr
& 15;
1236 env
->ctr
= regs
.ctr
;
1238 cpu_write_xer(env
, regs
.xer
);
1239 env
->msr
= regs
.msr
;
1242 env
->spr
[SPR_SRR0
] = regs
.srr0
;
1243 env
->spr
[SPR_SRR1
] = regs
.srr1
;
1245 env
->spr
[SPR_SPRG0
] = regs
.sprg0
;
1246 env
->spr
[SPR_SPRG1
] = regs
.sprg1
;
1247 env
->spr
[SPR_SPRG2
] = regs
.sprg2
;
1248 env
->spr
[SPR_SPRG3
] = regs
.sprg3
;
1249 env
->spr
[SPR_SPRG4
] = regs
.sprg4
;
1250 env
->spr
[SPR_SPRG5
] = regs
.sprg5
;
1251 env
->spr
[SPR_SPRG6
] = regs
.sprg6
;
1252 env
->spr
[SPR_SPRG7
] = regs
.sprg7
;
1254 env
->spr
[SPR_BOOKE_PID
] = regs
.pid
;
1256 for (i
= 0; i
< 32; i
++) {
1257 env
->gpr
[i
] = regs
.gpr
[i
];
1262 if (cap_booke_sregs
) {
1263 ret
= kvmppc_get_booke_sregs(cpu
);
1270 ret
= kvmppc_get_books_sregs(cpu
);
1277 kvm_get_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
1284 * We deliberately ignore errors here, for kernels which have
1285 * the ONE_REG calls, but don't support the specific
1286 * registers, there's a reasonable chance things will still
1287 * work, at least until we try to migrate.
1289 for (i
= 0; i
< 1024; i
++) {
1290 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
1293 kvm_get_one_spr(cs
, id
, i
);
1299 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
1300 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
1302 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
1303 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
1305 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
1306 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
1307 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
1308 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
1309 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
1310 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
1311 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1312 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1313 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1314 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1318 if (kvm_get_vpa(cs
) < 0) {
1319 trace_kvm_failed_get_vpa();
1323 kvm_get_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1330 int kvmppc_set_interrupt(PowerPCCPU
*cpu
, int irq
, int level
)
1332 unsigned virq
= level
? KVM_INTERRUPT_SET_LEVEL
: KVM_INTERRUPT_UNSET
;
1334 if (irq
!= PPC_INTERRUPT_EXT
) {
1338 if (!kvm_enabled() || !cap_interrupt_unset
|| !cap_interrupt_level
) {
1342 kvm_vcpu_ioctl(CPU(cpu
), KVM_INTERRUPT
, &virq
);
1347 #if defined(TARGET_PPC64)
1348 #define PPC_INPUT_INT PPC970_INPUT_INT
1350 #define PPC_INPUT_INT PPC6xx_INPUT_INT
1353 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
1355 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1356 CPUPPCState
*env
= &cpu
->env
;
1360 qemu_mutex_lock_iothread();
1363 * PowerPC QEMU tracks the various core input pins (interrupt,
1364 * critical interrupt, reset, etc) in PPC-specific
1365 * env->irq_input_state.
1367 if (!cap_interrupt_level
&&
1368 run
->ready_for_interrupt_injection
&&
1369 (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1370 (env
->irq_input_state
& (1 << PPC_INPUT_INT
)))
1373 * For now KVM disregards the 'irq' argument. However, in the
1374 * future KVM could cache it in-kernel to avoid a heavyweight
1375 * exit when reading the UIC.
1377 irq
= KVM_INTERRUPT_SET
;
1379 trace_kvm_injected_interrupt(irq
);
1380 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &irq
);
1382 printf("cpu %d fail inject %x\n", cs
->cpu_index
, irq
);
1385 /* Always wake up soon in case the interrupt was level based */
1386 timer_mod(idle_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1387 (NANOSECONDS_PER_SECOND
/ 50));
1391 * We don't know if there are more interrupts pending after
1392 * this. However, the guest will return to userspace in the course
1393 * of handling this one anyways, so we will get a chance to
1397 qemu_mutex_unlock_iothread();
1400 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
1402 return MEMTXATTRS_UNSPECIFIED
;
1405 int kvm_arch_process_async_events(CPUState
*cs
)
1410 static int kvmppc_handle_halt(PowerPCCPU
*cpu
)
1412 CPUState
*cs
= CPU(cpu
);
1413 CPUPPCState
*env
= &cpu
->env
;
1415 if (!(cs
->interrupt_request
& CPU_INTERRUPT_HARD
) && (msr_ee
)) {
1417 cs
->exception_index
= EXCP_HLT
;
1423 /* map dcr access to existing qemu dcr emulation */
1424 static int kvmppc_handle_dcr_read(CPUPPCState
*env
,
1425 uint32_t dcrn
, uint32_t *data
)
1427 if (ppc_dcr_read(env
->dcr_env
, dcrn
, data
) < 0) {
1428 fprintf(stderr
, "Read to unhandled DCR (0x%x)\n", dcrn
);
1434 static int kvmppc_handle_dcr_write(CPUPPCState
*env
,
1435 uint32_t dcrn
, uint32_t data
)
1437 if (ppc_dcr_write(env
->dcr_env
, dcrn
, data
) < 0) {
1438 fprintf(stderr
, "Write to unhandled DCR (0x%x)\n", dcrn
);
1444 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1446 /* Mixed endian case is not handled */
1447 uint32_t sc
= debug_inst_opcode
;
1449 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1451 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 1)) {
1458 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1462 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 0) ||
1463 sc
!= debug_inst_opcode
||
1464 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1472 static int find_hw_breakpoint(target_ulong addr
, int type
)
1476 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1477 <= ARRAY_SIZE(hw_debug_points
));
1479 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1480 if (hw_debug_points
[n
].addr
== addr
&&
1481 hw_debug_points
[n
].type
== type
) {
1489 static int find_hw_watchpoint(target_ulong addr
, int *flag
)
1493 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_ACCESS
);
1495 *flag
= BP_MEM_ACCESS
;
1499 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_WRITE
);
1501 *flag
= BP_MEM_WRITE
;
1505 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_READ
);
1507 *flag
= BP_MEM_READ
;
1514 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1515 target_ulong len
, int type
)
1517 if ((nb_hw_breakpoint
+ nb_hw_watchpoint
) >= ARRAY_SIZE(hw_debug_points
)) {
1521 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].addr
= addr
;
1522 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].type
= type
;
1525 case GDB_BREAKPOINT_HW
:
1526 if (nb_hw_breakpoint
>= max_hw_breakpoint
) {
1530 if (find_hw_breakpoint(addr
, type
) >= 0) {
1537 case GDB_WATCHPOINT_WRITE
:
1538 case GDB_WATCHPOINT_READ
:
1539 case GDB_WATCHPOINT_ACCESS
:
1540 if (nb_hw_watchpoint
>= max_hw_watchpoint
) {
1544 if (find_hw_breakpoint(addr
, type
) >= 0) {
1558 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1559 target_ulong len
, int type
)
1563 n
= find_hw_breakpoint(addr
, type
);
1569 case GDB_BREAKPOINT_HW
:
1573 case GDB_WATCHPOINT_WRITE
:
1574 case GDB_WATCHPOINT_READ
:
1575 case GDB_WATCHPOINT_ACCESS
:
1582 hw_debug_points
[n
] = hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
];
1587 void kvm_arch_remove_all_hw_breakpoints(void)
1589 nb_hw_breakpoint
= nb_hw_watchpoint
= 0;
1592 void kvm_arch_update_guest_debug(CPUState
*cs
, struct kvm_guest_debug
*dbg
)
1596 /* Software Breakpoint updates */
1597 if (kvm_sw_breakpoints_active(cs
)) {
1598 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1601 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1602 <= ARRAY_SIZE(hw_debug_points
));
1603 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
) <= ARRAY_SIZE(dbg
->arch
.bp
));
1605 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1606 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1607 memset(dbg
->arch
.bp
, 0, sizeof(dbg
->arch
.bp
));
1608 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1609 switch (hw_debug_points
[n
].type
) {
1610 case GDB_BREAKPOINT_HW
:
1611 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_BREAKPOINT
;
1613 case GDB_WATCHPOINT_WRITE
:
1614 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
;
1616 case GDB_WATCHPOINT_READ
:
1617 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_READ
;
1619 case GDB_WATCHPOINT_ACCESS
:
1620 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
|
1621 KVMPPC_DEBUG_WATCH_READ
;
1624 cpu_abort(cs
, "Unsupported breakpoint type\n");
1626 dbg
->arch
.bp
[n
].addr
= hw_debug_points
[n
].addr
;
1631 static int kvm_handle_hw_breakpoint(CPUState
*cs
,
1632 struct kvm_debug_exit_arch
*arch_info
)
1638 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1639 if (arch_info
->status
& KVMPPC_DEBUG_BREAKPOINT
) {
1640 n
= find_hw_breakpoint(arch_info
->address
, GDB_BREAKPOINT_HW
);
1644 } else if (arch_info
->status
& (KVMPPC_DEBUG_WATCH_READ
|
1645 KVMPPC_DEBUG_WATCH_WRITE
)) {
1646 n
= find_hw_watchpoint(arch_info
->address
, &flag
);
1649 cs
->watchpoint_hit
= &hw_watchpoint
;
1650 hw_watchpoint
.vaddr
= hw_debug_points
[n
].addr
;
1651 hw_watchpoint
.flags
= flag
;
1658 static int kvm_handle_singlestep(void)
1663 static int kvm_handle_sw_breakpoint(void)
1668 static int kvm_handle_debug(PowerPCCPU
*cpu
, struct kvm_run
*run
)
1670 CPUState
*cs
= CPU(cpu
);
1671 CPUPPCState
*env
= &cpu
->env
;
1672 struct kvm_debug_exit_arch
*arch_info
= &run
->debug
.arch
;
1674 if (cs
->singlestep_enabled
) {
1675 return kvm_handle_singlestep();
1678 if (arch_info
->status
) {
1679 return kvm_handle_hw_breakpoint(cs
, arch_info
);
1682 if (kvm_find_sw_breakpoint(cs
, arch_info
->address
)) {
1683 return kvm_handle_sw_breakpoint();
1687 * QEMU is not able to handle debug exception, so inject
1688 * program exception to guest;
1689 * Yes program exception NOT debug exception !!
1690 * When QEMU is using debug resources then debug exception must
1691 * be always set. To achieve this we set MSR_DE and also set
1692 * MSRP_DEP so guest cannot change MSR_DE.
1693 * When emulating debug resource for guest we want guest
1694 * to control MSR_DE (enable/disable debug interrupt on need).
1695 * Supporting both configurations are NOT possible.
1696 * So the result is that we cannot share debug resources
1697 * between QEMU and Guest on BOOKE architecture.
1698 * In the current design QEMU gets the priority over guest,
1699 * this means that if QEMU is using debug resources then guest
1701 * For software breakpoint QEMU uses a privileged instruction;
1702 * So there cannot be any reason that we are here for guest
1703 * set debug exception, only possibility is guest executed a
1704 * privileged / illegal instruction and that's why we are
1705 * injecting a program interrupt.
1707 cpu_synchronize_state(cs
);
1709 * env->nip is PC, so increment this by 4 to use
1710 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1713 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
1714 env
->error_code
= POWERPC_EXCP_INVAL
;
1715 ppc_cpu_do_interrupt(cs
);
1720 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
1722 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1723 CPUPPCState
*env
= &cpu
->env
;
1726 qemu_mutex_lock_iothread();
1728 switch (run
->exit_reason
) {
1730 if (run
->dcr
.is_write
) {
1731 trace_kvm_handle_dcr_write();
1732 ret
= kvmppc_handle_dcr_write(env
, run
->dcr
.dcrn
, run
->dcr
.data
);
1734 trace_kvm_handle_dcr_read();
1735 ret
= kvmppc_handle_dcr_read(env
, run
->dcr
.dcrn
, &run
->dcr
.data
);
1739 trace_kvm_handle_halt();
1740 ret
= kvmppc_handle_halt(cpu
);
1742 #if defined(TARGET_PPC64)
1743 case KVM_EXIT_PAPR_HCALL
:
1744 trace_kvm_handle_papr_hcall();
1745 run
->papr_hcall
.ret
= spapr_hypercall(cpu
,
1747 run
->papr_hcall
.args
);
1752 trace_kvm_handle_epr();
1753 run
->epr
.epr
= ldl_phys(cs
->as
, env
->mpic_iack
);
1756 case KVM_EXIT_WATCHDOG
:
1757 trace_kvm_handle_watchdog_expiry();
1758 watchdog_perform_action();
1762 case KVM_EXIT_DEBUG
:
1763 trace_kvm_handle_debug_exception();
1764 if (kvm_handle_debug(cpu
, run
)) {
1768 /* re-enter, this exception was guest-internal */
1773 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1778 qemu_mutex_unlock_iothread();
1782 int kvmppc_or_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1784 CPUState
*cs
= CPU(cpu
);
1785 uint32_t bits
= tsr_bits
;
1786 struct kvm_one_reg reg
= {
1787 .id
= KVM_REG_PPC_OR_TSR
,
1788 .addr
= (uintptr_t) &bits
,
1791 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1794 int kvmppc_clear_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1797 CPUState
*cs
= CPU(cpu
);
1798 uint32_t bits
= tsr_bits
;
1799 struct kvm_one_reg reg
= {
1800 .id
= KVM_REG_PPC_CLEAR_TSR
,
1801 .addr
= (uintptr_t) &bits
,
1804 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1807 int kvmppc_set_tcr(PowerPCCPU
*cpu
)
1809 CPUState
*cs
= CPU(cpu
);
1810 CPUPPCState
*env
= &cpu
->env
;
1811 uint32_t tcr
= env
->spr
[SPR_BOOKE_TCR
];
1813 struct kvm_one_reg reg
= {
1814 .id
= KVM_REG_PPC_TCR
,
1815 .addr
= (uintptr_t) &tcr
,
1818 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1821 int kvmppc_booke_watchdog_enable(PowerPCCPU
*cpu
)
1823 CPUState
*cs
= CPU(cpu
);
1826 if (!kvm_enabled()) {
1830 if (!cap_ppc_watchdog
) {
1831 printf("warning: KVM does not support watchdog");
1835 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_BOOKE_WATCHDOG
, 0);
1837 fprintf(stderr
, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1838 __func__
, strerror(-ret
));
1845 static int read_cpuinfo(const char *field
, char *value
, int len
)
1849 int field_len
= strlen(field
);
1852 f
= fopen("/proc/cpuinfo", "r");
1858 if (!fgets(line
, sizeof(line
), f
)) {
1861 if (!strncmp(line
, field
, field_len
)) {
1862 pstrcpy(value
, len
, line
);
1873 uint32_t kvmppc_get_tbfreq(void)
1877 uint32_t retval
= NANOSECONDS_PER_SECOND
;
1879 if (read_cpuinfo("timebase", line
, sizeof(line
))) {
1883 ns
= strchr(line
, ':');
1893 bool kvmppc_get_host_serial(char **value
)
1895 return g_file_get_contents("/proc/device-tree/system-id", value
, NULL
,
1899 bool kvmppc_get_host_model(char **value
)
1901 return g_file_get_contents("/proc/device-tree/model", value
, NULL
, NULL
);
1904 /* Try to find a device tree node for a CPU with clock-frequency property */
1905 static int kvmppc_find_cpu_dt(char *buf
, int buf_len
)
1907 struct dirent
*dirp
;
1910 dp
= opendir(PROC_DEVTREE_CPU
);
1912 printf("Can't open directory " PROC_DEVTREE_CPU
"\n");
1917 while ((dirp
= readdir(dp
)) != NULL
) {
1919 snprintf(buf
, buf_len
, "%s%s/clock-frequency", PROC_DEVTREE_CPU
,
1921 f
= fopen(buf
, "r");
1923 snprintf(buf
, buf_len
, "%s%s", PROC_DEVTREE_CPU
, dirp
->d_name
);
1930 if (buf
[0] == '\0') {
1931 printf("Unknown host!\n");
1938 static uint64_t kvmppc_read_int_dt(const char *filename
)
1947 f
= fopen(filename
, "rb");
1952 len
= fread(&u
, 1, sizeof(u
), f
);
1956 /* property is a 32-bit quantity */
1957 return be32_to_cpu(u
.v32
);
1959 return be64_to_cpu(u
.v64
);
1966 * Read a CPU node property from the host device tree that's a single
1967 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1968 * (can't find or open the property, or doesn't understand the format)
1970 static uint64_t kvmppc_read_int_cpu_dt(const char *propname
)
1972 char buf
[PATH_MAX
], *tmp
;
1975 if (kvmppc_find_cpu_dt(buf
, sizeof(buf
))) {
1979 tmp
= g_strdup_printf("%s/%s", buf
, propname
);
1980 val
= kvmppc_read_int_dt(tmp
);
1986 uint64_t kvmppc_get_clockfreq(void)
1988 return kvmppc_read_int_cpu_dt("clock-frequency");
1991 static int kvmppc_get_dec_bits(void)
1993 int nr_bits
= kvmppc_read_int_cpu_dt("ibm,dec-bits");
2001 static int kvmppc_get_pvinfo(CPUPPCState
*env
, struct kvm_ppc_pvinfo
*pvinfo
)
2003 CPUState
*cs
= env_cpu(env
);
2005 if (kvm_vm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_PVINFO
) &&
2006 !kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_GET_PVINFO
, pvinfo
)) {
2013 int kvmppc_get_hasidle(CPUPPCState
*env
)
2015 struct kvm_ppc_pvinfo pvinfo
;
2017 if (!kvmppc_get_pvinfo(env
, &pvinfo
) &&
2018 (pvinfo
.flags
& KVM_PPC_PVINFO_FLAGS_EV_IDLE
)) {
2025 int kvmppc_get_hypercall(CPUPPCState
*env
, uint8_t *buf
, int buf_len
)
2027 uint32_t *hc
= (uint32_t *)buf
;
2028 struct kvm_ppc_pvinfo pvinfo
;
2030 if (!kvmppc_get_pvinfo(env
, &pvinfo
)) {
2031 memcpy(buf
, pvinfo
.hcall
, buf_len
);
2036 * Fallback to always fail hypercalls regardless of endianness:
2038 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2040 * b .+8 (becomes nop in wrong endian)
2041 * bswap32(li r3, -1)
2044 hc
[0] = cpu_to_be32(0x08000048);
2045 hc
[1] = cpu_to_be32(0x3860ffff);
2046 hc
[2] = cpu_to_be32(0x48000008);
2047 hc
[3] = cpu_to_be32(bswap32(0x3860ffff));
2052 static inline int kvmppc_enable_hcall(KVMState
*s
, target_ulong hcall
)
2054 return kvm_vm_enable_cap(s
, KVM_CAP_PPC_ENABLE_HCALL
, 0, hcall
, 1);
2057 void kvmppc_enable_logical_ci_hcalls(void)
2060 * FIXME: it would be nice if we could detect the cases where
2061 * we're using a device which requires the in kernel
2062 * implementation of these hcalls, but the kernel lacks them and
2063 * produce a warning.
2065 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_LOAD
);
2066 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_STORE
);
2069 void kvmppc_enable_set_mode_hcall(void)
2071 kvmppc_enable_hcall(kvm_state
, H_SET_MODE
);
2074 void kvmppc_enable_clear_ref_mod_hcalls(void)
2076 kvmppc_enable_hcall(kvm_state
, H_CLEAR_REF
);
2077 kvmppc_enable_hcall(kvm_state
, H_CLEAR_MOD
);
2080 void kvmppc_enable_h_page_init(void)
2082 kvmppc_enable_hcall(kvm_state
, H_PAGE_INIT
);
2085 void kvmppc_set_papr(PowerPCCPU
*cpu
)
2087 CPUState
*cs
= CPU(cpu
);
2090 if (!kvm_enabled()) {
2094 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_PAPR
, 0);
2096 error_report("This vCPU type or KVM version does not support PAPR");
2101 * Update the capability flag so we sync the right information
2107 int kvmppc_set_compat(PowerPCCPU
*cpu
, uint32_t compat_pvr
)
2109 return kvm_set_one_reg(CPU(cpu
), KVM_REG_PPC_ARCH_COMPAT
, &compat_pvr
);
2112 void kvmppc_set_mpic_proxy(PowerPCCPU
*cpu
, int mpic_proxy
)
2114 CPUState
*cs
= CPU(cpu
);
2117 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_EPR
, 0, mpic_proxy
);
2118 if (ret
&& mpic_proxy
) {
2119 error_report("This KVM version does not support EPR");
2124 int kvmppc_smt_threads(void)
2126 return cap_ppc_smt
? cap_ppc_smt
: 1;
2129 int kvmppc_set_smt_threads(int smt
)
2133 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_SMT
, 0, smt
, 0);
2140 void kvmppc_hint_smt_possible(Error
**errp
)
2146 assert(kvm_enabled());
2147 if (cap_ppc_smt_possible
) {
2148 g
= g_string_new("Available VSMT modes:");
2149 for (i
= 63; i
>= 0; i
--) {
2150 if ((1UL << i
) & cap_ppc_smt_possible
) {
2151 g_string_append_printf(g
, " %lu", (1UL << i
));
2154 s
= g_string_free(g
, false);
2155 error_append_hint(errp
, "%s.\n", s
);
2158 error_append_hint(errp
,
2159 "This KVM seems to be too old to support VSMT.\n");
2165 uint64_t kvmppc_rma_size(uint64_t current_size
, unsigned int hash_shift
)
2167 struct kvm_ppc_smmu_info info
;
2168 long rampagesize
, best_page_shift
;
2172 * Find the largest hardware supported page size that's less than
2173 * or equal to the (logical) backing page size of guest RAM
2175 kvm_get_smmu_info(&info
, &error_fatal
);
2176 rampagesize
= qemu_minrampagesize();
2177 best_page_shift
= 0;
2179 for (i
= 0; i
< KVM_PPC_PAGE_SIZES_MAX_SZ
; i
++) {
2180 struct kvm_ppc_one_seg_page_size
*sps
= &info
.sps
[i
];
2182 if (!sps
->page_shift
) {
2186 if ((sps
->page_shift
> best_page_shift
)
2187 && ((1UL << sps
->page_shift
) <= rampagesize
)) {
2188 best_page_shift
= sps
->page_shift
;
2192 return MIN(current_size
,
2193 1ULL << (best_page_shift
+ hash_shift
- 7));
2197 bool kvmppc_spapr_use_multitce(void)
2199 return cap_spapr_multitce
;
2202 int kvmppc_spapr_enable_inkernel_multitce(void)
2206 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2207 H_PUT_TCE_INDIRECT
, 1);
2209 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2216 void *kvmppc_create_spapr_tce(uint32_t liobn
, uint32_t page_shift
,
2217 uint64_t bus_offset
, uint32_t nb_table
,
2218 int *pfd
, bool need_vfio
)
2225 * Must set fd to -1 so we don't try to munmap when called for
2226 * destroying the table, which the upper layers -will- do
2229 if (!cap_spapr_tce
|| (need_vfio
&& !cap_spapr_vfio
)) {
2233 if (cap_spapr_tce_64
) {
2234 struct kvm_create_spapr_tce_64 args
= {
2236 .page_shift
= page_shift
,
2237 .offset
= bus_offset
>> page_shift
,
2241 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE_64
, &args
);
2244 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2248 } else if (cap_spapr_tce
) {
2249 uint64_t window_size
= (uint64_t) nb_table
<< page_shift
;
2250 struct kvm_create_spapr_tce args
= {
2252 .window_size
= window_size
,
2254 if ((window_size
!= args
.window_size
) || bus_offset
) {
2257 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE
, &args
);
2259 fprintf(stderr
, "KVM: Failed to create TCE table for liobn 0x%x\n",
2267 len
= nb_table
* sizeof(uint64_t);
2268 /* FIXME: round this up to page size */
2270 table
= mmap(NULL
, len
, PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, 0);
2271 if (table
== MAP_FAILED
) {
2272 fprintf(stderr
, "KVM: Failed to map TCE table for liobn 0x%x\n",
2282 int kvmppc_remove_spapr_tce(void *table
, int fd
, uint32_t nb_table
)
2290 len
= nb_table
* sizeof(uint64_t);
2291 if ((munmap(table
, len
) < 0) ||
2293 fprintf(stderr
, "KVM: Unexpected error removing TCE table: %s",
2295 /* Leak the table */
2301 int kvmppc_reset_htab(int shift_hint
)
2303 uint32_t shift
= shift_hint
;
2305 if (!kvm_enabled()) {
2306 /* Full emulation, tell caller to allocate htab itself */
2309 if (kvm_vm_check_extension(kvm_state
, KVM_CAP_PPC_ALLOC_HTAB
)) {
2311 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_ALLOCATE_HTAB
, &shift
);
2312 if (ret
== -ENOTTY
) {
2314 * At least some versions of PR KVM advertise the
2315 * capability, but don't implement the ioctl(). Oops.
2316 * Return 0 so that we allocate the htab in qemu, as is
2320 } else if (ret
< 0) {
2327 * We have a kernel that predates the htab reset calls. For PR
2328 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2329 * this era, it has allocated a 16MB fixed size hash table
2332 if (kvmppc_is_pr(kvm_state
)) {
2333 /* PR - tell caller to allocate htab */
2336 /* HV - assume 16MB kernel allocated htab */
2341 static inline uint32_t mfpvr(void)
2350 static void alter_insns(uint64_t *word
, uint64_t flags
, bool on
)
2359 static void kvmppc_host_cpu_class_init(ObjectClass
*oc
, void *data
)
2361 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2362 uint32_t dcache_size
= kvmppc_read_int_cpu_dt("d-cache-size");
2363 uint32_t icache_size
= kvmppc_read_int_cpu_dt("i-cache-size");
2365 /* Now fix up the class with information we can query from the host */
2368 alter_insns(&pcc
->insns_flags
, PPC_ALTIVEC
,
2369 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_ALTIVEC
);
2370 alter_insns(&pcc
->insns_flags2
, PPC2_VSX
,
2371 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_VSX
);
2372 alter_insns(&pcc
->insns_flags2
, PPC2_DFP
,
2373 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_DFP
);
2375 if (dcache_size
!= -1) {
2376 pcc
->l1_dcache_size
= dcache_size
;
2379 if (icache_size
!= -1) {
2380 pcc
->l1_icache_size
= icache_size
;
2383 #if defined(TARGET_PPC64)
2384 pcc
->radix_page_info
= kvm_get_radix_page_info();
2386 if ((pcc
->pvr
& 0xffffff00) == CPU_POWERPC_POWER9_DD1
) {
2388 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2389 * compliant. More importantly, advertising ISA 3.00
2390 * architected mode may prevent guests from activating
2391 * necessary DD1 workarounds.
2393 pcc
->pcr_supported
&= ~(PCR_COMPAT_3_00
| PCR_COMPAT_2_07
2394 | PCR_COMPAT_2_06
| PCR_COMPAT_2_05
);
2396 #endif /* defined(TARGET_PPC64) */
2399 bool kvmppc_has_cap_epr(void)
2404 bool kvmppc_has_cap_fixup_hcalls(void)
2406 return cap_fixup_hcalls
;
2409 bool kvmppc_has_cap_htm(void)
2414 bool kvmppc_has_cap_mmu_radix(void)
2416 return cap_mmu_radix
;
2419 bool kvmppc_has_cap_mmu_hash_v3(void)
2421 return cap_mmu_hash_v3
;
2424 static bool kvmppc_power8_host(void)
2429 uint32_t base_pvr
= CPU_POWERPC_POWER_SERVER_MASK
& mfpvr();
2430 ret
= (base_pvr
== CPU_POWERPC_POWER8E_BASE
) ||
2431 (base_pvr
== CPU_POWERPC_POWER8NVL_BASE
) ||
2432 (base_pvr
== CPU_POWERPC_POWER8_BASE
);
2434 #endif /* TARGET_PPC64 */
2438 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c
)
2440 bool l1d_thread_priv_req
= !kvmppc_power8_host();
2442 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_L1D_FLUSH_PR
) {
2444 } else if ((!l1d_thread_priv_req
||
2445 c
.character
& c
.character_mask
& H_CPU_CHAR_L1D_THREAD_PRIV
) &&
2446 (c
.character
& c
.character_mask
2447 & (H_CPU_CHAR_L1D_FLUSH_ORI30
| H_CPU_CHAR_L1D_FLUSH_TRIG2
))) {
2454 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c
)
2456 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_BNDS_CHK_SPEC_BAR
) {
2458 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_SPEC_BAR_ORI31
) {
2465 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c
)
2467 if ((~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) &&
2468 (~c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) &&
2469 (~c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
)) {
2470 return SPAPR_CAP_FIXED_NA
;
2471 } else if (c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) {
2472 return SPAPR_CAP_WORKAROUND
;
2473 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) {
2474 return SPAPR_CAP_FIXED_CCD
;
2475 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
) {
2476 return SPAPR_CAP_FIXED_IBS
;
2482 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c
)
2484 if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTR_FLUSH_ASSIST
) {
2490 bool kvmppc_has_cap_xive(void)
2495 static void kvmppc_get_cpu_characteristics(KVMState
*s
)
2497 struct kvm_ppc_cpu_char c
;
2501 cap_ppc_safe_cache
= 0;
2502 cap_ppc_safe_bounds_check
= 0;
2503 cap_ppc_safe_indirect_branch
= 0;
2505 ret
= kvm_vm_check_extension(s
, KVM_CAP_PPC_GET_CPU_CHAR
);
2509 ret
= kvm_vm_ioctl(s
, KVM_PPC_GET_CPU_CHAR
, &c
);
2514 cap_ppc_safe_cache
= parse_cap_ppc_safe_cache(c
);
2515 cap_ppc_safe_bounds_check
= parse_cap_ppc_safe_bounds_check(c
);
2516 cap_ppc_safe_indirect_branch
= parse_cap_ppc_safe_indirect_branch(c
);
2517 cap_ppc_count_cache_flush_assist
=
2518 parse_cap_ppc_count_cache_flush_assist(c
);
2521 int kvmppc_get_cap_safe_cache(void)
2523 return cap_ppc_safe_cache
;
2526 int kvmppc_get_cap_safe_bounds_check(void)
2528 return cap_ppc_safe_bounds_check
;
2531 int kvmppc_get_cap_safe_indirect_branch(void)
2533 return cap_ppc_safe_indirect_branch
;
2536 int kvmppc_get_cap_count_cache_flush_assist(void)
2538 return cap_ppc_count_cache_flush_assist
;
2541 bool kvmppc_has_cap_nested_kvm_hv(void)
2543 return !!cap_ppc_nested_kvm_hv
;
2546 int kvmppc_set_cap_nested_kvm_hv(int enable
)
2548 return kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_NESTED_HV
, 0, enable
);
2551 bool kvmppc_has_cap_spapr_vfio(void)
2553 return cap_spapr_vfio
;
2556 int kvmppc_get_cap_large_decr(void)
2558 return cap_large_decr
;
2561 int kvmppc_enable_cap_large_decr(PowerPCCPU
*cpu
, int enable
)
2563 CPUState
*cs
= CPU(cpu
);
2566 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2567 /* Do we need to modify the LPCR? */
2568 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2574 kvm_set_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2575 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2577 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2585 PowerPCCPUClass
*kvm_ppc_get_host_cpu_class(void)
2587 uint32_t host_pvr
= mfpvr();
2588 PowerPCCPUClass
*pvr_pcc
;
2590 pvr_pcc
= ppc_cpu_class_by_pvr(host_pvr
);
2591 if (pvr_pcc
== NULL
) {
2592 pvr_pcc
= ppc_cpu_class_by_pvr_mask(host_pvr
);
2598 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
)
2600 TypeInfo type_info
= {
2601 .name
= TYPE_HOST_POWERPC_CPU
,
2602 .class_init
= kvmppc_host_cpu_class_init
,
2604 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2605 PowerPCCPUClass
*pvr_pcc
;
2610 pvr_pcc
= kvm_ppc_get_host_cpu_class();
2611 if (pvr_pcc
== NULL
) {
2614 type_info
.parent
= object_class_get_name(OBJECT_CLASS(pvr_pcc
));
2615 type_register(&type_info
);
2616 if (object_dynamic_cast(OBJECT(ms
), TYPE_SPAPR_MACHINE
)) {
2617 /* override TCG default cpu type with 'host' cpu model */
2618 mc
->default_cpu_type
= TYPE_HOST_POWERPC_CPU
;
2621 oc
= object_class_by_name(type_info
.name
);
2625 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2626 * we want "POWER8" to be a "family" alias that points to the current
2627 * host CPU type, too)
2629 dc
= DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc
));
2630 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
2631 if (strcasecmp(ppc_cpu_aliases
[i
].alias
, dc
->desc
) == 0) {
2634 ppc_cpu_aliases
[i
].model
= g_strdup(object_class_get_name(oc
));
2635 suffix
= strstr(ppc_cpu_aliases
[i
].model
, POWERPC_CPU_TYPE_SUFFIX
);
2646 int kvmppc_define_rtas_kernel_token(uint32_t token
, const char *function
)
2648 struct kvm_rtas_token_args args
= {
2652 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_RTAS
)) {
2656 strncpy(args
.name
, function
, sizeof(args
.name
) - 1);
2658 return kvm_vm_ioctl(kvm_state
, KVM_PPC_RTAS_DEFINE_TOKEN
, &args
);
2661 int kvmppc_get_htab_fd(bool write
, uint64_t index
, Error
**errp
)
2663 struct kvm_get_htab_fd s
= {
2664 .flags
= write
? KVM_GET_HTAB_WRITE
: 0,
2665 .start_index
= index
,
2670 error_setg(errp
, "KVM version doesn't support %s the HPT",
2671 write
? "writing" : "reading");
2675 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_HTAB_FD
, &s
);
2677 error_setg(errp
, "Unable to open fd for %s HPT %s KVM: %s",
2678 write
? "writing" : "reading", write
? "to" : "from",
2686 int kvmppc_save_htab(QEMUFile
*f
, int fd
, size_t bufsize
, int64_t max_ns
)
2688 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2689 uint8_t buf
[bufsize
];
2693 rc
= read(fd
, buf
, bufsize
);
2695 fprintf(stderr
, "Error reading data from KVM HTAB fd: %s\n",
2699 uint8_t *buffer
= buf
;
2702 struct kvm_get_htab_header
*head
=
2703 (struct kvm_get_htab_header
*) buffer
;
2704 size_t chunksize
= sizeof(*head
) +
2705 HASH_PTE_SIZE_64
* head
->n_valid
;
2707 qemu_put_be32(f
, head
->index
);
2708 qemu_put_be16(f
, head
->n_valid
);
2709 qemu_put_be16(f
, head
->n_invalid
);
2710 qemu_put_buffer(f
, (void *)(head
+ 1),
2711 HASH_PTE_SIZE_64
* head
->n_valid
);
2713 buffer
+= chunksize
;
2719 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) < max_ns
)));
2721 return (rc
== 0) ? 1 : 0;
2724 int kvmppc_load_htab_chunk(QEMUFile
*f
, int fd
, uint32_t index
,
2725 uint16_t n_valid
, uint16_t n_invalid
)
2727 struct kvm_get_htab_header
*buf
;
2728 size_t chunksize
= sizeof(*buf
) + n_valid
* HASH_PTE_SIZE_64
;
2731 buf
= alloca(chunksize
);
2733 buf
->n_valid
= n_valid
;
2734 buf
->n_invalid
= n_invalid
;
2736 qemu_get_buffer(f
, (void *)(buf
+ 1), HASH_PTE_SIZE_64
* n_valid
);
2738 rc
= write(fd
, buf
, chunksize
);
2740 fprintf(stderr
, "Error writing KVM hash table: %s\n",
2744 if (rc
!= chunksize
) {
2745 /* We should never get a short write on a single chunk */
2746 fprintf(stderr
, "Short write, restoring KVM hash table\n");
2752 bool kvm_arch_stop_on_emulation_error(CPUState
*cpu
)
2757 void kvm_arch_init_irq_routing(KVMState
*s
)
2761 void kvmppc_read_hptes(ppc_hash_pte64_t
*hptes
, hwaddr ptex
, int n
)
2766 fd
= kvmppc_get_htab_fd(false, ptex
, &error_abort
);
2770 struct kvm_get_htab_header
*hdr
;
2771 int m
= n
< HPTES_PER_GROUP
? n
: HPTES_PER_GROUP
;
2772 char buf
[sizeof(*hdr
) + m
* HASH_PTE_SIZE_64
];
2774 rc
= read(fd
, buf
, sizeof(buf
));
2776 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2779 hdr
= (struct kvm_get_htab_header
*)buf
;
2780 while ((i
< n
) && ((char *)hdr
< (buf
+ rc
))) {
2781 int invalid
= hdr
->n_invalid
, valid
= hdr
->n_valid
;
2783 if (hdr
->index
!= (ptex
+ i
)) {
2784 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2785 " != (%"HWADDR_PRIu
" + %d", hdr
->index
, ptex
, i
);
2788 if (n
- i
< valid
) {
2791 memcpy(hptes
+ i
, hdr
+ 1, HASH_PTE_SIZE_64
* valid
);
2794 if ((n
- i
) < invalid
) {
2797 memset(hptes
+ i
, 0, invalid
* HASH_PTE_SIZE_64
);
2800 hdr
= (struct kvm_get_htab_header
*)
2801 ((char *)(hdr
+ 1) + HASH_PTE_SIZE_64
* hdr
->n_valid
);
2808 void kvmppc_write_hpte(hwaddr ptex
, uint64_t pte0
, uint64_t pte1
)
2812 struct kvm_get_htab_header hdr
;
2817 fd
= kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort
);
2819 buf
.hdr
.n_valid
= 1;
2820 buf
.hdr
.n_invalid
= 0;
2821 buf
.hdr
.index
= ptex
;
2822 buf
.pte0
= cpu_to_be64(pte0
);
2823 buf
.pte1
= cpu_to_be64(pte1
);
2825 rc
= write(fd
, &buf
, sizeof(buf
));
2826 if (rc
!= sizeof(buf
)) {
2827 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2832 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
2833 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
2838 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
2839 int vector
, PCIDevice
*dev
)
2844 int kvm_arch_release_virq_post(int virq
)
2849 int kvm_arch_msi_data_to_gsi(uint32_t data
)
2851 return data
& 0xffff;
2854 int kvmppc_enable_hwrng(void)
2856 if (!kvm_enabled() || !kvm_check_extension(kvm_state
, KVM_CAP_PPC_HWRNG
)) {
2860 return kvmppc_enable_hcall(kvm_state
, H_RANDOM
);
2863 void kvmppc_check_papr_resize_hpt(Error
**errp
)
2865 if (!kvm_enabled()) {
2866 return; /* No KVM, we're good */
2869 if (cap_resize_hpt
) {
2870 return; /* Kernel has explicit support, we're good */
2873 /* Otherwise fallback on looking for PR KVM */
2874 if (kvmppc_is_pr(kvm_state
)) {
2879 "Hash page table resizing not available with this KVM version");
2882 int kvmppc_resize_hpt_prepare(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2884 CPUState
*cs
= CPU(cpu
);
2885 struct kvm_ppc_resize_hpt rhpt
= {
2890 if (!cap_resize_hpt
) {
2894 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_PREPARE
, &rhpt
);
2897 int kvmppc_resize_hpt_commit(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2899 CPUState
*cs
= CPU(cpu
);
2900 struct kvm_ppc_resize_hpt rhpt
= {
2905 if (!cap_resize_hpt
) {
2909 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_COMMIT
, &rhpt
);
2913 * This is a helper function to detect a post migration scenario
2914 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2915 * the guest kernel can't handle a PVR value other than the actual host
2916 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2918 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2919 * (so, we're HV), return true. The workaround itself is done in
2922 * The order here is important: we'll only check for KVM PR as a
2923 * fallback if the guest kernel can't handle the situation itself.
2924 * We need to avoid as much as possible querying the running KVM type
2927 bool kvmppc_pvr_workaround_required(PowerPCCPU
*cpu
)
2929 CPUState
*cs
= CPU(cpu
);
2931 if (!kvm_enabled()) {
2935 if (cap_ppc_pvr_compat
) {
2939 return !kvmppc_is_pr(cs
->kvm_state
);
2942 void kvmppc_set_reg_ppc_online(PowerPCCPU
*cpu
, unsigned int online
)
2944 CPUState
*cs
= CPU(cpu
);
2946 if (kvm_enabled()) {
2947 kvm_set_one_reg(cs
, KVM_REG_PPC_ONLINE
, &online
);
2951 void kvmppc_set_reg_tb_offset(PowerPCCPU
*cpu
, int64_t tb_offset
)
2953 CPUState
*cs
= CPU(cpu
);
2955 if (kvm_enabled()) {
2956 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &tb_offset
);