target/i386/machine.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "exec/exec-all.h"
   4 #include "hw/i386/pc.h"
   5 #include "hw/isa/isa.h"
   6 #include "migration/cpu.h"
   7 #include "hyperv.h"
   8 #include "kvm_i386.h"
   9
  10 #include "sysemu/kvm.h"
  11 #include "sysemu/tcg.h"
  12
  13 #include "qemu/error-report.h"
  14
  15 static const VMStateDescription vmstate_segment = {
  16     .name = "segment",
  17     .version_id = 1,
  18     .minimum_version_id = 1,
  19     .fields = (VMStateField[]) {
  20         VMSTATE_UINT32(selector, SegmentCache),
  21         VMSTATE_UINTTL(base, SegmentCache),
  22         VMSTATE_UINT32(limit, SegmentCache),
  23         VMSTATE_UINT32(flags, SegmentCache),
  24         VMSTATE_END_OF_LIST()
  25     }
  26 };
  27
  28 #define VMSTATE_SEGMENT(_field, _state) {                            \
  29     .name       = (stringify(_field)),                               \
  30     .size       = sizeof(SegmentCache),                              \
  31     .vmsd       = &vmstate_segment,                                  \
  32     .flags      = VMS_STRUCT,                                        \
  33     .offset     = offsetof(_state, _field)                           \
  34             + type_check(SegmentCache,typeof_field(_state, _field))  \
  35 }
  36
  37 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  38     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  39
  40 static const VMStateDescription vmstate_xmm_reg = {
  41     .name = "xmm_reg",
  42     .version_id = 1,
  43     .minimum_version_id = 1,
  44     .fields = (VMStateField[]) {
  45         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  46         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  47         VMSTATE_END_OF_LIST()
  48     }
  49 };
  50
  51 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
  52     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  53                              vmstate_xmm_reg, ZMMReg)
  54
  55 /* YMMH format is the same as XMM, but for bits 128-255 */
  56 static const VMStateDescription vmstate_ymmh_reg = {
  57     .name = "ymmh_reg",
  58     .version_id = 1,
  59     .minimum_version_id = 1,
  60     .fields = (VMStateField[]) {
  61         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  62         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  63         VMSTATE_END_OF_LIST()
  64     }
  65 };
  66
  67 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
  68     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
  69                              vmstate_ymmh_reg, ZMMReg)
  70
  71 static const VMStateDescription vmstate_zmmh_reg = {
  72     .name = "zmmh_reg",
  73     .version_id = 1,
  74     .minimum_version_id = 1,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  77         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  78         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  79         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  80         VMSTATE_END_OF_LIST()
  81     }
  82 };
  83
  84 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
  85     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  86                              vmstate_zmmh_reg, ZMMReg)
  87
  88 #ifdef TARGET_X86_64
  89 static const VMStateDescription vmstate_hi16_zmm_reg = {
  90     .name = "hi16_zmm_reg",
  91     .version_id = 1,
  92     .minimum_version_id = 1,
  93     .fields = (VMStateField[]) {
  94         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  95         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  96         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  97         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  98         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  99         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
 100         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
 101         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
 102         VMSTATE_END_OF_LIST()
 103     }
 104 };
 105
 106 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
 107     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
 108                              vmstate_hi16_zmm_reg, ZMMReg)
 109 #endif
 110
 111 static const VMStateDescription vmstate_bnd_regs = {
 112     .name = "bnd_regs",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .fields = (VMStateField[]) {
 116         VMSTATE_UINT64(lb, BNDReg),
 117         VMSTATE_UINT64(ub, BNDReg),
 118         VMSTATE_END_OF_LIST()
 119     }
 120 };
 121
 122 #define VMSTATE_BND_REGS(_field, _state, _n)          \
 123     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
 124
 125 static const VMStateDescription vmstate_mtrr_var = {
 126     .name = "mtrr_var",
 127     .version_id = 1,
 128     .minimum_version_id = 1,
 129     .fields = (VMStateField[]) {
 130         VMSTATE_UINT64(base, MTRRVar),
 131         VMSTATE_UINT64(mask, MTRRVar),
 132         VMSTATE_END_OF_LIST()
 133     }
 134 };
 135
 136 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
 137     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
 138
 139 typedef struct x86_FPReg_tmp {
 140     FPReg *parent;
 141     uint64_t tmp_mant;
 142     uint16_t tmp_exp;
 143 } x86_FPReg_tmp;
 144
 145 static void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
 146 {
 147     CPU_LDoubleU temp;
 148
 149     temp.d = f;
 150     *pmant = temp.l.lower;
 151     *pexp = temp.l.upper;
 152 }
 153
 154 static floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
 155 {
 156     CPU_LDoubleU temp;
 157
 158     temp.l.upper = upper;
 159     temp.l.lower = mant;
 160     return temp.d;
 161 }
 162
 163 static int fpreg_pre_save(void *opaque)
 164 {
 165     x86_FPReg_tmp *tmp = opaque;
 166
 167     /* we save the real CPU data (in case of MMX usage only 'mant'
 168        contains the MMX register */
 169     cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d);
 170
 171     return 0;
 172 }
 173
 174 static int fpreg_post_load(void *opaque, int version)
 175 {
 176     x86_FPReg_tmp *tmp = opaque;
 177
 178     tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp);
 179     return 0;
 180 }
 181
 182 static const VMStateDescription vmstate_fpreg_tmp = {
 183     .name = "fpreg_tmp",
 184     .post_load = fpreg_post_load,
 185     .pre_save  = fpreg_pre_save,
 186     .fields = (VMStateField[]) {
 187         VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp),
 188         VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp),
 189         VMSTATE_END_OF_LIST()
 190     }
 191 };
 192
 193 static const VMStateDescription vmstate_fpreg = {
 194     .name = "fpreg",
 195     .fields = (VMStateField[]) {
 196         VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp),
 197         VMSTATE_END_OF_LIST()
 198     }
 199 };
 200
 201 static int cpu_pre_save(void *opaque)
 202 {
 203     X86CPU *cpu = opaque;
 204     CPUX86State *env = &cpu->env;
 205     int i;
 206
 207     /* FPU */
 208     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 209     env->fptag_vmstate = 0;
 210     for(i = 0; i < 8; i++) {
 211         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 212     }
 213
 214     env->fpregs_format_vmstate = 0;
 215
 216     /*
 217      * Real mode guest segments register DPL should be zero.
 218      * Older KVM version were setting it wrongly.
 219      * Fixing it will allow live migration to host with unrestricted guest
 220      * support (otherwise the migration will fail with invalid guest state
 221      * error).
 222      */
 223     if (!(env->cr[0] & CR0_PE_MASK) &&
 224         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 225         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 226         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 227         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 228         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 229         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 230         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 231     }
 232
 233 #ifdef CONFIG_KVM
 234     /*
 235      * In case vCPU may have enabled VMX, we need to make sure kernel have
 236      * required capabilities in order to perform migration correctly:
 237      *
 238      * 1) We must be able to extract vCPU nested-state from KVM.
 239      *
 240      * 2) In case vCPU is running in guest-mode and it has a pending exception,
 241      * we must be able to determine if it's in a pending or injected state.
 242      * Note that in case KVM don't have required capability to do so,
 243      * a pending/injected exception will always appear as an
 244      * injected exception.
 245      */
 246     if (kvm_enabled() && cpu_vmx_maybe_enabled(env) &&
 247         (!env->nested_state ||
 248          (!kvm_has_exception_payload() && (env->hflags & HF_GUEST_MASK) &&
 249           env->exception_injected))) {
 250         error_report("Guest maybe enabled nested virtualization but kernel "
 251                 "does not support required capabilities to save vCPU "
 252                 "nested state");
 253         return -EINVAL;
 254     }
 255 #endif
 256
 257     /*
 258      * When vCPU is running L2 and exception is still pending,
 259      * it can potentially be intercepted by L1 hypervisor.
 260      * In contrast to an injected exception which cannot be
 261      * intercepted anymore.
 262      *
 263      * Furthermore, when a L2 exception is intercepted by L1
 264      * hypervisor, it's exception payload (CR2/DR6 on #PF/#DB)
 265      * should not be set yet in the respective vCPU register.
 266      * Thus, in case an exception is pending, it is
 267      * important to save the exception payload seperately.
 268      *
 269      * Therefore, if an exception is not in a pending state
 270      * or vCPU is not in guest-mode, it is not important to
 271      * distinguish between a pending and injected exception
 272      * and we don't need to store seperately the exception payload.
 273      *
 274      * In order to preserve better backwards-compatabile migration,
 275      * convert a pending exception to an injected exception in
 276      * case it is not important to distingiush between them
 277      * as described above.
 278      */
 279     if (env->exception_pending && !(env->hflags & HF_GUEST_MASK)) {
 280         env->exception_pending = 0;
 281         env->exception_injected = 1;
 282
 283         if (env->exception_has_payload) {
 284             if (env->exception_nr == EXCP01_DB) {
 285                 env->dr[6] = env->exception_payload;
 286             } else if (env->exception_nr == EXCP0E_PAGE) {
 287                 env->cr[2] = env->exception_payload;
 288             }
 289         }
 290     }
 291
 292     return 0;
 293 }
 294
 295 static int cpu_post_load(void *opaque, int version_id)
 296 {
 297     X86CPU *cpu = opaque;
 298     CPUState *cs = CPU(cpu);
 299     CPUX86State *env = &cpu->env;
 300     int i;
 301
 302     if (env->tsc_khz && env->user_tsc_khz &&
 303         env->tsc_khz != env->user_tsc_khz) {
 304         error_report("Mismatch between user-specified TSC frequency and "
 305                      "migrated TSC frequency");
 306         return -EINVAL;
 307     }
 308
 309     if (env->fpregs_format_vmstate) {
 310         error_report("Unsupported old non-softfloat CPU state");
 311         return -EINVAL;
 312     }
 313     /*
 314      * Real mode guest segments register DPL should be zero.
 315      * Older KVM version were setting it wrongly.
 316      * Fixing it will allow live migration from such host that don't have
 317      * restricted guest support to a host with unrestricted guest support
 318      * (otherwise the migration will fail with invalid guest state
 319      * error).
 320      */
 321     if (!(env->cr[0] & CR0_PE_MASK) &&
 322         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 323         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 324         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 325         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 326         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 327         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 328         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 329     }
 330
 331     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
 332      * running under KVM.  This is wrong for conforming code segments.
 333      * Luckily, in our implementation the CPL field of hflags is redundant
 334      * and we can get the right value from the SS descriptor privilege level.
 335      */
 336     env->hflags &= ~HF_CPL_MASK;
 337     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 338
 339 #ifdef CONFIG_KVM
 340     if ((env->hflags & HF_GUEST_MASK) &&
 341         (!env->nested_state ||
 342         !(env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE))) {
 343         error_report("vCPU set in guest-mode inconsistent with "
 344                      "migrated kernel nested state");
 345         return -EINVAL;
 346     }
 347 #endif
 348
 349     /*
 350      * There are cases that we can get valid exception_nr with both
 351      * exception_pending and exception_injected being cleared.
 352      * This can happen in one of the following scenarios:
 353      * 1) Source is older QEMU without KVM_CAP_EXCEPTION_PAYLOAD support.
 354      * 2) Source is running on kernel without KVM_CAP_EXCEPTION_PAYLOAD support.
 355      * 3) "cpu/exception_info" subsection not sent because there is no exception
 356      *    pending or guest wasn't running L2 (See comment in cpu_pre_save()).
 357      *
 358      * In those cases, we can just deduce that a valid exception_nr means
 359      * we can treat the exception as already injected.
 360      */
 361     if ((env->exception_nr != -1) &&
 362         !env->exception_pending && !env->exception_injected) {
 363         env->exception_injected = 1;
 364     }
 365
 366     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 367     env->fpus = env->fpus_vmstate & ~0x3800;
 368     env->fptag_vmstate ^= 0xff;
 369     for(i = 0; i < 8; i++) {
 370         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 371     }
 372     if (tcg_enabled()) {
 373         target_ulong dr7;
 374         update_fp_status(env);
 375         update_mxcsr_status(env);
 376
 377         cpu_breakpoint_remove_all(cs, BP_CPU);
 378         cpu_watchpoint_remove_all(cs, BP_CPU);
 379
 380         /* Indicate all breakpoints disabled, as they are, then
 381            let the helper re-enable them.  */
 382         dr7 = env->dr[7];
 383         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
 384         cpu_x86_update_dr7(env, dr7);
 385     }
 386     tlb_flush(cs);
 387     return 0;
 388 }
 389
 390 static bool async_pf_msr_needed(void *opaque)
 391 {
 392     X86CPU *cpu = opaque;
 393
 394     return cpu->env.async_pf_en_msr != 0;
 395 }
 396
 397 static bool pv_eoi_msr_needed(void *opaque)
 398 {
 399     X86CPU *cpu = opaque;
 400
 401     return cpu->env.pv_eoi_en_msr != 0;
 402 }
 403
 404 static bool steal_time_msr_needed(void *opaque)
 405 {
 406     X86CPU *cpu = opaque;
 407
 408     return cpu->env.steal_time_msr != 0;
 409 }
 410
 411 static bool exception_info_needed(void *opaque)
 412 {
 413     X86CPU *cpu = opaque;
 414     CPUX86State *env = &cpu->env;
 415
 416     /*
 417      * It is important to save exception-info only in case
 418      * we need to distingiush between a pending and injected
 419      * exception. Which is only required in case there is a
 420      * pending exception and vCPU is running L2.
 421      * For more info, refer to comment in cpu_pre_save().
 422      */
 423     return env->exception_pending && (env->hflags & HF_GUEST_MASK);
 424 }
 425
 426 static const VMStateDescription vmstate_exception_info = {
 427     .name = "cpu/exception_info",
 428     .version_id = 1,
 429     .minimum_version_id = 1,
 430     .needed = exception_info_needed,
 431     .fields = (VMStateField[]) {
 432         VMSTATE_UINT8(env.exception_pending, X86CPU),
 433         VMSTATE_UINT8(env.exception_injected, X86CPU),
 434         VMSTATE_UINT8(env.exception_has_payload, X86CPU),
 435         VMSTATE_UINT64(env.exception_payload, X86CPU),
 436         VMSTATE_END_OF_LIST()
 437     }
 438 };
 439
 440 static const VMStateDescription vmstate_steal_time_msr = {
 441     .name = "cpu/steal_time_msr",
 442     .version_id = 1,
 443     .minimum_version_id = 1,
 444     .needed = steal_time_msr_needed,
 445     .fields = (VMStateField[]) {
 446         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 447         VMSTATE_END_OF_LIST()
 448     }
 449 };
 450
 451 static const VMStateDescription vmstate_async_pf_msr = {
 452     .name = "cpu/async_pf_msr",
 453     .version_id = 1,
 454     .minimum_version_id = 1,
 455     .needed = async_pf_msr_needed,
 456     .fields = (VMStateField[]) {
 457         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 458         VMSTATE_END_OF_LIST()
 459     }
 460 };
 461
 462 static const VMStateDescription vmstate_pv_eoi_msr = {
 463     .name = "cpu/async_pv_eoi_msr",
 464     .version_id = 1,
 465     .minimum_version_id = 1,
 466     .needed = pv_eoi_msr_needed,
 467     .fields = (VMStateField[]) {
 468         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 469         VMSTATE_END_OF_LIST()
 470     }
 471 };
 472
 473 static bool fpop_ip_dp_needed(void *opaque)
 474 {
 475     X86CPU *cpu = opaque;
 476     CPUX86State *env = &cpu->env;
 477
 478     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 479 }
 480
 481 static const VMStateDescription vmstate_fpop_ip_dp = {
 482     .name = "cpu/fpop_ip_dp",
 483     .version_id = 1,
 484     .minimum_version_id = 1,
 485     .needed = fpop_ip_dp_needed,
 486     .fields = (VMStateField[]) {
 487         VMSTATE_UINT16(env.fpop, X86CPU),
 488         VMSTATE_UINT64(env.fpip, X86CPU),
 489         VMSTATE_UINT64(env.fpdp, X86CPU),
 490         VMSTATE_END_OF_LIST()
 491     }
 492 };
 493
 494 static bool tsc_adjust_needed(void *opaque)
 495 {
 496     X86CPU *cpu = opaque;
 497     CPUX86State *env = &cpu->env;
 498
 499     return env->tsc_adjust != 0;
 500 }
 501
 502 static const VMStateDescription vmstate_msr_tsc_adjust = {
 503     .name = "cpu/msr_tsc_adjust",
 504     .version_id = 1,
 505     .minimum_version_id = 1,
 506     .needed = tsc_adjust_needed,
 507     .fields = (VMStateField[]) {
 508         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 509         VMSTATE_END_OF_LIST()
 510     }
 511 };
 512
 513 static bool msr_smi_count_needed(void *opaque)
 514 {
 515     X86CPU *cpu = opaque;
 516     CPUX86State *env = &cpu->env;
 517
 518     return cpu->migrate_smi_count && env->msr_smi_count != 0;
 519 }
 520
 521 static const VMStateDescription vmstate_msr_smi_count = {
 522     .name = "cpu/msr_smi_count",
 523     .version_id = 1,
 524     .minimum_version_id = 1,
 525     .needed = msr_smi_count_needed,
 526     .fields = (VMStateField[]) {
 527         VMSTATE_UINT64(env.msr_smi_count, X86CPU),
 528         VMSTATE_END_OF_LIST()
 529     }
 530 };
 531
 532 static bool tscdeadline_needed(void *opaque)
 533 {
 534     X86CPU *cpu = opaque;
 535     CPUX86State *env = &cpu->env;
 536
 537     return env->tsc_deadline != 0;
 538 }
 539
 540 static const VMStateDescription vmstate_msr_tscdeadline = {
 541     .name = "cpu/msr_tscdeadline",
 542     .version_id = 1,
 543     .minimum_version_id = 1,
 544     .needed = tscdeadline_needed,
 545     .fields = (VMStateField[]) {
 546         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 547         VMSTATE_END_OF_LIST()
 548     }
 549 };
 550
 551 static bool misc_enable_needed(void *opaque)
 552 {
 553     X86CPU *cpu = opaque;
 554     CPUX86State *env = &cpu->env;
 555
 556     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 557 }
 558
 559 static bool feature_control_needed(void *opaque)
 560 {
 561     X86CPU *cpu = opaque;
 562     CPUX86State *env = &cpu->env;
 563
 564     return env->msr_ia32_feature_control != 0;
 565 }
 566
 567 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 568     .name = "cpu/msr_ia32_misc_enable",
 569     .version_id = 1,
 570     .minimum_version_id = 1,
 571     .needed = misc_enable_needed,
 572     .fields = (VMStateField[]) {
 573         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 574         VMSTATE_END_OF_LIST()
 575     }
 576 };
 577
 578 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 579     .name = "cpu/msr_ia32_feature_control",
 580     .version_id = 1,
 581     .minimum_version_id = 1,
 582     .needed = feature_control_needed,
 583     .fields = (VMStateField[]) {
 584         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 585         VMSTATE_END_OF_LIST()
 586     }
 587 };
 588
 589 static bool pmu_enable_needed(void *opaque)
 590 {
 591     X86CPU *cpu = opaque;
 592     CPUX86State *env = &cpu->env;
 593     int i;
 594
 595     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 596         env->msr_global_status || env->msr_global_ovf_ctrl) {
 597         return true;
 598     }
 599     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 600         if (env->msr_fixed_counters[i]) {
 601             return true;
 602         }
 603     }
 604     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 605         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 606             return true;
 607         }
 608     }
 609
 610     return false;
 611 }
 612
 613 static const VMStateDescription vmstate_msr_architectural_pmu = {
 614     .name = "cpu/msr_architectural_pmu",
 615     .version_id = 1,
 616     .minimum_version_id = 1,
 617     .needed = pmu_enable_needed,
 618     .fields = (VMStateField[]) {
 619         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 620         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 621         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 622         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 623         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 624         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 625         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 626         VMSTATE_END_OF_LIST()
 627     }
 628 };
 629
 630 static bool mpx_needed(void *opaque)
 631 {
 632     X86CPU *cpu = opaque;
 633     CPUX86State *env = &cpu->env;
 634     unsigned int i;
 635
 636     for (i = 0; i < 4; i++) {
 637         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 638             return true;
 639         }
 640     }
 641
 642     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 643         return true;
 644     }
 645
 646     return !!env->msr_bndcfgs;
 647 }
 648
 649 static const VMStateDescription vmstate_mpx = {
 650     .name = "cpu/mpx",
 651     .version_id = 1,
 652     .minimum_version_id = 1,
 653     .needed = mpx_needed,
 654     .fields = (VMStateField[]) {
 655         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 656         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 657         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 658         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 659         VMSTATE_END_OF_LIST()
 660     }
 661 };
 662
 663 static bool hyperv_hypercall_enable_needed(void *opaque)
 664 {
 665     X86CPU *cpu = opaque;
 666     CPUX86State *env = &cpu->env;
 667
 668     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 669 }
 670
 671 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 672     .name = "cpu/msr_hyperv_hypercall",
 673     .version_id = 1,
 674     .minimum_version_id = 1,
 675     .needed = hyperv_hypercall_enable_needed,
 676     .fields = (VMStateField[]) {
 677         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 678         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 679         VMSTATE_END_OF_LIST()
 680     }
 681 };
 682
 683 static bool hyperv_vapic_enable_needed(void *opaque)
 684 {
 685     X86CPU *cpu = opaque;
 686     CPUX86State *env = &cpu->env;
 687
 688     return env->msr_hv_vapic != 0;
 689 }
 690
 691 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 692     .name = "cpu/msr_hyperv_vapic",
 693     .version_id = 1,
 694     .minimum_version_id = 1,
 695     .needed = hyperv_vapic_enable_needed,
 696     .fields = (VMStateField[]) {
 697         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 698         VMSTATE_END_OF_LIST()
 699     }
 700 };
 701
 702 static bool hyperv_time_enable_needed(void *opaque)
 703 {
 704     X86CPU *cpu = opaque;
 705     CPUX86State *env = &cpu->env;
 706
 707     return env->msr_hv_tsc != 0;
 708 }
 709
 710 static const VMStateDescription vmstate_msr_hyperv_time = {
 711     .name = "cpu/msr_hyperv_time",
 712     .version_id = 1,
 713     .minimum_version_id = 1,
 714     .needed = hyperv_time_enable_needed,
 715     .fields = (VMStateField[]) {
 716         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 717         VMSTATE_END_OF_LIST()
 718     }
 719 };
 720
 721 static bool hyperv_crash_enable_needed(void *opaque)
 722 {
 723     X86CPU *cpu = opaque;
 724     CPUX86State *env = &cpu->env;
 725     int i;
 726
 727     for (i = 0; i < HV_CRASH_PARAMS; i++) {
 728         if (env->msr_hv_crash_params[i]) {
 729             return true;
 730         }
 731     }
 732     return false;
 733 }
 734
 735 static const VMStateDescription vmstate_msr_hyperv_crash = {
 736     .name = "cpu/msr_hyperv_crash",
 737     .version_id = 1,
 738     .minimum_version_id = 1,
 739     .needed = hyperv_crash_enable_needed,
 740     .fields = (VMStateField[]) {
 741         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params, X86CPU, HV_CRASH_PARAMS),
 742         VMSTATE_END_OF_LIST()
 743     }
 744 };
 745
 746 static bool hyperv_runtime_enable_needed(void *opaque)
 747 {
 748     X86CPU *cpu = opaque;
 749     CPUX86State *env = &cpu->env;
 750
 751     if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
 752         return false;
 753     }
 754
 755     return env->msr_hv_runtime != 0;
 756 }
 757
 758 static const VMStateDescription vmstate_msr_hyperv_runtime = {
 759     .name = "cpu/msr_hyperv_runtime",
 760     .version_id = 1,
 761     .minimum_version_id = 1,
 762     .needed = hyperv_runtime_enable_needed,
 763     .fields = (VMStateField[]) {
 764         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
 765         VMSTATE_END_OF_LIST()
 766     }
 767 };
 768
 769 static bool hyperv_synic_enable_needed(void *opaque)
 770 {
 771     X86CPU *cpu = opaque;
 772     CPUX86State *env = &cpu->env;
 773     int i;
 774
 775     if (env->msr_hv_synic_control != 0 ||
 776         env->msr_hv_synic_evt_page != 0 ||
 777         env->msr_hv_synic_msg_page != 0) {
 778         return true;
 779     }
 780
 781     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
 782         if (env->msr_hv_synic_sint[i] != 0) {
 783             return true;
 784         }
 785     }
 786
 787     return false;
 788 }
 789
 790 static int hyperv_synic_post_load(void *opaque, int version_id)
 791 {
 792     X86CPU *cpu = opaque;
 793     hyperv_x86_synic_update(cpu);
 794     return 0;
 795 }
 796
 797 static const VMStateDescription vmstate_msr_hyperv_synic = {
 798     .name = "cpu/msr_hyperv_synic",
 799     .version_id = 1,
 800     .minimum_version_id = 1,
 801     .needed = hyperv_synic_enable_needed,
 802     .post_load = hyperv_synic_post_load,
 803     .fields = (VMStateField[]) {
 804         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
 805         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
 806         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
 807         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU, HV_SINT_COUNT),
 808         VMSTATE_END_OF_LIST()
 809     }
 810 };
 811
 812 static bool hyperv_stimer_enable_needed(void *opaque)
 813 {
 814     X86CPU *cpu = opaque;
 815     CPUX86State *env = &cpu->env;
 816     int i;
 817
 818     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
 819         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
 820             return true;
 821         }
 822     }
 823     return false;
 824 }
 825
 826 static const VMStateDescription vmstate_msr_hyperv_stimer = {
 827     .name = "cpu/msr_hyperv_stimer",
 828     .version_id = 1,
 829     .minimum_version_id = 1,
 830     .needed = hyperv_stimer_enable_needed,
 831     .fields = (VMStateField[]) {
 832         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config, X86CPU,
 833                              HV_STIMER_COUNT),
 834         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count, X86CPU, HV_STIMER_COUNT),
 835         VMSTATE_END_OF_LIST()
 836     }
 837 };
 838
 839 static bool hyperv_reenlightenment_enable_needed(void *opaque)
 840 {
 841     X86CPU *cpu = opaque;
 842     CPUX86State *env = &cpu->env;
 843
 844     return env->msr_hv_reenlightenment_control != 0 ||
 845         env->msr_hv_tsc_emulation_control != 0 ||
 846         env->msr_hv_tsc_emulation_status != 0;
 847 }
 848
 849 static const VMStateDescription vmstate_msr_hyperv_reenlightenment = {
 850     .name = "cpu/msr_hyperv_reenlightenment",
 851     .version_id = 1,
 852     .minimum_version_id = 1,
 853     .needed = hyperv_reenlightenment_enable_needed,
 854     .fields = (VMStateField[]) {
 855         VMSTATE_UINT64(env.msr_hv_reenlightenment_control, X86CPU),
 856         VMSTATE_UINT64(env.msr_hv_tsc_emulation_control, X86CPU),
 857         VMSTATE_UINT64(env.msr_hv_tsc_emulation_status, X86CPU),
 858         VMSTATE_END_OF_LIST()
 859     }
 860 };
 861
 862 static bool avx512_needed(void *opaque)
 863 {
 864     X86CPU *cpu = opaque;
 865     CPUX86State *env = &cpu->env;
 866     unsigned int i;
 867
 868     for (i = 0; i < NB_OPMASK_REGS; i++) {
 869         if (env->opmask_regs[i]) {
 870             return true;
 871         }
 872     }
 873
 874     for (i = 0; i < CPU_NB_REGS; i++) {
 875 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
 876         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
 877             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
 878             return true;
 879         }
 880 #ifdef TARGET_X86_64
 881         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
 882             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
 883             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
 884             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
 885             return true;
 886         }
 887 #endif
 888     }
 889
 890     return false;
 891 }
 892
 893 static const VMStateDescription vmstate_avx512 = {
 894     .name = "cpu/avx512",
 895     .version_id = 1,
 896     .minimum_version_id = 1,
 897     .needed = avx512_needed,
 898     .fields = (VMStateField[]) {
 899         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
 900         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
 901 #ifdef TARGET_X86_64
 902         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
 903 #endif
 904         VMSTATE_END_OF_LIST()
 905     }
 906 };
 907
 908 static bool xss_needed(void *opaque)
 909 {
 910     X86CPU *cpu = opaque;
 911     CPUX86State *env = &cpu->env;
 912
 913     return env->xss != 0;
 914 }
 915
 916 static const VMStateDescription vmstate_xss = {
 917     .name = "cpu/xss",
 918     .version_id = 1,
 919     .minimum_version_id = 1,
 920     .needed = xss_needed,
 921     .fields = (VMStateField[]) {
 922         VMSTATE_UINT64(env.xss, X86CPU),
 923         VMSTATE_END_OF_LIST()
 924     }
 925 };
 926
 927 #ifdef TARGET_X86_64
 928 static bool pkru_needed(void *opaque)
 929 {
 930     X86CPU *cpu = opaque;
 931     CPUX86State *env = &cpu->env;
 932
 933     return env->pkru != 0;
 934 }
 935
 936 static const VMStateDescription vmstate_pkru = {
 937     .name = "cpu/pkru",
 938     .version_id = 1,
 939     .minimum_version_id = 1,
 940     .needed = pkru_needed,
 941     .fields = (VMStateField[]){
 942         VMSTATE_UINT32(env.pkru, X86CPU),
 943         VMSTATE_END_OF_LIST()
 944     }
 945 };
 946 #endif
 947
 948 static bool tsc_khz_needed(void *opaque)
 949 {
 950     X86CPU *cpu = opaque;
 951     CPUX86State *env = &cpu->env;
 952     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
 953     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
 954     return env->tsc_khz && pcmc->save_tsc_khz;
 955 }
 956
 957 static const VMStateDescription vmstate_tsc_khz = {
 958     .name = "cpu/tsc_khz",
 959     .version_id = 1,
 960     .minimum_version_id = 1,
 961     .needed = tsc_khz_needed,
 962     .fields = (VMStateField[]) {
 963         VMSTATE_INT64(env.tsc_khz, X86CPU),
 964         VMSTATE_END_OF_LIST()
 965     }
 966 };
 967
 968 #ifdef CONFIG_KVM
 969
 970 static bool vmx_vmcs12_needed(void *opaque)
 971 {
 972     struct kvm_nested_state *nested_state = opaque;
 973     return (nested_state->size >
 974             offsetof(struct kvm_nested_state, data.vmx[0].vmcs12));
 975 }
 976
 977 static const VMStateDescription vmstate_vmx_vmcs12 = {
 978     .name = "cpu/kvm_nested_state/vmx/vmcs12",
 979     .version_id = 1,
 980     .minimum_version_id = 1,
 981     .needed = vmx_vmcs12_needed,
 982     .fields = (VMStateField[]) {
 983         VMSTATE_UINT8_ARRAY(data.vmx[0].vmcs12,
 984                             struct kvm_nested_state,
 985                             KVM_STATE_NESTED_VMX_VMCS_SIZE),
 986         VMSTATE_END_OF_LIST()
 987     }
 988 };
 989
 990 static bool vmx_shadow_vmcs12_needed(void *opaque)
 991 {
 992     struct kvm_nested_state *nested_state = opaque;
 993     return (nested_state->size >
 994             offsetof(struct kvm_nested_state, data.vmx[0].shadow_vmcs12));
 995 }
 996
 997 static const VMStateDescription vmstate_vmx_shadow_vmcs12 = {
 998     .name = "cpu/kvm_nested_state/vmx/shadow_vmcs12",
 999     .version_id = 1,
1000     .minimum_version_id = 1,
1001     .needed = vmx_shadow_vmcs12_needed,
1002     .fields = (VMStateField[]) {
1003         VMSTATE_UINT8_ARRAY(data.vmx[0].shadow_vmcs12,
1004                             struct kvm_nested_state,
1005                             KVM_STATE_NESTED_VMX_VMCS_SIZE),
1006         VMSTATE_END_OF_LIST()
1007     }
1008 };
1009
1010 static bool vmx_nested_state_needed(void *opaque)
1011 {
1012     struct kvm_nested_state *nested_state = opaque;
1013
1014     return (nested_state->format == KVM_STATE_NESTED_FORMAT_VMX &&
1015             nested_state->hdr.vmx.vmxon_pa != -1ull);
1016 }
1017
1018 static const VMStateDescription vmstate_vmx_nested_state = {
1019     .name = "cpu/kvm_nested_state/vmx",
1020     .version_id = 1,
1021     .minimum_version_id = 1,
1022     .needed = vmx_nested_state_needed,
1023     .fields = (VMStateField[]) {
1024         VMSTATE_U64(hdr.vmx.vmxon_pa, struct kvm_nested_state),
1025         VMSTATE_U64(hdr.vmx.vmcs12_pa, struct kvm_nested_state),
1026         VMSTATE_U16(hdr.vmx.smm.flags, struct kvm_nested_state),
1027         VMSTATE_END_OF_LIST()
1028     },
1029     .subsections = (const VMStateDescription*[]) {
1030         &vmstate_vmx_vmcs12,
1031         &vmstate_vmx_shadow_vmcs12,
1032         NULL,
1033     }
1034 };
1035
1036 static bool nested_state_needed(void *opaque)
1037 {
1038     X86CPU *cpu = opaque;
1039     CPUX86State *env = &cpu->env;
1040
1041     return (env->nested_state &&
1042             vmx_nested_state_needed(env->nested_state));
1043 }
1044
1045 static int nested_state_post_load(void *opaque, int version_id)
1046 {
1047     X86CPU *cpu = opaque;
1048     CPUX86State *env = &cpu->env;
1049     struct kvm_nested_state *nested_state = env->nested_state;
1050     int min_nested_state_len = offsetof(struct kvm_nested_state, data);
1051     int max_nested_state_len = kvm_max_nested_state_length();
1052
1053     /*
1054      * If our kernel don't support setting nested state
1055      * and we have received nested state from migration stream,
1056      * we need to fail migration
1057      */
1058     if (max_nested_state_len <= 0) {
1059         error_report("Received nested state when kernel cannot restore it");
1060         return -EINVAL;
1061     }
1062
1063     /*
1064      * Verify that the size of received nested_state struct
1065      * at least cover required header and is not larger
1066      * than the max size that our kernel support
1067      */
1068     if (nested_state->size < min_nested_state_len) {
1069         error_report("Received nested state size less than min: "
1070                      "len=%d, min=%d",
1071                      nested_state->size, min_nested_state_len);
1072         return -EINVAL;
1073     }
1074     if (nested_state->size > max_nested_state_len) {
1075         error_report("Recieved unsupported nested state size: "
1076                      "nested_state->size=%d, max=%d",
1077                      nested_state->size, max_nested_state_len);
1078         return -EINVAL;
1079     }
1080
1081     /* Verify format is valid */
1082     if ((nested_state->format != KVM_STATE_NESTED_FORMAT_VMX) &&
1083         (nested_state->format != KVM_STATE_NESTED_FORMAT_SVM)) {
1084         error_report("Received invalid nested state format: %d",
1085                      nested_state->format);
1086         return -EINVAL;
1087     }
1088
1089     return 0;
1090 }
1091
1092 static const VMStateDescription vmstate_kvm_nested_state = {
1093     .name = "cpu/kvm_nested_state",
1094     .version_id = 1,
1095     .minimum_version_id = 1,
1096     .fields = (VMStateField[]) {
1097         VMSTATE_U16(flags, struct kvm_nested_state),
1098         VMSTATE_U16(format, struct kvm_nested_state),
1099         VMSTATE_U32(size, struct kvm_nested_state),
1100         VMSTATE_END_OF_LIST()
1101     },
1102     .subsections = (const VMStateDescription*[]) {
1103         &vmstate_vmx_nested_state,
1104         NULL
1105     }
1106 };
1107
1108 static const VMStateDescription vmstate_nested_state = {
1109     .name = "cpu/nested_state",
1110     .version_id = 1,
1111     .minimum_version_id = 1,
1112     .needed = nested_state_needed,
1113     .post_load = nested_state_post_load,
1114     .fields = (VMStateField[]) {
1115         VMSTATE_STRUCT_POINTER(env.nested_state, X86CPU,
1116                 vmstate_kvm_nested_state,
1117                 struct kvm_nested_state),
1118         VMSTATE_END_OF_LIST()
1119     }
1120 };
1121
1122 #endif
1123
1124 static bool mcg_ext_ctl_needed(void *opaque)
1125 {
1126     X86CPU *cpu = opaque;
1127     CPUX86State *env = &cpu->env;
1128     return cpu->enable_lmce && env->mcg_ext_ctl;
1129 }
1130
1131 static const VMStateDescription vmstate_mcg_ext_ctl = {
1132     .name = "cpu/mcg_ext_ctl",
1133     .version_id = 1,
1134     .minimum_version_id = 1,
1135     .needed = mcg_ext_ctl_needed,
1136     .fields = (VMStateField[]) {
1137         VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU),
1138         VMSTATE_END_OF_LIST()
1139     }
1140 };
1141
1142 static bool spec_ctrl_needed(void *opaque)
1143 {
1144     X86CPU *cpu = opaque;
1145     CPUX86State *env = &cpu->env;
1146
1147     return env->spec_ctrl != 0;
1148 }
1149
1150 static const VMStateDescription vmstate_spec_ctrl = {
1151     .name = "cpu/spec_ctrl",
1152     .version_id = 1,
1153     .minimum_version_id = 1,
1154     .needed = spec_ctrl_needed,
1155     .fields = (VMStateField[]){
1156         VMSTATE_UINT64(env.spec_ctrl, X86CPU),
1157         VMSTATE_END_OF_LIST()
1158     }
1159 };
1160
1161 static bool intel_pt_enable_needed(void *opaque)
1162 {
1163     X86CPU *cpu = opaque;
1164     CPUX86State *env = &cpu->env;
1165     int i;
1166
1167     if (env->msr_rtit_ctrl || env->msr_rtit_status ||
1168         env->msr_rtit_output_base || env->msr_rtit_output_mask ||
1169         env->msr_rtit_cr3_match) {
1170         return true;
1171     }
1172
1173     for (i = 0; i < MAX_RTIT_ADDRS; i++) {
1174         if (env->msr_rtit_addrs[i]) {
1175             return true;
1176         }
1177     }
1178
1179     return false;
1180 }
1181
1182 static const VMStateDescription vmstate_msr_intel_pt = {
1183     .name = "cpu/intel_pt",
1184     .version_id = 1,
1185     .minimum_version_id = 1,
1186     .needed = intel_pt_enable_needed,
1187     .fields = (VMStateField[]) {
1188         VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU),
1189         VMSTATE_UINT64(env.msr_rtit_status, X86CPU),
1190         VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU),
1191         VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU),
1192         VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU),
1193         VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS),
1194         VMSTATE_END_OF_LIST()
1195     }
1196 };
1197
1198 static bool virt_ssbd_needed(void *opaque)
1199 {
1200     X86CPU *cpu = opaque;
1201     CPUX86State *env = &cpu->env;
1202
1203     return env->virt_ssbd != 0;
1204 }
1205
1206 static const VMStateDescription vmstate_msr_virt_ssbd = {
1207     .name = "cpu/virt_ssbd",
1208     .version_id = 1,
1209     .minimum_version_id = 1,
1210     .needed = virt_ssbd_needed,
1211     .fields = (VMStateField[]){
1212         VMSTATE_UINT64(env.virt_ssbd, X86CPU),
1213         VMSTATE_END_OF_LIST()
1214     }
1215 };
1216
1217 static bool svm_npt_needed(void *opaque)
1218 {
1219     X86CPU *cpu = opaque;
1220     CPUX86State *env = &cpu->env;
1221
1222     return !!(env->hflags2 & HF2_NPT_MASK);
1223 }
1224
1225 static const VMStateDescription vmstate_svm_npt = {
1226     .name = "cpu/svn_npt",
1227     .version_id = 1,
1228     .minimum_version_id = 1,
1229     .needed = svm_npt_needed,
1230     .fields = (VMStateField[]){
1231         VMSTATE_UINT64(env.nested_cr3, X86CPU),
1232         VMSTATE_UINT32(env.nested_pg_mode, X86CPU),
1233         VMSTATE_END_OF_LIST()
1234     }
1235 };
1236
1237 #ifndef TARGET_X86_64
1238 static bool intel_efer32_needed(void *opaque)
1239 {
1240     X86CPU *cpu = opaque;
1241     CPUX86State *env = &cpu->env;
1242
1243     return env->efer != 0;
1244 }
1245
1246 static const VMStateDescription vmstate_efer32 = {
1247     .name = "cpu/efer32",
1248     .version_id = 1,
1249     .minimum_version_id = 1,
1250     .needed = intel_efer32_needed,
1251     .fields = (VMStateField[]) {
1252         VMSTATE_UINT64(env.efer, X86CPU),
1253         VMSTATE_END_OF_LIST()
1254     }
1255 };
1256 #endif
1257
1258 VMStateDescription vmstate_x86_cpu = {
1259     .name = "cpu",
1260     .version_id = 12,
1261     .minimum_version_id = 11,
1262     .pre_save = cpu_pre_save,
1263     .post_load = cpu_post_load,
1264     .fields = (VMStateField[]) {
1265         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
1266         VMSTATE_UINTTL(env.eip, X86CPU),
1267         VMSTATE_UINTTL(env.eflags, X86CPU),
1268         VMSTATE_UINT32(env.hflags, X86CPU),
1269         /* FPU */
1270         VMSTATE_UINT16(env.fpuc, X86CPU),
1271         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
1272         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
1273         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
1274
1275         VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg),
1276
1277         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
1278         VMSTATE_SEGMENT(env.ldt, X86CPU),
1279         VMSTATE_SEGMENT(env.tr, X86CPU),
1280         VMSTATE_SEGMENT(env.gdt, X86CPU),
1281         VMSTATE_SEGMENT(env.idt, X86CPU),
1282
1283         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
1284         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
1285         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
1286
1287         VMSTATE_UINTTL(env.cr[0], X86CPU),
1288         VMSTATE_UINTTL(env.cr[2], X86CPU),
1289         VMSTATE_UINTTL(env.cr[3], X86CPU),
1290         VMSTATE_UINTTL(env.cr[4], X86CPU),
1291         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
1292         /* MMU */
1293         VMSTATE_INT32(env.a20_mask, X86CPU),
1294         /* XMM */
1295         VMSTATE_UINT32(env.mxcsr, X86CPU),
1296         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
1297
1298 #ifdef TARGET_X86_64
1299         VMSTATE_UINT64(env.efer, X86CPU),
1300         VMSTATE_UINT64(env.star, X86CPU),
1301         VMSTATE_UINT64(env.lstar, X86CPU),
1302         VMSTATE_UINT64(env.cstar, X86CPU),
1303         VMSTATE_UINT64(env.fmask, X86CPU),
1304         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
1305 #endif
1306         VMSTATE_UINT32(env.smbase, X86CPU),
1307
1308         VMSTATE_UINT64(env.pat, X86CPU),
1309         VMSTATE_UINT32(env.hflags2, X86CPU),
1310
1311         VMSTATE_UINT64(env.vm_hsave, X86CPU),
1312         VMSTATE_UINT64(env.vm_vmcb, X86CPU),
1313         VMSTATE_UINT64(env.tsc_offset, X86CPU),
1314         VMSTATE_UINT64(env.intercept, X86CPU),
1315         VMSTATE_UINT16(env.intercept_cr_read, X86CPU),
1316         VMSTATE_UINT16(env.intercept_cr_write, X86CPU),
1317         VMSTATE_UINT16(env.intercept_dr_read, X86CPU),
1318         VMSTATE_UINT16(env.intercept_dr_write, X86CPU),
1319         VMSTATE_UINT32(env.intercept_exceptions, X86CPU),
1320         VMSTATE_UINT8(env.v_tpr, X86CPU),
1321         /* MTRRs */
1322         VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11),
1323         VMSTATE_UINT64(env.mtrr_deftype, X86CPU),
1324         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
1325         /* KVM-related states */
1326         VMSTATE_INT32(env.interrupt_injected, X86CPU),
1327         VMSTATE_UINT32(env.mp_state, X86CPU),
1328         VMSTATE_UINT64(env.tsc, X86CPU),
1329         VMSTATE_INT32(env.exception_nr, X86CPU),
1330         VMSTATE_UINT8(env.soft_interrupt, X86CPU),
1331         VMSTATE_UINT8(env.nmi_injected, X86CPU),
1332         VMSTATE_UINT8(env.nmi_pending, X86CPU),
1333         VMSTATE_UINT8(env.has_error_code, X86CPU),
1334         VMSTATE_UINT32(env.sipi_vector, X86CPU),
1335         /* MCE */
1336         VMSTATE_UINT64(env.mcg_cap, X86CPU),
1337         VMSTATE_UINT64(env.mcg_status, X86CPU),
1338         VMSTATE_UINT64(env.mcg_ctl, X86CPU),
1339         VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4),
1340         /* rdtscp */
1341         VMSTATE_UINT64(env.tsc_aux, X86CPU),
1342         /* KVM pvclock msr */
1343         VMSTATE_UINT64(env.system_time_msr, X86CPU),
1344         VMSTATE_UINT64(env.wall_clock_msr, X86CPU),
1345         /* XSAVE related fields */
1346         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
1347         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
1348         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
1349         VMSTATE_END_OF_LIST()
1350         /* The above list is not sorted /wrt version numbers, watch out! */
1351     },
1352     .subsections = (const VMStateDescription*[]) {
1353         &vmstate_exception_info,
1354         &vmstate_async_pf_msr,
1355         &vmstate_pv_eoi_msr,
1356         &vmstate_steal_time_msr,
1357         &vmstate_fpop_ip_dp,
1358         &vmstate_msr_tsc_adjust,
1359         &vmstate_msr_tscdeadline,
1360         &vmstate_msr_ia32_misc_enable,
1361         &vmstate_msr_ia32_feature_control,
1362         &vmstate_msr_architectural_pmu,
1363         &vmstate_mpx,
1364         &vmstate_msr_hypercall_hypercall,
1365         &vmstate_msr_hyperv_vapic,
1366         &vmstate_msr_hyperv_time,
1367         &vmstate_msr_hyperv_crash,
1368         &vmstate_msr_hyperv_runtime,
1369         &vmstate_msr_hyperv_synic,
1370         &vmstate_msr_hyperv_stimer,
1371         &vmstate_msr_hyperv_reenlightenment,
1372         &vmstate_avx512,
1373         &vmstate_xss,
1374         &vmstate_tsc_khz,
1375         &vmstate_msr_smi_count,
1376 #ifdef TARGET_X86_64
1377         &vmstate_pkru,
1378 #endif
1379         &vmstate_spec_ctrl,
1380         &vmstate_mcg_ext_ctl,
1381         &vmstate_msr_intel_pt,
1382         &vmstate_msr_virt_ssbd,
1383         &vmstate_svm_npt,
1384 #ifndef TARGET_X86_64
1385         &vmstate_efer32,
1386 #endif
1387 #ifdef CONFIG_KVM
1388         &vmstate_nested_state,
1389 #endif
1390         NULL
1391     }
1392 };