hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cpu/core.h"
  12 #include "hw/ppc/spapr_cpu_core.h"
  13 #include "hw/qdev-properties.h"
  14 #include "migration/vmstate.h"
  15 #include "target/ppc/cpu.h"
  16 #include "hw/ppc/spapr.h"
  17 #include "qapi/error.h"
  18 #include "sysemu/cpus.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/ppc/kvm_ppc.h"
  21 #include "hw/ppc/ppc.h"
  22 #include "target/ppc/mmu-hash64.h"
  23 #include "sysemu/numa.h"
  24 #include "sysemu/reset.h"
  25 #include "sysemu/hw_accel.h"
  26 #include "qemu/error-report.h"
  27
  28 static void spapr_cpu_reset(void *opaque)
  29 {
  30     PowerPCCPU *cpu = opaque;
  31     CPUState *cs = CPU(cpu);
  32     CPUPPCState *env = &cpu->env;
  33     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  34     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  35     target_ulong lpcr;
  36
  37     cpu_reset(cs);
  38
  39     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  40      * reset code and the rest are explicitly started up by the guest
  41      * using an RTAS call */
  42     cs->halted = 1;
  43
  44     /* Set compatibility mode to match the boot CPU, which was either set
  45      * by the machine reset code or by CAS. This should never fail.
  46      */
  47     ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
  48
  49     env->spr[SPR_HIOR] = 0;
  50
  51     lpcr = env->spr[SPR_LPCR];
  52
  53     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  54      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  55      * the settings below ensure proper operations with TCG in absence of
  56      * a real hypervisor.
  57      *
  58      * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
  59      * real mode accesses, which thankfully defaults to 0 and isn't
  60      * accessible in guest mode.
  61      *
  62      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  63      * we don't get spurious wakups before an RTAS start-cpu call.
  64      * For the same reason, set PSSCR_EC.
  65      */
  66     lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  67     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  68     env->spr[SPR_PSSCR] |= PSSCR_EC;
  69
  70     /* Set RMLS to the max (ie, 16G) */
  71     lpcr &= ~LPCR_RMLS;
  72     lpcr |= 1ull << LPCR_RMLS_SHIFT;
  73
  74     ppc_store_lpcr(cpu, lpcr);
  75
  76     /* Set a full AMOR so guest can use the AMR as it sees fit */
  77     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  78
  79     spapr_cpu->vpa_addr = 0;
  80     spapr_cpu->slb_shadow_addr = 0;
  81     spapr_cpu->slb_shadow_size = 0;
  82     spapr_cpu->dtl_addr = 0;
  83     spapr_cpu->dtl_size = 0;
  84
  85     spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
  86
  87     kvm_check_mmu(cpu, &error_fatal);
  88 }
  89
  90 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
  91 {
  92     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  93     CPUPPCState *env = &cpu->env;
  94
  95     env->nip = nip;
  96     env->gpr[3] = r3;
  97     kvmppc_set_reg_ppc_online(cpu, 1);
  98     CPU(cpu)->halted = 0;
  99     /* Enable Power-saving mode Exit Cause exceptions */
 100     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
 101 }
 102
 103 /*
 104  * Return the sPAPR CPU core type for @model which essentially is the CPU
 105  * model specified with -cpu cmdline option.
 106  */
 107 const char *spapr_get_cpu_core_type(const char *cpu_type)
 108 {
 109     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 110     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 111                                       len, cpu_type);
 112     ObjectClass *oc = object_class_by_name(core_type);
 113
 114     g_free(core_type);
 115     if (!oc) {
 116         return NULL;
 117     }
 118
 119     return object_class_get_name(oc);
 120 }
 121
 122 static bool slb_shadow_needed(void *opaque)
 123 {
 124     SpaprCpuState *spapr_cpu = opaque;
 125
 126     return spapr_cpu->slb_shadow_addr != 0;
 127 }
 128
 129 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
 130     .name = "spapr_cpu/vpa/slb_shadow",
 131     .version_id = 1,
 132     .minimum_version_id = 1,
 133     .needed = slb_shadow_needed,
 134     .fields = (VMStateField[]) {
 135         VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
 136         VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
 137         VMSTATE_END_OF_LIST()
 138     }
 139 };
 140
 141 static bool dtl_needed(void *opaque)
 142 {
 143     SpaprCpuState *spapr_cpu = opaque;
 144
 145     return spapr_cpu->dtl_addr != 0;
 146 }
 147
 148 static const VMStateDescription vmstate_spapr_cpu_dtl = {
 149     .name = "spapr_cpu/vpa/dtl",
 150     .version_id = 1,
 151     .minimum_version_id = 1,
 152     .needed = dtl_needed,
 153     .fields = (VMStateField[]) {
 154         VMSTATE_UINT64(dtl_addr, SpaprCpuState),
 155         VMSTATE_UINT64(dtl_size, SpaprCpuState),
 156         VMSTATE_END_OF_LIST()
 157     }
 158 };
 159
 160 static bool vpa_needed(void *opaque)
 161 {
 162     SpaprCpuState *spapr_cpu = opaque;
 163
 164     return spapr_cpu->vpa_addr != 0;
 165 }
 166
 167 static const VMStateDescription vmstate_spapr_cpu_vpa = {
 168     .name = "spapr_cpu/vpa",
 169     .version_id = 1,
 170     .minimum_version_id = 1,
 171     .needed = vpa_needed,
 172     .fields = (VMStateField[]) {
 173         VMSTATE_UINT64(vpa_addr, SpaprCpuState),
 174         VMSTATE_END_OF_LIST()
 175     },
 176     .subsections = (const VMStateDescription * []) {
 177         &vmstate_spapr_cpu_slb_shadow,
 178         &vmstate_spapr_cpu_dtl,
 179         NULL
 180     }
 181 };
 182
 183 static const VMStateDescription vmstate_spapr_cpu_state = {
 184     .name = "spapr_cpu",
 185     .version_id = 1,
 186     .minimum_version_id = 1,
 187     .fields = (VMStateField[]) {
 188         VMSTATE_END_OF_LIST()
 189     },
 190     .subsections = (const VMStateDescription * []) {
 191         &vmstate_spapr_cpu_vpa,
 192         NULL
 193     }
 194 };
 195
 196 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 197 {
 198     if (!sc->pre_3_0_migration) {
 199         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 200     }
 201     qemu_unregister_reset(spapr_cpu_reset, cpu);
 202     if (spapr_cpu_state(cpu)->icp) {
 203         object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
 204     }
 205     if (spapr_cpu_state(cpu)->tctx) {
 206         object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
 207     }
 208     cpu_remove_sync(CPU(cpu));
 209     object_unparent(OBJECT(cpu));
 210 }
 211
 212 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
 213 {
 214     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 215     CPUCore *cc = CPU_CORE(dev);
 216     int i;
 217
 218     for (i = 0; i < cc->nr_threads; i++) {
 219         spapr_unrealize_vcpu(sc->threads[i], sc);
 220     }
 221     g_free(sc->threads);
 222 }
 223
 224 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
 225                                SpaprCpuCore *sc, Error **errp)
 226 {
 227     CPUPPCState *env = &cpu->env;
 228     CPUState *cs = CPU(cpu);
 229     Error *local_err = NULL;
 230
 231     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 232     if (local_err) {
 233         goto error;
 234     }
 235
 236     /* Set time-base frequency to 512 MHz */
 237     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 238
 239     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 240     kvmppc_set_papr(cpu);
 241
 242     qemu_register_reset(spapr_cpu_reset, cpu);
 243     spapr_cpu_reset(cpu);
 244
 245     spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
 246     if (local_err) {
 247         goto error_unregister;
 248     }
 249
 250     if (!sc->pre_3_0_migration) {
 251         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 252                          cpu->machine_data);
 253     }
 254
 255     return;
 256
 257 error_unregister:
 258     qemu_unregister_reset(spapr_cpu_reset, cpu);
 259     cpu_remove_sync(CPU(cpu));
 260 error:
 261     error_propagate(errp, local_err);
 262 }
 263
 264 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
 265 {
 266     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 267     CPUCore *cc = CPU_CORE(sc);
 268     Object *obj;
 269     char *id;
 270     CPUState *cs;
 271     PowerPCCPU *cpu;
 272     Error *local_err = NULL;
 273
 274     obj = object_new(scc->cpu_type);
 275
 276     cs = CPU(obj);
 277     cpu = POWERPC_CPU(obj);
 278     cs->cpu_index = cc->core_id + i;
 279     spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 280     if (local_err) {
 281         goto err;
 282     }
 283
 284     cpu->node_id = sc->node_id;
 285
 286     id = g_strdup_printf("thread[%d]", i);
 287     object_property_add_child(OBJECT(sc), id, obj, &local_err);
 288     g_free(id);
 289     if (local_err) {
 290         goto err;
 291     }
 292
 293     cpu->machine_data = g_new0(SpaprCpuState, 1);
 294
 295     object_unref(obj);
 296     return cpu;
 297
 298 err:
 299     object_unref(obj);
 300     error_propagate(errp, local_err);
 301     return NULL;
 302 }
 303
 304 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 305 {
 306     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 307
 308     cpu->machine_data = NULL;
 309     g_free(spapr_cpu);
 310     object_unparent(OBJECT(cpu));
 311 }
 312
 313 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 314 {
 315     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 316      * tries to add a sPAPR CPU core to a non-pseries machine.
 317      */
 318     SpaprMachineState *spapr =
 319         (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
 320                                                   TYPE_SPAPR_MACHINE);
 321     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 322     CPUCore *cc = CPU_CORE(OBJECT(dev));
 323     Error *local_err = NULL;
 324     int i, j;
 325
 326     if (!spapr) {
 327         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 328         return;
 329     }
 330
 331     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 332     for (i = 0; i < cc->nr_threads; i++) {
 333         sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
 334         if (local_err) {
 335             goto err;
 336         }
 337     }
 338
 339     for (j = 0; j < cc->nr_threads; j++) {
 340         spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
 341         if (local_err) {
 342             goto err_unrealize;
 343         }
 344     }
 345     return;
 346
 347 err_unrealize:
 348     while (--j >= 0) {
 349         spapr_unrealize_vcpu(sc->threads[j], sc);
 350     }
 351 err:
 352     while (--i >= 0) {
 353         spapr_delete_vcpu(sc->threads[i], sc);
 354     }
 355     g_free(sc->threads);
 356     error_propagate(errp, local_err);
 357 }
 358
 359 static Property spapr_cpu_core_properties[] = {
 360     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 361     DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
 362                      false),
 363     DEFINE_PROP_END_OF_LIST()
 364 };
 365
 366 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(oc);
 369     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 370
 371     dc->realize = spapr_cpu_core_realize;
 372     dc->unrealize = spapr_cpu_core_unrealize;
 373     dc->props = spapr_cpu_core_properties;
 374     scc->cpu_type = data;
 375 }
 376
 377 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 378     {                                                   \
 379         .parent = TYPE_SPAPR_CPU_CORE,                  \
 380         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 381         .class_init = spapr_cpu_core_class_init,        \
 382         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 383     }
 384
 385 static const TypeInfo spapr_cpu_core_type_infos[] = {
 386     {
 387         .name = TYPE_SPAPR_CPU_CORE,
 388         .parent = TYPE_CPU_CORE,
 389         .abstract = true,
 390         .instance_size = sizeof(SpaprCpuCore),
 391         .class_size = sizeof(SpaprCpuCoreClass),
 392     },
 393     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 394     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 395     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 396     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 397     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 398     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 399     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 400     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 401     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 402     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 403     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 404 #ifdef CONFIG_KVM
 405     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 406 #endif
 407 };
 408
 409 DEFINE_TYPES(spapr_cpu_core_type_infos)