2 * Copyright (C) 2014-2016 Broadcom Corporation
3 * Copyright (c) 2017 Red Hat, Inc.
4 * Written by Prem Mallappa, Eric Auger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "sysemu/sysemu.h"
22 #include "hw/sysbus.h"
23 #include "migration/vmstate.h"
24 #include "hw/qdev-core.h"
25 #include "hw/pci/pci.h"
26 #include "exec/address-spaces.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
33 #include "hw/arm/smmuv3.h"
34 #include "smmuv3-internal.h"
37 * smmuv3_trigger_irq - pulse @irq if enabled and update
38 * GERROR register in case of GERROR interrupt
41 * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
43 static void smmuv3_trigger_irq(SMMUv3State
*s
, SMMUIrq irq
,
51 pulse
= smmuv3_eventq_irq_enabled(s
);
54 qemu_log_mask(LOG_UNIMP
, "PRI not yet supported\n");
56 case SMMU_IRQ_CMD_SYNC
:
61 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
62 uint32_t new_gerrors
= ~pending
& gerror_mask
;
65 /* only toggle non pending errors */
68 s
->gerror
^= new_gerrors
;
69 trace_smmuv3_write_gerror(new_gerrors
, s
->gerror
);
71 pulse
= smmuv3_gerror_irq_enabled(s
);
76 trace_smmuv3_trigger_irq(irq
);
77 qemu_irq_pulse(s
->irq
[irq
]);
81 static void smmuv3_write_gerrorn(SMMUv3State
*s
, uint32_t new_gerrorn
)
83 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
84 uint32_t toggled
= s
->gerrorn
^ new_gerrorn
;
86 if (toggled
& ~pending
) {
87 qemu_log_mask(LOG_GUEST_ERROR
,
88 "guest toggles non pending errors = 0x%x\n",
93 * We do not raise any error in case guest toggles bits corresponding
94 * to not active IRQs (CONSTRAINED UNPREDICTABLE)
96 s
->gerrorn
= new_gerrorn
;
98 trace_smmuv3_write_gerrorn(toggled
& pending
, s
->gerrorn
);
101 static inline MemTxResult
queue_read(SMMUQueue
*q
, void *data
)
103 dma_addr_t addr
= Q_CONS_ENTRY(q
);
105 return dma_memory_read(&address_space_memory
, addr
, data
, q
->entry_size
);
108 static MemTxResult
queue_write(SMMUQueue
*q
, void *data
)
110 dma_addr_t addr
= Q_PROD_ENTRY(q
);
113 ret
= dma_memory_write(&address_space_memory
, addr
, data
, q
->entry_size
);
114 if (ret
!= MEMTX_OK
) {
122 static MemTxResult
smmuv3_write_eventq(SMMUv3State
*s
, Evt
*evt
)
124 SMMUQueue
*q
= &s
->eventq
;
127 if (!smmuv3_eventq_enabled(s
)) {
131 if (smmuv3_q_full(q
)) {
135 r
= queue_write(q
, evt
);
140 if (!smmuv3_q_empty(q
)) {
141 smmuv3_trigger_irq(s
, SMMU_IRQ_EVTQ
, 0);
146 void smmuv3_record_event(SMMUv3State
*s
, SMMUEventInfo
*info
)
151 if (!smmuv3_eventq_enabled(s
)) {
155 EVT_SET_TYPE(&evt
, info
->type
);
156 EVT_SET_SID(&evt
, info
->sid
);
158 switch (info
->type
) {
162 EVT_SET_SSID(&evt
, info
->u
.f_uut
.ssid
);
163 EVT_SET_SSV(&evt
, info
->u
.f_uut
.ssv
);
164 EVT_SET_ADDR(&evt
, info
->u
.f_uut
.addr
);
165 EVT_SET_RNW(&evt
, info
->u
.f_uut
.rnw
);
166 EVT_SET_PNU(&evt
, info
->u
.f_uut
.pnu
);
167 EVT_SET_IND(&evt
, info
->u
.f_uut
.ind
);
169 case SMMU_EVT_C_BAD_STREAMID
:
170 EVT_SET_SSID(&evt
, info
->u
.c_bad_streamid
.ssid
);
171 EVT_SET_SSV(&evt
, info
->u
.c_bad_streamid
.ssv
);
173 case SMMU_EVT_F_STE_FETCH
:
174 EVT_SET_SSID(&evt
, info
->u
.f_ste_fetch
.ssid
);
175 EVT_SET_SSV(&evt
, info
->u
.f_ste_fetch
.ssv
);
176 EVT_SET_ADDR(&evt
, info
->u
.f_ste_fetch
.addr
);
178 case SMMU_EVT_C_BAD_STE
:
179 EVT_SET_SSID(&evt
, info
->u
.c_bad_ste
.ssid
);
180 EVT_SET_SSV(&evt
, info
->u
.c_bad_ste
.ssv
);
182 case SMMU_EVT_F_STREAM_DISABLED
:
184 case SMMU_EVT_F_TRANS_FORBIDDEN
:
185 EVT_SET_ADDR(&evt
, info
->u
.f_transl_forbidden
.addr
);
186 EVT_SET_RNW(&evt
, info
->u
.f_transl_forbidden
.rnw
);
188 case SMMU_EVT_C_BAD_SUBSTREAMID
:
189 EVT_SET_SSID(&evt
, info
->u
.c_bad_substream
.ssid
);
191 case SMMU_EVT_F_CD_FETCH
:
192 EVT_SET_SSID(&evt
, info
->u
.f_cd_fetch
.ssid
);
193 EVT_SET_SSV(&evt
, info
->u
.f_cd_fetch
.ssv
);
194 EVT_SET_ADDR(&evt
, info
->u
.f_cd_fetch
.addr
);
196 case SMMU_EVT_C_BAD_CD
:
197 EVT_SET_SSID(&evt
, info
->u
.c_bad_cd
.ssid
);
198 EVT_SET_SSV(&evt
, info
->u
.c_bad_cd
.ssv
);
200 case SMMU_EVT_F_WALK_EABT
:
201 case SMMU_EVT_F_TRANSLATION
:
202 case SMMU_EVT_F_ADDR_SIZE
:
203 case SMMU_EVT_F_ACCESS
:
204 case SMMU_EVT_F_PERMISSION
:
205 EVT_SET_STALL(&evt
, info
->u
.f_walk_eabt
.stall
);
206 EVT_SET_STAG(&evt
, info
->u
.f_walk_eabt
.stag
);
207 EVT_SET_SSID(&evt
, info
->u
.f_walk_eabt
.ssid
);
208 EVT_SET_SSV(&evt
, info
->u
.f_walk_eabt
.ssv
);
209 EVT_SET_S2(&evt
, info
->u
.f_walk_eabt
.s2
);
210 EVT_SET_ADDR(&evt
, info
->u
.f_walk_eabt
.addr
);
211 EVT_SET_RNW(&evt
, info
->u
.f_walk_eabt
.rnw
);
212 EVT_SET_PNU(&evt
, info
->u
.f_walk_eabt
.pnu
);
213 EVT_SET_IND(&evt
, info
->u
.f_walk_eabt
.ind
);
214 EVT_SET_CLASS(&evt
, info
->u
.f_walk_eabt
.class);
215 EVT_SET_ADDR2(&evt
, info
->u
.f_walk_eabt
.addr2
);
217 case SMMU_EVT_F_CFG_CONFLICT
:
218 EVT_SET_SSID(&evt
, info
->u
.f_cfg_conflict
.ssid
);
219 EVT_SET_SSV(&evt
, info
->u
.f_cfg_conflict
.ssv
);
221 /* rest is not implemented */
222 case SMMU_EVT_F_BAD_ATS_TREQ
:
223 case SMMU_EVT_F_TLB_CONFLICT
:
224 case SMMU_EVT_E_PAGE_REQ
:
226 g_assert_not_reached();
229 trace_smmuv3_record_event(smmu_event_string(info
->type
), info
->sid
);
230 r
= smmuv3_write_eventq(s
, &evt
);
232 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_EVENTQ_ABT_ERR_MASK
);
234 info
->recorded
= true;
237 static void smmuv3_init_regs(SMMUv3State
*s
)
240 * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
241 * multi-level stream table
243 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, S1P
, 1); /* stage 1 supported */
244 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTF
, 2); /* AArch64 PTW only */
245 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, COHACC
, 1); /* IO coherent */
246 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, ASID16
, 1); /* 16-bit ASID */
247 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTENDIAN
, 2); /* little endian */
248 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STALL_MODEL
, 1); /* No stall */
249 /* terminated transaction will always be aborted/error returned */
250 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TERM_MODEL
, 1);
251 /* 2-level stream table supported */
252 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STLEVEL
, 1);
254 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, SIDSIZE
, SMMU_IDR1_SIDSIZE
);
255 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, EVENTQS
, SMMU_EVENTQS
);
256 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, CMDQS
, SMMU_CMDQS
);
258 /* 4K and 64K granule support */
259 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN4K
, 1);
260 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN64K
, 1);
261 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, OAS
, SMMU_IDR5_OAS
); /* 44 bits */
263 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 5, SMMU_CMDQS
);
266 s
->cmdq
.entry_size
= sizeof(struct Cmd
);
267 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 5, SMMU_EVENTQS
);
270 s
->eventq
.entry_size
= sizeof(struct Evt
);
276 static int smmu_get_ste(SMMUv3State
*s
, dma_addr_t addr
, STE
*buf
,
277 SMMUEventInfo
*event
)
281 trace_smmuv3_get_ste(addr
);
282 /* TODO: guarantee 64-bit single-copy atomicity */
283 ret
= dma_memory_read(&address_space_memory
, addr
,
284 (void *)buf
, sizeof(*buf
));
285 if (ret
!= MEMTX_OK
) {
286 qemu_log_mask(LOG_GUEST_ERROR
,
287 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
288 event
->type
= SMMU_EVT_F_STE_FETCH
;
289 event
->u
.f_ste_fetch
.addr
= addr
;
296 /* @ssid > 0 not supported yet */
297 static int smmu_get_cd(SMMUv3State
*s
, STE
*ste
, uint32_t ssid
,
298 CD
*buf
, SMMUEventInfo
*event
)
300 dma_addr_t addr
= STE_CTXPTR(ste
);
303 trace_smmuv3_get_cd(addr
);
304 /* TODO: guarantee 64-bit single-copy atomicity */
305 ret
= dma_memory_read(&address_space_memory
, addr
,
306 (void *)buf
, sizeof(*buf
));
307 if (ret
!= MEMTX_OK
) {
308 qemu_log_mask(LOG_GUEST_ERROR
,
309 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
310 event
->type
= SMMU_EVT_F_CD_FETCH
;
311 event
->u
.f_ste_fetch
.addr
= addr
;
317 /* Returns < 0 in case of invalid STE, 0 otherwise */
318 static int decode_ste(SMMUv3State
*s
, SMMUTransCfg
*cfg
,
319 STE
*ste
, SMMUEventInfo
*event
)
323 if (!STE_VALID(ste
)) {
327 config
= STE_CONFIG(ste
);
329 if (STE_CFG_ABORT(config
)) {
334 if (STE_CFG_BYPASS(config
)) {
335 cfg
->bypassed
= true;
339 if (STE_CFG_S2_ENABLED(config
)) {
340 qemu_log_mask(LOG_UNIMP
, "SMMUv3 does not support stage 2 yet\n");
344 if (STE_S1CDMAX(ste
) != 0) {
345 qemu_log_mask(LOG_UNIMP
,
346 "SMMUv3 does not support multiple context descriptors yet\n");
350 if (STE_S1STALLD(ste
)) {
351 qemu_log_mask(LOG_UNIMP
,
352 "SMMUv3 S1 stalling fault model not allowed yet\n");
358 event
->type
= SMMU_EVT_C_BAD_STE
;
363 * smmu_find_ste - Return the stream table entry associated
368 * @ste: returned stream table entry
369 * @event: handle to an event info
371 * Supports linear and 2-level stream table
372 * Return 0 on success, -EINVAL otherwise
374 static int smmu_find_ste(SMMUv3State
*s
, uint32_t sid
, STE
*ste
,
375 SMMUEventInfo
*event
)
380 trace_smmuv3_find_ste(sid
, s
->features
, s
->sid_split
);
381 /* Check SID range */
382 if (sid
> (1 << SMMU_IDR1_SIDSIZE
)) {
383 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
386 if (s
->features
& SMMU_FEATURE_2LVL_STE
) {
387 int l1_ste_offset
, l2_ste_offset
, max_l2_ste
, span
;
388 dma_addr_t strtab_base
, l1ptr
, l2ptr
;
391 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
;
392 l1_ste_offset
= sid
>> s
->sid_split
;
393 l2_ste_offset
= sid
& ((1 << s
->sid_split
) - 1);
394 l1ptr
= (dma_addr_t
)(strtab_base
+ l1_ste_offset
* sizeof(l1std
));
395 /* TODO: guarantee 64-bit single-copy atomicity */
396 ret
= dma_memory_read(&address_space_memory
, l1ptr
,
397 (uint8_t *)&l1std
, sizeof(l1std
));
398 if (ret
!= MEMTX_OK
) {
399 qemu_log_mask(LOG_GUEST_ERROR
,
400 "Could not read L1PTR at 0X%"PRIx64
"\n", l1ptr
);
401 event
->type
= SMMU_EVT_F_STE_FETCH
;
402 event
->u
.f_ste_fetch
.addr
= l1ptr
;
406 span
= L1STD_SPAN(&l1std
);
409 /* l2ptr is not valid */
410 qemu_log_mask(LOG_GUEST_ERROR
,
411 "invalid sid=%d (L1STD span=0)\n", sid
);
412 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
415 max_l2_ste
= (1 << span
) - 1;
416 l2ptr
= l1std_l2ptr(&l1std
);
417 trace_smmuv3_find_ste_2lvl(s
->strtab_base
, l1ptr
, l1_ste_offset
,
418 l2ptr
, l2_ste_offset
, max_l2_ste
);
419 if (l2_ste_offset
> max_l2_ste
) {
420 qemu_log_mask(LOG_GUEST_ERROR
,
421 "l2_ste_offset=%d > max_l2_ste=%d\n",
422 l2_ste_offset
, max_l2_ste
);
423 event
->type
= SMMU_EVT_C_BAD_STE
;
426 addr
= l2ptr
+ l2_ste_offset
* sizeof(*ste
);
428 addr
= s
->strtab_base
+ sid
* sizeof(*ste
);
431 if (smmu_get_ste(s
, addr
, ste
, event
)) {
438 static int decode_cd(SMMUTransCfg
*cfg
, CD
*cd
, SMMUEventInfo
*event
)
443 if (!CD_VALID(cd
) || !CD_AARCH64(cd
)) {
447 goto bad_cd
; /* SMMU_IDR0.TERM_MODEL == 1 */
450 goto bad_cd
; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */
452 if (CD_HA(cd
) || CD_HD(cd
)) {
453 goto bad_cd
; /* HTTU = 0 */
456 /* we support only those at the moment */
460 cfg
->oas
= oas2bits(CD_IPS(cd
));
461 cfg
->oas
= MIN(oas2bits(SMMU_IDR5_OAS
), cfg
->oas
);
462 cfg
->tbi
= CD_TBI(cd
);
463 cfg
->asid
= CD_ASID(cd
);
465 trace_smmuv3_decode_cd(cfg
->oas
);
467 /* decode data dependent on TT */
468 for (i
= 0; i
<= 1; i
++) {
470 SMMUTransTableInfo
*tt
= &cfg
->tt
[i
];
472 cfg
->tt
[i
].disabled
= CD_EPD(cd
, i
);
473 if (cfg
->tt
[i
].disabled
) {
478 if (tsz
< 16 || tsz
> 39) {
483 tt
->granule_sz
= tg2granule(tg
, i
);
484 if ((tt
->granule_sz
!= 12 && tt
->granule_sz
!= 16) || CD_ENDI(cd
)) {
489 tt
->ttb
= CD_TTB(cd
, i
);
490 if (tt
->ttb
& ~(MAKE_64BIT_MASK(0, cfg
->oas
))) {
493 trace_smmuv3_decode_cd_tt(i
, tt
->tsz
, tt
->ttb
, tt
->granule_sz
);
496 event
->record_trans_faults
= CD_R(cd
);
501 event
->type
= SMMU_EVT_C_BAD_CD
;
506 * smmuv3_decode_config - Prepare the translation configuration
507 * for the @mr iommu region
508 * @mr: iommu memory region the translation config must be prepared for
509 * @cfg: output translation configuration which is populated through
510 * the different configuration decoding steps
511 * @event: must be zero'ed by the caller
513 * return < 0 in case of config decoding error (@event is filled
514 * accordingly). Return 0 otherwise.
516 static int smmuv3_decode_config(IOMMUMemoryRegion
*mr
, SMMUTransCfg
*cfg
,
517 SMMUEventInfo
*event
)
519 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
520 uint32_t sid
= smmu_get_sid(sdev
);
521 SMMUv3State
*s
= sdev
->smmu
;
526 ret
= smmu_find_ste(s
, sid
, &ste
, event
);
531 ret
= decode_ste(s
, cfg
, &ste
, event
);
536 if (cfg
->aborted
|| cfg
->bypassed
) {
540 ret
= smmu_get_cd(s
, &ste
, 0 /* ssid */, &cd
, event
);
545 return decode_cd(cfg
, &cd
, event
);
549 * smmuv3_get_config - Look up for a cached copy of configuration data for
550 * @sdev and on cache miss performs a configuration structure decoding from
553 * @sdev: SMMUDevice handle
554 * @event: output event info
556 * The configuration cache contains data resulting from both STE and CD
557 * decoding under the form of an SMMUTransCfg struct. The hash table is indexed
558 * by the SMMUDevice handle.
560 static SMMUTransCfg
*smmuv3_get_config(SMMUDevice
*sdev
, SMMUEventInfo
*event
)
562 SMMUv3State
*s
= sdev
->smmu
;
563 SMMUState
*bc
= &s
->smmu_state
;
566 cfg
= g_hash_table_lookup(bc
->configs
, sdev
);
568 sdev
->cfg_cache_hits
++;
569 trace_smmuv3_config_cache_hit(smmu_get_sid(sdev
),
570 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
571 100 * sdev
->cfg_cache_hits
/
572 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
574 sdev
->cfg_cache_misses
++;
575 trace_smmuv3_config_cache_miss(smmu_get_sid(sdev
),
576 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
577 100 * sdev
->cfg_cache_hits
/
578 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
579 cfg
= g_new0(SMMUTransCfg
, 1);
581 if (!smmuv3_decode_config(&sdev
->iommu
, cfg
, event
)) {
582 g_hash_table_insert(bc
->configs
, sdev
, cfg
);
591 static void smmuv3_flush_config(SMMUDevice
*sdev
)
593 SMMUv3State
*s
= sdev
->smmu
;
594 SMMUState
*bc
= &s
->smmu_state
;
596 trace_smmuv3_config_cache_inv(smmu_get_sid(sdev
));
597 g_hash_table_remove(bc
->configs
, sdev
);
600 static IOMMUTLBEntry
smmuv3_translate(IOMMUMemoryRegion
*mr
, hwaddr addr
,
601 IOMMUAccessFlags flag
, int iommu_idx
)
603 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
604 SMMUv3State
*s
= sdev
->smmu
;
605 uint32_t sid
= smmu_get_sid(sdev
);
606 SMMUEventInfo event
= {.type
= SMMU_EVT_NONE
, .sid
= sid
};
607 SMMUPTWEventInfo ptw_info
= {};
608 SMMUTranslationStatus status
;
609 SMMUState
*bs
= ARM_SMMU(s
);
610 uint64_t page_mask
, aligned_addr
;
611 IOMMUTLBEntry
*cached_entry
= NULL
;
612 SMMUTransTableInfo
*tt
;
613 SMMUTransCfg
*cfg
= NULL
;
614 IOMMUTLBEntry entry
= {
615 .target_as
= &address_space_memory
,
617 .translated_addr
= addr
,
618 .addr_mask
= ~(hwaddr
)0,
621 SMMUIOTLBKey key
, *new_key
;
623 qemu_mutex_lock(&s
->mutex
);
625 if (!smmu_enabled(s
)) {
626 status
= SMMU_TRANS_DISABLE
;
630 cfg
= smmuv3_get_config(sdev
, &event
);
632 status
= SMMU_TRANS_ERROR
;
637 status
= SMMU_TRANS_ABORT
;
642 status
= SMMU_TRANS_BYPASS
;
646 tt
= select_tt(cfg
, addr
);
648 if (event
.record_trans_faults
) {
649 event
.type
= SMMU_EVT_F_TRANSLATION
;
650 event
.u
.f_translation
.addr
= addr
;
651 event
.u
.f_translation
.rnw
= flag
& 0x1;
653 status
= SMMU_TRANS_ERROR
;
657 page_mask
= (1ULL << (tt
->granule_sz
)) - 1;
658 aligned_addr
= addr
& ~page_mask
;
660 key
.asid
= cfg
->asid
;
661 key
.iova
= aligned_addr
;
663 cached_entry
= g_hash_table_lookup(bs
->iotlb
, &key
);
666 trace_smmu_iotlb_cache_hit(cfg
->asid
, aligned_addr
,
667 cfg
->iotlb_hits
, cfg
->iotlb_misses
,
668 100 * cfg
->iotlb_hits
/
669 (cfg
->iotlb_hits
+ cfg
->iotlb_misses
));
670 if ((flag
& IOMMU_WO
) && !(cached_entry
->perm
& IOMMU_WO
)) {
671 status
= SMMU_TRANS_ERROR
;
672 if (event
.record_trans_faults
) {
673 event
.type
= SMMU_EVT_F_PERMISSION
;
674 event
.u
.f_permission
.addr
= addr
;
675 event
.u
.f_permission
.rnw
= flag
& 0x1;
678 status
= SMMU_TRANS_SUCCESS
;
684 trace_smmu_iotlb_cache_miss(cfg
->asid
, addr
& ~page_mask
,
685 cfg
->iotlb_hits
, cfg
->iotlb_misses
,
686 100 * cfg
->iotlb_hits
/
687 (cfg
->iotlb_hits
+ cfg
->iotlb_misses
));
689 if (g_hash_table_size(bs
->iotlb
) >= SMMU_IOTLB_MAX_SIZE
) {
690 smmu_iotlb_inv_all(bs
);
693 cached_entry
= g_new0(IOMMUTLBEntry
, 1);
695 if (smmu_ptw(cfg
, aligned_addr
, flag
, cached_entry
, &ptw_info
)) {
696 g_free(cached_entry
);
697 switch (ptw_info
.type
) {
698 case SMMU_PTW_ERR_WALK_EABT
:
699 event
.type
= SMMU_EVT_F_WALK_EABT
;
700 event
.u
.f_walk_eabt
.addr
= addr
;
701 event
.u
.f_walk_eabt
.rnw
= flag
& 0x1;
702 event
.u
.f_walk_eabt
.class = 0x1;
703 event
.u
.f_walk_eabt
.addr2
= ptw_info
.addr
;
705 case SMMU_PTW_ERR_TRANSLATION
:
706 if (event
.record_trans_faults
) {
707 event
.type
= SMMU_EVT_F_TRANSLATION
;
708 event
.u
.f_translation
.addr
= addr
;
709 event
.u
.f_translation
.rnw
= flag
& 0x1;
712 case SMMU_PTW_ERR_ADDR_SIZE
:
713 if (event
.record_trans_faults
) {
714 event
.type
= SMMU_EVT_F_ADDR_SIZE
;
715 event
.u
.f_addr_size
.addr
= addr
;
716 event
.u
.f_addr_size
.rnw
= flag
& 0x1;
719 case SMMU_PTW_ERR_ACCESS
:
720 if (event
.record_trans_faults
) {
721 event
.type
= SMMU_EVT_F_ACCESS
;
722 event
.u
.f_access
.addr
= addr
;
723 event
.u
.f_access
.rnw
= flag
& 0x1;
726 case SMMU_PTW_ERR_PERMISSION
:
727 if (event
.record_trans_faults
) {
728 event
.type
= SMMU_EVT_F_PERMISSION
;
729 event
.u
.f_permission
.addr
= addr
;
730 event
.u
.f_permission
.rnw
= flag
& 0x1;
734 g_assert_not_reached();
736 status
= SMMU_TRANS_ERROR
;
738 new_key
= g_new0(SMMUIOTLBKey
, 1);
739 new_key
->asid
= cfg
->asid
;
740 new_key
->iova
= aligned_addr
;
741 g_hash_table_insert(bs
->iotlb
, new_key
, cached_entry
);
742 status
= SMMU_TRANS_SUCCESS
;
746 qemu_mutex_unlock(&s
->mutex
);
748 case SMMU_TRANS_SUCCESS
:
750 entry
.translated_addr
= cached_entry
->translated_addr
+
752 entry
.addr_mask
= cached_entry
->addr_mask
;
753 trace_smmuv3_translate_success(mr
->parent_obj
.name
, sid
, addr
,
754 entry
.translated_addr
, entry
.perm
);
756 case SMMU_TRANS_DISABLE
:
758 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
759 trace_smmuv3_translate_disable(mr
->parent_obj
.name
, sid
, addr
,
762 case SMMU_TRANS_BYPASS
:
764 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
765 trace_smmuv3_translate_bypass(mr
->parent_obj
.name
, sid
, addr
,
768 case SMMU_TRANS_ABORT
:
769 /* no event is recorded on abort */
770 trace_smmuv3_translate_abort(mr
->parent_obj
.name
, sid
, addr
,
773 case SMMU_TRANS_ERROR
:
774 qemu_log_mask(LOG_GUEST_ERROR
,
775 "%s translation failed for iova=0x%"PRIx64
"(%s)\n",
776 mr
->parent_obj
.name
, addr
, smmu_event_string(event
.type
));
777 smmuv3_record_event(s
, &event
);
785 * smmuv3_notify_iova - call the notifier @n for a given
786 * @asid and @iova tuple.
788 * @mr: IOMMU mr region handle
789 * @n: notifier to be called
790 * @asid: address space ID or negative value if we don't care
793 static void smmuv3_notify_iova(IOMMUMemoryRegion
*mr
,
798 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
799 SMMUEventInfo event
= {};
800 SMMUTransTableInfo
*tt
;
804 cfg
= smmuv3_get_config(sdev
, &event
);
806 qemu_log_mask(LOG_GUEST_ERROR
,
807 "%s error decoding the configuration for iommu mr=%s\n",
808 __func__
, mr
->parent_obj
.name
);
812 if (asid
>= 0 && cfg
->asid
!= asid
) {
816 tt
= select_tt(cfg
, iova
);
821 entry
.target_as
= &address_space_memory
;
823 entry
.addr_mask
= (1 << tt
->granule_sz
) - 1;
824 entry
.perm
= IOMMU_NONE
;
826 memory_region_notify_one(n
, &entry
);
829 /* invalidate an asid/iova tuple in all mr's */
830 static void smmuv3_inv_notifiers_iova(SMMUState
*s
, int asid
, dma_addr_t iova
)
834 QLIST_FOREACH(sdev
, &s
->devices_with_notifiers
, next
) {
835 IOMMUMemoryRegion
*mr
= &sdev
->iommu
;
838 trace_smmuv3_inv_notifiers_iova(mr
->parent_obj
.name
, asid
, iova
);
840 IOMMU_NOTIFIER_FOREACH(n
, mr
) {
841 smmuv3_notify_iova(mr
, n
, asid
, iova
);
846 static int smmuv3_cmdq_consume(SMMUv3State
*s
)
848 SMMUState
*bs
= ARM_SMMU(s
);
849 SMMUCmdError cmd_error
= SMMU_CERROR_NONE
;
850 SMMUQueue
*q
= &s
->cmdq
;
851 SMMUCommandType type
= 0;
853 if (!smmuv3_cmdq_enabled(s
)) {
857 * some commands depend on register values, typically CR0. In case those
858 * register values change while handling the command, spec says it
859 * is UNPREDICTABLE whether the command is interpreted under the new
863 while (!smmuv3_q_empty(q
)) {
864 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
867 trace_smmuv3_cmdq_consume(Q_PROD(q
), Q_CONS(q
),
868 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
870 if (FIELD_EX32(pending
, GERROR
, CMDQ_ERR
)) {
874 if (queue_read(q
, &cmd
) != MEMTX_OK
) {
875 cmd_error
= SMMU_CERROR_ABT
;
879 type
= CMD_TYPE(&cmd
);
881 trace_smmuv3_cmdq_opcode(smmu_cmd_string(type
));
883 qemu_mutex_lock(&s
->mutex
);
886 if (CMD_SYNC_CS(&cmd
) & CMD_SYNC_SIG_IRQ
) {
887 smmuv3_trigger_irq(s
, SMMU_IRQ_CMD_SYNC
, 0);
890 case SMMU_CMD_PREFETCH_CONFIG
:
891 case SMMU_CMD_PREFETCH_ADDR
:
893 case SMMU_CMD_CFGI_STE
:
895 uint32_t sid
= CMD_SID(&cmd
);
896 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, sid
);
899 if (CMD_SSEC(&cmd
)) {
900 cmd_error
= SMMU_CERROR_ILL
;
908 trace_smmuv3_cmdq_cfgi_ste(sid
);
909 sdev
= container_of(mr
, SMMUDevice
, iommu
);
910 smmuv3_flush_config(sdev
);
914 case SMMU_CMD_CFGI_STE_RANGE
: /* same as SMMU_CMD_CFGI_ALL */
916 uint32_t start
= CMD_SID(&cmd
), end
, i
;
917 uint8_t range
= CMD_STE_RANGE(&cmd
);
919 if (CMD_SSEC(&cmd
)) {
920 cmd_error
= SMMU_CERROR_ILL
;
924 end
= start
+ (1 << (range
+ 1)) - 1;
925 trace_smmuv3_cmdq_cfgi_ste_range(start
, end
);
927 for (i
= start
; i
<= end
; i
++) {
928 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, i
);
934 sdev
= container_of(mr
, SMMUDevice
, iommu
);
935 smmuv3_flush_config(sdev
);
939 case SMMU_CMD_CFGI_CD
:
940 case SMMU_CMD_CFGI_CD_ALL
:
942 uint32_t sid
= CMD_SID(&cmd
);
943 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, sid
);
946 if (CMD_SSEC(&cmd
)) {
947 cmd_error
= SMMU_CERROR_ILL
;
955 trace_smmuv3_cmdq_cfgi_cd(sid
);
956 sdev
= container_of(mr
, SMMUDevice
, iommu
);
957 smmuv3_flush_config(sdev
);
960 case SMMU_CMD_TLBI_NH_ASID
:
962 uint16_t asid
= CMD_ASID(&cmd
);
964 trace_smmuv3_cmdq_tlbi_nh_asid(asid
);
965 smmu_inv_notifiers_all(&s
->smmu_state
);
966 smmu_iotlb_inv_asid(bs
, asid
);
969 case SMMU_CMD_TLBI_NH_ALL
:
970 case SMMU_CMD_TLBI_NSNH_ALL
:
971 trace_smmuv3_cmdq_tlbi_nh();
972 smmu_inv_notifiers_all(&s
->smmu_state
);
973 smmu_iotlb_inv_all(bs
);
975 case SMMU_CMD_TLBI_NH_VAA
:
977 dma_addr_t addr
= CMD_ADDR(&cmd
);
978 uint16_t vmid
= CMD_VMID(&cmd
);
980 trace_smmuv3_cmdq_tlbi_nh_vaa(vmid
, addr
);
981 smmuv3_inv_notifiers_iova(bs
, -1, addr
);
982 smmu_iotlb_inv_all(bs
);
985 case SMMU_CMD_TLBI_NH_VA
:
987 uint16_t asid
= CMD_ASID(&cmd
);
988 uint16_t vmid
= CMD_VMID(&cmd
);
989 dma_addr_t addr
= CMD_ADDR(&cmd
);
990 bool leaf
= CMD_LEAF(&cmd
);
992 trace_smmuv3_cmdq_tlbi_nh_va(vmid
, asid
, addr
, leaf
);
993 smmuv3_inv_notifiers_iova(bs
, asid
, addr
);
994 smmu_iotlb_inv_iova(bs
, asid
, addr
);
997 case SMMU_CMD_TLBI_EL3_ALL
:
998 case SMMU_CMD_TLBI_EL3_VA
:
999 case SMMU_CMD_TLBI_EL2_ALL
:
1000 case SMMU_CMD_TLBI_EL2_ASID
:
1001 case SMMU_CMD_TLBI_EL2_VA
:
1002 case SMMU_CMD_TLBI_EL2_VAA
:
1003 case SMMU_CMD_TLBI_S12_VMALL
:
1004 case SMMU_CMD_TLBI_S2_IPA
:
1005 case SMMU_CMD_ATC_INV
:
1006 case SMMU_CMD_PRI_RESP
:
1007 case SMMU_CMD_RESUME
:
1008 case SMMU_CMD_STALL_TERM
:
1009 trace_smmuv3_unhandled_cmd(type
);
1012 cmd_error
= SMMU_CERROR_ILL
;
1013 qemu_log_mask(LOG_GUEST_ERROR
,
1014 "Illegal command type: %d\n", CMD_TYPE(&cmd
));
1017 qemu_mutex_unlock(&s
->mutex
);
1022 * We only increment the cons index after the completion of
1023 * the command. We do that because the SYNC returns immediately
1024 * and does not check the completion of previous commands
1030 trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type
), cmd_error
);
1031 smmu_write_cmdq_err(s
, cmd_error
);
1032 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_CMDQ_ERR_MASK
);
1035 trace_smmuv3_cmdq_consume_out(Q_PROD(q
), Q_CONS(q
),
1036 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
1041 static MemTxResult
smmu_writell(SMMUv3State
*s
, hwaddr offset
,
1042 uint64_t data
, MemTxAttrs attrs
)
1045 case A_GERROR_IRQ_CFG0
:
1046 s
->gerror_irq_cfg0
= data
;
1049 s
->strtab_base
= data
;
1052 s
->cmdq
.base
= data
;
1053 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1054 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1055 s
->cmdq
.log2size
= SMMU_CMDQS
;
1059 s
->eventq
.base
= data
;
1060 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1061 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1062 s
->eventq
.log2size
= SMMU_EVENTQS
;
1065 case A_EVENTQ_IRQ_CFG0
:
1066 s
->eventq_irq_cfg0
= data
;
1069 qemu_log_mask(LOG_UNIMP
,
1070 "%s Unexpected 64-bit access to 0x%"PRIx64
" (WI)\n",
1076 static MemTxResult
smmu_writel(SMMUv3State
*s
, hwaddr offset
,
1077 uint64_t data
, MemTxAttrs attrs
)
1082 s
->cr0ack
= data
& ~SMMU_CR0_RESERVED
;
1083 /* in case the command queue has been enabled */
1084 smmuv3_cmdq_consume(s
);
1096 smmuv3_write_gerrorn(s
, data
);
1098 * By acknowledging the CMDQ_ERR, SW may notify cmds can
1099 * be processed again
1101 smmuv3_cmdq_consume(s
);
1103 case A_GERROR_IRQ_CFG0
: /* 64b */
1104 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 0, 32, data
);
1106 case A_GERROR_IRQ_CFG0
+ 4:
1107 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 32, 32, data
);
1109 case A_GERROR_IRQ_CFG1
:
1110 s
->gerror_irq_cfg1
= data
;
1112 case A_GERROR_IRQ_CFG2
:
1113 s
->gerror_irq_cfg2
= data
;
1115 case A_STRTAB_BASE
: /* 64b */
1116 s
->strtab_base
= deposit64(s
->strtab_base
, 0, 32, data
);
1118 case A_STRTAB_BASE
+ 4:
1119 s
->strtab_base
= deposit64(s
->strtab_base
, 32, 32, data
);
1121 case A_STRTAB_BASE_CFG
:
1122 s
->strtab_base_cfg
= data
;
1123 if (FIELD_EX32(data
, STRTAB_BASE_CFG
, FMT
) == 1) {
1124 s
->sid_split
= FIELD_EX32(data
, STRTAB_BASE_CFG
, SPLIT
);
1125 s
->features
|= SMMU_FEATURE_2LVL_STE
;
1128 case A_CMDQ_BASE
: /* 64b */
1129 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 32, data
);
1130 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1131 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1132 s
->cmdq
.log2size
= SMMU_CMDQS
;
1135 case A_CMDQ_BASE
+ 4: /* 64b */
1136 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 32, 32, data
);
1139 s
->cmdq
.prod
= data
;
1140 smmuv3_cmdq_consume(s
);
1143 s
->cmdq
.cons
= data
;
1145 case A_EVENTQ_BASE
: /* 64b */
1146 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 32, data
);
1147 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1148 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1149 s
->eventq
.log2size
= SMMU_EVENTQS
;
1152 case A_EVENTQ_BASE
+ 4:
1153 s
->eventq
.base
= deposit64(s
->eventq
.base
, 32, 32, data
);
1156 s
->eventq
.prod
= data
;
1159 s
->eventq
.cons
= data
;
1161 case A_EVENTQ_IRQ_CFG0
: /* 64b */
1162 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 0, 32, data
);
1164 case A_EVENTQ_IRQ_CFG0
+ 4:
1165 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 32, 32, data
);
1167 case A_EVENTQ_IRQ_CFG1
:
1168 s
->eventq_irq_cfg1
= data
;
1170 case A_EVENTQ_IRQ_CFG2
:
1171 s
->eventq_irq_cfg2
= data
;
1174 qemu_log_mask(LOG_UNIMP
,
1175 "%s Unexpected 32-bit access to 0x%"PRIx64
" (WI)\n",
1181 static MemTxResult
smmu_write_mmio(void *opaque
, hwaddr offset
, uint64_t data
,
1182 unsigned size
, MemTxAttrs attrs
)
1184 SMMUState
*sys
= opaque
;
1185 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1188 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1193 r
= smmu_writell(s
, offset
, data
, attrs
);
1196 r
= smmu_writel(s
, offset
, data
, attrs
);
1203 trace_smmuv3_write_mmio(offset
, data
, size
, r
);
1207 static MemTxResult
smmu_readll(SMMUv3State
*s
, hwaddr offset
,
1208 uint64_t *data
, MemTxAttrs attrs
)
1211 case A_GERROR_IRQ_CFG0
:
1212 *data
= s
->gerror_irq_cfg0
;
1215 *data
= s
->strtab_base
;
1218 *data
= s
->cmdq
.base
;
1221 *data
= s
->eventq
.base
;
1225 qemu_log_mask(LOG_UNIMP
,
1226 "%s Unexpected 64-bit access to 0x%"PRIx64
" (RAZ)\n",
1232 static MemTxResult
smmu_readl(SMMUv3State
*s
, hwaddr offset
,
1233 uint64_t *data
, MemTxAttrs attrs
)
1236 case A_IDREGS
... A_IDREGS
+ 0x2f:
1237 *data
= smmuv3_idreg(offset
- A_IDREGS
);
1239 case A_IDR0
... A_IDR5
:
1240 *data
= s
->idr
[(offset
- A_IDR0
) / 4];
1261 case A_IRQ_CTRL_ACK
:
1262 *data
= s
->irq_ctrl
;
1270 case A_GERROR_IRQ_CFG0
: /* 64b */
1271 *data
= extract64(s
->gerror_irq_cfg0
, 0, 32);
1273 case A_GERROR_IRQ_CFG0
+ 4:
1274 *data
= extract64(s
->gerror_irq_cfg0
, 32, 32);
1276 case A_GERROR_IRQ_CFG1
:
1277 *data
= s
->gerror_irq_cfg1
;
1279 case A_GERROR_IRQ_CFG2
:
1280 *data
= s
->gerror_irq_cfg2
;
1282 case A_STRTAB_BASE
: /* 64b */
1283 *data
= extract64(s
->strtab_base
, 0, 32);
1285 case A_STRTAB_BASE
+ 4: /* 64b */
1286 *data
= extract64(s
->strtab_base
, 32, 32);
1288 case A_STRTAB_BASE_CFG
:
1289 *data
= s
->strtab_base_cfg
;
1291 case A_CMDQ_BASE
: /* 64b */
1292 *data
= extract64(s
->cmdq
.base
, 0, 32);
1294 case A_CMDQ_BASE
+ 4:
1295 *data
= extract64(s
->cmdq
.base
, 32, 32);
1298 *data
= s
->cmdq
.prod
;
1301 *data
= s
->cmdq
.cons
;
1303 case A_EVENTQ_BASE
: /* 64b */
1304 *data
= extract64(s
->eventq
.base
, 0, 32);
1306 case A_EVENTQ_BASE
+ 4: /* 64b */
1307 *data
= extract64(s
->eventq
.base
, 32, 32);
1310 *data
= s
->eventq
.prod
;
1313 *data
= s
->eventq
.cons
;
1317 qemu_log_mask(LOG_UNIMP
,
1318 "%s unhandled 32-bit access at 0x%"PRIx64
" (RAZ)\n",
1324 static MemTxResult
smmu_read_mmio(void *opaque
, hwaddr offset
, uint64_t *data
,
1325 unsigned size
, MemTxAttrs attrs
)
1327 SMMUState
*sys
= opaque
;
1328 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1331 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1336 r
= smmu_readll(s
, offset
, data
, attrs
);
1339 r
= smmu_readl(s
, offset
, data
, attrs
);
1346 trace_smmuv3_read_mmio(offset
, *data
, size
, r
);
1350 static const MemoryRegionOps smmu_mem_ops
= {
1351 .read_with_attrs
= smmu_read_mmio
,
1352 .write_with_attrs
= smmu_write_mmio
,
1353 .endianness
= DEVICE_LITTLE_ENDIAN
,
1355 .min_access_size
= 4,
1356 .max_access_size
= 8,
1359 .min_access_size
= 4,
1360 .max_access_size
= 8,
1364 static void smmu_init_irq(SMMUv3State
*s
, SysBusDevice
*dev
)
1368 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
1369 sysbus_init_irq(dev
, &s
->irq
[i
]);
1373 static void smmu_reset(DeviceState
*dev
)
1375 SMMUv3State
*s
= ARM_SMMUV3(dev
);
1376 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1378 c
->parent_reset(dev
);
1380 smmuv3_init_regs(s
);
1383 static void smmu_realize(DeviceState
*d
, Error
**errp
)
1385 SMMUState
*sys
= ARM_SMMU(d
);
1386 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1387 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1388 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
1389 Error
*local_err
= NULL
;
1391 c
->parent_realize(d
, &local_err
);
1393 error_propagate(errp
, local_err
);
1397 qemu_mutex_init(&s
->mutex
);
1399 memory_region_init_io(&sys
->iomem
, OBJECT(s
),
1400 &smmu_mem_ops
, sys
, TYPE_ARM_SMMUV3
, 0x20000);
1402 sys
->mrtypename
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
;
1404 sysbus_init_mmio(dev
, &sys
->iomem
);
1406 smmu_init_irq(s
, dev
);
1409 static const VMStateDescription vmstate_smmuv3_queue
= {
1410 .name
= "smmuv3_queue",
1412 .minimum_version_id
= 1,
1413 .fields
= (VMStateField
[]) {
1414 VMSTATE_UINT64(base
, SMMUQueue
),
1415 VMSTATE_UINT32(prod
, SMMUQueue
),
1416 VMSTATE_UINT32(cons
, SMMUQueue
),
1417 VMSTATE_UINT8(log2size
, SMMUQueue
),
1418 VMSTATE_END_OF_LIST(),
1422 static const VMStateDescription vmstate_smmuv3
= {
1425 .minimum_version_id
= 1,
1426 .fields
= (VMStateField
[]) {
1427 VMSTATE_UINT32(features
, SMMUv3State
),
1428 VMSTATE_UINT8(sid_size
, SMMUv3State
),
1429 VMSTATE_UINT8(sid_split
, SMMUv3State
),
1431 VMSTATE_UINT32_ARRAY(cr
, SMMUv3State
, 3),
1432 VMSTATE_UINT32(cr0ack
, SMMUv3State
),
1433 VMSTATE_UINT32(statusr
, SMMUv3State
),
1434 VMSTATE_UINT32(irq_ctrl
, SMMUv3State
),
1435 VMSTATE_UINT32(gerror
, SMMUv3State
),
1436 VMSTATE_UINT32(gerrorn
, SMMUv3State
),
1437 VMSTATE_UINT64(gerror_irq_cfg0
, SMMUv3State
),
1438 VMSTATE_UINT32(gerror_irq_cfg1
, SMMUv3State
),
1439 VMSTATE_UINT32(gerror_irq_cfg2
, SMMUv3State
),
1440 VMSTATE_UINT64(strtab_base
, SMMUv3State
),
1441 VMSTATE_UINT32(strtab_base_cfg
, SMMUv3State
),
1442 VMSTATE_UINT64(eventq_irq_cfg0
, SMMUv3State
),
1443 VMSTATE_UINT32(eventq_irq_cfg1
, SMMUv3State
),
1444 VMSTATE_UINT32(eventq_irq_cfg2
, SMMUv3State
),
1446 VMSTATE_STRUCT(cmdq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1447 VMSTATE_STRUCT(eventq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1449 VMSTATE_END_OF_LIST(),
1453 static void smmuv3_instance_init(Object
*obj
)
1455 /* Nothing much to do here as of now */
1458 static void smmuv3_class_init(ObjectClass
*klass
, void *data
)
1460 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1461 SMMUv3Class
*c
= ARM_SMMUV3_CLASS(klass
);
1463 dc
->vmsd
= &vmstate_smmuv3
;
1464 device_class_set_parent_reset(dc
, smmu_reset
, &c
->parent_reset
);
1465 c
->parent_realize
= dc
->realize
;
1466 dc
->realize
= smmu_realize
;
1469 static void smmuv3_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
1470 IOMMUNotifierFlag old
,
1471 IOMMUNotifierFlag
new)
1473 SMMUDevice
*sdev
= container_of(iommu
, SMMUDevice
, iommu
);
1474 SMMUv3State
*s3
= sdev
->smmu
;
1475 SMMUState
*s
= &(s3
->smmu_state
);
1477 if (new & IOMMU_NOTIFIER_MAP
) {
1478 int bus_num
= pci_bus_num(sdev
->bus
);
1479 PCIDevice
*pcidev
= pci_find_device(sdev
->bus
, bus_num
, sdev
->devfn
);
1481 warn_report("SMMUv3 does not support notification on MAP: "
1482 "device %s will not function properly", pcidev
->name
);
1485 if (old
== IOMMU_NOTIFIER_NONE
) {
1486 trace_smmuv3_notify_flag_add(iommu
->parent_obj
.name
);
1487 QLIST_INSERT_HEAD(&s
->devices_with_notifiers
, sdev
, next
);
1488 } else if (new == IOMMU_NOTIFIER_NONE
) {
1489 trace_smmuv3_notify_flag_del(iommu
->parent_obj
.name
);
1490 QLIST_REMOVE(sdev
, next
);
1494 static void smmuv3_iommu_memory_region_class_init(ObjectClass
*klass
,
1497 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
1499 imrc
->translate
= smmuv3_translate
;
1500 imrc
->notify_flag_changed
= smmuv3_notify_flag_changed
;
1503 static const TypeInfo smmuv3_type_info
= {
1504 .name
= TYPE_ARM_SMMUV3
,
1505 .parent
= TYPE_ARM_SMMU
,
1506 .instance_size
= sizeof(SMMUv3State
),
1507 .instance_init
= smmuv3_instance_init
,
1508 .class_size
= sizeof(SMMUv3Class
),
1509 .class_init
= smmuv3_class_init
,
1512 static const TypeInfo smmuv3_iommu_memory_region_info
= {
1513 .parent
= TYPE_IOMMU_MEMORY_REGION
,
1514 .name
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
,
1515 .class_init
= smmuv3_iommu_memory_region_class_init
,
1518 static void smmuv3_register_types(void)
1520 type_register(&smmuv3_type_info
);
1521 type_register(&smmuv3_iommu_memory_region_info
);
1524 type_init(smmuv3_register_types
)