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Include hw/boards.h a bit less
[qemu/ar7.git] / hw / arm / omap2.c
blobe0a9c2da83ecbcec6c49547ce917fc7ea68124a9
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "sysemu/blockdev.h"
26 #include "sysemu/qtest.h"
27 #include "sysemu/reset.h"
28 #include "hw/boards.h"
29 #include "hw/irq.h"
30 #include "hw/qdev-properties.h"
31 #include "hw/arm/boot.h"
32 #include "hw/arm/omap.h"
33 #include "sysemu/sysemu.h"
34 #include "qemu/timer.h"
35 #include "chardev/char-fe.h"
36 #include "hw/block/flash.h"
37 #include "hw/arm/soc_dma.h"
38 #include "hw/sysbus.h"
39 #include "audio/audio.h"
40
41 /* Enhanced Audio Controller (CODEC only) */
42 struct omap_eac_s {
43 qemu_irq irq;
44 MemoryRegion iomem;
45
46 uint16_t sysconfig;
47 uint8_t config[4];
48 uint8_t control;
49 uint8_t address;
50 uint16_t data;
51 uint8_t vtol;
52 uint8_t vtsl;
53 uint16_t mixer;
54 uint16_t gain[4];
55 uint8_t att;
56 uint16_t max[7];
57
58 struct {
59 qemu_irq txdrq;
60 qemu_irq rxdrq;
61 uint32_t (*txrx)(void *opaque, uint32_t, int);
62 void *opaque;
63
64 #define EAC_BUF_LEN 1024
65 uint32_t rxbuf[EAC_BUF_LEN];
66 int rxoff;
67 int rxlen;
68 int rxavail;
69 uint32_t txbuf[EAC_BUF_LEN];
70 int txlen;
71 int txavail;
72
73 int enable;
74 int rate;
75
76 uint16_t config[4];
77
78 /* These need to be moved to the actual codec */
79 QEMUSoundCard card;
80 SWVoiceIn *in_voice;
81 SWVoiceOut *out_voice;
82 int hw_enable;
83 } codec;
84
85 struct {
86 uint8_t control;
87 uint16_t config;
88 } modem, bt;
89 };
90
91 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
92 {
93 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
94 }
95
96 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
97 {
98 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
99 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
100 }
101
102 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
103 {
104 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
105 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
106 }
107
108 static inline void omap_eac_in_refill(struct omap_eac_s *s)
109 {
110 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
111 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
112 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
113 int recv = 1;
114 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
115
116 left -= leftwrap;
117 start = 0;
118 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
119 leftwrap)) > 0) { /* Be defensive */
120 start += recv;
121 leftwrap -= recv;
122 }
123 if (recv <= 0)
124 s->codec.rxavail = 0;
125 else
126 s->codec.rxavail -= start >> 2;
127 s->codec.rxlen += start >> 2;
128
129 if (recv > 0 && left > 0) {
130 start = 0;
131 while (left && (recv = AUD_read(s->codec.in_voice,
132 (uint8_t *) s->codec.rxbuf + start,
133 left)) > 0) { /* Be defensive */
134 start += recv;
135 left -= recv;
136 }
137 if (recv <= 0)
138 s->codec.rxavail = 0;
139 else
140 s->codec.rxavail -= start >> 2;
141 s->codec.rxlen += start >> 2;
142 }
143 }
144
145 static inline void omap_eac_out_empty(struct omap_eac_s *s)
146 {
147 int left = s->codec.txlen << 2;
148 int start = 0;
149 int sent = 1;
150
151 while (left && (sent = AUD_write(s->codec.out_voice,
152 (uint8_t *) s->codec.txbuf + start,
153 left)) > 0) { /* Be defensive */
154 start += sent;
155 left -= sent;
156 }
157
158 if (!sent) {
159 s->codec.txavail = 0;
160 omap_eac_out_dmarequest_update(s);
161 }
162
163 if (start)
164 s->codec.txlen = 0;
165 }
166
167 static void omap_eac_in_cb(void *opaque, int avail_b)
168 {
169 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
170
171 s->codec.rxavail = avail_b >> 2;
172 omap_eac_in_refill(s);
173 /* TODO: possibly discard current buffer if overrun */
174 omap_eac_in_dmarequest_update(s);
175 }
176
177 static void omap_eac_out_cb(void *opaque, int free_b)
178 {
179 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
180
181 s->codec.txavail = free_b >> 2;
182 if (s->codec.txlen)
183 omap_eac_out_empty(s);
184 else
185 omap_eac_out_dmarequest_update(s);
186 }
187
188 static void omap_eac_enable_update(struct omap_eac_s *s)
189 {
190 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
191 (s->codec.config[1] & 2) && /* AUDEN */
192 s->codec.hw_enable;
193 }
194
195 static const int omap_eac_fsint[4] = {
196 8000,
197 11025,
198 22050,
199 44100,
200 };
201
202 static const int omap_eac_fsint2[8] = {
203 8000,
204 11025,
205 22050,
206 44100,
207 48000,
208 0, 0, 0,
209 };
210
211 static const int omap_eac_fsint3[16] = {
212 8000,
213 11025,
214 16000,
215 22050,
216 24000,
217 32000,
218 44100,
219 48000,
220 0, 0, 0, 0, 0, 0, 0, 0,
221 };
222
223 static void omap_eac_rate_update(struct omap_eac_s *s)
224 {
225 int fsint[3];
226
227 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
228 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
229 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
230 if (fsint[2] < 0xf)
231 s->codec.rate = omap_eac_fsint3[fsint[2]];
232 else if (fsint[1] < 0x7)
233 s->codec.rate = omap_eac_fsint2[fsint[1]];
234 else
235 s->codec.rate = omap_eac_fsint[fsint[0]];
236 }
237
238 static void omap_eac_volume_update(struct omap_eac_s *s)
239 {
240 /* TODO */
241 }
242
243 static void omap_eac_format_update(struct omap_eac_s *s)
244 {
245 struct audsettings fmt;
246
247 /* The hardware buffers at most one sample */
248 if (s->codec.rxlen)
249 s->codec.rxlen = 1;
250
251 if (s->codec.in_voice) {
252 AUD_set_active_in(s->codec.in_voice, 0);
253 AUD_close_in(&s->codec.card, s->codec.in_voice);
254 s->codec.in_voice = NULL;
255 }
256 if (s->codec.out_voice) {
257 omap_eac_out_empty(s);
258 AUD_set_active_out(s->codec.out_voice, 0);
259 AUD_close_out(&s->codec.card, s->codec.out_voice);
260 s->codec.out_voice = NULL;
261 s->codec.txavail = 0;
262 }
263 /* Discard what couldn't be written */
264 s->codec.txlen = 0;
265
266 omap_eac_enable_update(s);
267 if (!s->codec.enable)
268 return;
269
270 omap_eac_rate_update(s);
271 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
272 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
273 fmt.freq = s->codec.rate;
274 /* TODO: signedness possibly depends on the CODEC hardware - or
275 * does I2S specify it? */
276 /* All register writes are 16 bits so we we store 16-bit samples
277 * in the buffers regardless of AGCFR[B8_16] value. */
278 fmt.fmt = AUDIO_FORMAT_U16;
279
280 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
281 "eac.codec.in", s, omap_eac_in_cb, &fmt);
282 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
283 "eac.codec.out", s, omap_eac_out_cb, &fmt);
284
285 omap_eac_volume_update(s);
286
287 AUD_set_active_in(s->codec.in_voice, 1);
288 AUD_set_active_out(s->codec.out_voice, 1);
289 }
290
291 static void omap_eac_reset(struct omap_eac_s *s)
292 {
293 s->sysconfig = 0;
294 s->config[0] = 0x0c;
295 s->config[1] = 0x09;
296 s->config[2] = 0xab;
297 s->config[3] = 0x03;
298 s->control = 0x00;
299 s->address = 0x00;
300 s->data = 0x0000;
301 s->vtol = 0x00;
302 s->vtsl = 0x00;
303 s->mixer = 0x0000;
304 s->gain[0] = 0xe7e7;
305 s->gain[1] = 0x6767;
306 s->gain[2] = 0x6767;
307 s->gain[3] = 0x6767;
308 s->att = 0xce;
309 s->max[0] = 0;
310 s->max[1] = 0;
311 s->max[2] = 0;
312 s->max[3] = 0;
313 s->max[4] = 0;
314 s->max[5] = 0;
315 s->max[6] = 0;
316
317 s->modem.control = 0x00;
318 s->modem.config = 0x0000;
319 s->bt.control = 0x00;
320 s->bt.config = 0x0000;
321 s->codec.config[0] = 0x0649;
322 s->codec.config[1] = 0x0000;
323 s->codec.config[2] = 0x0007;
324 s->codec.config[3] = 0x1ffc;
325 s->codec.rxoff = 0;
326 s->codec.rxlen = 0;
327 s->codec.txlen = 0;
328 s->codec.rxavail = 0;
329 s->codec.txavail = 0;
330
331 omap_eac_format_update(s);
332 omap_eac_interrupt_update(s);
333 }
334
335 static uint64_t omap_eac_read(void *opaque, hwaddr addr,
336 unsigned size)
337 {
338 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
339 uint32_t ret;
340
341 if (size != 2) {
342 return omap_badwidth_read16(opaque, addr);
343 }
344
345 switch (addr) {
346 case 0x000: /* CPCFR1 */
347 return s->config[0];
348 case 0x004: /* CPCFR2 */
349 return s->config[1];
350 case 0x008: /* CPCFR3 */
351 return s->config[2];
352 case 0x00c: /* CPCFR4 */
353 return s->config[3];
354
355 case 0x010: /* CPTCTL */
356 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
357 ((s->codec.txlen < s->codec.txavail) << 5);
358
359 case 0x014: /* CPTTADR */
360 return s->address;
361 case 0x018: /* CPTDATL */
362 return s->data & 0xff;
363 case 0x01c: /* CPTDATH */
364 return s->data >> 8;
365 case 0x020: /* CPTVSLL */
366 return s->vtol;
367 case 0x024: /* CPTVSLH */
368 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
369 case 0x040: /* MPCTR */
370 return s->modem.control;
371 case 0x044: /* MPMCCFR */
372 return s->modem.config;
373 case 0x060: /* BPCTR */
374 return s->bt.control;
375 case 0x064: /* BPMCCFR */
376 return s->bt.config;
377 case 0x080: /* AMSCFR */
378 return s->mixer;
379 case 0x084: /* AMVCTR */
380 return s->gain[0];
381 case 0x088: /* AM1VCTR */
382 return s->gain[1];
383 case 0x08c: /* AM2VCTR */
384 return s->gain[2];
385 case 0x090: /* AM3VCTR */
386 return s->gain[3];
387 case 0x094: /* ASTCTR */
388 return s->att;
389 case 0x098: /* APD1LCR */
390 return s->max[0];
391 case 0x09c: /* APD1RCR */
392 return s->max[1];
393 case 0x0a0: /* APD2LCR */
394 return s->max[2];
395 case 0x0a4: /* APD2RCR */
396 return s->max[3];
397 case 0x0a8: /* APD3LCR */
398 return s->max[4];
399 case 0x0ac: /* APD3RCR */
400 return s->max[5];
401 case 0x0b0: /* APD4R */
402 return s->max[6];
403 case 0x0b4: /* ADWR */
404 /* This should be write-only? Docs list it as read-only. */
405 return 0x0000;
406 case 0x0b8: /* ADRDR */
407 if (likely(s->codec.rxlen > 1)) {
408 ret = s->codec.rxbuf[s->codec.rxoff ++];
409 s->codec.rxlen --;
410 s->codec.rxoff &= EAC_BUF_LEN - 1;
411 return ret;
412 } else if (s->codec.rxlen) {
413 ret = s->codec.rxbuf[s->codec.rxoff ++];
414 s->codec.rxlen --;
415 s->codec.rxoff &= EAC_BUF_LEN - 1;
416 if (s->codec.rxavail)
417 omap_eac_in_refill(s);
418 omap_eac_in_dmarequest_update(s);
419 return ret;
420 }
421 return 0x0000;
422 case 0x0bc: /* AGCFR */
423 return s->codec.config[0];
424 case 0x0c0: /* AGCTR */
425 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
426 case 0x0c4: /* AGCFR2 */
427 return s->codec.config[2];
428 case 0x0c8: /* AGCFR3 */
429 return s->codec.config[3];
430 case 0x0cc: /* MBPDMACTR */
431 case 0x0d0: /* MPDDMARR */
432 case 0x0d8: /* MPUDMARR */
433 case 0x0e4: /* BPDDMARR */
434 case 0x0ec: /* BPUDMARR */
435 return 0x0000;
436
437 case 0x100: /* VERSION_NUMBER */
438 return 0x0010;
439
440 case 0x104: /* SYSCONFIG */
441 return s->sysconfig;
442
443 case 0x108: /* SYSSTATUS */
444 return 1 | 0xe; /* RESETDONE | stuff */
445 }
446
447 OMAP_BAD_REG(addr);
448 return 0;
449 }
450
451 static void omap_eac_write(void *opaque, hwaddr addr,
452 uint64_t value, unsigned size)
453 {
454 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
455
456 if (size != 2) {
457 omap_badwidth_write16(opaque, addr, value);
458 return;
459 }
460
461 switch (addr) {
462 case 0x098: /* APD1LCR */
463 case 0x09c: /* APD1RCR */
464 case 0x0a0: /* APD2LCR */
465 case 0x0a4: /* APD2RCR */
466 case 0x0a8: /* APD3LCR */
467 case 0x0ac: /* APD3RCR */
468 case 0x0b0: /* APD4R */
469 case 0x0b8: /* ADRDR */
470 case 0x0d0: /* MPDDMARR */
471 case 0x0d8: /* MPUDMARR */
472 case 0x0e4: /* BPDDMARR */
473 case 0x0ec: /* BPUDMARR */
474 case 0x100: /* VERSION_NUMBER */
475 case 0x108: /* SYSSTATUS */
476 OMAP_RO_REG(addr);
477 return;
478
479 case 0x000: /* CPCFR1 */
480 s->config[0] = value & 0xff;
481 omap_eac_format_update(s);
482 break;
483 case 0x004: /* CPCFR2 */
484 s->config[1] = value & 0xff;
485 omap_eac_format_update(s);
486 break;
487 case 0x008: /* CPCFR3 */
488 s->config[2] = value & 0xff;
489 omap_eac_format_update(s);
490 break;
491 case 0x00c: /* CPCFR4 */
492 s->config[3] = value & 0xff;
493 omap_eac_format_update(s);
494 break;
495
496 case 0x010: /* CPTCTL */
497 /* Assuming TXF and TXE bits are read-only... */
498 s->control = value & 0x5f;
499 omap_eac_interrupt_update(s);
500 break;
501
502 case 0x014: /* CPTTADR */
503 s->address = value & 0xff;
504 break;
505 case 0x018: /* CPTDATL */
506 s->data &= 0xff00;
507 s->data |= value & 0xff;
508 break;
509 case 0x01c: /* CPTDATH */
510 s->data &= 0x00ff;
511 s->data |= value << 8;
512 break;
513 case 0x020: /* CPTVSLL */
514 s->vtol = value & 0xf8;
515 break;
516 case 0x024: /* CPTVSLH */
517 s->vtsl = value & 0x9f;
518 break;
519 case 0x040: /* MPCTR */
520 s->modem.control = value & 0x8f;
521 break;
522 case 0x044: /* MPMCCFR */
523 s->modem.config = value & 0x7fff;
524 break;
525 case 0x060: /* BPCTR */
526 s->bt.control = value & 0x8f;
527 break;
528 case 0x064: /* BPMCCFR */
529 s->bt.config = value & 0x7fff;
530 break;
531 case 0x080: /* AMSCFR */
532 s->mixer = value & 0x0fff;
533 break;
534 case 0x084: /* AMVCTR */
535 s->gain[0] = value & 0xffff;
536 break;
537 case 0x088: /* AM1VCTR */
538 s->gain[1] = value & 0xff7f;
539 break;
540 case 0x08c: /* AM2VCTR */
541 s->gain[2] = value & 0xff7f;
542 break;
543 case 0x090: /* AM3VCTR */
544 s->gain[3] = value & 0xff7f;
545 break;
546 case 0x094: /* ASTCTR */
547 s->att = value & 0xff;
548 break;
549
550 case 0x0b4: /* ADWR */
551 s->codec.txbuf[s->codec.txlen ++] = value;
552 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
553 s->codec.txlen == s->codec.txavail)) {
554 if (s->codec.txavail)
555 omap_eac_out_empty(s);
556 /* Discard what couldn't be written */
557 s->codec.txlen = 0;
558 }
559 break;
560
561 case 0x0bc: /* AGCFR */
562 s->codec.config[0] = value & 0x07ff;
563 omap_eac_format_update(s);
564 break;
565 case 0x0c0: /* AGCTR */
566 s->codec.config[1] = value & 0x780f;
567 omap_eac_format_update(s);
568 break;
569 case 0x0c4: /* AGCFR2 */
570 s->codec.config[2] = value & 0x003f;
571 omap_eac_format_update(s);
572 break;
573 case 0x0c8: /* AGCFR3 */
574 s->codec.config[3] = value & 0xffff;
575 omap_eac_format_update(s);
576 break;
577 case 0x0cc: /* MBPDMACTR */
578 case 0x0d4: /* MPDDMAWR */
579 case 0x0e0: /* MPUDMAWR */
580 case 0x0e8: /* BPDDMAWR */
581 case 0x0f0: /* BPUDMAWR */
582 break;
583
584 case 0x104: /* SYSCONFIG */
585 if (value & (1 << 1)) /* SOFTRESET */
586 omap_eac_reset(s);
587 s->sysconfig = value & 0x31d;
588 break;
589
590 default:
591 OMAP_BAD_REG(addr);
592 return;
593 }
594 }
595
596 static const MemoryRegionOps omap_eac_ops = {
597 .read = omap_eac_read,
598 .write = omap_eac_write,
599 .endianness = DEVICE_NATIVE_ENDIAN,
600 };
601
602 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
603 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
604 {
605 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
606
607 s->irq = irq;
608 s->codec.rxdrq = *drq ++;
609 s->codec.txdrq = *drq;
610 omap_eac_reset(s);
611
612 AUD_register_card("OMAP EAC", &s->codec.card);
613
614 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
615 omap_l4_region_size(ta, 0));
616 omap_l4_attach(ta, 0, &s->iomem);
617
618 return s;
619 }
620
621 /* STI/XTI (emulation interface) console - reverse engineered only */
622 struct omap_sti_s {
623 qemu_irq irq;
624 MemoryRegion iomem;
625 MemoryRegion iomem_fifo;
626 CharBackend chr;
627
628 uint32_t sysconfig;
629 uint32_t systest;
630 uint32_t irqst;
631 uint32_t irqen;
632 uint32_t clkcontrol;
633 uint32_t serial_config;
634 };
635
636 #define STI_TRACE_CONSOLE_CHANNEL 239
637 #define STI_TRACE_CONTROL_CHANNEL 253
638
639 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
640 {
641 qemu_set_irq(s->irq, s->irqst & s->irqen);
642 }
643
644 static void omap_sti_reset(struct omap_sti_s *s)
645 {
646 s->sysconfig = 0;
647 s->irqst = 0;
648 s->irqen = 0;
649 s->clkcontrol = 0;
650 s->serial_config = 0;
651
652 omap_sti_interrupt_update(s);
653 }
654
655 static uint64_t omap_sti_read(void *opaque, hwaddr addr,
656 unsigned size)
657 {
658 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
659
660 if (size != 4) {
661 return omap_badwidth_read32(opaque, addr);
662 }
663
664 switch (addr) {
665 case 0x00: /* STI_REVISION */
666 return 0x10;
667
668 case 0x10: /* STI_SYSCONFIG */
669 return s->sysconfig;
670
671 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
672 return 0x00;
673
674 case 0x18: /* STI_IRQSTATUS */
675 return s->irqst;
676
677 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
678 return s->irqen;
679
680 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
681 case 0x28: /* STI_RX_DR / XTI_RXDATA */
682 /* TODO */
683 return 0;
684
685 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
686 return s->clkcontrol;
687
688 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
689 return s->serial_config;
690 }
691
692 OMAP_BAD_REG(addr);
693 return 0;
694 }
695
696 static void omap_sti_write(void *opaque, hwaddr addr,
697 uint64_t value, unsigned size)
698 {
699 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
700
701 if (size != 4) {
702 omap_badwidth_write32(opaque, addr, value);
703 return;
704 }
705
706 switch (addr) {
707 case 0x00: /* STI_REVISION */
708 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
709 OMAP_RO_REG(addr);
710 return;
711
712 case 0x10: /* STI_SYSCONFIG */
713 if (value & (1 << 1)) /* SOFTRESET */
714 omap_sti_reset(s);
715 s->sysconfig = value & 0xfe;
716 break;
717
718 case 0x18: /* STI_IRQSTATUS */
719 s->irqst &= ~value;
720 omap_sti_interrupt_update(s);
721 break;
722
723 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
724 s->irqen = value & 0xffff;
725 omap_sti_interrupt_update(s);
726 break;
727
728 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
729 s->clkcontrol = value & 0xff;
730 break;
731
732 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
733 s->serial_config = value & 0xff;
734 break;
735
736 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
737 case 0x28: /* STI_RX_DR / XTI_RXDATA */
738 /* TODO */
739 return;
740
741 default:
742 OMAP_BAD_REG(addr);
743 return;
744 }
745 }
746
747 static const MemoryRegionOps omap_sti_ops = {
748 .read = omap_sti_read,
749 .write = omap_sti_write,
750 .endianness = DEVICE_NATIVE_ENDIAN,
751 };
752
753 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
754 unsigned size)
755 {
756 OMAP_BAD_REG(addr);
757 return 0;
758 }
759
760 static void omap_sti_fifo_write(void *opaque, hwaddr addr,
761 uint64_t value, unsigned size)
762 {
763 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
764 int ch = addr >> 6;
765 uint8_t byte = value;
766
767 if (size != 1) {
768 omap_badwidth_write8(opaque, addr, size);
769 return;
770 }
771
772 if (ch == STI_TRACE_CONTROL_CHANNEL) {
773 /* Flush channel <i>value</i>. */
774 /* XXX this blocks entire thread. Rewrite to use
775 * qemu_chr_fe_write and background I/O callbacks */
776 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\r", 1);
777 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
778 if (value == 0xc0 || value == 0xc3) {
779 /* Open channel <i>ch</i>. */
780 } else if (value == 0x00) {
781 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\n", 1);
782 } else {
783 qemu_chr_fe_write_all(&s->chr, &byte, 1);
784 }
785 }
786 }
787
788 static const MemoryRegionOps omap_sti_fifo_ops = {
789 .read = omap_sti_fifo_read,
790 .write = omap_sti_fifo_write,
791 .endianness = DEVICE_NATIVE_ENDIAN,
792 };
793
794 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
795 MemoryRegion *sysmem,
796 hwaddr channel_base, qemu_irq irq, omap_clk clk,
797 Chardev *chr)
798 {
799 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
800
801 s->irq = irq;
802 omap_sti_reset(s);
803
804 qemu_chr_fe_init(&s->chr, chr ?: qemu_chr_new("null", "null", NULL),
805 &error_abort);
806
807 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
808 omap_l4_region_size(ta, 0));
809 omap_l4_attach(ta, 0, &s->iomem);
810
811 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
812 "omap.sti.fifo", 0x10000);
813 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
814
815 return s;
816 }
817
818 /* L4 Interconnect */
819 #define L4TA(n) (n)
820 #define L4TAO(n) ((n) + 39)
821
822 static const struct omap_l4_region_s omap_l4_region[125] = {
823 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
824 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
825 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
826 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
827 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
828 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
829 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
830 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
831 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
832 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
833 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
834 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
835 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
836 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
837 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
838 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
839 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
840 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
841 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
842 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
843 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
844 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
845 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
846 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
847 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
848 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
849 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
850 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
851 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
852 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
853 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
854 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
855 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
856 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
857 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
858 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
859 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
860 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
861 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
862 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
863 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
864 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
865 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
866 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
867 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
868 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
869 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
870 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
871 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
872 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
873 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
874 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
875 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
876 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
877 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
878 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
879 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
880 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
881 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
882 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
883 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
884 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
885 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
886 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
887 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
888 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
889 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
890 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
891 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
892 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
893 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
894 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
895 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
896 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
897 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
898 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
899 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
900 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
901 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
902 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
903 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
904 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
905 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
906 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
907 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
908 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
909 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
910 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
911 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
912 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
913 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
914 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
915 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
916 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
917 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
918 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
919 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
920 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
921 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
922 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
923 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
924 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
925 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
926 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
927 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
928 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
929 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
930 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
931 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
932 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
933 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
934 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
935 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
936 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
937 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
938 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
939 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
940 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
941 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
942 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
943 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
944 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
945 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
946 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
947 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
948 };
949
950 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
951 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
952 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
953 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
954 { L4TAO(3), 7, 3, 2 }, /* PRCM */
955 { L4TA(1), 10, 2, 1 }, /* BCM */
956 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
957 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
958 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
959 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
960 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
961 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
962 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
963 { L4TA(12), 38, 2, 1 }, /* sDMA */
964 { L4TA(13), 40, 5, 4 }, /* SSI */
965 { L4TAO(4), 45, 2, 1 }, /* USB */
966 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
967 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
968 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
969 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
970 { L4TA(18), 55, 2, 1 }, /* XTI */
971 { L4TA(19), 57, 2, 1 }, /* UART1 */
972 { L4TA(20), 59, 2, 1 }, /* UART2 */
973 { L4TA(21), 61, 2, 1 }, /* UART3 */
974 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
975 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
976 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
977 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
978 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
979 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
980 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
981 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
982 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
983 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
984 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
985 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
986 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
987 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
988 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
989 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
990 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
991 { L4TA(32), 97, 2, 1 }, /* EAC */
992 { L4TA(33), 99, 2, 1 }, /* FAC */
993 { L4TA(34), 101, 2, 1 }, /* IPC */
994 { L4TA(35), 103, 2, 1 }, /* SPI1 */
995 { L4TA(36), 105, 2, 1 }, /* SPI2 */
996 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
997 { L4TAO(10), 109, 2, 1 },
998 { L4TAO(11), 111, 2, 1 }, /* RNG */
999 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1000 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1001 { L4TA(37), 117, 2, 1 }, /* AES */
1002 { L4TA(38), 119, 2, 1 }, /* PKA */
1003 { -1, 121, 2, 1 },
1004 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1005 };
1006
1007 #define omap_l4ta(bus, cs) \
1008 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
1009 #define omap_l4tao(bus, cs) \
1010 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
1011
1012 /* Power, Reset, and Clock Management */
1013 struct omap_prcm_s {
1014 qemu_irq irq[3];
1015 struct omap_mpu_state_s *mpu;
1016 MemoryRegion iomem0;
1017 MemoryRegion iomem1;
1018
1019 uint32_t irqst[3];
1020 uint32_t irqen[3];
1021
1022 uint32_t sysconfig;
1023 uint32_t voltctrl;
1024 uint32_t scratch[20];
1025
1026 uint32_t clksrc[1];
1027 uint32_t clkout[1];
1028 uint32_t clkemul[1];
1029 uint32_t clkpol[1];
1030 uint32_t clksel[8];
1031 uint32_t clken[12];
1032 uint32_t clkctrl[4];
1033 uint32_t clkidle[7];
1034 uint32_t setuptime[2];
1035
1036 uint32_t wkup[3];
1037 uint32_t wken[3];
1038 uint32_t wkst[3];
1039 uint32_t rst[4];
1040 uint32_t rstctrl[1];
1041 uint32_t power[4];
1042 uint32_t rsttime_wkup;
1043
1044 uint32_t ev;
1045 uint32_t evtime[2];
1046
1047 int dpll_lock, apll_lock[2];
1048 };
1049
1050 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1051 {
1052 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1053 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1054 }
1055
1056 static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
1057 unsigned size)
1058 {
1059 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1060 uint32_t ret;
1061
1062 if (size != 4) {
1063 return omap_badwidth_read32(opaque, addr);
1064 }
1065
1066 switch (addr) {
1067 case 0x000: /* PRCM_REVISION */
1068 return 0x10;
1069
1070 case 0x010: /* PRCM_SYSCONFIG */
1071 return s->sysconfig;
1072
1073 case 0x018: /* PRCM_IRQSTATUS_MPU */
1074 return s->irqst[0];
1075
1076 case 0x01c: /* PRCM_IRQENABLE_MPU */
1077 return s->irqen[0];
1078
1079 case 0x050: /* PRCM_VOLTCTRL */
1080 return s->voltctrl;
1081 case 0x054: /* PRCM_VOLTST */
1082 return s->voltctrl & 3;
1083
1084 case 0x060: /* PRCM_CLKSRC_CTRL */
1085 return s->clksrc[0];
1086 case 0x070: /* PRCM_CLKOUT_CTRL */
1087 return s->clkout[0];
1088 case 0x078: /* PRCM_CLKEMUL_CTRL */
1089 return s->clkemul[0];
1090 case 0x080: /* PRCM_CLKCFG_CTRL */
1091 case 0x084: /* PRCM_CLKCFG_STATUS */
1092 return 0;
1093
1094 case 0x090: /* PRCM_VOLTSETUP */
1095 return s->setuptime[0];
1096
1097 case 0x094: /* PRCM_CLKSSETUP */
1098 return s->setuptime[1];
1099
1100 case 0x098: /* PRCM_POLCTRL */
1101 return s->clkpol[0];
1102
1103 case 0x0b0: /* GENERAL_PURPOSE1 */
1104 case 0x0b4: /* GENERAL_PURPOSE2 */
1105 case 0x0b8: /* GENERAL_PURPOSE3 */
1106 case 0x0bc: /* GENERAL_PURPOSE4 */
1107 case 0x0c0: /* GENERAL_PURPOSE5 */
1108 case 0x0c4: /* GENERAL_PURPOSE6 */
1109 case 0x0c8: /* GENERAL_PURPOSE7 */
1110 case 0x0cc: /* GENERAL_PURPOSE8 */
1111 case 0x0d0: /* GENERAL_PURPOSE9 */
1112 case 0x0d4: /* GENERAL_PURPOSE10 */
1113 case 0x0d8: /* GENERAL_PURPOSE11 */
1114 case 0x0dc: /* GENERAL_PURPOSE12 */
1115 case 0x0e0: /* GENERAL_PURPOSE13 */
1116 case 0x0e4: /* GENERAL_PURPOSE14 */
1117 case 0x0e8: /* GENERAL_PURPOSE15 */
1118 case 0x0ec: /* GENERAL_PURPOSE16 */
1119 case 0x0f0: /* GENERAL_PURPOSE17 */
1120 case 0x0f4: /* GENERAL_PURPOSE18 */
1121 case 0x0f8: /* GENERAL_PURPOSE19 */
1122 case 0x0fc: /* GENERAL_PURPOSE20 */
1123 return s->scratch[(addr - 0xb0) >> 2];
1124
1125 case 0x140: /* CM_CLKSEL_MPU */
1126 return s->clksel[0];
1127 case 0x148: /* CM_CLKSTCTRL_MPU */
1128 return s->clkctrl[0];
1129
1130 case 0x158: /* RM_RSTST_MPU */
1131 return s->rst[0];
1132 case 0x1c8: /* PM_WKDEP_MPU */
1133 return s->wkup[0];
1134 case 0x1d4: /* PM_EVGENCTRL_MPU */
1135 return s->ev;
1136 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1137 return s->evtime[0];
1138 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1139 return s->evtime[1];
1140 case 0x1e0: /* PM_PWSTCTRL_MPU */
1141 return s->power[0];
1142 case 0x1e4: /* PM_PWSTST_MPU */
1143 return 0;
1144
1145 case 0x200: /* CM_FCLKEN1_CORE */
1146 return s->clken[0];
1147 case 0x204: /* CM_FCLKEN2_CORE */
1148 return s->clken[1];
1149 case 0x210: /* CM_ICLKEN1_CORE */
1150 return s->clken[2];
1151 case 0x214: /* CM_ICLKEN2_CORE */
1152 return s->clken[3];
1153 case 0x21c: /* CM_ICLKEN4_CORE */
1154 return s->clken[4];
1155
1156 case 0x220: /* CM_IDLEST1_CORE */
1157 /* TODO: check the actual iclk status */
1158 return 0x7ffffff9;
1159 case 0x224: /* CM_IDLEST2_CORE */
1160 /* TODO: check the actual iclk status */
1161 return 0x00000007;
1162 case 0x22c: /* CM_IDLEST4_CORE */
1163 /* TODO: check the actual iclk status */
1164 return 0x0000001f;
1165
1166 case 0x230: /* CM_AUTOIDLE1_CORE */
1167 return s->clkidle[0];
1168 case 0x234: /* CM_AUTOIDLE2_CORE */
1169 return s->clkidle[1];
1170 case 0x238: /* CM_AUTOIDLE3_CORE */
1171 return s->clkidle[2];
1172 case 0x23c: /* CM_AUTOIDLE4_CORE */
1173 return s->clkidle[3];
1174
1175 case 0x240: /* CM_CLKSEL1_CORE */
1176 return s->clksel[1];
1177 case 0x244: /* CM_CLKSEL2_CORE */
1178 return s->clksel[2];
1179
1180 case 0x248: /* CM_CLKSTCTRL_CORE */
1181 return s->clkctrl[1];
1182
1183 case 0x2a0: /* PM_WKEN1_CORE */
1184 return s->wken[0];
1185 case 0x2a4: /* PM_WKEN2_CORE */
1186 return s->wken[1];
1187
1188 case 0x2b0: /* PM_WKST1_CORE */
1189 return s->wkst[0];
1190 case 0x2b4: /* PM_WKST2_CORE */
1191 return s->wkst[1];
1192 case 0x2c8: /* PM_WKDEP_CORE */
1193 return 0x1e;
1194
1195 case 0x2e0: /* PM_PWSTCTRL_CORE */
1196 return s->power[1];
1197 case 0x2e4: /* PM_PWSTST_CORE */
1198 return 0x000030 | (s->power[1] & 0xfc00);
1199
1200 case 0x300: /* CM_FCLKEN_GFX */
1201 return s->clken[5];
1202 case 0x310: /* CM_ICLKEN_GFX */
1203 return s->clken[6];
1204 case 0x320: /* CM_IDLEST_GFX */
1205 /* TODO: check the actual iclk status */
1206 return 0x00000001;
1207 case 0x340: /* CM_CLKSEL_GFX */
1208 return s->clksel[3];
1209 case 0x348: /* CM_CLKSTCTRL_GFX */
1210 return s->clkctrl[2];
1211 case 0x350: /* RM_RSTCTRL_GFX */
1212 return s->rstctrl[0];
1213 case 0x358: /* RM_RSTST_GFX */
1214 return s->rst[1];
1215 case 0x3c8: /* PM_WKDEP_GFX */
1216 return s->wkup[1];
1217
1218 case 0x3e0: /* PM_PWSTCTRL_GFX */
1219 return s->power[2];
1220 case 0x3e4: /* PM_PWSTST_GFX */
1221 return s->power[2] & 3;
1222
1223 case 0x400: /* CM_FCLKEN_WKUP */
1224 return s->clken[7];
1225 case 0x410: /* CM_ICLKEN_WKUP */
1226 return s->clken[8];
1227 case 0x420: /* CM_IDLEST_WKUP */
1228 /* TODO: check the actual iclk status */
1229 return 0x0000003f;
1230 case 0x430: /* CM_AUTOIDLE_WKUP */
1231 return s->clkidle[4];
1232 case 0x440: /* CM_CLKSEL_WKUP */
1233 return s->clksel[4];
1234 case 0x450: /* RM_RSTCTRL_WKUP */
1235 return 0;
1236 case 0x454: /* RM_RSTTIME_WKUP */
1237 return s->rsttime_wkup;
1238 case 0x458: /* RM_RSTST_WKUP */
1239 return s->rst[2];
1240 case 0x4a0: /* PM_WKEN_WKUP */
1241 return s->wken[2];
1242 case 0x4b0: /* PM_WKST_WKUP */
1243 return s->wkst[2];
1244
1245 case 0x500: /* CM_CLKEN_PLL */
1246 return s->clken[9];
1247 case 0x520: /* CM_IDLEST_CKGEN */
1248 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1249 if (!(s->clksel[6] & 3))
1250 /* Core uses 32-kHz clock */
1251 ret |= 3 << 0;
1252 else if (!s->dpll_lock)
1253 /* DPLL not locked, core uses ref_clk */
1254 ret |= 1 << 0;
1255 else
1256 /* Core uses DPLL */
1257 ret |= 2 << 0;
1258 return ret;
1259 case 0x530: /* CM_AUTOIDLE_PLL */
1260 return s->clkidle[5];
1261 case 0x540: /* CM_CLKSEL1_PLL */
1262 return s->clksel[5];
1263 case 0x544: /* CM_CLKSEL2_PLL */
1264 return s->clksel[6];
1265
1266 case 0x800: /* CM_FCLKEN_DSP */
1267 return s->clken[10];
1268 case 0x810: /* CM_ICLKEN_DSP */
1269 return s->clken[11];
1270 case 0x820: /* CM_IDLEST_DSP */
1271 /* TODO: check the actual iclk status */
1272 return 0x00000103;
1273 case 0x830: /* CM_AUTOIDLE_DSP */
1274 return s->clkidle[6];
1275 case 0x840: /* CM_CLKSEL_DSP */
1276 return s->clksel[7];
1277 case 0x848: /* CM_CLKSTCTRL_DSP */
1278 return s->clkctrl[3];
1279 case 0x850: /* RM_RSTCTRL_DSP */
1280 return 0;
1281 case 0x858: /* RM_RSTST_DSP */
1282 return s->rst[3];
1283 case 0x8c8: /* PM_WKDEP_DSP */
1284 return s->wkup[2];
1285 case 0x8e0: /* PM_PWSTCTRL_DSP */
1286 return s->power[3];
1287 case 0x8e4: /* PM_PWSTST_DSP */
1288 return 0x008030 | (s->power[3] & 0x3003);
1289
1290 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1291 return s->irqst[1];
1292 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1293 return s->irqen[1];
1294
1295 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1296 return s->irqst[2];
1297 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1298 return s->irqen[2];
1299 }
1300
1301 OMAP_BAD_REG(addr);
1302 return 0;
1303 }
1304
1305 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1306 {
1307 int mode[2];
1308
1309 mode[0] = (s->clken[9] >> 6) & 3;
1310 s->apll_lock[0] = (mode[0] == 3);
1311 mode[1] = (s->clken[9] >> 2) & 3;
1312 s->apll_lock[1] = (mode[1] == 3);
1313 /* TODO: update clocks */
1314
1315 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1316 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1317 __func__);
1318 }
1319
1320 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1321 {
1322 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1323 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1324 omap_clk core = omap_findclk(s->mpu, "core_clk");
1325 int mode = (s->clken[9] >> 0) & 3;
1326 int mult, div;
1327
1328 mult = (s->clksel[5] >> 12) & 0x3ff;
1329 div = (s->clksel[5] >> 8) & 0xf;
1330 if (mult == 0 || mult == 1)
1331 mode = 1; /* Bypass */
1332
1333 s->dpll_lock = 0;
1334 switch (mode) {
1335 case 0:
1336 fprintf(stderr, "%s: bad EN_DPLL\n", __func__);
1337 break;
1338 case 1: /* Low-power bypass mode (Default) */
1339 case 2: /* Fast-relock bypass mode */
1340 omap_clk_setrate(dpll, 1, 1);
1341 omap_clk_setrate(dpll_x2, 1, 1);
1342 break;
1343 case 3: /* Lock mode */
1344 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1345
1346 omap_clk_setrate(dpll, div + 1, mult);
1347 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1348 break;
1349 }
1350
1351 switch ((s->clksel[6] >> 0) & 3) {
1352 case 0:
1353 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1354 break;
1355 case 1:
1356 omap_clk_reparent(core, dpll);
1357 break;
1358 case 2:
1359 /* Default */
1360 omap_clk_reparent(core, dpll_x2);
1361 break;
1362 case 3:
1363 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __func__);
1364 break;
1365 }
1366 }
1367
1368 static void omap_prcm_write(void *opaque, hwaddr addr,
1369 uint64_t value, unsigned size)
1370 {
1371 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1372
1373 if (size != 4) {
1374 omap_badwidth_write32(opaque, addr, value);
1375 return;
1376 }
1377
1378 switch (addr) {
1379 case 0x000: /* PRCM_REVISION */
1380 case 0x054: /* PRCM_VOLTST */
1381 case 0x084: /* PRCM_CLKCFG_STATUS */
1382 case 0x1e4: /* PM_PWSTST_MPU */
1383 case 0x220: /* CM_IDLEST1_CORE */
1384 case 0x224: /* CM_IDLEST2_CORE */
1385 case 0x22c: /* CM_IDLEST4_CORE */
1386 case 0x2c8: /* PM_WKDEP_CORE */
1387 case 0x2e4: /* PM_PWSTST_CORE */
1388 case 0x320: /* CM_IDLEST_GFX */
1389 case 0x3e4: /* PM_PWSTST_GFX */
1390 case 0x420: /* CM_IDLEST_WKUP */
1391 case 0x520: /* CM_IDLEST_CKGEN */
1392 case 0x820: /* CM_IDLEST_DSP */
1393 case 0x8e4: /* PM_PWSTST_DSP */
1394 OMAP_RO_REG(addr);
1395 return;
1396
1397 case 0x010: /* PRCM_SYSCONFIG */
1398 s->sysconfig = value & 1;
1399 break;
1400
1401 case 0x018: /* PRCM_IRQSTATUS_MPU */
1402 s->irqst[0] &= ~value;
1403 omap_prcm_int_update(s, 0);
1404 break;
1405 case 0x01c: /* PRCM_IRQENABLE_MPU */
1406 s->irqen[0] = value & 0x3f;
1407 omap_prcm_int_update(s, 0);
1408 break;
1409
1410 case 0x050: /* PRCM_VOLTCTRL */
1411 s->voltctrl = value & 0xf1c3;
1412 break;
1413
1414 case 0x060: /* PRCM_CLKSRC_CTRL */
1415 s->clksrc[0] = value & 0xdb;
1416 /* TODO update clocks */
1417 break;
1418
1419 case 0x070: /* PRCM_CLKOUT_CTRL */
1420 s->clkout[0] = value & 0xbbbb;
1421 /* TODO update clocks */
1422 break;
1423
1424 case 0x078: /* PRCM_CLKEMUL_CTRL */
1425 s->clkemul[0] = value & 1;
1426 /* TODO update clocks */
1427 break;
1428
1429 case 0x080: /* PRCM_CLKCFG_CTRL */
1430 break;
1431
1432 case 0x090: /* PRCM_VOLTSETUP */
1433 s->setuptime[0] = value & 0xffff;
1434 break;
1435 case 0x094: /* PRCM_CLKSSETUP */
1436 s->setuptime[1] = value & 0xffff;
1437 break;
1438
1439 case 0x098: /* PRCM_POLCTRL */
1440 s->clkpol[0] = value & 0x701;
1441 break;
1442
1443 case 0x0b0: /* GENERAL_PURPOSE1 */
1444 case 0x0b4: /* GENERAL_PURPOSE2 */
1445 case 0x0b8: /* GENERAL_PURPOSE3 */
1446 case 0x0bc: /* GENERAL_PURPOSE4 */
1447 case 0x0c0: /* GENERAL_PURPOSE5 */
1448 case 0x0c4: /* GENERAL_PURPOSE6 */
1449 case 0x0c8: /* GENERAL_PURPOSE7 */
1450 case 0x0cc: /* GENERAL_PURPOSE8 */
1451 case 0x0d0: /* GENERAL_PURPOSE9 */
1452 case 0x0d4: /* GENERAL_PURPOSE10 */
1453 case 0x0d8: /* GENERAL_PURPOSE11 */
1454 case 0x0dc: /* GENERAL_PURPOSE12 */
1455 case 0x0e0: /* GENERAL_PURPOSE13 */
1456 case 0x0e4: /* GENERAL_PURPOSE14 */
1457 case 0x0e8: /* GENERAL_PURPOSE15 */
1458 case 0x0ec: /* GENERAL_PURPOSE16 */
1459 case 0x0f0: /* GENERAL_PURPOSE17 */
1460 case 0x0f4: /* GENERAL_PURPOSE18 */
1461 case 0x0f8: /* GENERAL_PURPOSE19 */
1462 case 0x0fc: /* GENERAL_PURPOSE20 */
1463 s->scratch[(addr - 0xb0) >> 2] = value;
1464 break;
1465
1466 case 0x140: /* CM_CLKSEL_MPU */
1467 s->clksel[0] = value & 0x1f;
1468 /* TODO update clocks */
1469 break;
1470 case 0x148: /* CM_CLKSTCTRL_MPU */
1471 s->clkctrl[0] = value & 0x1f;
1472 break;
1473
1474 case 0x158: /* RM_RSTST_MPU */
1475 s->rst[0] &= ~value;
1476 break;
1477 case 0x1c8: /* PM_WKDEP_MPU */
1478 s->wkup[0] = value & 0x15;
1479 break;
1480
1481 case 0x1d4: /* PM_EVGENCTRL_MPU */
1482 s->ev = value & 0x1f;
1483 break;
1484 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1485 s->evtime[0] = value;
1486 break;
1487 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1488 s->evtime[1] = value;
1489 break;
1490
1491 case 0x1e0: /* PM_PWSTCTRL_MPU */
1492 s->power[0] = value & 0xc0f;
1493 break;
1494
1495 case 0x200: /* CM_FCLKEN1_CORE */
1496 s->clken[0] = value & 0xbfffffff;
1497 /* TODO update clocks */
1498 /* The EN_EAC bit only gets/puts func_96m_clk. */
1499 break;
1500 case 0x204: /* CM_FCLKEN2_CORE */
1501 s->clken[1] = value & 0x00000007;
1502 /* TODO update clocks */
1503 break;
1504 case 0x210: /* CM_ICLKEN1_CORE */
1505 s->clken[2] = value & 0xfffffff9;
1506 /* TODO update clocks */
1507 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1508 break;
1509 case 0x214: /* CM_ICLKEN2_CORE */
1510 s->clken[3] = value & 0x00000007;
1511 /* TODO update clocks */
1512 break;
1513 case 0x21c: /* CM_ICLKEN4_CORE */
1514 s->clken[4] = value & 0x0000001f;
1515 /* TODO update clocks */
1516 break;
1517
1518 case 0x230: /* CM_AUTOIDLE1_CORE */
1519 s->clkidle[0] = value & 0xfffffff9;
1520 /* TODO update clocks */
1521 break;
1522 case 0x234: /* CM_AUTOIDLE2_CORE */
1523 s->clkidle[1] = value & 0x00000007;
1524 /* TODO update clocks */
1525 break;
1526 case 0x238: /* CM_AUTOIDLE3_CORE */
1527 s->clkidle[2] = value & 0x00000007;
1528 /* TODO update clocks */
1529 break;
1530 case 0x23c: /* CM_AUTOIDLE4_CORE */
1531 s->clkidle[3] = value & 0x0000001f;
1532 /* TODO update clocks */
1533 break;
1534
1535 case 0x240: /* CM_CLKSEL1_CORE */
1536 s->clksel[1] = value & 0x0fffbf7f;
1537 /* TODO update clocks */
1538 break;
1539
1540 case 0x244: /* CM_CLKSEL2_CORE */
1541 s->clksel[2] = value & 0x00fffffc;
1542 /* TODO update clocks */
1543 break;
1544
1545 case 0x248: /* CM_CLKSTCTRL_CORE */
1546 s->clkctrl[1] = value & 0x7;
1547 break;
1548
1549 case 0x2a0: /* PM_WKEN1_CORE */
1550 s->wken[0] = value & 0x04667ff8;
1551 break;
1552 case 0x2a4: /* PM_WKEN2_CORE */
1553 s->wken[1] = value & 0x00000005;
1554 break;
1555
1556 case 0x2b0: /* PM_WKST1_CORE */
1557 s->wkst[0] &= ~value;
1558 break;
1559 case 0x2b4: /* PM_WKST2_CORE */
1560 s->wkst[1] &= ~value;
1561 break;
1562
1563 case 0x2e0: /* PM_PWSTCTRL_CORE */
1564 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1565 break;
1566
1567 case 0x300: /* CM_FCLKEN_GFX */
1568 s->clken[5] = value & 6;
1569 /* TODO update clocks */
1570 break;
1571 case 0x310: /* CM_ICLKEN_GFX */
1572 s->clken[6] = value & 1;
1573 /* TODO update clocks */
1574 break;
1575 case 0x340: /* CM_CLKSEL_GFX */
1576 s->clksel[3] = value & 7;
1577 /* TODO update clocks */
1578 break;
1579 case 0x348: /* CM_CLKSTCTRL_GFX */
1580 s->clkctrl[2] = value & 1;
1581 break;
1582 case 0x350: /* RM_RSTCTRL_GFX */
1583 s->rstctrl[0] = value & 1;
1584 /* TODO: reset */
1585 break;
1586 case 0x358: /* RM_RSTST_GFX */
1587 s->rst[1] &= ~value;
1588 break;
1589 case 0x3c8: /* PM_WKDEP_GFX */
1590 s->wkup[1] = value & 0x13;
1591 break;
1592 case 0x3e0: /* PM_PWSTCTRL_GFX */
1593 s->power[2] = (value & 0x00c0f) | (3 << 2);
1594 break;
1595
1596 case 0x400: /* CM_FCLKEN_WKUP */
1597 s->clken[7] = value & 0xd;
1598 /* TODO update clocks */
1599 break;
1600 case 0x410: /* CM_ICLKEN_WKUP */
1601 s->clken[8] = value & 0x3f;
1602 /* TODO update clocks */
1603 break;
1604 case 0x430: /* CM_AUTOIDLE_WKUP */
1605 s->clkidle[4] = value & 0x0000003f;
1606 /* TODO update clocks */
1607 break;
1608 case 0x440: /* CM_CLKSEL_WKUP */
1609 s->clksel[4] = value & 3;
1610 /* TODO update clocks */
1611 break;
1612 case 0x450: /* RM_RSTCTRL_WKUP */
1613 /* TODO: reset */
1614 if (value & 2)
1615 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1616 break;
1617 case 0x454: /* RM_RSTTIME_WKUP */
1618 s->rsttime_wkup = value & 0x1fff;
1619 break;
1620 case 0x458: /* RM_RSTST_WKUP */
1621 s->rst[2] &= ~value;
1622 break;
1623 case 0x4a0: /* PM_WKEN_WKUP */
1624 s->wken[2] = value & 0x00000005;
1625 break;
1626 case 0x4b0: /* PM_WKST_WKUP */
1627 s->wkst[2] &= ~value;
1628 break;
1629
1630 case 0x500: /* CM_CLKEN_PLL */
1631 if (value & 0xffffff30)
1632 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1633 "future compatibility\n", __func__);
1634 if ((s->clken[9] ^ value) & 0xcc) {
1635 s->clken[9] &= ~0xcc;
1636 s->clken[9] |= value & 0xcc;
1637 omap_prcm_apll_update(s);
1638 }
1639 if ((s->clken[9] ^ value) & 3) {
1640 s->clken[9] &= ~3;
1641 s->clken[9] |= value & 3;
1642 omap_prcm_dpll_update(s);
1643 }
1644 break;
1645 case 0x530: /* CM_AUTOIDLE_PLL */
1646 s->clkidle[5] = value & 0x000000cf;
1647 /* TODO update clocks */
1648 break;
1649 case 0x540: /* CM_CLKSEL1_PLL */
1650 if (value & 0xfc4000d7)
1651 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1652 "future compatibility\n", __func__);
1653 if ((s->clksel[5] ^ value) & 0x003fff00) {
1654 s->clksel[5] = value & 0x03bfff28;
1655 omap_prcm_dpll_update(s);
1656 }
1657 /* TODO update the other clocks */
1658
1659 s->clksel[5] = value & 0x03bfff28;
1660 break;
1661 case 0x544: /* CM_CLKSEL2_PLL */
1662 if (value & ~3)
1663 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1664 "future compatibility\n", __func__);
1665 if (s->clksel[6] != (value & 3)) {
1666 s->clksel[6] = value & 3;
1667 omap_prcm_dpll_update(s);
1668 }
1669 break;
1670
1671 case 0x800: /* CM_FCLKEN_DSP */
1672 s->clken[10] = value & 0x501;
1673 /* TODO update clocks */
1674 break;
1675 case 0x810: /* CM_ICLKEN_DSP */
1676 s->clken[11] = value & 0x2;
1677 /* TODO update clocks */
1678 break;
1679 case 0x830: /* CM_AUTOIDLE_DSP */
1680 s->clkidle[6] = value & 0x2;
1681 /* TODO update clocks */
1682 break;
1683 case 0x840: /* CM_CLKSEL_DSP */
1684 s->clksel[7] = value & 0x3fff;
1685 /* TODO update clocks */
1686 break;
1687 case 0x848: /* CM_CLKSTCTRL_DSP */
1688 s->clkctrl[3] = value & 0x101;
1689 break;
1690 case 0x850: /* RM_RSTCTRL_DSP */
1691 /* TODO: reset */
1692 break;
1693 case 0x858: /* RM_RSTST_DSP */
1694 s->rst[3] &= ~value;
1695 break;
1696 case 0x8c8: /* PM_WKDEP_DSP */
1697 s->wkup[2] = value & 0x13;
1698 break;
1699 case 0x8e0: /* PM_PWSTCTRL_DSP */
1700 s->power[3] = (value & 0x03017) | (3 << 2);
1701 break;
1702
1703 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1704 s->irqst[1] &= ~value;
1705 omap_prcm_int_update(s, 1);
1706 break;
1707 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1708 s->irqen[1] = value & 0x7;
1709 omap_prcm_int_update(s, 1);
1710 break;
1711
1712 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1713 s->irqst[2] &= ~value;
1714 omap_prcm_int_update(s, 2);
1715 break;
1716 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1717 s->irqen[2] = value & 0x7;
1718 omap_prcm_int_update(s, 2);
1719 break;
1720
1721 default:
1722 OMAP_BAD_REG(addr);
1723 return;
1724 }
1725 }
1726
1727 static const MemoryRegionOps omap_prcm_ops = {
1728 .read = omap_prcm_read,
1729 .write = omap_prcm_write,
1730 .endianness = DEVICE_NATIVE_ENDIAN,
1731 };
1732
1733 static void omap_prcm_reset(struct omap_prcm_s *s)
1734 {
1735 s->sysconfig = 0;
1736 s->irqst[0] = 0;
1737 s->irqst[1] = 0;
1738 s->irqst[2] = 0;
1739 s->irqen[0] = 0;
1740 s->irqen[1] = 0;
1741 s->irqen[2] = 0;
1742 s->voltctrl = 0x1040;
1743 s->ev = 0x14;
1744 s->evtime[0] = 0;
1745 s->evtime[1] = 0;
1746 s->clkctrl[0] = 0;
1747 s->clkctrl[1] = 0;
1748 s->clkctrl[2] = 0;
1749 s->clkctrl[3] = 0;
1750 s->clken[1] = 7;
1751 s->clken[3] = 7;
1752 s->clken[4] = 0;
1753 s->clken[5] = 0;
1754 s->clken[6] = 0;
1755 s->clken[7] = 0xc;
1756 s->clken[8] = 0x3e;
1757 s->clken[9] = 0x0d;
1758 s->clken[10] = 0;
1759 s->clken[11] = 0;
1760 s->clkidle[0] = 0;
1761 s->clkidle[2] = 7;
1762 s->clkidle[3] = 0;
1763 s->clkidle[4] = 0;
1764 s->clkidle[5] = 0x0c;
1765 s->clkidle[6] = 0;
1766 s->clksel[0] = 0x01;
1767 s->clksel[1] = 0x02100121;
1768 s->clksel[2] = 0x00000000;
1769 s->clksel[3] = 0x01;
1770 s->clksel[4] = 0;
1771 s->clksel[7] = 0x0121;
1772 s->wkup[0] = 0x15;
1773 s->wkup[1] = 0x13;
1774 s->wkup[2] = 0x13;
1775 s->wken[0] = 0x04667ff8;
1776 s->wken[1] = 0x00000005;
1777 s->wken[2] = 5;
1778 s->wkst[0] = 0;
1779 s->wkst[1] = 0;
1780 s->wkst[2] = 0;
1781 s->power[0] = 0x00c;
1782 s->power[1] = 4;
1783 s->power[2] = 0x0000c;
1784 s->power[3] = 0x14;
1785 s->rstctrl[0] = 1;
1786 s->rst[3] = 1;
1787 omap_prcm_apll_update(s);
1788 omap_prcm_dpll_update(s);
1789 }
1790
1791 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1792 {
1793 s->setuptime[0] = 0;
1794 s->setuptime[1] = 0;
1795 memset(&s->scratch, 0, sizeof(s->scratch));
1796 s->rst[0] = 0x01;
1797 s->rst[1] = 0x00;
1798 s->rst[2] = 0x01;
1799 s->clken[0] = 0;
1800 s->clken[2] = 0;
1801 s->clkidle[1] = 0;
1802 s->clksel[5] = 0;
1803 s->clksel[6] = 2;
1804 s->clksrc[0] = 0x43;
1805 s->clkout[0] = 0x0303;
1806 s->clkemul[0] = 0;
1807 s->clkpol[0] = 0x100;
1808 s->rsttime_wkup = 0x1002;
1809
1810 omap_prcm_reset(s);
1811 }
1812
1813 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1814 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1815 struct omap_mpu_state_s *mpu)
1816 {
1817 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1);
1818
1819 s->irq[0] = mpu_int;
1820 s->irq[1] = dsp_int;
1821 s->irq[2] = iva_int;
1822 s->mpu = mpu;
1823 omap_prcm_coldreset(s);
1824
1825 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
1826 omap_l4_region_size(ta, 0));
1827 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
1828 omap_l4_region_size(ta, 1));
1829 omap_l4_attach(ta, 0, &s->iomem0);
1830 omap_l4_attach(ta, 1, &s->iomem1);
1831
1832 return s;
1833 }
1834
1835 /* System and Pinout control */
1836 struct omap_sysctl_s {
1837 struct omap_mpu_state_s *mpu;
1838 MemoryRegion iomem;
1839
1840 uint32_t sysconfig;
1841 uint32_t devconfig;
1842 uint32_t psaconfig;
1843 uint32_t padconf[0x45];
1844 uint8_t obs;
1845 uint32_t msuspendmux[5];
1846 };
1847
1848 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
1849 {
1850
1851 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1852 int pad_offset, byte_offset;
1853 int value;
1854
1855 switch (addr) {
1856 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1857 pad_offset = (addr - 0x30) >> 2;
1858 byte_offset = (addr - 0x30) & (4 - 1);
1859
1860 value = s->padconf[pad_offset];
1861 value = (value >> (byte_offset * 8)) & 0xff;
1862
1863 return value;
1864
1865 default:
1866 break;
1867 }
1868
1869 OMAP_BAD_REG(addr);
1870 return 0;
1871 }
1872
1873 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
1874 {
1875 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1876
1877 switch (addr) {
1878 case 0x000: /* CONTROL_REVISION */
1879 return 0x20;
1880
1881 case 0x010: /* CONTROL_SYSCONFIG */
1882 return s->sysconfig;
1883
1884 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1885 return s->padconf[(addr - 0x30) >> 2];
1886
1887 case 0x270: /* CONTROL_DEBOBS */
1888 return s->obs;
1889
1890 case 0x274: /* CONTROL_DEVCONF */
1891 return s->devconfig;
1892
1893 case 0x28c: /* CONTROL_EMU_SUPPORT */
1894 return 0;
1895
1896 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1897 return s->msuspendmux[0];
1898 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1899 return s->msuspendmux[1];
1900 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1901 return s->msuspendmux[2];
1902 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1903 return s->msuspendmux[3];
1904 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1905 return s->msuspendmux[4];
1906 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1907 return 0;
1908
1909 case 0x2b8: /* CONTROL_PSA_CTRL */
1910 return s->psaconfig;
1911 case 0x2bc: /* CONTROL_PSA_CMD */
1912 case 0x2c0: /* CONTROL_PSA_VALUE */
1913 return 0;
1914
1915 case 0x2b0: /* CONTROL_SEC_CTRL */
1916 return 0x800000f1;
1917 case 0x2d0: /* CONTROL_SEC_EMU */
1918 return 0x80000015;
1919 case 0x2d4: /* CONTROL_SEC_TAP */
1920 return 0x8000007f;
1921 case 0x2b4: /* CONTROL_SEC_TEST */
1922 case 0x2f0: /* CONTROL_SEC_STATUS */
1923 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1924 /* Secure mode is not present on general-pusrpose device. Outside
1925 * secure mode these values cannot be read or written. */
1926 return 0;
1927
1928 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1929 return 0xff;
1930 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1931 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1932 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1933 /* No secure mode so no Extended Secure RAM present. */
1934 return 0;
1935
1936 case 0x2f8: /* CONTROL_STATUS */
1937 /* Device Type => General-purpose */
1938 return 0x0300;
1939 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1940
1941 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1942 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1943 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1944 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1945 return 0xdecafbad;
1946
1947 case 0x310: /* CONTROL_RAND_KEY_0 */
1948 case 0x314: /* CONTROL_RAND_KEY_1 */
1949 case 0x318: /* CONTROL_RAND_KEY_2 */
1950 case 0x31c: /* CONTROL_RAND_KEY_3 */
1951 case 0x320: /* CONTROL_CUST_KEY_0 */
1952 case 0x324: /* CONTROL_CUST_KEY_1 */
1953 case 0x330: /* CONTROL_TEST_KEY_0 */
1954 case 0x334: /* CONTROL_TEST_KEY_1 */
1955 case 0x338: /* CONTROL_TEST_KEY_2 */
1956 case 0x33c: /* CONTROL_TEST_KEY_3 */
1957 case 0x340: /* CONTROL_TEST_KEY_4 */
1958 case 0x344: /* CONTROL_TEST_KEY_5 */
1959 case 0x348: /* CONTROL_TEST_KEY_6 */
1960 case 0x34c: /* CONTROL_TEST_KEY_7 */
1961 case 0x350: /* CONTROL_TEST_KEY_8 */
1962 case 0x354: /* CONTROL_TEST_KEY_9 */
1963 /* Can only be accessed in secure mode and when C_FieldAccEnable
1964 * bit is set in CONTROL_SEC_CTRL.
1965 * TODO: otherwise an interconnect access error is generated. */
1966 return 0;
1967 }
1968
1969 OMAP_BAD_REG(addr);
1970 return 0;
1971 }
1972
1973 static void omap_sysctl_write8(void *opaque, hwaddr addr,
1974 uint32_t value)
1975 {
1976 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1977 int pad_offset, byte_offset;
1978 int prev_value;
1979
1980 switch (addr) {
1981 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1982 pad_offset = (addr - 0x30) >> 2;
1983 byte_offset = (addr - 0x30) & (4 - 1);
1984
1985 prev_value = s->padconf[pad_offset];
1986 prev_value &= ~(0xff << (byte_offset * 8));
1987 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1988 s->padconf[pad_offset] = prev_value;
1989 break;
1990
1991 default:
1992 OMAP_BAD_REG(addr);
1993 break;
1994 }
1995 }
1996
1997 static void omap_sysctl_write(void *opaque, hwaddr addr,
1998 uint32_t value)
1999 {
2000 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2001
2002 switch (addr) {
2003 case 0x000: /* CONTROL_REVISION */
2004 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2005 case 0x2c0: /* CONTROL_PSA_VALUE */
2006 case 0x2f8: /* CONTROL_STATUS */
2007 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2008 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2009 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2010 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2011 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2012 case 0x310: /* CONTROL_RAND_KEY_0 */
2013 case 0x314: /* CONTROL_RAND_KEY_1 */
2014 case 0x318: /* CONTROL_RAND_KEY_2 */
2015 case 0x31c: /* CONTROL_RAND_KEY_3 */
2016 case 0x320: /* CONTROL_CUST_KEY_0 */
2017 case 0x324: /* CONTROL_CUST_KEY_1 */
2018 case 0x330: /* CONTROL_TEST_KEY_0 */
2019 case 0x334: /* CONTROL_TEST_KEY_1 */
2020 case 0x338: /* CONTROL_TEST_KEY_2 */
2021 case 0x33c: /* CONTROL_TEST_KEY_3 */
2022 case 0x340: /* CONTROL_TEST_KEY_4 */
2023 case 0x344: /* CONTROL_TEST_KEY_5 */
2024 case 0x348: /* CONTROL_TEST_KEY_6 */
2025 case 0x34c: /* CONTROL_TEST_KEY_7 */
2026 case 0x350: /* CONTROL_TEST_KEY_8 */
2027 case 0x354: /* CONTROL_TEST_KEY_9 */
2028 OMAP_RO_REG(addr);
2029 return;
2030
2031 case 0x010: /* CONTROL_SYSCONFIG */
2032 s->sysconfig = value & 0x1e;
2033 break;
2034
2035 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2036 /* XXX: should check constant bits */
2037 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2038 break;
2039
2040 case 0x270: /* CONTROL_DEBOBS */
2041 s->obs = value & 0xff;
2042 break;
2043
2044 case 0x274: /* CONTROL_DEVCONF */
2045 s->devconfig = value & 0xffffc7ff;
2046 break;
2047
2048 case 0x28c: /* CONTROL_EMU_SUPPORT */
2049 break;
2050
2051 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2052 s->msuspendmux[0] = value & 0x3fffffff;
2053 break;
2054 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2055 s->msuspendmux[1] = value & 0x3fffffff;
2056 break;
2057 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2058 s->msuspendmux[2] = value & 0x3fffffff;
2059 break;
2060 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2061 s->msuspendmux[3] = value & 0x3fffffff;
2062 break;
2063 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2064 s->msuspendmux[4] = value & 0x3fffffff;
2065 break;
2066
2067 case 0x2b8: /* CONTROL_PSA_CTRL */
2068 s->psaconfig = value & 0x1c;
2069 s->psaconfig |= (value & 0x20) ? 2 : 1;
2070 break;
2071 case 0x2bc: /* CONTROL_PSA_CMD */
2072 break;
2073
2074 case 0x2b0: /* CONTROL_SEC_CTRL */
2075 case 0x2b4: /* CONTROL_SEC_TEST */
2076 case 0x2d0: /* CONTROL_SEC_EMU */
2077 case 0x2d4: /* CONTROL_SEC_TAP */
2078 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2079 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2080 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2081 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2082 case 0x2f0: /* CONTROL_SEC_STATUS */
2083 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2084 break;
2085
2086 default:
2087 OMAP_BAD_REG(addr);
2088 return;
2089 }
2090 }
2091
2092 static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
2093 unsigned size)
2094 {
2095 switch (size) {
2096 case 1:
2097 return omap_sysctl_read8(opaque, addr);
2098 case 2:
2099 return omap_badwidth_read32(opaque, addr); /* TODO */
2100 case 4:
2101 return omap_sysctl_read(opaque, addr);
2102 default:
2103 g_assert_not_reached();
2104 }
2105 }
2106
2107 static void omap_sysctl_writefn(void *opaque, hwaddr addr,
2108 uint64_t value, unsigned size)
2109 {
2110 switch (size) {
2111 case 1:
2112 omap_sysctl_write8(opaque, addr, value);
2113 break;
2114 case 2:
2115 omap_badwidth_write32(opaque, addr, value); /* TODO */
2116 break;
2117 case 4:
2118 omap_sysctl_write(opaque, addr, value);
2119 break;
2120 default:
2121 g_assert_not_reached();
2122 }
2123 }
2124
2125 static const MemoryRegionOps omap_sysctl_ops = {
2126 .read = omap_sysctl_readfn,
2127 .write = omap_sysctl_writefn,
2128 .valid.min_access_size = 1,
2129 .valid.max_access_size = 4,
2130 .endianness = DEVICE_NATIVE_ENDIAN,
2131 };
2132
2133 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2134 {
2135 /* (power-on reset) */
2136 s->sysconfig = 0;
2137 s->obs = 0;
2138 s->devconfig = 0x0c000000;
2139 s->msuspendmux[0] = 0x00000000;
2140 s->msuspendmux[1] = 0x00000000;
2141 s->msuspendmux[2] = 0x00000000;
2142 s->msuspendmux[3] = 0x00000000;
2143 s->msuspendmux[4] = 0x00000000;
2144 s->psaconfig = 1;
2145
2146 s->padconf[0x00] = 0x000f0f0f;
2147 s->padconf[0x01] = 0x00000000;
2148 s->padconf[0x02] = 0x00000000;
2149 s->padconf[0x03] = 0x00000000;
2150 s->padconf[0x04] = 0x00000000;
2151 s->padconf[0x05] = 0x00000000;
2152 s->padconf[0x06] = 0x00000000;
2153 s->padconf[0x07] = 0x00000000;
2154 s->padconf[0x08] = 0x08080800;
2155 s->padconf[0x09] = 0x08080808;
2156 s->padconf[0x0a] = 0x08080808;
2157 s->padconf[0x0b] = 0x08080808;
2158 s->padconf[0x0c] = 0x08080808;
2159 s->padconf[0x0d] = 0x08080800;
2160 s->padconf[0x0e] = 0x08080808;
2161 s->padconf[0x0f] = 0x08080808;
2162 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2163 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2164 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2165 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2166 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2167 s->padconf[0x15] = 0x18181818;
2168 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2169 s->padconf[0x17] = 0x1f001f00;
2170 s->padconf[0x18] = 0x1f1f1f1f;
2171 s->padconf[0x19] = 0x00000000;
2172 s->padconf[0x1a] = 0x1f180000;
2173 s->padconf[0x1b] = 0x00001f1f;
2174 s->padconf[0x1c] = 0x1f001f00;
2175 s->padconf[0x1d] = 0x00000000;
2176 s->padconf[0x1e] = 0x00000000;
2177 s->padconf[0x1f] = 0x08000000;
2178 s->padconf[0x20] = 0x08080808;
2179 s->padconf[0x21] = 0x08080808;
2180 s->padconf[0x22] = 0x0f080808;
2181 s->padconf[0x23] = 0x0f0f0f0f;
2182 s->padconf[0x24] = 0x000f0f0f;
2183 s->padconf[0x25] = 0x1f1f1f0f;
2184 s->padconf[0x26] = 0x080f0f1f;
2185 s->padconf[0x27] = 0x070f1808;
2186 s->padconf[0x28] = 0x0f070707;
2187 s->padconf[0x29] = 0x000f0f1f;
2188 s->padconf[0x2a] = 0x0f0f0f1f;
2189 s->padconf[0x2b] = 0x08000000;
2190 s->padconf[0x2c] = 0x0000001f;
2191 s->padconf[0x2d] = 0x0f0f1f00;
2192 s->padconf[0x2e] = 0x1f1f0f0f;
2193 s->padconf[0x2f] = 0x0f1f1f1f;
2194 s->padconf[0x30] = 0x0f0f0f0f;
2195 s->padconf[0x31] = 0x0f1f0f1f;
2196 s->padconf[0x32] = 0x0f0f0f0f;
2197 s->padconf[0x33] = 0x0f1f0f1f;
2198 s->padconf[0x34] = 0x1f1f0f0f;
2199 s->padconf[0x35] = 0x0f0f1f1f;
2200 s->padconf[0x36] = 0x0f0f1f0f;
2201 s->padconf[0x37] = 0x0f0f0f0f;
2202 s->padconf[0x38] = 0x1f18180f;
2203 s->padconf[0x39] = 0x1f1f1f1f;
2204 s->padconf[0x3a] = 0x00001f1f;
2205 s->padconf[0x3b] = 0x00000000;
2206 s->padconf[0x3c] = 0x00000000;
2207 s->padconf[0x3d] = 0x0f0f0f0f;
2208 s->padconf[0x3e] = 0x18000f0f;
2209 s->padconf[0x3f] = 0x00070000;
2210 s->padconf[0x40] = 0x00000707;
2211 s->padconf[0x41] = 0x0f1f0700;
2212 s->padconf[0x42] = 0x1f1f070f;
2213 s->padconf[0x43] = 0x0008081f;
2214 s->padconf[0x44] = 0x00000800;
2215 }
2216
2217 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2218 omap_clk iclk, struct omap_mpu_state_s *mpu)
2219 {
2220 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1);
2221
2222 s->mpu = mpu;
2223 omap_sysctl_reset(s);
2224
2225 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
2226 omap_l4_region_size(ta, 0));
2227 omap_l4_attach(ta, 0, &s->iomem);
2228
2229 return s;
2230 }
2231
2232 /* General chip reset */
2233 static void omap2_mpu_reset(void *opaque)
2234 {
2235 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2236
2237 omap_dma_reset(mpu->dma);
2238 omap_prcm_reset(mpu->prcm);
2239 omap_sysctl_reset(mpu->sysc);
2240 omap_gp_timer_reset(mpu->gptimer[0]);
2241 omap_gp_timer_reset(mpu->gptimer[1]);
2242 omap_gp_timer_reset(mpu->gptimer[2]);
2243 omap_gp_timer_reset(mpu->gptimer[3]);
2244 omap_gp_timer_reset(mpu->gptimer[4]);
2245 omap_gp_timer_reset(mpu->gptimer[5]);
2246 omap_gp_timer_reset(mpu->gptimer[6]);
2247 omap_gp_timer_reset(mpu->gptimer[7]);
2248 omap_gp_timer_reset(mpu->gptimer[8]);
2249 omap_gp_timer_reset(mpu->gptimer[9]);
2250 omap_gp_timer_reset(mpu->gptimer[10]);
2251 omap_gp_timer_reset(mpu->gptimer[11]);
2252 omap_synctimer_reset(mpu->synctimer);
2253 omap_sdrc_reset(mpu->sdrc);
2254 omap_gpmc_reset(mpu->gpmc);
2255 omap_dss_reset(mpu->dss);
2256 omap_uart_reset(mpu->uart[0]);
2257 omap_uart_reset(mpu->uart[1]);
2258 omap_uart_reset(mpu->uart[2]);
2259 omap_mmc_reset(mpu->mmc);
2260 omap_mcspi_reset(mpu->mcspi[0]);
2261 omap_mcspi_reset(mpu->mcspi[1]);
2262 cpu_reset(CPU(mpu->cpu));
2263 }
2264
2265 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2266 hwaddr addr)
2267 {
2268 return 1;
2269 }
2270
2271 static const struct dma_irq_map omap2_dma_irq_map[] = {
2272 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2273 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2274 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2275 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2276 };
2277
2278 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
2279 unsigned long sdram_size,
2280 const char *cpu_type)
2281 {
2282 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
2283 qemu_irq dma_irqs[4];
2284 DriveInfo *dinfo;
2285 int i;
2286 SysBusDevice *busdev;
2287 struct omap_target_agent_s *ta;
2288
2289 /* Core */
2290 s->mpu_model = omap2420;
2291 s->cpu = ARM_CPU(cpu_create(cpu_type));
2292 s->sdram_size = sdram_size;
2293 s->sram_size = OMAP242X_SRAM_SIZE;
2294
2295 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
2296
2297 /* Clocks */
2298 omap_clk_init(s);
2299
2300 /* Memory-mapped stuff */
2301 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
2302 s->sdram_size);
2303 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
2304 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
2305 &error_fatal);
2306 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
2307
2308 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
2309
2310 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2311 s->ih[0] = qdev_create(NULL, "omap2-intc");
2312 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
2313 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
2314 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
2315 qdev_init_nofail(s->ih[0]);
2316 busdev = SYS_BUS_DEVICE(s->ih[0]);
2317 sysbus_connect_irq(busdev, 0,
2318 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
2319 sysbus_connect_irq(busdev, 1,
2320 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
2321 sysbus_mmio_map(busdev, 0, 0x480fe000);
2322 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2323 qdev_get_gpio_in(s->ih[0],
2324 OMAP_INT_24XX_PRCM_MPU_IRQ),
2325 NULL, NULL, s);
2326
2327 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2328 omap_findclk(s, "omapctrl_iclk"), s);
2329
2330 for (i = 0; i < 4; i++) {
2331 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2332 omap2_dma_irq_map[i].intr);
2333 }
2334 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
2335 omap_findclk(s, "sdma_iclk"),
2336 omap_findclk(s, "sdma_fclk"));
2337 s->port->addr_valid = omap2_validate_addr;
2338
2339 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2340 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
2341 OMAP2_Q2_BASE, s->sdram_size);
2342 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
2343 OMAP2_SRAM_BASE, s->sram_size);
2344
2345 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
2346 qdev_get_gpio_in(s->ih[0],
2347 OMAP_INT_24XX_UART1_IRQ),
2348 omap_findclk(s, "uart1_fclk"),
2349 omap_findclk(s, "uart1_iclk"),
2350 s->drq[OMAP24XX_DMA_UART1_TX],
2351 s->drq[OMAP24XX_DMA_UART1_RX],
2352 "uart1",
2353 serial_hd(0));
2354 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
2355 qdev_get_gpio_in(s->ih[0],
2356 OMAP_INT_24XX_UART2_IRQ),
2357 omap_findclk(s, "uart2_fclk"),
2358 omap_findclk(s, "uart2_iclk"),
2359 s->drq[OMAP24XX_DMA_UART2_TX],
2360 s->drq[OMAP24XX_DMA_UART2_RX],
2361 "uart2",
2362 serial_hd(0) ? serial_hd(1) : NULL);
2363 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
2364 qdev_get_gpio_in(s->ih[0],
2365 OMAP_INT_24XX_UART3_IRQ),
2366 omap_findclk(s, "uart3_fclk"),
2367 omap_findclk(s, "uart3_iclk"),
2368 s->drq[OMAP24XX_DMA_UART3_TX],
2369 s->drq[OMAP24XX_DMA_UART3_RX],
2370 "uart3",
2371 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
2372
2373 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2374 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
2375 omap_findclk(s, "wu_gpt1_clk"),
2376 omap_findclk(s, "wu_l4_iclk"));
2377 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2378 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
2379 omap_findclk(s, "core_gpt2_clk"),
2380 omap_findclk(s, "core_l4_iclk"));
2381 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2382 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
2383 omap_findclk(s, "core_gpt3_clk"),
2384 omap_findclk(s, "core_l4_iclk"));
2385 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2386 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
2387 omap_findclk(s, "core_gpt4_clk"),
2388 omap_findclk(s, "core_l4_iclk"));
2389 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2390 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
2391 omap_findclk(s, "core_gpt5_clk"),
2392 omap_findclk(s, "core_l4_iclk"));
2393 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2394 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
2395 omap_findclk(s, "core_gpt6_clk"),
2396 omap_findclk(s, "core_l4_iclk"));
2397 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2398 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
2399 omap_findclk(s, "core_gpt7_clk"),
2400 omap_findclk(s, "core_l4_iclk"));
2401 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2402 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
2403 omap_findclk(s, "core_gpt8_clk"),
2404 omap_findclk(s, "core_l4_iclk"));
2405 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2406 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
2407 omap_findclk(s, "core_gpt9_clk"),
2408 omap_findclk(s, "core_l4_iclk"));
2409 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2410 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
2411 omap_findclk(s, "core_gpt10_clk"),
2412 omap_findclk(s, "core_l4_iclk"));
2413 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2414 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
2415 omap_findclk(s, "core_gpt11_clk"),
2416 omap_findclk(s, "core_l4_iclk"));
2417 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2418 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
2419 omap_findclk(s, "core_gpt12_clk"),
2420 omap_findclk(s, "core_l4_iclk"));
2421
2422 omap_tap_init(omap_l4ta(s->l4, 2), s);
2423
2424 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2425 omap_findclk(s, "clk32-kHz"),
2426 omap_findclk(s, "core_l4_iclk"));
2427
2428 s->i2c[0] = qdev_create(NULL, "omap_i2c");
2429 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
2430 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
2431 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
2432 qdev_init_nofail(s->i2c[0]);
2433 busdev = SYS_BUS_DEVICE(s->i2c[0]);
2434 sysbus_connect_irq(busdev, 0,
2435 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
2436 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
2437 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
2438 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
2439
2440 s->i2c[1] = qdev_create(NULL, "omap_i2c");
2441 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
2442 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
2443 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
2444 qdev_init_nofail(s->i2c[1]);
2445 busdev = SYS_BUS_DEVICE(s->i2c[1]);
2446 sysbus_connect_irq(busdev, 0,
2447 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
2448 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
2449 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
2450 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
2451
2452 s->gpio = qdev_create(NULL, "omap2-gpio");
2453 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2454 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
2455 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
2456 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
2457 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
2458 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
2459 if (s->mpu_model == omap2430) {
2460 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
2461 }
2462 qdev_init_nofail(s->gpio);
2463 busdev = SYS_BUS_DEVICE(s->gpio);
2464 sysbus_connect_irq(busdev, 0,
2465 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2466 sysbus_connect_irq(busdev, 3,
2467 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2468 sysbus_connect_irq(busdev, 6,
2469 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2470 sysbus_connect_irq(busdev, 9,
2471 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
2472 if (s->mpu_model == omap2430) {
2473 sysbus_connect_irq(busdev, 12,
2474 qdev_get_gpio_in(s->ih[0],
2475 OMAP_INT_243X_GPIO_BANK5));
2476 }
2477 ta = omap_l4ta(s->l4, 3);
2478 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2479 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2480 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2481 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2482 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2483
2484 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
2485 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2486 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
2487 s->drq[OMAP24XX_DMA_GPMC]);
2488
2489 dinfo = drive_get(IF_SD, 0, 0);
2490 if (!dinfo && !qtest_enabled()) {
2491 warn_report("missing SecureDigital device");
2492 }
2493 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9),
2494 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
2495 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
2496 &s->drq[OMAP24XX_DMA_MMC1_TX],
2497 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2498
2499 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2500 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
2501 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2502 omap_findclk(s, "spi1_fclk"),
2503 omap_findclk(s, "spi1_iclk"));
2504 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2505 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
2506 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2507 omap_findclk(s, "spi2_fclk"),
2508 omap_findclk(s, "spi2_iclk"));
2509
2510 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
2511 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2512 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2513 s->drq[OMAP24XX_DMA_DSS],
2514 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2515 omap_findclk(s, "dss_54m_clk"),
2516 omap_findclk(s, "dss_l3_iclk"),
2517 omap_findclk(s, "dss_l4_iclk"));
2518
2519 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
2520 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2521 omap_findclk(s, "emul_ck"),
2522 serial_hd(0) && serial_hd(1) && serial_hd(2) ?
2523 serial_hd(3) : NULL);
2524
2525 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2526 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
2527 /* Ten consecutive lines */
2528 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2529 omap_findclk(s, "func_96m_clk"),
2530 omap_findclk(s, "core_l4_iclk"));
2531
2532 /* All register mappings (includin those not currenlty implemented):
2533 * SystemControlMod 48000000 - 48000fff
2534 * SystemControlL4 48001000 - 48001fff
2535 * 32kHz Timer Mod 48004000 - 48004fff
2536 * 32kHz Timer L4 48005000 - 48005fff
2537 * PRCM ModA 48008000 - 480087ff
2538 * PRCM ModB 48008800 - 48008fff
2539 * PRCM L4 48009000 - 48009fff
2540 * TEST-BCM Mod 48012000 - 48012fff
2541 * TEST-BCM L4 48013000 - 48013fff
2542 * TEST-TAP Mod 48014000 - 48014fff
2543 * TEST-TAP L4 48015000 - 48015fff
2544 * GPIO1 Mod 48018000 - 48018fff
2545 * GPIO Top 48019000 - 48019fff
2546 * GPIO2 Mod 4801a000 - 4801afff
2547 * GPIO L4 4801b000 - 4801bfff
2548 * GPIO3 Mod 4801c000 - 4801cfff
2549 * GPIO4 Mod 4801e000 - 4801efff
2550 * WDTIMER1 Mod 48020000 - 48010fff
2551 * WDTIMER Top 48021000 - 48011fff
2552 * WDTIMER2 Mod 48022000 - 48012fff
2553 * WDTIMER L4 48023000 - 48013fff
2554 * WDTIMER3 Mod 48024000 - 48014fff
2555 * WDTIMER3 L4 48025000 - 48015fff
2556 * WDTIMER4 Mod 48026000 - 48016fff
2557 * WDTIMER4 L4 48027000 - 48017fff
2558 * GPTIMER1 Mod 48028000 - 48018fff
2559 * GPTIMER1 L4 48029000 - 48019fff
2560 * GPTIMER2 Mod 4802a000 - 4801afff
2561 * GPTIMER2 L4 4802b000 - 4801bfff
2562 * L4-Config AP 48040000 - 480407ff
2563 * L4-Config IP 48040800 - 48040fff
2564 * L4-Config LA 48041000 - 48041fff
2565 * ARM11ETB Mod 48048000 - 48049fff
2566 * ARM11ETB L4 4804a000 - 4804afff
2567 * DISPLAY Top 48050000 - 480503ff
2568 * DISPLAY DISPC 48050400 - 480507ff
2569 * DISPLAY RFBI 48050800 - 48050bff
2570 * DISPLAY VENC 48050c00 - 48050fff
2571 * DISPLAY L4 48051000 - 48051fff
2572 * CAMERA Top 48052000 - 480523ff
2573 * CAMERA core 48052400 - 480527ff
2574 * CAMERA DMA 48052800 - 48052bff
2575 * CAMERA MMU 48052c00 - 48052fff
2576 * CAMERA L4 48053000 - 48053fff
2577 * SDMA Mod 48056000 - 48056fff
2578 * SDMA L4 48057000 - 48057fff
2579 * SSI Top 48058000 - 48058fff
2580 * SSI GDD 48059000 - 48059fff
2581 * SSI Port1 4805a000 - 4805afff
2582 * SSI Port2 4805b000 - 4805bfff
2583 * SSI L4 4805c000 - 4805cfff
2584 * USB Mod 4805e000 - 480fefff
2585 * USB L4 4805f000 - 480fffff
2586 * WIN_TRACER1 Mod 48060000 - 48060fff
2587 * WIN_TRACER1 L4 48061000 - 48061fff
2588 * WIN_TRACER2 Mod 48062000 - 48062fff
2589 * WIN_TRACER2 L4 48063000 - 48063fff
2590 * WIN_TRACER3 Mod 48064000 - 48064fff
2591 * WIN_TRACER3 L4 48065000 - 48065fff
2592 * WIN_TRACER4 Top 48066000 - 480660ff
2593 * WIN_TRACER4 ETT 48066100 - 480661ff
2594 * WIN_TRACER4 WT 48066200 - 480662ff
2595 * WIN_TRACER4 L4 48067000 - 48067fff
2596 * XTI Mod 48068000 - 48068fff
2597 * XTI L4 48069000 - 48069fff
2598 * UART1 Mod 4806a000 - 4806afff
2599 * UART1 L4 4806b000 - 4806bfff
2600 * UART2 Mod 4806c000 - 4806cfff
2601 * UART2 L4 4806d000 - 4806dfff
2602 * UART3 Mod 4806e000 - 4806efff
2603 * UART3 L4 4806f000 - 4806ffff
2604 * I2C1 Mod 48070000 - 48070fff
2605 * I2C1 L4 48071000 - 48071fff
2606 * I2C2 Mod 48072000 - 48072fff
2607 * I2C2 L4 48073000 - 48073fff
2608 * McBSP1 Mod 48074000 - 48074fff
2609 * McBSP1 L4 48075000 - 48075fff
2610 * McBSP2 Mod 48076000 - 48076fff
2611 * McBSP2 L4 48077000 - 48077fff
2612 * GPTIMER3 Mod 48078000 - 48078fff
2613 * GPTIMER3 L4 48079000 - 48079fff
2614 * GPTIMER4 Mod 4807a000 - 4807afff
2615 * GPTIMER4 L4 4807b000 - 4807bfff
2616 * GPTIMER5 Mod 4807c000 - 4807cfff
2617 * GPTIMER5 L4 4807d000 - 4807dfff
2618 * GPTIMER6 Mod 4807e000 - 4807efff
2619 * GPTIMER6 L4 4807f000 - 4807ffff
2620 * GPTIMER7 Mod 48080000 - 48080fff
2621 * GPTIMER7 L4 48081000 - 48081fff
2622 * GPTIMER8 Mod 48082000 - 48082fff
2623 * GPTIMER8 L4 48083000 - 48083fff
2624 * GPTIMER9 Mod 48084000 - 48084fff
2625 * GPTIMER9 L4 48085000 - 48085fff
2626 * GPTIMER10 Mod 48086000 - 48086fff
2627 * GPTIMER10 L4 48087000 - 48087fff
2628 * GPTIMER11 Mod 48088000 - 48088fff
2629 * GPTIMER11 L4 48089000 - 48089fff
2630 * GPTIMER12 Mod 4808a000 - 4808afff
2631 * GPTIMER12 L4 4808b000 - 4808bfff
2632 * EAC Mod 48090000 - 48090fff
2633 * EAC L4 48091000 - 48091fff
2634 * FAC Mod 48092000 - 48092fff
2635 * FAC L4 48093000 - 48093fff
2636 * MAILBOX Mod 48094000 - 48094fff
2637 * MAILBOX L4 48095000 - 48095fff
2638 * SPI1 Mod 48098000 - 48098fff
2639 * SPI1 L4 48099000 - 48099fff
2640 * SPI2 Mod 4809a000 - 4809afff
2641 * SPI2 L4 4809b000 - 4809bfff
2642 * MMC/SDIO Mod 4809c000 - 4809cfff
2643 * MMC/SDIO L4 4809d000 - 4809dfff
2644 * MS_PRO Mod 4809e000 - 4809efff
2645 * MS_PRO L4 4809f000 - 4809ffff
2646 * RNG Mod 480a0000 - 480a0fff
2647 * RNG L4 480a1000 - 480a1fff
2648 * DES3DES Mod 480a2000 - 480a2fff
2649 * DES3DES L4 480a3000 - 480a3fff
2650 * SHA1MD5 Mod 480a4000 - 480a4fff
2651 * SHA1MD5 L4 480a5000 - 480a5fff
2652 * AES Mod 480a6000 - 480a6fff
2653 * AES L4 480a7000 - 480a7fff
2654 * PKA Mod 480a8000 - 480a9fff
2655 * PKA L4 480aa000 - 480aafff
2656 * MG Mod 480b0000 - 480b0fff
2657 * MG L4 480b1000 - 480b1fff
2658 * HDQ/1-wire Mod 480b2000 - 480b2fff
2659 * HDQ/1-wire L4 480b3000 - 480b3fff
2660 * MPU interrupt 480fe000 - 480fefff
2661 * STI channel base 54000000 - 5400ffff
2662 * IVA RAM 5c000000 - 5c01ffff
2663 * IVA ROM 5c020000 - 5c027fff
2664 * IMG_BUF_A 5c040000 - 5c040fff
2665 * IMG_BUF_B 5c042000 - 5c042fff
2666 * VLCDS 5c048000 - 5c0487ff
2667 * IMX_COEF 5c049000 - 5c04afff
2668 * IMX_CMD 5c051000 - 5c051fff
2669 * VLCDQ 5c053000 - 5c0533ff
2670 * VLCDH 5c054000 - 5c054fff
2671 * SEQ_CMD 5c055000 - 5c055fff
2672 * IMX_REG 5c056000 - 5c0560ff
2673 * VLCD_REG 5c056100 - 5c0561ff
2674 * SEQ_REG 5c056200 - 5c0562ff
2675 * IMG_BUF_REG 5c056300 - 5c0563ff
2676 * SEQIRQ_REG 5c056400 - 5c0564ff
2677 * OCP_REG 5c060000 - 5c060fff
2678 * SYSC_REG 5c070000 - 5c070fff
2679 * MMU_REG 5d000000 - 5d000fff
2680 * sDMA R 68000400 - 680005ff
2681 * sDMA W 68000600 - 680007ff
2682 * Display Control 68000800 - 680009ff
2683 * DSP subsystem 68000a00 - 68000bff
2684 * MPU subsystem 68000c00 - 68000dff
2685 * IVA subsystem 68001000 - 680011ff
2686 * USB 68001200 - 680013ff
2687 * Camera 68001400 - 680015ff
2688 * VLYNQ (firewall) 68001800 - 68001bff
2689 * VLYNQ 68001e00 - 68001fff
2690 * SSI 68002000 - 680021ff
2691 * L4 68002400 - 680025ff
2692 * DSP (firewall) 68002800 - 68002bff
2693 * DSP subsystem 68002e00 - 68002fff
2694 * IVA (firewall) 68003000 - 680033ff
2695 * IVA 68003600 - 680037ff
2696 * GFX 68003a00 - 68003bff
2697 * CMDWR emulation 68003c00 - 68003dff
2698 * SMS 68004000 - 680041ff
2699 * OCM 68004200 - 680043ff
2700 * GPMC 68004400 - 680045ff
2701 * RAM (firewall) 68005000 - 680053ff
2702 * RAM (err login) 68005400 - 680057ff
2703 * ROM (firewall) 68005800 - 68005bff
2704 * ROM (err login) 68005c00 - 68005fff
2705 * GPMC (firewall) 68006000 - 680063ff
2706 * GPMC (err login) 68006400 - 680067ff
2707 * SMS (err login) 68006c00 - 68006fff
2708 * SMS registers 68008000 - 68008fff
2709 * SDRC registers 68009000 - 68009fff
2710 * GPMC registers 6800a000 6800afff
2711 */
2712
2713 qemu_register_reset(omap2_mpu_reset, s);
2714
2715 return s;
2716 }
AR7 emulation for QEMU