hw/arm/nrf51_soc.c

   1 /*
   2  * Nordic Semiconductor nRF51 SoC
   3  * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
   4  *
   5  * Copyright 2018 Joel Stanley <joel@jms.id.au>
   6  *
   7  * This code is licensed under the GPL version 2 or later.  See
   8  * the COPYING file in the top-level directory.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qapi/error.h"
  13 #include "hw/arm/boot.h"
  14 #include "hw/sysbus.h"
  15 #include "hw/misc/unimp.h"
  16 #include "exec/address-spaces.h"
  17 #include "sysemu/sysemu.h"
  18 #include "qemu/log.h"
  19 #include "cpu.h"
  20
  21 #include "hw/arm/nrf51.h"
  22 #include "hw/arm/nrf51_soc.h"
  23
  24 /*
  25  * The size and base is for the NRF51822 part. If other parts
  26  * are supported in the future, add a sub-class of NRF51SoC for
  27  * the specific variants
  28  */
  29 #define NRF51822_FLASH_PAGES    256
  30 #define NRF51822_SRAM_PAGES     16
  31 #define NRF51822_FLASH_SIZE     (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
  32 #define NRF51822_SRAM_SIZE      (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
  33
  34 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
  35
  36 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
  37 {
  38     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  39                   __func__, addr, size);
  40     return 1;
  41 }
  42
  43 static void clock_write(void *opaque, hwaddr addr, uint64_t data,
  44                         unsigned int size)
  45 {
  46     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  47                   __func__, addr, data, size);
  48 }
  49
  50 static const MemoryRegionOps clock_ops = {
  51     .read = clock_read,
  52     .write = clock_write
  53 };
  54
  55
  56 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
  57 {
  58     NRF51State *s = NRF51_SOC(dev_soc);
  59     MemoryRegion *mr;
  60     Error *err = NULL;
  61     uint8_t i = 0;
  62     hwaddr base_addr = 0;
  63
  64     if (!s->board_memory) {
  65         error_setg(errp, "memory property was not set");
  66         return;
  67     }
  68
  69     object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
  70             &err);
  71     if (err) {
  72         error_propagate(errp, err);
  73         return;
  74     }
  75     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  76     if (err) {
  77         error_propagate(errp, err);
  78         return;
  79     }
  80
  81     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
  82
  83     memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
  84                            &err);
  85     if (err) {
  86         error_propagate(errp, err);
  87         return;
  88     }
  89     memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
  90
  91     /* UART */
  92     object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
  93     if (err) {
  94         error_propagate(errp, err);
  95         return;
  96     }
  97     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
  98     memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
  99     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
 100                        qdev_get_gpio_in(DEVICE(&s->cpu),
 101                        BASE_TO_IRQ(NRF51_UART_BASE)));
 102
 103     /* RNG */
 104     object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
 105     if (err) {
 106         error_propagate(errp, err);
 107         return;
 108     }
 109
 110     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
 111     memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
 112     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
 113                        qdev_get_gpio_in(DEVICE(&s->cpu),
 114                        BASE_TO_IRQ(NRF51_RNG_BASE)));
 115
 116     /* UICR, FICR, NVMC, FLASH */
 117     object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
 118                              &err);
 119     if (err) {
 120         error_propagate(errp, err);
 121         return;
 122     }
 123
 124     object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
 125     if (err) {
 126         error_propagate(errp, err);
 127         return;
 128     }
 129
 130     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
 131     memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
 132     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
 133     memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
 134     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
 135     memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
 136     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
 137     memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
 138
 139     /* GPIO */
 140     object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
 141     if (err) {
 142         error_propagate(errp, err);
 143         return;
 144     }
 145
 146     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
 147     memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
 148
 149     /* Pass all GPIOs to the SOC layer so they are available to the board */
 150     qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
 151
 152     /* TIMER */
 153     for (i = 0; i < NRF51_NUM_TIMERS; i++) {
 154         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 155         if (err) {
 156             error_propagate(errp, err);
 157             return;
 158         }
 159
 160         base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
 161
 162         sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
 163         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
 164                            qdev_get_gpio_in(DEVICE(&s->cpu),
 165                                             BASE_TO_IRQ(base_addr)));
 166     }
 167
 168     /* STUB Peripherals */
 169     memory_region_init_io(&s->clock, NULL, &clock_ops, NULL,
 170                           "nrf51_soc.clock", 0x1000);
 171     memory_region_add_subregion_overlap(&s->container,
 172                                         NRF51_IOMEM_BASE, &s->clock, -1);
 173
 174     create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
 175                                 NRF51_IOMEM_SIZE);
 176     create_unimplemented_device("nrf51_soc.private",
 177                                 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
 178 }
 179
 180 static void nrf51_soc_init(Object *obj)
 181 {
 182     uint8_t i = 0;
 183
 184     NRF51State *s = NRF51_SOC(obj);
 185
 186     memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
 187
 188     sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
 189                           TYPE_ARMV7M);
 190     qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
 191                          ARM_CPU_TYPE_NAME("cortex-m0"));
 192     qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
 193
 194     sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
 195                            TYPE_NRF51_UART);
 196     object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
 197                               &error_abort);
 198
 199     sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
 200                            TYPE_NRF51_RNG);
 201
 202     sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
 203
 204     sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
 205                           TYPE_NRF51_GPIO);
 206
 207     for (i = 0; i < NRF51_NUM_TIMERS; i++) {
 208         sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
 209                               sizeof(s->timer[i]), TYPE_NRF51_TIMER);
 210
 211     }
 212 }
 213
 214 static Property nrf51_soc_properties[] = {
 215     DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
 216                      MemoryRegion *),
 217     DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
 218     DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
 219                        NRF51822_FLASH_SIZE),
 220     DEFINE_PROP_END_OF_LIST(),
 221 };
 222
 223 static void nrf51_soc_class_init(ObjectClass *klass, void *data)
 224 {
 225     DeviceClass *dc = DEVICE_CLASS(klass);
 226
 227     dc->realize = nrf51_soc_realize;
 228     dc->props = nrf51_soc_properties;
 229 }
 230
 231 static const TypeInfo nrf51_soc_info = {
 232     .name          = TYPE_NRF51_SOC,
 233     .parent        = TYPE_SYS_BUS_DEVICE,
 234     .instance_size = sizeof(NRF51State),
 235     .instance_init = nrf51_soc_init,
 236     .class_init    = nrf51_soc_class_init,
 237 };
 238
 239 static void nrf51_soc_types(void)
 240 {
 241     type_register_static(&nrf51_soc_info);
 242 }
 243 type_init(nrf51_soc_types)