target/s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef S390X_CPU_H
  24 #define S390X_CPU_H
  25
  26 #include "qemu-common.h"
  27 #include "cpu-qom.h"
  28
  29 #define TARGET_LONG_BITS 64
  30
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46 #define TARGET_INSN_START_EXTRA_WORDS 1
  47
  48 #define MMU_MODE0_SUFFIX _primary
  49 #define MMU_MODE1_SUFFIX _secondary
  50 #define MMU_MODE2_SUFFIX _home
  51
  52 #define MMU_USER_IDX 0
  53
  54 #define MAX_EXT_QUEUE 16
  55 #define MAX_IO_QUEUE 16
  56 #define MAX_MCHK_QUEUE 16
  57
  58 #define PSW_MCHK_MASK 0x0004000000000000
  59 #define PSW_IO_MASK 0x0200000000000000
  60
  61 typedef struct PSW {
  62     uint64_t mask;
  63     uint64_t addr;
  64 } PSW;
  65
  66 typedef struct ExtQueue {
  67     uint32_t code;
  68     uint32_t param;
  69     uint32_t param64;
  70 } ExtQueue;
  71
  72 typedef struct IOIntQueue {
  73     uint16_t id;
  74     uint16_t nr;
  75     uint32_t parm;
  76     uint32_t word;
  77 } IOIntQueue;
  78
  79 typedef struct MchkQueue {
  80     uint16_t type;
  81 } MchkQueue;
  82
  83 typedef struct CPUS390XState {
  84     uint64_t regs[16];     /* GP registers */
  85     /*
  86      * The floating point registers are part of the vector registers.
  87      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  88      */
  89     CPU_DoubleU vregs[32][2];  /* vector registers */
  90     uint32_t aregs[16];    /* access registers */
  91     uint8_t riccb[64];     /* runtime instrumentation control */
  92     uint64_t gscb[4];      /* guarded storage control */
  93
  94     /* Fields up to this point are not cleared by initial CPU reset */
  95     struct {} start_initial_reset_fields;
  96
  97     uint32_t fpc;          /* floating-point control register */
  98     uint32_t cc_op;
  99
 100     float_status fpu_status; /* passed to softfloat lib */
 101
 102     /* The low part of a 128-bit return, or remainder of a divide.  */
 103     uint64_t retxl;
 104
 105     PSW psw;
 106
 107     uint64_t cc_src;
 108     uint64_t cc_dst;
 109     uint64_t cc_vr;
 110
 111     uint64_t ex_value;
 112
 113     uint64_t __excp_addr;
 114     uint64_t psa;
 115
 116     uint32_t int_pgm_code;
 117     uint32_t int_pgm_ilen;
 118
 119     uint32_t int_svc_code;
 120     uint32_t int_svc_ilen;
 121
 122     uint64_t per_address;
 123     uint16_t per_perc_atmid;
 124
 125     uint64_t cregs[16]; /* control registers */
 126
 127     ExtQueue ext_queue[MAX_EXT_QUEUE];
 128     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 129     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 130
 131     int pending_int;
 132     int ext_index;
 133     int io_index[8];
 134     int mchk_index;
 135
 136     uint64_t ckc;
 137     uint64_t cputm;
 138     uint32_t todpr;
 139
 140     uint64_t pfault_token;
 141     uint64_t pfault_compare;
 142     uint64_t pfault_select;
 143
 144     uint64_t gbea;
 145     uint64_t pp;
 146
 147     /* Fields up to this point are cleared by a CPU reset */
 148     struct {} end_reset_fields;
 149
 150     CPU_COMMON
 151
 152     uint32_t cpu_num;
 153     uint64_t cpuid;
 154
 155     uint64_t tod_offset;
 156     uint64_t tod_basetime;
 157     QEMUTimer *tod_timer;
 158
 159     QEMUTimer *cpu_timer;
 160
 161     /*
 162      * The cpu state represents the logical state of a cpu. In contrast to other
 163      * architectures, there is a difference between a halt and a stop on s390.
 164      * If all cpus are either stopped (including check stop) or in the disabled
 165      * wait state, the vm can be shut down.
 166      */
 167 #define CPU_STATE_UNINITIALIZED        0x00
 168 #define CPU_STATE_STOPPED              0x01
 169 #define CPU_STATE_CHECK_STOP           0x02
 170 #define CPU_STATE_OPERATING            0x03
 171 #define CPU_STATE_LOAD                 0x04
 172     uint8_t cpu_state;
 173
 174     /* currently processed sigp order */
 175     uint8_t sigp_order;
 176
 177 } CPUS390XState;
 178
 179 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 180 {
 181     return &cs->vregs[nr][0];
 182 }
 183
 184 /**
 185  * S390CPU:
 186  * @env: #CPUS390XState.
 187  *
 188  * An S/390 CPU.
 189  */
 190 struct S390CPU {
 191     /*< private >*/
 192     CPUState parent_obj;
 193     /*< public >*/
 194
 195     CPUS390XState env;
 196     int64_t id;
 197     S390CPUModel *model;
 198     /* needed for live migration */
 199     void *irqstate;
 200     uint32_t irqstate_saved_size;
 201 };
 202
 203 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
 204 {
 205     return container_of(env, S390CPU, env);
 206 }
 207
 208 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
 209
 210 #define ENV_OFFSET offsetof(S390CPU, env)
 211
 212 #ifndef CONFIG_USER_ONLY
 213 extern const struct VMStateDescription vmstate_s390_cpu;
 214 #endif
 215
 216 void s390_cpu_do_interrupt(CPUState *cpu);
 217 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
 218 void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 219                          int flags);
 220 int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 221                               int cpuid, void *opaque);
 222
 223 hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 224 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
 225 int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 226 int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 227 void s390_cpu_gdb_init(CPUState *cs);
 228 void s390x_cpu_debug_excp_handler(CPUState *cs);
 229
 230 #include "sysemu/kvm.h"
 231
 232 /* distinguish between 24 bit and 31 bit addressing */
 233 #define HIGH_ORDER_BIT 0x80000000
 234
 235 /* Interrupt Codes */
 236 /* Program Interrupts */
 237 #define PGM_OPERATION                   0x0001
 238 #define PGM_PRIVILEGED                  0x0002
 239 #define PGM_EXECUTE                     0x0003
 240 #define PGM_PROTECTION                  0x0004
 241 #define PGM_ADDRESSING                  0x0005
 242 #define PGM_SPECIFICATION               0x0006
 243 #define PGM_DATA                        0x0007
 244 #define PGM_FIXPT_OVERFLOW              0x0008
 245 #define PGM_FIXPT_DIVIDE                0x0009
 246 #define PGM_DEC_OVERFLOW                0x000a
 247 #define PGM_DEC_DIVIDE                  0x000b
 248 #define PGM_HFP_EXP_OVERFLOW            0x000c
 249 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 250 #define PGM_HFP_SIGNIFICANCE            0x000e
 251 #define PGM_HFP_DIVIDE                  0x000f
 252 #define PGM_SEGMENT_TRANS               0x0010
 253 #define PGM_PAGE_TRANS                  0x0011
 254 #define PGM_TRANS_SPEC                  0x0012
 255 #define PGM_SPECIAL_OP                  0x0013
 256 #define PGM_OPERAND                     0x0015
 257 #define PGM_TRACE_TABLE                 0x0016
 258 #define PGM_SPACE_SWITCH                0x001c
 259 #define PGM_HFP_SQRT                    0x001d
 260 #define PGM_PC_TRANS_SPEC               0x001f
 261 #define PGM_AFX_TRANS                   0x0020
 262 #define PGM_ASX_TRANS                   0x0021
 263 #define PGM_LX_TRANS                    0x0022
 264 #define PGM_EX_TRANS                    0x0023
 265 #define PGM_PRIM_AUTH                   0x0024
 266 #define PGM_SEC_AUTH                    0x0025
 267 #define PGM_ALET_SPEC                   0x0028
 268 #define PGM_ALEN_SPEC                   0x0029
 269 #define PGM_ALE_SEQ                     0x002a
 270 #define PGM_ASTE_VALID                  0x002b
 271 #define PGM_ASTE_SEQ                    0x002c
 272 #define PGM_EXT_AUTH                    0x002d
 273 #define PGM_STACK_FULL                  0x0030
 274 #define PGM_STACK_EMPTY                 0x0031
 275 #define PGM_STACK_SPEC                  0x0032
 276 #define PGM_STACK_TYPE                  0x0033
 277 #define PGM_STACK_OP                    0x0034
 278 #define PGM_ASCE_TYPE                   0x0038
 279 #define PGM_REG_FIRST_TRANS             0x0039
 280 #define PGM_REG_SEC_TRANS               0x003a
 281 #define PGM_REG_THIRD_TRANS             0x003b
 282 #define PGM_MONITOR                     0x0040
 283 #define PGM_PER                         0x0080
 284 #define PGM_CRYPTO                      0x0119
 285
 286 /* External Interrupts */
 287 #define EXT_INTERRUPT_KEY               0x0040
 288 #define EXT_CLOCK_COMP                  0x1004
 289 #define EXT_CPU_TIMER                   0x1005
 290 #define EXT_MALFUNCTION                 0x1200
 291 #define EXT_EMERGENCY                   0x1201
 292 #define EXT_EXTERNAL_CALL               0x1202
 293 #define EXT_ETR                         0x1406
 294 #define EXT_SERVICE                     0x2401
 295 #define EXT_VIRTIO                      0x2603
 296
 297 /* PSW defines */
 298 #undef PSW_MASK_PER
 299 #undef PSW_MASK_DAT
 300 #undef PSW_MASK_IO
 301 #undef PSW_MASK_EXT
 302 #undef PSW_MASK_KEY
 303 #undef PSW_SHIFT_KEY
 304 #undef PSW_MASK_MCHECK
 305 #undef PSW_MASK_WAIT
 306 #undef PSW_MASK_PSTATE
 307 #undef PSW_MASK_ASC
 308 #undef PSW_SHIFT_ASC
 309 #undef PSW_MASK_CC
 310 #undef PSW_MASK_PM
 311 #undef PSW_MASK_64
 312 #undef PSW_MASK_32
 313 #undef PSW_MASK_ESA_ADDR
 314
 315 #define PSW_MASK_PER            0x4000000000000000ULL
 316 #define PSW_MASK_DAT            0x0400000000000000ULL
 317 #define PSW_MASK_IO             0x0200000000000000ULL
 318 #define PSW_MASK_EXT            0x0100000000000000ULL
 319 #define PSW_MASK_KEY            0x00F0000000000000ULL
 320 #define PSW_SHIFT_KEY           52
 321 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 322 #define PSW_MASK_WAIT           0x0002000000000000ULL
 323 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 324 #define PSW_MASK_ASC            0x0000C00000000000ULL
 325 #define PSW_SHIFT_ASC           46
 326 #define PSW_MASK_CC             0x0000300000000000ULL
 327 #define PSW_MASK_PM             0x00000F0000000000ULL
 328 #define PSW_MASK_64             0x0000000100000000ULL
 329 #define PSW_MASK_32             0x0000000080000000ULL
 330 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 331
 332 #undef PSW_ASC_PRIMARY
 333 #undef PSW_ASC_ACCREG
 334 #undef PSW_ASC_SECONDARY
 335 #undef PSW_ASC_HOME
 336
 337 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 338 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 339 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 340 #define PSW_ASC_HOME            0x0000C00000000000ULL
 341
 342 /* the address space values shifted */
 343 #define AS_PRIMARY              0
 344 #define AS_ACCREG               1
 345 #define AS_SECONDARY            2
 346 #define AS_HOME                 3
 347
 348 /* tb flags */
 349
 350 #define FLAG_MASK_PSW_SHIFT     31
 351 #define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 352 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 353 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 354 #define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 355 #define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 356 #define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_PSTATE \
 357                                 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 358
 359 /* Control register 0 bits */
 360 #define CR0_LOWPROT             0x0000000010000000ULL
 361 #define CR0_SECONDARY           0x0000000004000000ULL
 362 #define CR0_EDAT                0x0000000000800000ULL
 363
 364 /* MMU */
 365 #define MMU_PRIMARY_IDX         0
 366 #define MMU_SECONDARY_IDX       1
 367 #define MMU_HOME_IDX            2
 368
 369 static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)
 370 {
 371     uint16_t pkm = env->cregs[3] >> 16;
 372
 373     if (env->psw.mask & PSW_MASK_PSTATE) {
 374         /* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */
 375         return pkm & (0x80 >> psw_key);
 376     }
 377     return true;
 378 }
 379
 380 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 381 {
 382     switch (env->psw.mask & PSW_MASK_ASC) {
 383     case PSW_ASC_PRIMARY:
 384         return MMU_PRIMARY_IDX;
 385     case PSW_ASC_SECONDARY:
 386         return MMU_SECONDARY_IDX;
 387     case PSW_ASC_HOME:
 388         return MMU_HOME_IDX;
 389     case PSW_ASC_ACCREG:
 390         /* Fallthrough: access register mode is not yet supported */
 391     default:
 392         abort();
 393     }
 394 }
 395
 396 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 397                                         target_ulong *cs_base, uint32_t *flags)
 398 {
 399     *pc = env->psw.addr;
 400     *cs_base = env->ex_value;
 401     *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 402 }
 403
 404 #define MAX_ILEN 6
 405
 406 /* While the PoO talks about ILC (a number between 1-3) what is actually
 407    stored in LowCore is shifted left one bit (an even between 2-6).  As
 408    this is the actual length of the insn and therefore more useful, that
 409    is what we want to pass around and manipulate.  To make sure that we
 410    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 411 static inline int get_ilen(uint8_t opc)
 412 {
 413     switch (opc >> 6) {
 414     case 0:
 415         return 2;
 416     case 1:
 417     case 2:
 418         return 4;
 419     default:
 420         return 6;
 421     }
 422 }
 423
 424 /* PER bits from control register 9 */
 425 #define PER_CR9_EVENT_BRANCH           0x80000000
 426 #define PER_CR9_EVENT_IFETCH           0x40000000
 427 #define PER_CR9_EVENT_STORE            0x20000000
 428 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 429 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 430 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 431 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 432
 433 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 434 #define PER_CODE_EVENT_BRANCH          0x8000
 435 #define PER_CODE_EVENT_IFETCH          0x4000
 436 #define PER_CODE_EVENT_STORE           0x2000
 437 #define PER_CODE_EVENT_STORE_REAL      0x0800
 438 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 439
 440 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
 441    entry when a PER exception is triggered.  */
 442 static inline uint8_t get_per_atmid(CPUS390XState *env)
 443 {
 444     return ((env->psw.mask & PSW_MASK_64) ?      (1 << 7) : 0) |
 445            (                                     (1 << 6)    ) |
 446            ((env->psw.mask & PSW_MASK_32) ?      (1 << 5) : 0) |
 447            ((env->psw.mask & PSW_MASK_DAT)?      (1 << 4) : 0) |
 448            ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
 449            ((env->psw.mask & PSW_ASC_ACCREG)?    (1 << 2) : 0);
 450 }
 451
 452 /* Check if an address is within the PER starting address and the PER
 453    ending address.  The address range might loop.  */
 454 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
 455 {
 456     if (env->cregs[10] <= env->cregs[11]) {
 457         return env->cregs[10] <= addr && addr <= env->cregs[11];
 458     } else {
 459         return env->cregs[10] <= addr || addr <= env->cregs[11];
 460     }
 461 }
 462
 463 S390CPU *cpu_s390x_init(const char *cpu_model);
 464 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
 465 S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
 466 void s390x_translate_init(void);
 467
 468 /* you can call this signal handler from your SIGBUS and SIGSEGV
 469    signal handlers to inform the virtual CPU of exceptions. non zero
 470    is returned if the signal was handled by the virtual CPU.  */
 471 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 472                            void *puc);
 473 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 474                               int mmu_idx);
 475
 476
 477 #ifndef CONFIG_USER_ONLY
 478 void do_restart_interrupt(CPUS390XState *env);
 479 void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 480                                    MMUAccessType access_type,
 481                                    int mmu_idx, uintptr_t retaddr);
 482
 483 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 484                                        uint8_t *ar)
 485 {
 486     hwaddr addr = 0;
 487     uint8_t reg;
 488
 489     reg = ipb >> 28;
 490     if (reg > 0) {
 491         addr = env->regs[reg];
 492     }
 493     addr += (ipb >> 16) & 0xfff;
 494     if (ar) {
 495         *ar = reg;
 496     }
 497
 498     return addr;
 499 }
 500
 501 /* Base/displacement are at the same locations. */
 502 #define decode_basedisp_rs decode_basedisp_s
 503
 504 /* helper functions for run_on_cpu() */
 505 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
 506 {
 507     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 508
 509     scc->cpu_reset(cs);
 510 }
 511 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
 512 {
 513     cpu_reset(cs);
 514 }
 515
 516 void s390x_tod_timer(void *opaque);
 517 void s390x_cpu_timer(void *opaque);
 518
 519 int s390_virtio_hypercall(CPUS390XState *env);
 520
 521 #ifdef CONFIG_KVM
 522 void kvm_s390_service_interrupt(uint32_t parm);
 523 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 524 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 525 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 526 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 527 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 528                     int len, bool is_write);
 529 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 530 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 531 #else
 532 static inline void kvm_s390_service_interrupt(uint32_t parm)
 533 {
 534 }
 535 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 536 {
 537     return -ENOSYS;
 538 }
 539 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 540 {
 541     return -ENOSYS;
 542 }
 543 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 544                                   void *hostbuf, int len, bool is_write)
 545 {
 546     return -ENOSYS;
 547 }
 548 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 549                                              uint64_t te_code)
 550 {
 551 }
 552 #endif
 553
 554 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 555 {
 556     if (kvm_enabled()) {
 557         return kvm_s390_get_clock(tod_high, tod_low);
 558     }
 559     /* Fixme TCG */
 560     *tod_high = 0;
 561     *tod_low = 0;
 562     return 0;
 563 }
 564
 565 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 566 {
 567     if (kvm_enabled()) {
 568         return kvm_s390_set_clock(tod_high, tod_low);
 569     }
 570     /* Fixme TCG */
 571     return 0;
 572 }
 573
 574 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 575 unsigned int s390_cpu_halt(S390CPU *cpu);
 576 void s390_cpu_unhalt(S390CPU *cpu);
 577 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 578 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 579 {
 580     return cpu->env.cpu_state;
 581 }
 582
 583 void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 584                     uint64_t param64);
 585
 586 /* ioinst.c */
 587 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
 588 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
 589 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
 590 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 591 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 592 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
 593 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 594 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 595 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
 596 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
 597 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
 598                         uint32_t ipb);
 599 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
 600 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
 601 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
 602
 603 /* service interrupts are floating therefore we must not pass an cpustate */
 604 void s390_sclp_extint(uint32_t parm);
 605
 606 #else
 607 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 608 {
 609     return 0;
 610 }
 611
 612 static inline void s390_cpu_unhalt(S390CPU *cpu)
 613 {
 614 }
 615
 616 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 617 {
 618     return 0;
 619 }
 620 #endif
 621
 622 extern void subsystem_reset(void);
 623
 624 #define cpu_init(model) CPU(cpu_s390x_init(model))
 625 #define cpu_signal_handler cpu_s390x_signal_handler
 626
 627 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 628 #define cpu_list s390_cpu_list
 629 void s390_cpu_model_register_props(Object *obj);
 630 void s390_cpu_model_class_register_props(ObjectClass *oc);
 631 void s390_realize_cpu_model(CPUState *cs, Error **errp);
 632 ObjectClass *s390_cpu_class_by_name(const char *name);
 633 const char *s390_default_cpu_model_name(void);
 634
 635 #define EXCP_EXT 1 /* external interrupt */
 636 #define EXCP_SVC 2 /* supervisor call (syscall) */
 637 #define EXCP_PGM 3 /* program interruption */
 638 #define EXCP_IO  7 /* I/O interrupt */
 639 #define EXCP_MCHK 8 /* machine check */
 640
 641 #define INTERRUPT_EXT        (1 << 0)
 642 #define INTERRUPT_TOD        (1 << 1)
 643 #define INTERRUPT_CPUTIMER   (1 << 2)
 644 #define INTERRUPT_IO         (1 << 3)
 645 #define INTERRUPT_MCHK       (1 << 4)
 646
 647 /* Program Status Word.  */
 648 #define S390_PSWM_REGNUM 0
 649 #define S390_PSWA_REGNUM 1
 650 /* General Purpose Registers.  */
 651 #define S390_R0_REGNUM 2
 652 #define S390_R1_REGNUM 3
 653 #define S390_R2_REGNUM 4
 654 #define S390_R3_REGNUM 5
 655 #define S390_R4_REGNUM 6
 656 #define S390_R5_REGNUM 7
 657 #define S390_R6_REGNUM 8
 658 #define S390_R7_REGNUM 9
 659 #define S390_R8_REGNUM 10
 660 #define S390_R9_REGNUM 11
 661 #define S390_R10_REGNUM 12
 662 #define S390_R11_REGNUM 13
 663 #define S390_R12_REGNUM 14
 664 #define S390_R13_REGNUM 15
 665 #define S390_R14_REGNUM 16
 666 #define S390_R15_REGNUM 17
 667 /* Total Core Registers. */
 668 #define S390_NUM_CORE_REGS 18
 669
 670 /* CC optimization */
 671
 672 /* Instead of computing the condition codes after each x86 instruction,
 673  * QEMU just stores the result (called CC_DST), the type of operation
 674  * (called CC_OP) and whatever operands are needed (CC_SRC and possibly
 675  * CC_VR). When the condition codes are needed, the condition codes can
 676  * be calculated using this information. Condition codes are not generated
 677  * if they are only needed for conditional branches.
 678  */
 679 enum cc_op {
 680     CC_OP_CONST0 = 0,           /* CC is 0 */
 681     CC_OP_CONST1,               /* CC is 1 */
 682     CC_OP_CONST2,               /* CC is 2 */
 683     CC_OP_CONST3,               /* CC is 3 */
 684
 685     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 686     CC_OP_STATIC,               /* CC value is env->cc_op */
 687
 688     CC_OP_NZ,                   /* env->cc_dst != 0 */
 689     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 690     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 691     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 692     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 693     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 694     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 695
 696     CC_OP_ADD_64,               /* overflow on add (64bit) */
 697     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 698     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 699     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 700     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 701     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 702     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 703     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 704
 705     CC_OP_ADD_32,               /* overflow on add (32bit) */
 706     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 707     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 708     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 709     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 710     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 711     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 712     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 713
 714     CC_OP_COMP_32,              /* complement */
 715     CC_OP_COMP_64,              /* complement */
 716
 717     CC_OP_TM_32,                /* test under mask (32bit) */
 718     CC_OP_TM_64,                /* test under mask (64bit) */
 719
 720     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 721     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 722     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 723
 724     CC_OP_ICM,                  /* insert characters under mask */
 725     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 726     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 727     CC_OP_FLOGR,                /* find leftmost one */
 728     CC_OP_MAX
 729 };
 730
 731 const char *cc_name(enum cc_op cc_op);
 732
 733 static inline void setcc(S390CPU *cpu, uint64_t cc)
 734 {
 735     CPUS390XState *env = &cpu->env;
 736
 737     env->psw.mask &= ~(3ull << 44);
 738     env->psw.mask |= (cc & 3) << 44;
 739     env->cc_op = cc;
 740 }
 741
 742 #ifndef CONFIG_USER_ONLY
 743
 744 typedef struct LowCore
 745 {
 746     /* prefix area: defined by architecture */
 747     uint32_t        ccw1[2];                  /* 0x000 */
 748     uint32_t        ccw2[4];                  /* 0x008 */
 749     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 750     uint32_t        ext_params;               /* 0x080 */
 751     uint16_t        cpu_addr;                 /* 0x084 */
 752     uint16_t        ext_int_code;             /* 0x086 */
 753     uint16_t        svc_ilen;                 /* 0x088 */
 754     uint16_t        svc_code;                 /* 0x08a */
 755     uint16_t        pgm_ilen;                 /* 0x08c */
 756     uint16_t        pgm_code;                 /* 0x08e */
 757     uint32_t        data_exc_code;            /* 0x090 */
 758     uint16_t        mon_class_num;            /* 0x094 */
 759     uint16_t        per_perc_atmid;           /* 0x096 */
 760     uint64_t        per_address;              /* 0x098 */
 761     uint8_t         exc_access_id;            /* 0x0a0 */
 762     uint8_t         per_access_id;            /* 0x0a1 */
 763     uint8_t         op_access_id;             /* 0x0a2 */
 764     uint8_t         ar_access_id;             /* 0x0a3 */
 765     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 766     uint64_t        trans_exc_code;           /* 0x0a8 */
 767     uint64_t        monitor_code;             /* 0x0b0 */
 768     uint16_t        subchannel_id;            /* 0x0b8 */
 769     uint16_t        subchannel_nr;            /* 0x0ba */
 770     uint32_t        io_int_parm;              /* 0x0bc */
 771     uint32_t        io_int_word;              /* 0x0c0 */
 772     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 773     uint32_t        stfl_fac_list;            /* 0x0c8 */
 774     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 775     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 776     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 777     uint32_t        external_damage_code;     /* 0x0f4 */
 778     uint64_t        failing_storage_address;  /* 0x0f8 */
 779     uint8_t         pad6[0x110-0x100];        /* 0x100 */
 780     uint64_t        per_breaking_event_addr;  /* 0x110 */
 781     uint8_t         pad7[0x120-0x118];        /* 0x118 */
 782     PSW             restart_old_psw;          /* 0x120 */
 783     PSW             external_old_psw;         /* 0x130 */
 784     PSW             svc_old_psw;              /* 0x140 */
 785     PSW             program_old_psw;          /* 0x150 */
 786     PSW             mcck_old_psw;             /* 0x160 */
 787     PSW             io_old_psw;               /* 0x170 */
 788     uint8_t         pad8[0x1a0-0x180];        /* 0x180 */
 789     PSW             restart_new_psw;          /* 0x1a0 */
 790     PSW             external_new_psw;         /* 0x1b0 */
 791     PSW             svc_new_psw;              /* 0x1c0 */
 792     PSW             program_new_psw;          /* 0x1d0 */
 793     PSW             mcck_new_psw;             /* 0x1e0 */
 794     PSW             io_new_psw;               /* 0x1f0 */
 795     PSW             return_psw;               /* 0x200 */
 796     uint8_t         irb[64];                  /* 0x210 */
 797     uint64_t        sync_enter_timer;         /* 0x250 */
 798     uint64_t        async_enter_timer;        /* 0x258 */
 799     uint64_t        exit_timer;               /* 0x260 */
 800     uint64_t        last_update_timer;        /* 0x268 */
 801     uint64_t        user_timer;               /* 0x270 */
 802     uint64_t        system_timer;             /* 0x278 */
 803     uint64_t        last_update_clock;        /* 0x280 */
 804     uint64_t        steal_clock;              /* 0x288 */
 805     PSW             return_mcck_psw;          /* 0x290 */
 806     uint8_t         pad9[0xc00-0x2a0];        /* 0x2a0 */
 807     /* System info area */
 808     uint64_t        save_area[16];            /* 0xc00 */
 809     uint8_t         pad10[0xd40-0xc80];       /* 0xc80 */
 810     uint64_t        kernel_stack;             /* 0xd40 */
 811     uint64_t        thread_info;              /* 0xd48 */
 812     uint64_t        async_stack;              /* 0xd50 */
 813     uint64_t        kernel_asce;              /* 0xd58 */
 814     uint64_t        user_asce;                /* 0xd60 */
 815     uint64_t        panic_stack;              /* 0xd68 */
 816     uint64_t        user_exec_asce;           /* 0xd70 */
 817     uint8_t         pad11[0xdc0-0xd78];       /* 0xd78 */
 818
 819     /* SMP info area: defined by DJB */
 820     uint64_t        clock_comparator;         /* 0xdc0 */
 821     uint64_t        ext_call_fast;            /* 0xdc8 */
 822     uint64_t        percpu_offset;            /* 0xdd0 */
 823     uint64_t        current_task;             /* 0xdd8 */
 824     uint32_t        softirq_pending;          /* 0xde0 */
 825     uint32_t        pad_0x0de4;               /* 0xde4 */
 826     uint64_t        int_clock;                /* 0xde8 */
 827     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 828
 829     /* 0xe00 is used as indicator for dump tools */
 830     /* whether the kernel died with panic() or not */
 831     uint32_t        panic_magic;              /* 0xe00 */
 832
 833     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 834
 835     /* 64 bit extparam used for pfault, diag 250 etc  */
 836     uint64_t        ext_params2;               /* 0x11B8 */
 837
 838     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 839
 840     /* System info area */
 841
 842     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 843     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 844     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 845     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 846     uint32_t        prefixreg_save_area;       /* 0x1318 */
 847     uint32_t        fpt_creg_save_area;        /* 0x131c */
 848     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 849     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 850     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 851     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 852     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 853     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 854     uint64_t        cregs_save_area[16];       /* 0x1380 */
 855
 856     /* align to the top of the prefix area */
 857
 858     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 859 } QEMU_PACKED LowCore;
 860
 861 LowCore *cpu_map_lowcore(CPUS390XState *env);
 862 void cpu_unmap_lowcore(LowCore *lowcore);
 863
 864 #endif
 865
 866 /* STSI */
 867 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 868 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 869 #define STSI_LEVEL_1            0x0000000010000000ULL
 870 #define STSI_LEVEL_2            0x0000000020000000ULL
 871 #define STSI_LEVEL_3            0x0000000030000000ULL
 872 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 873 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 874 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 875 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 876
 877 /* Basic Machine Configuration */
 878 struct sysib_111 {
 879     uint32_t res1[8];
 880     uint8_t  manuf[16];
 881     uint8_t  type[4];
 882     uint8_t  res2[12];
 883     uint8_t  model[16];
 884     uint8_t  sequence[16];
 885     uint8_t  plant[4];
 886     uint8_t  res3[156];
 887 };
 888
 889 /* Basic Machine CPU */
 890 struct sysib_121 {
 891     uint32_t res1[80];
 892     uint8_t  sequence[16];
 893     uint8_t  plant[4];
 894     uint8_t  res2[2];
 895     uint16_t cpu_addr;
 896     uint8_t  res3[152];
 897 };
 898
 899 /* Basic Machine CPUs */
 900 struct sysib_122 {
 901     uint8_t res1[32];
 902     uint32_t capability;
 903     uint16_t total_cpus;
 904     uint16_t active_cpus;
 905     uint16_t standby_cpus;
 906     uint16_t reserved_cpus;
 907     uint16_t adjustments[2026];
 908 };
 909
 910 /* LPAR CPU */
 911 struct sysib_221 {
 912     uint32_t res1[80];
 913     uint8_t  sequence[16];
 914     uint8_t  plant[4];
 915     uint16_t cpu_id;
 916     uint16_t cpu_addr;
 917     uint8_t  res3[152];
 918 };
 919
 920 /* LPAR CPUs */
 921 struct sysib_222 {
 922     uint32_t res1[32];
 923     uint16_t lpar_num;
 924     uint8_t  res2;
 925     uint8_t  lcpuc;
 926     uint16_t total_cpus;
 927     uint16_t conf_cpus;
 928     uint16_t standby_cpus;
 929     uint16_t reserved_cpus;
 930     uint8_t  name[8];
 931     uint32_t caf;
 932     uint8_t  res3[16];
 933     uint16_t dedicated_cpus;
 934     uint16_t shared_cpus;
 935     uint8_t  res4[180];
 936 };
 937
 938 /* VM CPUs */
 939 struct sysib_322 {
 940     uint8_t  res1[31];
 941     uint8_t  count;
 942     struct {
 943         uint8_t  res2[4];
 944         uint16_t total_cpus;
 945         uint16_t conf_cpus;
 946         uint16_t standby_cpus;
 947         uint16_t reserved_cpus;
 948         uint8_t  name[8];
 949         uint32_t caf;
 950         uint8_t  cpi[16];
 951         uint8_t res5[3];
 952         uint8_t ext_name_encoding;
 953         uint32_t res3;
 954         uint8_t uuid[16];
 955     } vm[8];
 956     uint8_t res4[1504];
 957     uint8_t ext_names[8][256];
 958 };
 959
 960 /* MMU defines */
 961 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 962 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 963 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 964 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 965 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 966 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 967 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 968 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 969 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 970 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 971 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 972 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 973
 974 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 975 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 976 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 977 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 978 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 979 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 980 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 981 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 982 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 983
 984 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 985 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 986 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 987 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 988
 989 #define VADDR_PX                0xff000   /* page index bits                  */
 990
 991 #define _PAGE_RO        0x200            /* HW read-only bit  */
 992 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 993 #define _PAGE_RES0      0x800            /* bit must be zero  */
 994
 995 #define SK_C                    (0x1 << 1)
 996 #define SK_R                    (0x1 << 2)
 997 #define SK_F                    (0x1 << 3)
 998 #define SK_ACC_MASK             (0xf << 4)
 999
1000 /* SIGP order codes */
1001 #define SIGP_SENSE             0x01
1002 #define SIGP_EXTERNAL_CALL     0x02
1003 #define SIGP_EMERGENCY         0x03
1004 #define SIGP_START             0x04
1005 #define SIGP_STOP              0x05
1006 #define SIGP_RESTART           0x06
1007 #define SIGP_STOP_STORE_STATUS 0x09
1008 #define SIGP_INITIAL_CPU_RESET 0x0b
1009 #define SIGP_CPU_RESET         0x0c
1010 #define SIGP_SET_PREFIX        0x0d
1011 #define SIGP_STORE_STATUS_ADDR 0x0e
1012 #define SIGP_SET_ARCH          0x12
1013 #define SIGP_STORE_ADTL_STATUS 0x17
1014
1015 /* SIGP condition codes */
1016 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1017 #define SIGP_CC_STATUS_STORED       1
1018 #define SIGP_CC_BUSY                2
1019 #define SIGP_CC_NOT_OPERATIONAL     3
1020
1021 /* SIGP status bits */
1022 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
1023 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
1024 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1025 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
1026 #define SIGP_STAT_STOPPED           0x00000040UL
1027 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
1028 #define SIGP_STAT_CHECK_STOP        0x00000010UL
1029 #define SIGP_STAT_INOPERATIVE       0x00000004UL
1030 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
1031 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
1032
1033 /* SIGP SET ARCHITECTURE modes */
1034 #define SIGP_MODE_ESA_S390 0
1035 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1036 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1037
1038 /* SIGP order code mask corresponding to bit positions 56-63 */
1039 #define SIGP_ORDER_MASK 0x000000ff
1040
1041 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1042 uint64_t get_psw_mask(CPUS390XState *env);
1043 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);
1044 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1045                   target_ulong *raddr, int *flags, bool exc);
1046 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1047 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1048                  uint64_t vr);
1049 void s390_cpu_recompute_watchpoints(CPUState *cs);
1050
1051 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1052                          int len, bool is_write);
1053
1054 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
1055         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1056 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
1057         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1058 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
1059         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1060
1061 /* The value of the TOD clock for 1.1.1970. */
1062 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1063
1064 /* Converts ns to s390's clock format */
1065 static inline uint64_t time2tod(uint64_t ns) {
1066     return (ns << 9) / 125;
1067 }
1068
1069 /* Converts s390's clock format to ns */
1070 static inline uint64_t tod2time(uint64_t t) {
1071     return (t * 125) >> 9;
1072 }
1073
1074 /* from s390-virtio-ccw */
1075 #define MEM_SECTION_SIZE             0x10000000UL
1076 #define MAX_AVAIL_SLOTS              32
1077
1078 /* fpu_helper.c */
1079 uint32_t set_cc_nz_f32(float32 v);
1080 uint32_t set_cc_nz_f64(float64 v);
1081 uint32_t set_cc_nz_f128(float128 v);
1082
1083 /* misc_helper.c */
1084 #ifndef CONFIG_USER_ONLY
1085 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1086 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1087 #endif
1088 /* automatically detect the instruction length */
1089 #define ILEN_AUTO                   0xff
1090 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1091 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
1092 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1093                                      uintptr_t retaddr);
1094
1095 #ifdef CONFIG_KVM
1096 void kvm_s390_program_interrupt(S390CPU *cpu, uint16_t code);
1097 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1098                            uint16_t subchannel_nr, uint32_t io_int_parm,
1099                            uint32_t io_int_word);
1100 void kvm_s390_crw_mchk(void);
1101 void kvm_s390_enable_css_support(S390CPU *cpu);
1102 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1103                                     int vq, bool assign);
1104 int kvm_s390_cpu_restart(S390CPU *cpu);
1105 int kvm_s390_get_memslot_count(void);
1106 int kvm_s390_cmma_active(void);
1107 void kvm_s390_cmma_reset(void);
1108 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1109 void kvm_s390_reset_vcpu(S390CPU *cpu);
1110 int kvm_s390_set_mem_limit(uint64_t new_limit, uint64_t *hw_limit);
1111 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1112 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1113 int kvm_s390_get_ri(void);
1114 int kvm_s390_get_gs(void);
1115 void kvm_s390_crypto_reset(void);
1116 #else
1117 static inline void kvm_s390_program_interrupt(S390CPU *cpu, uint16_t code)
1118 {
1119 }
1120 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1121                                         uint16_t subchannel_nr,
1122                                         uint32_t io_int_parm,
1123                                         uint32_t io_int_word)
1124 {
1125 }
1126 static inline void kvm_s390_crw_mchk(void)
1127 {
1128 }
1129 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1130 {
1131 }
1132 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1133                                                   uint32_t sch, int vq,
1134                                                   bool assign)
1135 {
1136     return -ENOSYS;
1137 }
1138 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1139 {
1140     return -ENOSYS;
1141 }
1142 static inline void kvm_s390_cmma_reset(void)
1143 {
1144 }
1145 static inline int kvm_s390_get_memslot_count(void)
1146 {
1147   return MAX_AVAIL_SLOTS;
1148 }
1149 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1150 {
1151     return -ENOSYS;
1152 }
1153 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1154 {
1155 }
1156 static inline int kvm_s390_set_mem_limit(uint64_t new_limit, uint64_t *hw_limit)
1157 {
1158     return 0;
1159 }
1160 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1161 {
1162 }
1163 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1164 {
1165     return 0;
1166 }
1167 static inline int kvm_s390_get_ri(void)
1168 {
1169     return 0;
1170 }
1171 static inline int kvm_s390_get_gs(void)
1172 {
1173     return 0;
1174 }
1175 static inline void kvm_s390_crypto_reset(void)
1176 {
1177 }
1178 #endif
1179
1180 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1181 {
1182     if (kvm_enabled()) {
1183         return kvm_s390_set_mem_limit(new_limit, hw_limit);
1184     }
1185     return 0;
1186 }
1187
1188 static inline void s390_cmma_reset(void)
1189 {
1190     if (kvm_enabled()) {
1191         kvm_s390_cmma_reset();
1192     }
1193 }
1194
1195 static inline int s390_cpu_restart(S390CPU *cpu)
1196 {
1197     if (kvm_enabled()) {
1198         return kvm_s390_cpu_restart(cpu);
1199     }
1200     return -ENOSYS;
1201 }
1202
1203 static inline int s390_get_memslot_count(void)
1204 {
1205     if (kvm_enabled()) {
1206         return kvm_s390_get_memslot_count();
1207     } else {
1208         return MAX_AVAIL_SLOTS;
1209     }
1210 }
1211
1212 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1213                        uint32_t io_int_parm, uint32_t io_int_word);
1214 void s390_crw_mchk(void);
1215
1216 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1217                                               uint32_t sch_id, int vq,
1218                                               bool assign)
1219 {
1220     if (kvm_enabled()) {
1221         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1222     } else {
1223         return 0;
1224     }
1225 }
1226
1227 static inline void s390_crypto_reset(void)
1228 {
1229     if (kvm_enabled()) {
1230         kvm_s390_crypto_reset();
1231     }
1232 }
1233
1234 static inline bool s390_get_squash_mcss(void)
1235 {
1236     if (object_property_get_bool(OBJECT(qdev_get_machine()), "s390-squash-mcss",
1237                                  NULL)) {
1238         return true;
1239     }
1240
1241     return false;
1242 }
1243
1244 /* machine check interruption code */
1245
1246 /* subclasses */
1247 #define MCIC_SC_SD 0x8000000000000000ULL
1248 #define MCIC_SC_PD 0x4000000000000000ULL
1249 #define MCIC_SC_SR 0x2000000000000000ULL
1250 #define MCIC_SC_CD 0x0800000000000000ULL
1251 #define MCIC_SC_ED 0x0400000000000000ULL
1252 #define MCIC_SC_DG 0x0100000000000000ULL
1253 #define MCIC_SC_W  0x0080000000000000ULL
1254 #define MCIC_SC_CP 0x0040000000000000ULL
1255 #define MCIC_SC_SP 0x0020000000000000ULL
1256 #define MCIC_SC_CK 0x0010000000000000ULL
1257
1258 /* subclass modifiers */
1259 #define MCIC_SCM_B  0x0002000000000000ULL
1260 #define MCIC_SCM_DA 0x0000000020000000ULL
1261 #define MCIC_SCM_AP 0x0000000000080000ULL
1262
1263 /* storage errors */
1264 #define MCIC_SE_SE 0x0000800000000000ULL
1265 #define MCIC_SE_SC 0x0000400000000000ULL
1266 #define MCIC_SE_KE 0x0000200000000000ULL
1267 #define MCIC_SE_DS 0x0000100000000000ULL
1268 #define MCIC_SE_IE 0x0000000080000000ULL
1269
1270 /* validity bits */
1271 #define MCIC_VB_WP 0x0000080000000000ULL
1272 #define MCIC_VB_MS 0x0000040000000000ULL
1273 #define MCIC_VB_PM 0x0000020000000000ULL
1274 #define MCIC_VB_IA 0x0000010000000000ULL
1275 #define MCIC_VB_FA 0x0000008000000000ULL
1276 #define MCIC_VB_VR 0x0000004000000000ULL
1277 #define MCIC_VB_EC 0x0000002000000000ULL
1278 #define MCIC_VB_FP 0x0000001000000000ULL
1279 #define MCIC_VB_GR 0x0000000800000000ULL
1280 #define MCIC_VB_CR 0x0000000400000000ULL
1281 #define MCIC_VB_ST 0x0000000100000000ULL
1282 #define MCIC_VB_AR 0x0000000040000000ULL
1283 #define MCIC_VB_GS 0x0000000008000000ULL
1284 #define MCIC_VB_PR 0x0000000000200000ULL
1285 #define MCIC_VB_FC 0x0000000000100000ULL
1286 #define MCIC_VB_CT 0x0000000000020000ULL
1287 #define MCIC_VB_CC 0x0000000000010000ULL
1288
1289 #endif