hw/ppc/spapr_irq.c

   1 /*
   2  * QEMU PowerPC sPAPR IRQ interface
   3  *
   4  * Copyright (c) 2018, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "qapi/error.h"
  14 #include "hw/ppc/spapr.h"
  15 #include "hw/ppc/spapr_xive.h"
  16 #include "hw/ppc/xics.h"
  17 #include "sysemu/kvm.h"
  18
  19 #include "trace.h"
  20
  21 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
  22 {
  23     spapr->irq_map_nr = nr_msis;
  24     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
  25 }
  26
  27 int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
  28                         Error **errp)
  29 {
  30     int irq;
  31
  32     /*
  33      * The 'align_mask' parameter of bitmap_find_next_zero_area()
  34      * should be one less than a power of 2; 0 means no
  35      * alignment. Adapt the 'align' value of the former allocator
  36      * to fit the requirements of bitmap_find_next_zero_area()
  37      */
  38     align -= 1;
  39
  40     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
  41                                      align);
  42     if (irq == spapr->irq_map_nr) {
  43         error_setg(errp, "can't find a free %d-IRQ block", num);
  44         return -1;
  45     }
  46
  47     bitmap_set(spapr->irq_map, irq, num);
  48
  49     return irq + SPAPR_IRQ_MSI;
  50 }
  51
  52 void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
  53 {
  54     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
  55 }
  56
  57 void spapr_irq_msi_reset(sPAPRMachineState *spapr)
  58 {
  59     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
  60 }
  61
  62
  63 /*
  64  * XICS IRQ backend.
  65  */
  66
  67 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
  68                                   const char *type_ics,
  69                                   int nr_irqs, Error **errp)
  70 {
  71     Error *local_err = NULL;
  72     Object *obj;
  73
  74     obj = object_new(type_ics);
  75     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
  76     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
  77                                    &error_abort);
  78     object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
  79     if (local_err) {
  80         goto error;
  81     }
  82     object_property_set_bool(obj, true, "realized", &local_err);
  83     if (local_err) {
  84         goto error;
  85     }
  86
  87     return ICS_BASE(obj);
  88
  89 error:
  90     error_propagate(errp, local_err);
  91     return NULL;
  92 }
  93
  94 static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
  95 {
  96     MachineState *machine = MACHINE(spapr);
  97     int nr_irqs = spapr->irq->nr_irqs;
  98     Error *local_err = NULL;
  99
 100     if (kvm_enabled()) {
 101         if (machine_kernel_irqchip_allowed(machine) &&
 102             !xics_kvm_init(spapr, &local_err)) {
 103             spapr->icp_type = TYPE_KVM_ICP;
 104             spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
 105                                           &local_err);
 106         }
 107         if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
 108             error_prepend(&local_err,
 109                           "kernel_irqchip requested but unavailable: ");
 110             goto error;
 111         }
 112         error_free(local_err);
 113         local_err = NULL;
 114     }
 115
 116     if (!spapr->ics) {
 117         xics_spapr_init(spapr);
 118         spapr->icp_type = TYPE_ICP;
 119         spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
 120                                       &local_err);
 121     }
 122
 123 error:
 124     error_propagate(errp, local_err);
 125 }
 126
 127 #define ICS_IRQ_FREE(ics, srcno)   \
 128     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
 129
 130 static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
 131                                 Error **errp)
 132 {
 133     ICSState *ics = spapr->ics;
 134
 135     assert(ics);
 136
 137     if (!ics_valid_irq(ics, irq)) {
 138         error_setg(errp, "IRQ %d is invalid", irq);
 139         return -1;
 140     }
 141
 142     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
 143         error_setg(errp, "IRQ %d is not free", irq);
 144         return -1;
 145     }
 146
 147     ics_set_irq_type(ics, irq - ics->offset, lsi);
 148     return 0;
 149 }
 150
 151 static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
 152 {
 153     ICSState *ics = spapr->ics;
 154     uint32_t srcno = irq - ics->offset;
 155     int i;
 156
 157     if (ics_valid_irq(ics, irq)) {
 158         trace_spapr_irq_free(0, irq, num);
 159         for (i = srcno; i < srcno + num; ++i) {
 160             if (ICS_IRQ_FREE(ics, i)) {
 161                 trace_spapr_irq_free_warn(0, i);
 162             }
 163             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
 164         }
 165     }
 166 }
 167
 168 static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
 169 {
 170     ICSState *ics = spapr->ics;
 171     uint32_t srcno = irq - ics->offset;
 172
 173     if (ics_valid_irq(ics, irq)) {
 174         return ics->qirqs[srcno];
 175     }
 176
 177     return NULL;
 178 }
 179
 180 static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
 181 {
 182     CPUState *cs;
 183
 184     CPU_FOREACH(cs) {
 185         PowerPCCPU *cpu = POWERPC_CPU(cs);
 186
 187         icp_pic_print_info(ICP(cpu->intc), mon);
 188     }
 189
 190     ics_pic_print_info(spapr->ics, mon);
 191 }
 192
 193 static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
 194                                            PowerPCCPU *cpu, Error **errp)
 195 {
 196     Error *local_err = NULL;
 197     Object *obj;
 198
 199     obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
 200                      &local_err);
 201     if (local_err) {
 202         error_propagate(errp, local_err);
 203         return;
 204     }
 205
 206     cpu->intc = obj;
 207 }
 208
 209 static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
 210 {
 211     if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
 212         CPUState *cs;
 213         CPU_FOREACH(cs) {
 214             PowerPCCPU *cpu = POWERPC_CPU(cs);
 215             icp_resend(ICP(cpu->intc));
 216         }
 217     }
 218     return 0;
 219 }
 220
 221 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
 222 #define SPAPR_IRQ_XICS_NR_MSIS     \
 223     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
 224
 225 sPAPRIrq spapr_irq_xics = {
 226     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
 227     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
 228     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 229
 230     .init        = spapr_irq_init_xics,
 231     .claim       = spapr_irq_claim_xics,
 232     .free        = spapr_irq_free_xics,
 233     .qirq        = spapr_qirq_xics,
 234     .print_info  = spapr_irq_print_info_xics,
 235     .dt_populate = spapr_dt_xics,
 236     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 237     .post_load   = spapr_irq_post_load_xics,
 238 };
 239
 240 /*
 241  * XIVE IRQ backend.
 242  */
 243 static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
 244 {
 245     MachineState *machine = MACHINE(spapr);
 246     uint32_t nr_servers = spapr_max_server_number(spapr);
 247     DeviceState *dev;
 248     int i;
 249
 250     /* KVM XIVE device not yet available */
 251     if (kvm_enabled()) {
 252         if (machine_kernel_irqchip_required(machine)) {
 253             error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
 254             return;
 255         }
 256     }
 257
 258     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
 259     qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
 260     /*
 261      * 8 XIVE END structures per CPU. One for each available priority
 262      */
 263     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
 264     qdev_init_nofail(dev);
 265
 266     spapr->xive = SPAPR_XIVE(dev);
 267
 268     /* Enable the CPU IPIs */
 269     for (i = 0; i < nr_servers; ++i) {
 270         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
 271     }
 272
 273     spapr_xive_hcall_init(spapr);
 274 }
 275
 276 static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
 277                                 Error **errp)
 278 {
 279     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
 280         error_setg(errp, "IRQ %d is invalid", irq);
 281         return -1;
 282     }
 283     return 0;
 284 }
 285
 286 static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
 287 {
 288     int i;
 289
 290     for (i = irq; i < irq + num; ++i) {
 291         spapr_xive_irq_free(spapr->xive, i);
 292     }
 293 }
 294
 295 static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
 296 {
 297     sPAPRXive *xive = spapr->xive;
 298     XiveSource *xsrc = &xive->source;
 299
 300     if (irq >= xive->nr_irqs) {
 301         return NULL;
 302     }
 303
 304     /* The sPAPR machine/device should have claimed the IRQ before */
 305     assert(xive_eas_is_valid(&xive->eat[irq]));
 306
 307     return xsrc->qirqs[irq];
 308 }
 309
 310 static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
 311                                       Monitor *mon)
 312 {
 313     CPUState *cs;
 314
 315     CPU_FOREACH(cs) {
 316         PowerPCCPU *cpu = POWERPC_CPU(cs);
 317
 318         xive_tctx_pic_print_info(cpu->tctx, mon);
 319     }
 320
 321     spapr_xive_pic_print_info(spapr->xive, mon);
 322 }
 323
 324 static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
 325                                            PowerPCCPU *cpu, Error **errp)
 326 {
 327     Error *local_err = NULL;
 328     Object *obj;
 329
 330     obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
 331     if (local_err) {
 332         error_propagate(errp, local_err);
 333         return;
 334     }
 335
 336     cpu->tctx = XIVE_TCTX(obj);
 337
 338     /*
 339      * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
 340      * don't beneficiate from the reset of the XIVE IRQ backend
 341      */
 342     spapr_xive_set_tctx_os_cam(cpu->tctx);
 343 }
 344
 345 static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
 346 {
 347     return 0;
 348 }
 349
 350 static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
 351 {
 352     CPUState *cs;
 353
 354     CPU_FOREACH(cs) {
 355         PowerPCCPU *cpu = POWERPC_CPU(cs);
 356
 357         /* (TCG) Set the OS CAM line of the thread interrupt context. */
 358         spapr_xive_set_tctx_os_cam(cpu->tctx);
 359     }
 360 }
 361
 362 /*
 363  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
 364  * with XICS.
 365  */
 366
 367 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
 368 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
 369
 370 sPAPRIrq spapr_irq_xive = {
 371     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
 372     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
 373     .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
 374
 375     .init        = spapr_irq_init_xive,
 376     .claim       = spapr_irq_claim_xive,
 377     .free        = spapr_irq_free_xive,
 378     .qirq        = spapr_qirq_xive,
 379     .print_info  = spapr_irq_print_info_xive,
 380     .dt_populate = spapr_dt_xive,
 381     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
 382     .post_load   = spapr_irq_post_load_xive,
 383     .reset       = spapr_irq_reset_xive,
 384 };
 385
 386 /*
 387  * sPAPR IRQ frontend routines for devices
 388  */
 389 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
 390 {
 391     /* Initialize the MSI IRQ allocator. */
 392     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
 393         spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
 394     }
 395
 396     spapr->irq->init(spapr, errp);
 397 }
 398
 399 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
 400 {
 401     return spapr->irq->claim(spapr, irq, lsi, errp);
 402 }
 403
 404 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
 405 {
 406     spapr->irq->free(spapr, irq, num);
 407 }
 408
 409 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
 410 {
 411     return spapr->irq->qirq(spapr, irq);
 412 }
 413
 414 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
 415 {
 416     return spapr->irq->post_load(spapr, version_id);
 417 }
 418
 419 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
 420 {
 421     if (spapr->irq->reset) {
 422         spapr->irq->reset(spapr, errp);
 423     }
 424 }
 425
 426 /*
 427  * XICS legacy routines - to deprecate one day
 428  */
 429
 430 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
 431 {
 432     int first, i;
 433
 434     for (first = 0; first < ics->nr_irqs; first += alignnum) {
 435         if (num > (ics->nr_irqs - first)) {
 436             return -1;
 437         }
 438         for (i = first; i < first + num; ++i) {
 439             if (!ICS_IRQ_FREE(ics, i)) {
 440                 break;
 441             }
 442         }
 443         if (i == (first + num)) {
 444             return first;
 445         }
 446     }
 447
 448     return -1;
 449 }
 450
 451 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
 452 {
 453     ICSState *ics = spapr->ics;
 454     int first = -1;
 455
 456     assert(ics);
 457
 458     /*
 459      * MSIMesage::data is used for storing VIRQ so
 460      * it has to be aligned to num to support multiple
 461      * MSI vectors. MSI-X is not affected by this.
 462      * The hint is used for the first IRQ, the rest should
 463      * be allocated continuously.
 464      */
 465     if (align) {
 466         assert((num == 1) || (num == 2) || (num == 4) ||
 467                (num == 8) || (num == 16) || (num == 32));
 468         first = ics_find_free_block(ics, num, num);
 469     } else {
 470         first = ics_find_free_block(ics, num, 1);
 471     }
 472
 473     if (first < 0) {
 474         error_setg(errp, "can't find a free %d-IRQ block", num);
 475         return -1;
 476     }
 477
 478     return first + ics->offset;
 479 }
 480
 481 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
 482
 483 sPAPRIrq spapr_irq_xics_legacy = {
 484     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 485     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 486     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 487
 488     .init        = spapr_irq_init_xics,
 489     .claim       = spapr_irq_claim_xics,
 490     .free        = spapr_irq_free_xics,
 491     .qirq        = spapr_qirq_xics,
 492     .print_info  = spapr_irq_print_info_xics,
 493     .dt_populate = spapr_dt_xics,
 494     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 495     .post_load   = spapr_irq_post_load_xics,
 496 };