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tests/acpi: allow changes for microvm/APIC.pcie
[qemu/ar7.git] / hw / arm / aspeed_soc.c
blob7eefd54ac07a7a41f48466848386455dad62064d
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_VIC] = 0x1E6C0000,
35 [ASPEED_DEV_SDMC] = 0x1E6E0000,
36 [ASPEED_DEV_SCU] = 0x1E6E2000,
37 [ASPEED_DEV_XDMA] = 0x1E6E7000,
38 [ASPEED_DEV_VIDEO] = 0x1E700000,
39 [ASPEED_DEV_ADC] = 0x1E6E9000,
40 [ASPEED_DEV_SRAM] = 0x1E720000,
41 [ASPEED_DEV_SDHCI] = 0x1E740000,
42 [ASPEED_DEV_GPIO] = 0x1E780000,
43 [ASPEED_DEV_RTC] = 0x1E781000,
44 [ASPEED_DEV_TIMER1] = 0x1E782000,
45 [ASPEED_DEV_WDT] = 0x1E785000,
46 [ASPEED_DEV_PWM] = 0x1E786000,
47 [ASPEED_DEV_LPC] = 0x1E789000,
48 [ASPEED_DEV_IBT] = 0x1E789140,
49 [ASPEED_DEV_I2C] = 0x1E78A000,
50 [ASPEED_DEV_ETH1] = 0x1E660000,
51 [ASPEED_DEV_ETH2] = 0x1E680000,
52 [ASPEED_DEV_UART1] = 0x1E783000,
53 [ASPEED_DEV_UART5] = 0x1E784000,
54 [ASPEED_DEV_VUART] = 0x1E787000,
55 [ASPEED_DEV_SDRAM] = 0x40000000,
56 };
57
58 static const hwaddr aspeed_soc_ast2500_memmap[] = {
59 [ASPEED_DEV_IOMEM] = 0x1E600000,
60 [ASPEED_DEV_FMC] = 0x1E620000,
61 [ASPEED_DEV_SPI1] = 0x1E630000,
62 [ASPEED_DEV_SPI2] = 0x1E631000,
63 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
64 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
65 [ASPEED_DEV_VIC] = 0x1E6C0000,
66 [ASPEED_DEV_SDMC] = 0x1E6E0000,
67 [ASPEED_DEV_SCU] = 0x1E6E2000,
68 [ASPEED_DEV_XDMA] = 0x1E6E7000,
69 [ASPEED_DEV_ADC] = 0x1E6E9000,
70 [ASPEED_DEV_VIDEO] = 0x1E700000,
71 [ASPEED_DEV_SRAM] = 0x1E720000,
72 [ASPEED_DEV_SDHCI] = 0x1E740000,
73 [ASPEED_DEV_GPIO] = 0x1E780000,
74 [ASPEED_DEV_RTC] = 0x1E781000,
75 [ASPEED_DEV_TIMER1] = 0x1E782000,
76 [ASPEED_DEV_WDT] = 0x1E785000,
77 [ASPEED_DEV_PWM] = 0x1E786000,
78 [ASPEED_DEV_LPC] = 0x1E789000,
79 [ASPEED_DEV_IBT] = 0x1E789140,
80 [ASPEED_DEV_I2C] = 0x1E78A000,
81 [ASPEED_DEV_ETH1] = 0x1E660000,
82 [ASPEED_DEV_ETH2] = 0x1E680000,
83 [ASPEED_DEV_UART1] = 0x1E783000,
84 [ASPEED_DEV_UART5] = 0x1E784000,
85 [ASPEED_DEV_VUART] = 0x1E787000,
86 [ASPEED_DEV_SDRAM] = 0x80000000,
87 };
88
89 static const int aspeed_soc_ast2400_irqmap[] = {
90 [ASPEED_DEV_UART1] = 9,
91 [ASPEED_DEV_UART2] = 32,
92 [ASPEED_DEV_UART3] = 33,
93 [ASPEED_DEV_UART4] = 34,
94 [ASPEED_DEV_UART5] = 10,
95 [ASPEED_DEV_VUART] = 8,
96 [ASPEED_DEV_FMC] = 19,
97 [ASPEED_DEV_EHCI1] = 5,
98 [ASPEED_DEV_EHCI2] = 13,
99 [ASPEED_DEV_SDMC] = 0,
100 [ASPEED_DEV_SCU] = 21,
101 [ASPEED_DEV_ADC] = 31,
102 [ASPEED_DEV_GPIO] = 20,
103 [ASPEED_DEV_RTC] = 22,
104 [ASPEED_DEV_TIMER1] = 16,
105 [ASPEED_DEV_TIMER2] = 17,
106 [ASPEED_DEV_TIMER3] = 18,
107 [ASPEED_DEV_TIMER4] = 35,
108 [ASPEED_DEV_TIMER5] = 36,
109 [ASPEED_DEV_TIMER6] = 37,
110 [ASPEED_DEV_TIMER7] = 38,
111 [ASPEED_DEV_TIMER8] = 39,
112 [ASPEED_DEV_WDT] = 27,
113 [ASPEED_DEV_PWM] = 28,
114 [ASPEED_DEV_LPC] = 8,
115 [ASPEED_DEV_IBT] = 8, /* LPC */
116 [ASPEED_DEV_I2C] = 12,
117 [ASPEED_DEV_ETH1] = 2,
118 [ASPEED_DEV_ETH2] = 3,
119 [ASPEED_DEV_XDMA] = 6,
120 [ASPEED_DEV_SDHCI] = 26,
121 };
122
123 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
124
125 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
126 {
127 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
128
129 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
130 }
131
132 static void aspeed_soc_init(Object *obj)
133 {
134 AspeedSoCState *s = ASPEED_SOC(obj);
135 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
136 int i;
137 char socname[8];
138 char typename[64];
139
140 if (sscanf(sc->name, "%7s", socname) != 1) {
141 g_assert_not_reached();
142 }
143
144 for (i = 0; i < sc->num_cpus; i++) {
145 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
146 }
147
148 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
149 object_initialize_child(obj, "scu", &s->scu, typename);
150 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
151 sc->silicon_rev);
152 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
153 "hw-strap1");
154 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
155 "hw-strap2");
156 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
157 "hw-prot-key");
158
159 object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
160
161 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
162
163 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
164 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
165
166 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
167 object_initialize_child(obj, "i2c", &s->i2c, typename);
168
169 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
170 object_initialize_child(obj, "fmc", &s->fmc, typename);
171 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
172
173 for (i = 0; i < sc->spis_num; i++) {
174 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
175 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
176 }
177
178 for (i = 0; i < sc->ehcis_num; i++) {
179 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
180 TYPE_PLATFORM_EHCI);
181 }
182
183 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
184 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
185 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
186 "ram-size");
187 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
188 "max-ram-size");
189
190 for (i = 0; i < sc->wdts_num; i++) {
191 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
192 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
193 }
194
195 for (i = 0; i < sc->macs_num; i++) {
196 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
197 TYPE_FTGMAC100);
198 }
199
200 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
201
202 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
203 object_initialize_child(obj, "gpio", &s->gpio, typename);
204
205 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
206
207 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
208
209 /* Init sd card slot class here so that they're under the correct parent */
210 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
211 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
212 TYPE_SYSBUS_SDHCI);
213 }
214 }
215
216 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
217 {
218 int i;
219 AspeedSoCState *s = ASPEED_SOC(dev);
220 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
221 Error *err = NULL;
222
223 /* IO space */
224 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
225 ASPEED_SOC_IOMEM_SIZE);
226
227 /* Video engine stub */
228 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
229 0x1000);
230
231 /* CPU */
232 for (i = 0; i < sc->num_cpus; i++) {
233 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
234 return;
235 }
236 }
237
238 /* SRAM */
239 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
240 sc->sram_size, &err);
241 if (err) {
242 error_propagate(errp, err);
243 return;
244 }
245 memory_region_add_subregion(get_system_memory(),
246 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
247
248 /* SCU */
249 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
250 return;
251 }
252 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
253
254 /* VIC */
255 if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
256 return;
257 }
258 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
259 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
260 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
261 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
262 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
263
264 /* RTC */
265 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
266 return;
267 }
268 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
269 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
270 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
271
272 /* Timer */
273 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
274 &error_abort);
275 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
276 return;
277 }
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
279 sc->memmap[ASPEED_DEV_TIMER1]);
280 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
281 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
282 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
283 }
284
285 /* UART - attach an 8250 to the IO space as our UART5 */
286 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
287 aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400,
288 serial_hd(0), DEVICE_LITTLE_ENDIAN);
289
290 /* I2C */
291 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
292 &error_abort);
293 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
294 return;
295 }
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
298 aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
299
300 /* FMC, The number of CS is set at the board level */
301 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
302 &error_abort);
303 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base",
304 sc->memmap[ASPEED_DEV_SDRAM], errp)) {
305 return;
306 }
307 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
308 return;
309 }
310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
311 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
312 s->fmc.ctrl->flash_window_base);
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
314 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
315
316 /* SPI */
317 for (i = 0; i < sc->spis_num; i++) {
318 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort);
319 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
320 return;
321 }
322 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
323 sc->memmap[ASPEED_DEV_SPI1 + i]);
324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
325 s->spi[i].ctrl->flash_window_base);
326 }
327
328 /* EHCI */
329 for (i = 0; i < sc->ehcis_num; i++) {
330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
331 return;
332 }
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
334 sc->memmap[ASPEED_DEV_EHCI1 + i]);
335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
336 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
337 }
338
339 /* SDMC - SDRAM Memory Controller */
340 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
341 return;
342 }
343 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
344
345 /* Watch dog */
346 for (i = 0; i < sc->wdts_num; i++) {
347 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
348
349 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
350 &error_abort);
351 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
352 return;
353 }
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
355 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
356 }
357
358 /* Net */
359 for (i = 0; i < sc->macs_num; i++) {
360 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
361 &error_abort);
362 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
363 return;
364 }
365 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
366 sc->memmap[ASPEED_DEV_ETH1 + i]);
367 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
368 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
369 }
370
371 /* XDMA */
372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
373 return;
374 }
375 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
376 sc->memmap[ASPEED_DEV_XDMA]);
377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
378 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
379
380 /* GPIO */
381 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
382 return;
383 }
384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
386 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
387
388 /* SDHCI */
389 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
390 return;
391 }
392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
393 sc->memmap[ASPEED_DEV_SDHCI]);
394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
395 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
396 }
397 static Property aspeed_soc_properties[] = {
398 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
399 MemoryRegion *),
400 DEFINE_PROP_END_OF_LIST(),
401 };
402
403 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
404 {
405 DeviceClass *dc = DEVICE_CLASS(oc);
406
407 dc->realize = aspeed_soc_realize;
408 /* Reason: Uses serial_hds and nd_table in realize() directly */
409 dc->user_creatable = false;
410 device_class_set_props(dc, aspeed_soc_properties);
411 }
412
413 static const TypeInfo aspeed_soc_type_info = {
414 .name = TYPE_ASPEED_SOC,
415 .parent = TYPE_DEVICE,
416 .instance_size = sizeof(AspeedSoCState),
417 .class_size = sizeof(AspeedSoCClass),
418 .class_init = aspeed_soc_class_init,
419 .abstract = true,
420 };
421
422 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
423 {
424 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
425
426 sc->name = "ast2400-a1";
427 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
428 sc->silicon_rev = AST2400_A1_SILICON_REV;
429 sc->sram_size = 0x8000;
430 sc->spis_num = 1;
431 sc->ehcis_num = 1;
432 sc->wdts_num = 2;
433 sc->macs_num = 2;
434 sc->irqmap = aspeed_soc_ast2400_irqmap;
435 sc->memmap = aspeed_soc_ast2400_memmap;
436 sc->num_cpus = 1;
437 }
438
439 static const TypeInfo aspeed_soc_ast2400_type_info = {
440 .name = "ast2400-a1",
441 .parent = TYPE_ASPEED_SOC,
442 .instance_init = aspeed_soc_init,
443 .instance_size = sizeof(AspeedSoCState),
444 .class_init = aspeed_soc_ast2400_class_init,
445 };
446
447 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
448 {
449 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
450
451 sc->name = "ast2500-a1";
452 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
453 sc->silicon_rev = AST2500_A1_SILICON_REV;
454 sc->sram_size = 0x9000;
455 sc->spis_num = 2;
456 sc->ehcis_num = 2;
457 sc->wdts_num = 3;
458 sc->macs_num = 2;
459 sc->irqmap = aspeed_soc_ast2500_irqmap;
460 sc->memmap = aspeed_soc_ast2500_memmap;
461 sc->num_cpus = 1;
462 }
463
464 static const TypeInfo aspeed_soc_ast2500_type_info = {
465 .name = "ast2500-a1",
466 .parent = TYPE_ASPEED_SOC,
467 .instance_init = aspeed_soc_init,
468 .instance_size = sizeof(AspeedSoCState),
469 .class_init = aspeed_soc_ast2500_class_init,
470 };
471 static void aspeed_soc_register_types(void)
472 {
473 type_register_static(&aspeed_soc_type_info);
474 type_register_static(&aspeed_soc_ast2400_type_info);
475 type_register_static(&aspeed_soc_ast2500_type_info);
476 };
477
478 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU